2 * Standard PCI Hot Plug Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/pci.h>
34 #include <linux/interrupt.h>
39 #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */
40 #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */
41 #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */
42 #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */
43 #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT)
44 #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE)
45 /* Redefine this flagword to set debug level */
46 #define DEBUG_LEVEL DBG_K_STANDARD
48 #define DEFINE_DBG_BUFFER char __dbg_str_buf[256];
50 #define DBG_PRINT( dbg_flags, args... ) \
52 if ( DEBUG_LEVEL & ( dbg_flags ) ) \
55 len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \
56 __FILE__, __LINE__, __FUNCTION__ ); \
57 sprintf( __dbg_str_buf + len, args ); \
58 printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \
62 #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]");
63 #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]");
65 #define DEFINE_DBG_BUFFER
66 #define DBG_ENTER_ROUTINE
67 #define DBG_LEAVE_ROUTINE
70 /* Slot Available Register I field definition */
71 #define SLOT_33MHZ 0x0000001f
72 #define SLOT_66MHZ_PCIX 0x00001f00
73 #define SLOT_100MHZ_PCIX 0x001f0000
74 #define SLOT_133MHZ_PCIX 0x1f000000
76 /* Slot Available Register II field definition */
77 #define SLOT_66MHZ 0x0000001f
78 #define SLOT_66MHZ_PCIX_266 0x00000f00
79 #define SLOT_100MHZ_PCIX_266 0x0000f000
80 #define SLOT_133MHZ_PCIX_266 0x000f0000
81 #define SLOT_66MHZ_PCIX_533 0x00f00000
82 #define SLOT_100MHZ_PCIX_533 0x0f000000
83 #define SLOT_133MHZ_PCIX_533 0xf0000000
86 /* Secondary Bus Configuration Register */
87 /* For PI = 1, Bits 0 to 2 have been encoded as follows to show current bus speed/mode */
90 #define PCIX_66MHZ 0x2
91 #define PCIX_100MHZ 0x3
92 #define PCIX_133MHZ 0x4
94 /* For PI = 2, Bits 0 to 3 have been encoded as follows to show current bus speed/mode */
97 #define PCIX_66MHZ 0x2
98 #define PCIX_100MHZ 0x3
99 #define PCIX_133MHZ 0x4
100 #define PCIX_66MHZ_ECC 0x5
101 #define PCIX_100MHZ_ECC 0x6
102 #define PCIX_133MHZ_ECC 0x7
103 #define PCIX_66MHZ_266 0x9
104 #define PCIX_100MHZ_266 0xa
105 #define PCIX_133MHZ_266 0xb
106 #define PCIX_66MHZ_533 0x11
107 #define PCIX_100MHZ_533 0x12
108 #define PCIX_133MHZ_533 0x13
110 /* Slot Configuration */
111 #define SLOT_NUM 0x0000001F
112 #define FIRST_DEV_NUM 0x00001F00
113 #define PSN 0x07FF0000
114 #define UPDOWN 0x20000000
115 #define MRLSENSOR 0x40000000
116 #define ATTN_BUTTON 0x80000000
118 /* Slot Status Field Definitions */
120 #define PWR_ONLY 0x0001
121 #define ENABLED 0x0002
122 #define DISABLED 0x0003
124 /* Power Indicator State */
125 #define PWR_LED_ON 0x0004
126 #define PWR_LED_BLINK 0x0008
127 #define PWR_LED_OFF 0x000c
129 /* Attention Indicator State */
130 #define ATTEN_LED_ON 0x0010
131 #define ATTEN_LED_BLINK 0x0020
132 #define ATTEN_LED_OFF 0x0030
135 #define pwr_fault 0x0040
137 /* Attention Button */
138 #define ATTEN_BUTTON 0x0080
141 #define MRL_SENSOR 0x0100
144 #define IS_66MHZ_CAP 0x0200
146 /* PRSNT1#/PRSNT2# */
147 #define SLOT_EMP 0x0c00
149 /* PCI-X Capability */
150 #define NON_PCIX 0x0000
151 #define PCIX_66 0x1000
152 #define PCIX_133 0x3000
153 #define PCIX_266 0x4000 /* For PI = 2 only */
154 #define PCIX_533 0x5000 /* For PI = 2 only */
156 /* SHPC 'write' operations/commands */
158 /* Slot operation - 0x00h to 0x3Fh */
160 #define NO_CHANGE 0x00
162 /* Slot state - Bits 0 & 1 of controller command register */
163 #define SET_SLOT_PWR 0x01
164 #define SET_SLOT_ENABLE 0x02
165 #define SET_SLOT_DISABLE 0x03
167 /* Power indicator state - Bits 2 & 3 of controller command register*/
168 #define SET_PWR_ON 0x04
169 #define SET_PWR_BLINK 0x08
170 #define SET_PWR_OFF 0x0C
172 /* Attention indicator state - Bits 4 & 5 of controller command register*/
173 #define SET_ATTN_ON 0x010
174 #define SET_ATTN_BLINK 0x020
175 #define SET_ATTN_OFF 0x030
177 /* Set bus speed/mode A - 0x40h to 0x47h */
178 #define SETA_PCI_33MHZ 0x40
179 #define SETA_PCI_66MHZ 0x41
180 #define SETA_PCIX_66MHZ 0x42
181 #define SETA_PCIX_100MHZ 0x43
182 #define SETA_PCIX_133MHZ 0x44
183 #define RESERV_1 0x45
184 #define RESERV_2 0x46
185 #define RESERV_3 0x47
187 /* Set bus speed/mode B - 0x50h to 0x5fh */
188 #define SETB_PCI_33MHZ 0x50
189 #define SETB_PCI_66MHZ 0x51
190 #define SETB_PCIX_66MHZ_PM 0x52
191 #define SETB_PCIX_100MHZ_PM 0x53
192 #define SETB_PCIX_133MHZ_PM 0x54
193 #define SETB_PCIX_66MHZ_EM 0x55
194 #define SETB_PCIX_100MHZ_EM 0x56
195 #define SETB_PCIX_133MHZ_EM 0x57
196 #define SETB_PCIX_66MHZ_266 0x58
197 #define SETB_PCIX_100MHZ_266 0x59
198 #define SETB_PCIX_133MHZ_266 0x5a
199 #define SETB_PCIX_66MHZ_533 0x5b
200 #define SETB_PCIX_100MHZ_533 0x5c
201 #define SETB_PCIX_133MHZ_533 0x5d
204 /* Power-on all slots - 0x48h */
205 #define SET_PWR_ON_ALL 0x48
207 /* Enable all slots - 0x49h */
208 #define SET_ENABLE_ALL 0x49
210 /* SHPC controller command error code */
211 #define SWITCH_OPEN 0x1
212 #define INVALID_CMD 0x2
213 #define INVALID_SPEED_MODE 0x4
215 /* For accessing SHPC Working Register Set */
216 #define DWORD_SELECT 0x2
217 #define DWORD_DATA 0x4
218 #define BASE_OFFSET 0x0
220 /* Field Offset in Logical Slot Register - byte boundary */
221 #define SLOT_EVENT_LATCH 0x2
222 #define SLOT_SERR_INT_MASK 0x3
224 static spinlock_t hpc_event_lock
;
226 DEFINE_DBG_BUFFER
/* Debug string buffer for entire HPC defined here */
227 static struct php_ctlr_state_s
*php_ctlr_list_head
; /* HPC state linked list */
228 static int ctlr_seq_num
= 0; /* Controller sequenc # */
229 static spinlock_t list_lock
;
231 static irqreturn_t
shpc_isr(int IRQ
, void *dev_id
, struct pt_regs
*regs
);
233 static void start_int_poll_timer(struct php_ctlr_state_s
*php_ctlr
, int seconds
);
234 static int hpc_check_cmd_status(struct controller
*ctrl
);
236 /* This is the interrupt polling timeout function. */
237 static void int_poll_timeout(unsigned long lphp_ctlr
)
239 struct php_ctlr_state_s
*php_ctlr
= (struct php_ctlr_state_s
*)lphp_ctlr
;
244 err("%s: Invalid HPC controller handle!\n", __FUNCTION__
);
248 /* Poll for interrupt events. regs == NULL => polling */
249 shpc_isr( 0, (void *)php_ctlr
, NULL
);
251 init_timer(&php_ctlr
->int_poll_timer
);
252 if (!shpchp_poll_time
)
253 shpchp_poll_time
= 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/
255 start_int_poll_timer(php_ctlr
, shpchp_poll_time
);
260 /* This function starts the interrupt polling timer. */
261 static void start_int_poll_timer(struct php_ctlr_state_s
*php_ctlr
, int seconds
)
264 err("%s: Invalid HPC controller handle!\n", __FUNCTION__
);
268 if ( ( seconds
<= 0 ) || ( seconds
> 60 ) )
269 seconds
= 2; /* Clamp to sane value */
271 php_ctlr
->int_poll_timer
.function
= &int_poll_timeout
;
272 php_ctlr
->int_poll_timer
.data
= (unsigned long)php_ctlr
; /* Instance data */
273 php_ctlr
->int_poll_timer
.expires
= jiffies
+ seconds
* HZ
;
274 add_timer(&php_ctlr
->int_poll_timer
);
279 static inline int shpc_wait_cmd(struct controller
*ctrl
)
282 unsigned int timeout_msec
= shpchp_poll_mode
? 2000 : 1000;
283 unsigned long timeout
= msecs_to_jiffies(timeout_msec
);
284 int rc
= wait_event_interruptible_timeout(ctrl
->queue
,
285 !ctrl
->cmd_busy
, timeout
);
288 err("Command not completed in %d msec\n", timeout_msec
);
291 info("Command was interrupted by a signal\n");
298 static int shpc_write_cmd(struct slot
*slot
, u8 t_slot
, u8 cmd
)
300 struct php_ctlr_state_s
*php_ctlr
= slot
->ctrl
->hpc_ctlr_handle
;
308 mutex_lock(&slot
->ctrl
->cmd_lock
);
311 err("%s: Invalid HPC controller handle!\n", __FUNCTION__
);
316 for (i
= 0; i
< 10; i
++) {
317 cmd_status
= readw(php_ctlr
->creg
+ CMD_STATUS
);
319 if (!(cmd_status
& 0x1))
321 /* Check every 0.1 sec for a total of 1 sec*/
325 cmd_status
= readw(php_ctlr
->creg
+ CMD_STATUS
);
327 if (cmd_status
& 0x1) {
328 /* After 1 sec and and the controller is still busy */
329 err("%s : Controller is still busy after 1 sec.\n", __FUNCTION__
);
335 temp_word
= (t_slot
<< 8) | (cmd
& 0xFF);
336 dbg("%s: t_slot %x cmd %x\n", __FUNCTION__
, t_slot
, cmd
);
338 /* To make sure the Controller Busy bit is 0 before we send out the
341 slot
->ctrl
->cmd_busy
= 1;
342 writew(temp_word
, php_ctlr
->creg
+ CMD
);
345 * Wait for command completion.
347 retval
= shpc_wait_cmd(slot
->ctrl
);
351 cmd_status
= hpc_check_cmd_status(slot
->ctrl
);
353 err("%s: Failed to issued command 0x%x (error code = %d)\n",
354 __FUNCTION__
, cmd
, cmd_status
);
358 mutex_unlock(&slot
->ctrl
->cmd_lock
);
364 static int hpc_check_cmd_status(struct controller
*ctrl
)
366 struct php_ctlr_state_s
*php_ctlr
= ctrl
->hpc_ctlr_handle
;
372 if (!ctrl
->hpc_ctlr_handle
) {
373 err("%s: Invalid HPC controller handle!\n", __FUNCTION__
);
377 cmd_status
= readw(php_ctlr
->creg
+ CMD_STATUS
) & 0x000F;
379 switch (cmd_status
>> 1) {
384 retval
= SWITCH_OPEN
;
385 err("%s: Switch opened!\n", __FUNCTION__
);
388 retval
= INVALID_CMD
;
389 err("%s: Invalid HPC command!\n", __FUNCTION__
);
392 retval
= INVALID_SPEED_MODE
;
393 err("%s: Invalid bus speed/mode!\n", __FUNCTION__
);
404 static int hpc_get_attention_status(struct slot
*slot
, u8
*status
)
406 struct php_ctlr_state_s
*php_ctlr
= slot
->ctrl
->hpc_ctlr_handle
;
413 if (!slot
->ctrl
->hpc_ctlr_handle
) {
414 err("%s: Invalid HPC controller handle!\n", __FUNCTION__
);
418 slot_reg
= readl(php_ctlr
->creg
+ SLOT1
+ 4*(slot
->hp_slot
));
419 slot_status
= (u16
) slot_reg
;
420 atten_led_state
= (slot_status
& 0x0030) >> 4;
422 switch (atten_led_state
) {
424 *status
= 0xFF; /* Reserved */
427 *status
= 1; /* On */
430 *status
= 2; /* Blink */
433 *status
= 0; /* Off */
444 static int hpc_get_power_status(struct slot
* slot
, u8
*status
)
446 struct php_ctlr_state_s
*php_ctlr
= slot
->ctrl
->hpc_ctlr_handle
;
454 if (!slot
->ctrl
->hpc_ctlr_handle
) {
455 err("%s: Invalid HPC controller handle!\n", __FUNCTION__
);
459 slot_reg
= readl(php_ctlr
->creg
+ SLOT1
+ 4*(slot
->hp_slot
));
460 slot_status
= (u16
) slot_reg
;
461 slot_state
= (slot_status
& 0x0003);
463 switch (slot_state
) {
468 *status
= 2; /* Powered only */
471 *status
= 1; /* Enabled */
474 *status
= 0; /* Disabled */
486 static int hpc_get_latch_status(struct slot
*slot
, u8
*status
)
488 struct php_ctlr_state_s
*php_ctlr
= slot
->ctrl
->hpc_ctlr_handle
;
494 if (!slot
->ctrl
->hpc_ctlr_handle
) {
495 err("%s: Invalid HPC controller handle!\n", __FUNCTION__
);
499 slot_reg
= readl(php_ctlr
->creg
+ SLOT1
+ 4*(slot
->hp_slot
));
500 slot_status
= (u16
)slot_reg
;
502 *status
= ((slot_status
& 0x0100) == 0) ? 0 : 1; /* 0 -> close; 1 -> open */
509 static int hpc_get_adapter_status(struct slot
*slot
, u8
*status
)
511 struct php_ctlr_state_s
*php_ctlr
= slot
->ctrl
->hpc_ctlr_handle
;
518 if (!slot
->ctrl
->hpc_ctlr_handle
) {
519 err("%s: Invalid HPC controller handle!\n", __FUNCTION__
);
523 slot_reg
= readl(php_ctlr
->creg
+ SLOT1
+ 4*(slot
->hp_slot
));
524 slot_status
= (u16
)slot_reg
;
525 card_state
= (u8
)((slot_status
& 0x0C00) >> 10);
526 *status
= (card_state
!= 0x3) ? 1 : 0;
532 static int hpc_get_prog_int(struct slot
*slot
, u8
*prog_int
)
534 struct php_ctlr_state_s
*php_ctlr
= slot
->ctrl
->hpc_ctlr_handle
;
538 if (!slot
->ctrl
->hpc_ctlr_handle
) {
539 err("%s: Invalid HPC controller handle!\n", __FUNCTION__
);
543 *prog_int
= readb(php_ctlr
->creg
+ PROG_INTERFACE
);
549 static int hpc_get_adapter_speed(struct slot
*slot
, enum pci_bus_speed
*value
)
551 struct php_ctlr_state_s
*php_ctlr
= slot
->ctrl
->hpc_ctlr_handle
;
553 u16 slot_status
, sec_bus_status
;
554 u8 m66_cap
, pcix_cap
, pi
;
559 if (!slot
->ctrl
->hpc_ctlr_handle
) {
560 err("%s: Invalid HPC controller handle!\n", __FUNCTION__
);
564 if (slot
->hp_slot
>= php_ctlr
->num_slots
) {
565 err("%s: Invalid HPC slot number!\n", __FUNCTION__
);
569 pi
= readb(php_ctlr
->creg
+ PROG_INTERFACE
);
570 slot_reg
= readl(php_ctlr
->creg
+ SLOT1
+ 4*(slot
->hp_slot
));
571 dbg("%s: pi = %d, slot_reg = %x\n", __FUNCTION__
, pi
, slot_reg
);
572 slot_status
= (u16
) slot_reg
;
573 dbg("%s: slot_status = %x\n", __FUNCTION__
, slot_status
);
574 sec_bus_status
= readw(php_ctlr
->creg
+ SEC_BUS_CONFIG
);
576 pcix_cap
= (u8
) ((slot_status
& 0x3000) >> 12);
577 dbg("%s: pcix_cap = %x\n", __FUNCTION__
, pcix_cap
);
578 m66_cap
= (u8
) ((slot_status
& 0x0200) >> 9);
579 dbg("%s: m66_cap = %x\n", __FUNCTION__
, m66_cap
);
585 *value
= m66_cap
? PCI_SPEED_66MHz
: PCI_SPEED_33MHz
;
588 *value
= PCI_SPEED_66MHz_PCIX
;
591 *value
= PCI_SPEED_133MHz_PCIX
;
594 *value
= PCI_SPEED_133MHz_PCIX_266
;
597 *value
= PCI_SPEED_133MHz_PCIX_533
;
599 case 2: /* Reserved */
601 *value
= PCI_SPEED_UNKNOWN
;
608 *value
= m66_cap
? PCI_SPEED_66MHz
: PCI_SPEED_33MHz
;
611 *value
= PCI_SPEED_66MHz_PCIX
;
614 *value
= PCI_SPEED_133MHz_PCIX
;
616 case 2: /* Reserved */
618 *value
= PCI_SPEED_UNKNOWN
;
624 dbg("Adapter speed = %d\n", *value
);
630 static int hpc_get_mode1_ECC_cap(struct slot
*slot
, u8
*mode
)
632 struct php_ctlr_state_s
*php_ctlr
= slot
->ctrl
->hpc_ctlr_handle
;
639 if (!slot
->ctrl
->hpc_ctlr_handle
) {
640 err("%s: Invalid HPC controller handle!\n", __FUNCTION__
);
644 pi
= readb(php_ctlr
->creg
+ PROG_INTERFACE
);
645 sec_bus_status
= readw(php_ctlr
->creg
+ SEC_BUS_CONFIG
);
648 *mode
= (sec_bus_status
& 0x0100) >> 8;
653 dbg("Mode 1 ECC cap = %d\n", *mode
);
659 static int hpc_query_power_fault(struct slot
* slot
)
661 struct php_ctlr_state_s
*php_ctlr
= slot
->ctrl
->hpc_ctlr_handle
;
664 u8 pwr_fault_state
, status
;
668 if (!slot
->ctrl
->hpc_ctlr_handle
) {
669 err("%s: Invalid HPC controller handle!\n", __FUNCTION__
);
673 slot_reg
= readl(php_ctlr
->creg
+ SLOT1
+ 4*(slot
->hp_slot
));
674 slot_status
= (u16
) slot_reg
;
675 pwr_fault_state
= (slot_status
& 0x0040) >> 7;
676 status
= (pwr_fault_state
== 1) ? 0 : 1;
679 /* Note: Logic 0 => fault */
683 static int hpc_set_attention_status(struct slot
*slot
, u8 value
)
685 struct php_ctlr_state_s
*php_ctlr
= slot
->ctrl
->hpc_ctlr_handle
;
689 if (!slot
->ctrl
->hpc_ctlr_handle
) {
690 err("%s: Invalid HPC controller handle!\n", __FUNCTION__
);
694 if (slot
->hp_slot
>= php_ctlr
->num_slots
) {
695 err("%s: Invalid HPC slot number!\n", __FUNCTION__
);
701 slot_cmd
= 0x30; /* OFF */
704 slot_cmd
= 0x10; /* ON */
707 slot_cmd
= 0x20; /* BLINK */
713 shpc_write_cmd(slot
, slot
->hp_slot
, slot_cmd
);
719 static void hpc_set_green_led_on(struct slot
*slot
)
721 struct php_ctlr_state_s
*php_ctlr
= slot
->ctrl
->hpc_ctlr_handle
;
724 if (!slot
->ctrl
->hpc_ctlr_handle
) {
725 err("%s: Invalid HPC controller handle!\n", __FUNCTION__
);
729 if (slot
->hp_slot
>= php_ctlr
->num_slots
) {
730 err("%s: Invalid HPC slot number!\n", __FUNCTION__
);
736 shpc_write_cmd(slot
, slot
->hp_slot
, slot_cmd
);
741 static void hpc_set_green_led_off(struct slot
*slot
)
743 struct php_ctlr_state_s
*php_ctlr
= slot
->ctrl
->hpc_ctlr_handle
;
746 if (!slot
->ctrl
->hpc_ctlr_handle
) {
747 err("%s: Invalid HPC controller handle!\n", __FUNCTION__
);
751 if (slot
->hp_slot
>= php_ctlr
->num_slots
) {
752 err("%s: Invalid HPC slot number!\n", __FUNCTION__
);
758 shpc_write_cmd(slot
, slot
->hp_slot
, slot_cmd
);
763 static void hpc_set_green_led_blink(struct slot
*slot
)
765 struct php_ctlr_state_s
*php_ctlr
= slot
->ctrl
->hpc_ctlr_handle
;
768 if (!slot
->ctrl
->hpc_ctlr_handle
) {
769 err("%s: Invalid HPC controller handle!\n", __FUNCTION__
);
773 if (slot
->hp_slot
>= php_ctlr
->num_slots
) {
774 err("%s: Invalid HPC slot number!\n", __FUNCTION__
);
780 shpc_write_cmd(slot
, slot
->hp_slot
, slot_cmd
);
785 int shpc_get_ctlr_slot_config(struct controller
*ctrl
,
786 int *num_ctlr_slots
, /* number of slots in this HPC */
787 int *first_device_num
, /* PCI dev num of the first slot in this SHPC */
788 int *physical_slot_num
, /* phy slot num of the first slot in this SHPC */
789 int *updown
, /* physical_slot_num increament: 1 or -1 */
792 struct php_ctlr_state_s
*php_ctlr
= ctrl
->hpc_ctlr_handle
;
796 if (!ctrl
->hpc_ctlr_handle
) {
797 err("%s: Invalid HPC controller handle!\n", __FUNCTION__
);
801 *first_device_num
= php_ctlr
->slot_device_offset
; /* Obtained in shpc_init() */
802 *num_ctlr_slots
= php_ctlr
->num_slots
; /* Obtained in shpc_init() */
804 *physical_slot_num
= (readl(php_ctlr
->creg
+ SLOT_CONFIG
) & PSN
) >> 16;
805 dbg("%s: physical_slot_num = %x\n", __FUNCTION__
, *physical_slot_num
);
806 *updown
= ((readl(php_ctlr
->creg
+ SLOT_CONFIG
) & UPDOWN
) >> 29) ? 1 : -1;
812 static void hpc_release_ctlr(struct controller
*ctrl
)
814 struct php_ctlr_state_s
*php_ctlr
= ctrl
->hpc_ctlr_handle
;
815 struct php_ctlr_state_s
*p
, *p_prev
;
819 if (!ctrl
->hpc_ctlr_handle
) {
820 err("%s: Invalid HPC controller handle!\n", __FUNCTION__
);
824 if (shpchp_poll_mode
) {
825 del_timer(&php_ctlr
->int_poll_timer
);
828 free_irq(php_ctlr
->irq
, ctrl
);
830 pci_disable_msi(php_ctlr
->pci_dev
);
833 if (php_ctlr
->pci_dev
) {
834 iounmap(php_ctlr
->creg
);
835 release_mem_region(ctrl
->mmio_base
, ctrl
->mmio_size
);
836 php_ctlr
->pci_dev
= NULL
;
839 spin_lock(&list_lock
);
840 p
= php_ctlr_list_head
;
845 p_prev
->pnext
= p
->pnext
;
847 php_ctlr_list_head
= p
->pnext
;
854 spin_unlock(&list_lock
);
862 static int hpc_power_on_slot(struct slot
* slot
)
864 struct php_ctlr_state_s
*php_ctlr
= slot
->ctrl
->hpc_ctlr_handle
;
870 if (!slot
->ctrl
->hpc_ctlr_handle
) {
871 err("%s: Invalid HPC controller handle!\n", __FUNCTION__
);
875 if (slot
->hp_slot
>= php_ctlr
->num_slots
) {
876 err("%s: Invalid HPC slot number!\n", __FUNCTION__
);
881 retval
= shpc_write_cmd(slot
, slot
->hp_slot
, slot_cmd
);
884 err("%s: Write command failed!\n", __FUNCTION__
);
893 static int hpc_slot_enable(struct slot
* slot
)
895 struct php_ctlr_state_s
*php_ctlr
= slot
->ctrl
->hpc_ctlr_handle
;
901 if (!slot
->ctrl
->hpc_ctlr_handle
) {
902 err("%s: Invalid HPC controller handle!\n", __FUNCTION__
);
906 if (slot
->hp_slot
>= php_ctlr
->num_slots
) {
907 err("%s: Invalid HPC slot number!\n", __FUNCTION__
);
910 /* 3A => Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */
913 retval
= shpc_write_cmd(slot
, slot
->hp_slot
, slot_cmd
);
916 err("%s: Write command failed!\n", __FUNCTION__
);
924 static int hpc_slot_disable(struct slot
* slot
)
926 struct php_ctlr_state_s
*php_ctlr
= slot
->ctrl
->hpc_ctlr_handle
;
932 if (!slot
->ctrl
->hpc_ctlr_handle
) {
933 err("%s: Invalid HPC controller handle!\n", __FUNCTION__
);
937 if (slot
->hp_slot
>= php_ctlr
->num_slots
) {
938 err("%s: Invalid HPC slot number!\n", __FUNCTION__
);
942 /* 1F => Slot - Disable, Power Indicator - Off, Attention Indicator - On */
945 retval
= shpc_write_cmd(slot
, slot
->hp_slot
, slot_cmd
);
948 err("%s: Write command failed!\n", __FUNCTION__
);
956 static int hpc_set_bus_speed_mode(struct slot
* slot
, enum pci_bus_speed value
)
961 struct php_ctlr_state_s
*php_ctlr
= slot
->ctrl
->hpc_ctlr_handle
;
965 if (!slot
->ctrl
->hpc_ctlr_handle
) {
966 err("%s: Invalid HPC controller handle!\n", __FUNCTION__
);
970 pi
= readb(php_ctlr
->creg
+ PROG_INTERFACE
);
975 slot_cmd
= SETA_PCI_33MHZ
;
978 slot_cmd
= SETA_PCI_66MHZ
;
981 slot_cmd
= SETA_PCIX_66MHZ
;
984 slot_cmd
= SETA_PCIX_100MHZ
;
987 slot_cmd
= SETA_PCIX_133MHZ
;
990 slot_cmd
= PCI_SPEED_UNKNOWN
;
997 slot_cmd
= SETB_PCI_33MHZ
;
1000 slot_cmd
= SETB_PCI_66MHZ
;
1003 slot_cmd
= SETB_PCIX_66MHZ_PM
;
1006 slot_cmd
= SETB_PCIX_100MHZ_PM
;
1009 slot_cmd
= SETB_PCIX_133MHZ_PM
;
1012 slot_cmd
= SETB_PCIX_66MHZ_EM
;
1015 slot_cmd
= SETB_PCIX_100MHZ_EM
;
1018 slot_cmd
= SETB_PCIX_133MHZ_EM
;
1021 slot_cmd
= SETB_PCIX_66MHZ_266
;
1024 slot_cmd
= SETB_PCIX_100MHZ_266
;
1027 slot_cmd
= SETB_PCIX_133MHZ_266
;
1030 slot_cmd
= SETB_PCIX_66MHZ_533
;
1033 slot_cmd
= SETB_PCIX_100MHZ_533
;
1036 slot_cmd
= SETB_PCIX_133MHZ_533
;
1039 slot_cmd
= PCI_SPEED_UNKNOWN
;
1045 retval
= shpc_write_cmd(slot
, 0, slot_cmd
);
1047 err("%s: Write command failed!\n", __FUNCTION__
);
1055 static irqreturn_t
shpc_isr(int IRQ
, void *dev_id
, struct pt_regs
*regs
)
1057 struct controller
*ctrl
= NULL
;
1058 struct php_ctlr_state_s
*php_ctlr
;
1059 u8 schedule_flag
= 0;
1061 u32 temp_dword
, intr_loc
, intr_loc2
;
1067 if (!shpchp_poll_mode
) {
1068 ctrl
= (struct controller
*)dev_id
;
1069 php_ctlr
= ctrl
->hpc_ctlr_handle
;
1071 php_ctlr
= (struct php_ctlr_state_s
*) dev_id
;
1072 ctrl
= (struct controller
*)php_ctlr
->callback_instance_id
;
1078 if (!php_ctlr
|| !php_ctlr
->creg
)
1081 /* Check to see if it was our interrupt */
1082 intr_loc
= readl(php_ctlr
->creg
+ INTR_LOC
);
1086 dbg("%s: intr_loc = %x\n",__FUNCTION__
, intr_loc
);
1088 if(!shpchp_poll_mode
) {
1089 /* Mask Global Interrupt Mask - see implementation note on p. 139 */
1090 /* of SHPC spec rev 1.0*/
1091 temp_dword
= readl(php_ctlr
->creg
+ SERR_INTR_ENABLE
);
1092 temp_dword
|= 0x00000001;
1093 writel(temp_dword
, php_ctlr
->creg
+ SERR_INTR_ENABLE
);
1095 intr_loc2
= readl(php_ctlr
->creg
+ INTR_LOC
);
1096 dbg("%s: intr_loc2 = %x\n",__FUNCTION__
, intr_loc2
);
1099 if (intr_loc
& 0x0001) {
1101 * Command Complete Interrupt Pending
1102 * RO only - clear by writing 1 to the Command Completion
1103 * Detect bit in Controller SERR-INT register
1105 temp_dword
= readl(php_ctlr
->creg
+ SERR_INTR_ENABLE
);
1106 temp_dword
&= 0xfffdffff;
1107 writel(temp_dword
, php_ctlr
->creg
+ SERR_INTR_ENABLE
);
1109 wake_up_interruptible(&ctrl
->queue
);
1112 if ((intr_loc
= (intr_loc
>> 1)) == 0)
1115 for (hp_slot
= 0; hp_slot
< ctrl
->num_slots
; hp_slot
++) {
1116 /* To find out which slot has interrupt pending */
1117 if ((intr_loc
>> hp_slot
) & 0x01) {
1118 temp_dword
= readl(php_ctlr
->creg
+ SLOT1
+ (4*hp_slot
));
1119 dbg("%s: Slot %x with intr, slot register = %x\n",
1120 __FUNCTION__
, hp_slot
, temp_dword
);
1121 temp_byte
= (temp_dword
>> 16) & 0xFF;
1122 if ((php_ctlr
->switch_change_callback
) && (temp_byte
& 0x08))
1123 schedule_flag
+= php_ctlr
->switch_change_callback(
1124 hp_slot
, php_ctlr
->callback_instance_id
);
1125 if ((php_ctlr
->attention_button_callback
) && (temp_byte
& 0x04))
1126 schedule_flag
+= php_ctlr
->attention_button_callback(
1127 hp_slot
, php_ctlr
->callback_instance_id
);
1128 if ((php_ctlr
->presence_change_callback
) && (temp_byte
& 0x01))
1129 schedule_flag
+= php_ctlr
->presence_change_callback(
1130 hp_slot
, php_ctlr
->callback_instance_id
);
1131 if ((php_ctlr
->power_fault_callback
) && (temp_byte
& 0x12))
1132 schedule_flag
+= php_ctlr
->power_fault_callback(
1133 hp_slot
, php_ctlr
->callback_instance_id
);
1135 /* Clear all slot events */
1136 temp_dword
= 0xe01f3fff;
1137 writel(temp_dword
, php_ctlr
->creg
+ SLOT1
+ (4*hp_slot
));
1139 intr_loc2
= readl(php_ctlr
->creg
+ INTR_LOC
);
1140 dbg("%s: intr_loc2 = %x\n",__FUNCTION__
, intr_loc2
);
1144 if (!shpchp_poll_mode
) {
1145 /* Unmask Global Interrupt Mask */
1146 temp_dword
= readl(php_ctlr
->creg
+ SERR_INTR_ENABLE
);
1147 temp_dword
&= 0xfffffffe;
1148 writel(temp_dword
, php_ctlr
->creg
+ SERR_INTR_ENABLE
);
1154 static int hpc_get_max_bus_speed (struct slot
*slot
, enum pci_bus_speed
*value
)
1156 struct php_ctlr_state_s
*php_ctlr
= slot
->ctrl
->hpc_ctlr_handle
;
1157 enum pci_bus_speed bus_speed
= PCI_SPEED_UNKNOWN
;
1160 u32 slot_avail1
, slot_avail2
;
1164 if (!slot
->ctrl
->hpc_ctlr_handle
) {
1165 err("%s: Invalid HPC controller handle!\n", __FUNCTION__
);
1169 if (slot
->hp_slot
>= php_ctlr
->num_slots
) {
1170 err("%s: Invalid HPC slot number!\n", __FUNCTION__
);
1174 pi
= readb(php_ctlr
->creg
+ PROG_INTERFACE
);
1175 slot_avail1
= readl(php_ctlr
->creg
+ SLOT_AVAIL1
);
1176 slot_avail2
= readl(php_ctlr
->creg
+ SLOT_AVAIL2
);
1179 if (slot_avail2
& SLOT_133MHZ_PCIX_533
)
1180 bus_speed
= PCIX_133MHZ_533
;
1181 else if (slot_avail2
& SLOT_100MHZ_PCIX_533
)
1182 bus_speed
= PCIX_100MHZ_533
;
1183 else if (slot_avail2
& SLOT_66MHZ_PCIX_533
)
1184 bus_speed
= PCIX_66MHZ_533
;
1185 else if (slot_avail2
& SLOT_133MHZ_PCIX_266
)
1186 bus_speed
= PCIX_133MHZ_266
;
1187 else if (slot_avail2
& SLOT_100MHZ_PCIX_266
)
1188 bus_speed
= PCIX_100MHZ_266
;
1189 else if (slot_avail2
& SLOT_66MHZ_PCIX_266
)
1190 bus_speed
= PCIX_66MHZ_266
;
1191 else if (slot_avail1
& SLOT_133MHZ_PCIX
)
1192 bus_speed
= PCIX_133MHZ
;
1193 else if (slot_avail1
& SLOT_100MHZ_PCIX
)
1194 bus_speed
= PCIX_100MHZ
;
1195 else if (slot_avail1
& SLOT_66MHZ_PCIX
)
1196 bus_speed
= PCIX_66MHZ
;
1197 else if (slot_avail2
& SLOT_66MHZ
)
1198 bus_speed
= PCI_66MHZ
;
1199 else if (slot_avail1
& SLOT_33MHZ
)
1200 bus_speed
= PCI_33MHZ
;
1201 else bus_speed
= PCI_SPEED_UNKNOWN
;
1203 if (slot_avail1
& SLOT_133MHZ_PCIX
)
1204 bus_speed
= PCIX_133MHZ
;
1205 else if (slot_avail1
& SLOT_100MHZ_PCIX
)
1206 bus_speed
= PCIX_100MHZ
;
1207 else if (slot_avail1
& SLOT_66MHZ_PCIX
)
1208 bus_speed
= PCIX_66MHZ
;
1209 else if (slot_avail2
& SLOT_66MHZ
)
1210 bus_speed
= PCI_66MHZ
;
1211 else if (slot_avail1
& SLOT_33MHZ
)
1212 bus_speed
= PCI_33MHZ
;
1213 else bus_speed
= PCI_SPEED_UNKNOWN
;
1217 dbg("Max bus speed = %d\n", bus_speed
);
1222 static int hpc_get_cur_bus_speed (struct slot
*slot
, enum pci_bus_speed
*value
)
1224 struct php_ctlr_state_s
*php_ctlr
= slot
->ctrl
->hpc_ctlr_handle
;
1225 enum pci_bus_speed bus_speed
= PCI_SPEED_UNKNOWN
;
1232 if (!slot
->ctrl
->hpc_ctlr_handle
) {
1233 err("%s: Invalid HPC controller handle!\n", __FUNCTION__
);
1237 if (slot
->hp_slot
>= php_ctlr
->num_slots
) {
1238 err("%s: Invalid HPC slot number!\n", __FUNCTION__
);
1242 pi
= readb(php_ctlr
->creg
+ PROG_INTERFACE
);
1243 sec_bus_status
= readw(php_ctlr
->creg
+ SEC_BUS_CONFIG
);
1246 switch (sec_bus_status
& 0x000f) {
1248 bus_speed
= PCI_SPEED_33MHz
;
1251 bus_speed
= PCI_SPEED_66MHz
;
1254 bus_speed
= PCI_SPEED_66MHz_PCIX
;
1257 bus_speed
= PCI_SPEED_100MHz_PCIX
;
1260 bus_speed
= PCI_SPEED_133MHz_PCIX
;
1263 bus_speed
= PCI_SPEED_66MHz_PCIX_ECC
;
1266 bus_speed
= PCI_SPEED_100MHz_PCIX_ECC
;
1269 bus_speed
= PCI_SPEED_133MHz_PCIX_ECC
;
1272 bus_speed
= PCI_SPEED_66MHz_PCIX_266
;
1275 bus_speed
= PCI_SPEED_100MHz_PCIX_266
;
1278 bus_speed
= PCI_SPEED_133MHz_PCIX_266
;
1281 bus_speed
= PCI_SPEED_66MHz_PCIX_533
;
1284 bus_speed
= PCI_SPEED_100MHz_PCIX_533
;
1287 bus_speed
= PCI_SPEED_133MHz_PCIX_533
;
1292 bus_speed
= PCI_SPEED_UNKNOWN
;
1296 /* In the case where pi is undefined, default it to 1 */
1297 switch (sec_bus_status
& 0x0007) {
1299 bus_speed
= PCI_SPEED_33MHz
;
1302 bus_speed
= PCI_SPEED_66MHz
;
1305 bus_speed
= PCI_SPEED_66MHz_PCIX
;
1308 bus_speed
= PCI_SPEED_100MHz_PCIX
;
1311 bus_speed
= PCI_SPEED_133MHz_PCIX
;
1314 bus_speed
= PCI_SPEED_UNKNOWN
; /* Reserved */
1317 bus_speed
= PCI_SPEED_UNKNOWN
; /* Reserved */
1320 bus_speed
= PCI_SPEED_UNKNOWN
; /* Reserved */
1323 bus_speed
= PCI_SPEED_UNKNOWN
;
1329 dbg("Current bus speed = %d\n", bus_speed
);
1334 static struct hpc_ops shpchp_hpc_ops
= {
1335 .power_on_slot
= hpc_power_on_slot
,
1336 .slot_enable
= hpc_slot_enable
,
1337 .slot_disable
= hpc_slot_disable
,
1338 .set_bus_speed_mode
= hpc_set_bus_speed_mode
,
1339 .set_attention_status
= hpc_set_attention_status
,
1340 .get_power_status
= hpc_get_power_status
,
1341 .get_attention_status
= hpc_get_attention_status
,
1342 .get_latch_status
= hpc_get_latch_status
,
1343 .get_adapter_status
= hpc_get_adapter_status
,
1345 .get_max_bus_speed
= hpc_get_max_bus_speed
,
1346 .get_cur_bus_speed
= hpc_get_cur_bus_speed
,
1347 .get_adapter_speed
= hpc_get_adapter_speed
,
1348 .get_mode1_ECC_cap
= hpc_get_mode1_ECC_cap
,
1349 .get_prog_int
= hpc_get_prog_int
,
1351 .query_power_fault
= hpc_query_power_fault
,
1352 .green_led_on
= hpc_set_green_led_on
,
1353 .green_led_off
= hpc_set_green_led_off
,
1354 .green_led_blink
= hpc_set_green_led_blink
,
1356 .release_ctlr
= hpc_release_ctlr
,
1359 inline static int shpc_indirect_creg_read(struct controller
*ctrl
, int index
,
1363 u32 cap_offset
= ctrl
->cap_offset
;
1364 struct pci_dev
*pdev
= ctrl
->pci_dev
;
1366 rc
= pci_write_config_byte(pdev
, cap_offset
+ DWORD_SELECT
, index
);
1369 return pci_read_config_dword(pdev
, cap_offset
+ DWORD_DATA
, value
);
1372 int shpc_init(struct controller
* ctrl
, struct pci_dev
* pdev
)
1374 struct php_ctlr_state_s
*php_ctlr
, *p
;
1375 void *instance_id
= ctrl
;
1376 int rc
, num_slots
= 0;
1378 static int first
= 1;
1379 u32 shpc_base_offset
;
1380 u32 tempdword
, slot_reg
;
1385 ctrl
->pci_dev
= pdev
; /* pci_dev of the P2P bridge */
1387 spin_lock_init(&list_lock
);
1388 php_ctlr
= kzalloc(sizeof(*php_ctlr
), GFP_KERNEL
);
1390 if (!php_ctlr
) { /* allocate controller state data */
1391 err("%s: HPC controller memory allocation error!\n", __FUNCTION__
);
1395 php_ctlr
->pci_dev
= pdev
; /* save pci_dev in context */
1397 if ((pdev
->vendor
== PCI_VENDOR_ID_AMD
) || (pdev
->device
==
1398 PCI_DEVICE_ID_AMD_GOLAM_7450
)) {
1399 /* amd shpc driver doesn't use Base Offset; assume 0 */
1400 ctrl
->mmio_base
= pci_resource_start(pdev
, 0);
1401 ctrl
->mmio_size
= pci_resource_len(pdev
, 0);
1403 ctrl
->cap_offset
= pci_find_capability(pdev
, PCI_CAP_ID_SHPC
);
1404 if (!ctrl
->cap_offset
) {
1405 err("%s : cap_offset == 0\n", __FUNCTION__
);
1406 goto abort_free_ctlr
;
1408 dbg("%s: cap_offset = %x\n", __FUNCTION__
, ctrl
->cap_offset
);
1410 rc
= shpc_indirect_creg_read(ctrl
, 0, &shpc_base_offset
);
1412 err("%s: cannot read base_offset\n", __FUNCTION__
);
1413 goto abort_free_ctlr
;
1416 rc
= shpc_indirect_creg_read(ctrl
, 3, &tempdword
);
1418 err("%s: cannot read slot config\n", __FUNCTION__
);
1419 goto abort_free_ctlr
;
1421 num_slots
= tempdword
& SLOT_NUM
;
1422 dbg("%s: num_slots (indirect) %x\n", __FUNCTION__
, num_slots
);
1424 for (i
= 0; i
< 9 + num_slots
; i
++) {
1425 rc
= shpc_indirect_creg_read(ctrl
, i
, &tempdword
);
1427 err("%s: cannot read creg (index = %d)\n",
1429 goto abort_free_ctlr
;
1431 dbg("%s: offset %d: value %x\n", __FUNCTION__
,i
,
1436 pci_resource_start(pdev
, 0) + shpc_base_offset
;
1437 ctrl
->mmio_size
= 0x24 + 0x4 * num_slots
;
1441 spin_lock_init(&hpc_event_lock
);
1445 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev
->vendor
, pdev
->device
, pdev
->subsystem_vendor
,
1446 pdev
->subsystem_device
);
1448 if (pci_enable_device(pdev
))
1449 goto abort_free_ctlr
;
1451 if (!request_mem_region(ctrl
->mmio_base
, ctrl
->mmio_size
, MY_NAME
)) {
1452 err("%s: cannot reserve MMIO region\n", __FUNCTION__
);
1453 goto abort_free_ctlr
;
1456 php_ctlr
->creg
= ioremap(ctrl
->mmio_base
, ctrl
->mmio_size
);
1457 if (!php_ctlr
->creg
) {
1458 err("%s: cannot remap MMIO region %lx @ %lx\n", __FUNCTION__
,
1459 ctrl
->mmio_size
, ctrl
->mmio_base
);
1460 release_mem_region(ctrl
->mmio_base
, ctrl
->mmio_size
);
1461 goto abort_free_ctlr
;
1463 dbg("%s: php_ctlr->creg %p\n", __FUNCTION__
, php_ctlr
->creg
);
1465 mutex_init(&ctrl
->crit_sect
);
1466 mutex_init(&ctrl
->cmd_lock
);
1468 /* Setup wait queue */
1469 init_waitqueue_head(&ctrl
->queue
);
1472 php_ctlr
->irq
= pdev
->irq
;
1473 php_ctlr
->attention_button_callback
= shpchp_handle_attention_button
,
1474 php_ctlr
->switch_change_callback
= shpchp_handle_switch_change
;
1475 php_ctlr
->presence_change_callback
= shpchp_handle_presence_change
;
1476 php_ctlr
->power_fault_callback
= shpchp_handle_power_fault
;
1477 php_ctlr
->callback_instance_id
= instance_id
;
1479 /* Return PCI Controller Info */
1480 php_ctlr
->slot_device_offset
= (readl(php_ctlr
->creg
+ SLOT_CONFIG
) & FIRST_DEV_NUM
) >> 8;
1481 php_ctlr
->num_slots
= readl(php_ctlr
->creg
+ SLOT_CONFIG
) & SLOT_NUM
;
1482 dbg("%s: slot_device_offset %x\n", __FUNCTION__
, php_ctlr
->slot_device_offset
);
1483 dbg("%s: num_slots %x\n", __FUNCTION__
, php_ctlr
->num_slots
);
1485 /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */
1486 tempdword
= readl(php_ctlr
->creg
+ SERR_INTR_ENABLE
);
1487 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__
, tempdword
);
1488 tempdword
= 0x0003000f;
1489 writel(tempdword
, php_ctlr
->creg
+ SERR_INTR_ENABLE
);
1490 tempdword
= readl(php_ctlr
->creg
+ SERR_INTR_ENABLE
);
1491 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__
, tempdword
);
1493 /* Mask the MRL sensor SERR Mask of individual slot in
1494 * Slot SERR-INT Mask & clear all the existing event if any
1496 for (hp_slot
= 0; hp_slot
< php_ctlr
->num_slots
; hp_slot
++) {
1497 slot_reg
= readl(php_ctlr
->creg
+ SLOT1
+ 4*hp_slot
);
1498 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__
,
1500 tempdword
= 0xffff3fff;
1501 writel(tempdword
, php_ctlr
->creg
+ SLOT1
+ (4*hp_slot
));
1504 if (shpchp_poll_mode
) {/* Install interrupt polling code */
1505 /* Install and start the interrupt polling timer */
1506 init_timer(&php_ctlr
->int_poll_timer
);
1507 start_int_poll_timer( php_ctlr
, 10 ); /* start with 10 second delay */
1509 /* Installs the interrupt handler */
1510 rc
= pci_enable_msi(pdev
);
1512 info("Can't get msi for the hotplug controller\n");
1513 info("Use INTx for the hotplug controller\n");
1515 php_ctlr
->irq
= pdev
->irq
;
1517 rc
= request_irq(php_ctlr
->irq
, shpc_isr
, SA_SHIRQ
, MY_NAME
, (void *) ctrl
);
1518 dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__
, php_ctlr
->irq
, ctlr_seq_num
, rc
);
1520 err("Can't get irq %d for the hotplug controller\n", php_ctlr
->irq
);
1521 goto abort_free_ctlr
;
1524 dbg("%s: HPC at b:d:f:irq=0x%x:%x:%x:%x\n", __FUNCTION__
,
1525 pdev
->bus
->number
, PCI_SLOT(pdev
->devfn
),
1526 PCI_FUNC(pdev
->devfn
), pdev
->irq
);
1527 get_hp_hw_control_from_firmware(pdev
);
1529 /* Add this HPC instance into the HPC list */
1530 spin_lock(&list_lock
);
1531 if (php_ctlr_list_head
== 0) {
1532 php_ctlr_list_head
= php_ctlr
;
1533 p
= php_ctlr_list_head
;
1536 p
= php_ctlr_list_head
;
1541 p
->pnext
= php_ctlr
;
1543 spin_unlock(&list_lock
);
1547 ctrl
->hpc_ctlr_handle
= php_ctlr
;
1548 ctrl
->hpc_ops
= &shpchp_hpc_ops
;
1550 for (hp_slot
= 0; hp_slot
< php_ctlr
->num_slots
; hp_slot
++) {
1551 slot_reg
= readl(php_ctlr
->creg
+ SLOT1
+ 4*hp_slot
);
1552 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__
,
1554 tempdword
= 0xe01f3fff;
1555 writel(tempdword
, php_ctlr
->creg
+ SLOT1
+ (4*hp_slot
));
1557 if (!shpchp_poll_mode
) {
1558 /* Unmask all general input interrupts and SERR */
1559 tempdword
= readl(php_ctlr
->creg
+ SERR_INTR_ENABLE
);
1560 tempdword
= 0x0000000a;
1561 writel(tempdword
, php_ctlr
->creg
+ SERR_INTR_ENABLE
);
1562 tempdword
= readl(php_ctlr
->creg
+ SERR_INTR_ENABLE
);
1563 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__
, tempdword
);
1569 /* We end up here for the many possible ways to fail this API. */