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MINI2440: Added new T35 (QVGA) and Innolux 5.6" (VGA) TFTs
[linux-2.6/mini2440.git] / drivers / s390 / net / qeth_core_main.c
blobc4a42d970158b62c6b96ebb044ee2fa777f70930
1 /*
2 * drivers/s390/net/qeth_core_main.c
3 *
4 * Copyright IBM Corp. 2007, 2009
5 * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
6 * Frank Pavlic <fpavlic@de.ibm.com>,
7 * Thomas Spatzier <tspat@de.ibm.com>,
8 * Frank Blaschka <frank.blaschka@de.ibm.com>
9 */
10
11 #define KMSG_COMPONENT "qeth"
12 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/string.h>
17 #include <linux/errno.h>
18 #include <linux/kernel.h>
19 #include <linux/ip.h>
20 #include <linux/tcp.h>
21 #include <linux/mii.h>
22 #include <linux/kthread.h>
23
24 #include <asm/ebcdic.h>
25 #include <asm/io.h>
26
27 #include "qeth_core.h"
28
29 struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
30 /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
31 /* N P A M L V H */
32 [QETH_DBF_SETUP] = {"qeth_setup",
33 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
34 [QETH_DBF_QERR] = {"qeth_qerr",
35 2, 1, 8, 2, &debug_hex_ascii_view, NULL},
36 [QETH_DBF_TRACE] = {"qeth_trace",
37 4, 1, 8, 3, &debug_hex_ascii_view, NULL},
38 [QETH_DBF_MSG] = {"qeth_msg",
39 8, 1, 128, 3, &debug_sprintf_view, NULL},
40 [QETH_DBF_SENSE] = {"qeth_sense",
41 2, 1, 64, 2, &debug_hex_ascii_view, NULL},
42 [QETH_DBF_MISC] = {"qeth_misc",
43 2, 1, 256, 2, &debug_hex_ascii_view, NULL},
44 [QETH_DBF_CTRL] = {"qeth_control",
45 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
46 };
47 EXPORT_SYMBOL_GPL(qeth_dbf);
48
49 struct qeth_card_list_struct qeth_core_card_list;
50 EXPORT_SYMBOL_GPL(qeth_core_card_list);
51 struct kmem_cache *qeth_core_header_cache;
52 EXPORT_SYMBOL_GPL(qeth_core_header_cache);
53
54 static struct device *qeth_core_root_dev;
55 static unsigned int known_devices[][10] = QETH_MODELLIST_ARRAY;
56 static struct lock_class_key qdio_out_skb_queue_key;
57
58 static void qeth_send_control_data_cb(struct qeth_channel *,
59 struct qeth_cmd_buffer *);
60 static int qeth_issue_next_read(struct qeth_card *);
61 static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
62 static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
63 static void qeth_free_buffer_pool(struct qeth_card *);
64 static int qeth_qdio_establish(struct qeth_card *);
65
66
67 static inline void __qeth_fill_buffer_frag(struct sk_buff *skb,
68 struct qdio_buffer *buffer, int is_tso,
69 int *next_element_to_fill)
70 {
71 struct skb_frag_struct *frag;
72 int fragno;
73 unsigned long addr;
74 int element, cnt, dlen;
75
76 fragno = skb_shinfo(skb)->nr_frags;
77 element = *next_element_to_fill;
78 dlen = 0;
79
80 if (is_tso)
81 buffer->element[element].flags =
82 SBAL_FLAGS_MIDDLE_FRAG;
83 else
84 buffer->element[element].flags =
85 SBAL_FLAGS_FIRST_FRAG;
86 dlen = skb->len - skb->data_len;
87 if (dlen) {
88 buffer->element[element].addr = skb->data;
89 buffer->element[element].length = dlen;
90 element++;
91 }
92 for (cnt = 0; cnt < fragno; cnt++) {
93 frag = &skb_shinfo(skb)->frags[cnt];
94 addr = (page_to_pfn(frag->page) << PAGE_SHIFT) +
95 frag->page_offset;
96 buffer->element[element].addr = (char *)addr;
97 buffer->element[element].length = frag->size;
98 if (cnt < (fragno - 1))
99 buffer->element[element].flags =
100 SBAL_FLAGS_MIDDLE_FRAG;
101 else
102 buffer->element[element].flags =
103 SBAL_FLAGS_LAST_FRAG;
104 element++;
105 }
106 *next_element_to_fill = element;
107 }
108
109 static inline const char *qeth_get_cardname(struct qeth_card *card)
110 {
111 if (card->info.guestlan) {
112 switch (card->info.type) {
113 case QETH_CARD_TYPE_OSAE:
114 return " Guest LAN QDIO";
115 case QETH_CARD_TYPE_IQD:
116 return " Guest LAN Hiper";
117 default:
118 return " unknown";
119 }
120 } else {
121 switch (card->info.type) {
122 case QETH_CARD_TYPE_OSAE:
123 return " OSD Express";
124 case QETH_CARD_TYPE_IQD:
125 return " HiperSockets";
126 case QETH_CARD_TYPE_OSN:
127 return " OSN QDIO";
128 default:
129 return " unknown";
130 }
131 }
132 return " n/a";
133 }
134
135 /* max length to be returned: 14 */
136 const char *qeth_get_cardname_short(struct qeth_card *card)
137 {
138 if (card->info.guestlan) {
139 switch (card->info.type) {
140 case QETH_CARD_TYPE_OSAE:
141 return "GuestLAN QDIO";
142 case QETH_CARD_TYPE_IQD:
143 return "GuestLAN Hiper";
144 default:
145 return "unknown";
146 }
147 } else {
148 switch (card->info.type) {
149 case QETH_CARD_TYPE_OSAE:
150 switch (card->info.link_type) {
151 case QETH_LINK_TYPE_FAST_ETH:
152 return "OSD_100";
153 case QETH_LINK_TYPE_HSTR:
154 return "HSTR";
155 case QETH_LINK_TYPE_GBIT_ETH:
156 return "OSD_1000";
157 case QETH_LINK_TYPE_10GBIT_ETH:
158 return "OSD_10GIG";
159 case QETH_LINK_TYPE_LANE_ETH100:
160 return "OSD_FE_LANE";
161 case QETH_LINK_TYPE_LANE_TR:
162 return "OSD_TR_LANE";
163 case QETH_LINK_TYPE_LANE_ETH1000:
164 return "OSD_GbE_LANE";
165 case QETH_LINK_TYPE_LANE:
166 return "OSD_ATM_LANE";
167 default:
168 return "OSD_Express";
169 }
170 case QETH_CARD_TYPE_IQD:
171 return "HiperSockets";
172 case QETH_CARD_TYPE_OSN:
173 return "OSN";
174 default:
175 return "unknown";
176 }
177 }
178 return "n/a";
179 }
180
181 void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
182 int clear_start_mask)
183 {
184 unsigned long flags;
185
186 spin_lock_irqsave(&card->thread_mask_lock, flags);
187 card->thread_allowed_mask = threads;
188 if (clear_start_mask)
189 card->thread_start_mask &= threads;
190 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
191 wake_up(&card->wait_q);
192 }
193 EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
194
195 int qeth_threads_running(struct qeth_card *card, unsigned long threads)
196 {
197 unsigned long flags;
198 int rc = 0;
199
200 spin_lock_irqsave(&card->thread_mask_lock, flags);
201 rc = (card->thread_running_mask & threads);
202 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
203 return rc;
204 }
205 EXPORT_SYMBOL_GPL(qeth_threads_running);
206
207 int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
208 {
209 return wait_event_interruptible(card->wait_q,
210 qeth_threads_running(card, threads) == 0);
211 }
212 EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
213
214 void qeth_clear_working_pool_list(struct qeth_card *card)
215 {
216 struct qeth_buffer_pool_entry *pool_entry, *tmp;
217
218 QETH_DBF_TEXT(TRACE, 5, "clwrklst");
219 list_for_each_entry_safe(pool_entry, tmp,
220 &card->qdio.in_buf_pool.entry_list, list){
221 list_del(&pool_entry->list);
222 }
223 }
224 EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
225
226 static int qeth_alloc_buffer_pool(struct qeth_card *card)
227 {
228 struct qeth_buffer_pool_entry *pool_entry;
229 void *ptr;
230 int i, j;
231
232 QETH_DBF_TEXT(TRACE, 5, "alocpool");
233 for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
234 pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
235 if (!pool_entry) {
236 qeth_free_buffer_pool(card);
237 return -ENOMEM;
238 }
239 for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
240 ptr = (void *) __get_free_page(GFP_KERNEL);
241 if (!ptr) {
242 while (j > 0)
243 free_page((unsigned long)
244 pool_entry->elements[--j]);
245 kfree(pool_entry);
246 qeth_free_buffer_pool(card);
247 return -ENOMEM;
248 }
249 pool_entry->elements[j] = ptr;
250 }
251 list_add(&pool_entry->init_list,
252 &card->qdio.init_pool.entry_list);
253 }
254 return 0;
255 }
256
257 int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
258 {
259 QETH_DBF_TEXT(TRACE, 2, "realcbp");
260
261 if ((card->state != CARD_STATE_DOWN) &&
262 (card->state != CARD_STATE_RECOVER))
263 return -EPERM;
264
265 /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
266 qeth_clear_working_pool_list(card);
267 qeth_free_buffer_pool(card);
268 card->qdio.in_buf_pool.buf_count = bufcnt;
269 card->qdio.init_pool.buf_count = bufcnt;
270 return qeth_alloc_buffer_pool(card);
271 }
272
273 int qeth_set_large_send(struct qeth_card *card,
274 enum qeth_large_send_types type)
275 {
276 int rc = 0;
277
278 if (card->dev == NULL) {
279 card->options.large_send = type;
280 return 0;
281 }
282 if (card->state == CARD_STATE_UP)
283 netif_tx_disable(card->dev);
284 card->options.large_send = type;
285 switch (card->options.large_send) {
286 case QETH_LARGE_SEND_TSO:
287 if (qeth_is_supported(card, IPA_OUTBOUND_TSO)) {
288 card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
289 NETIF_F_HW_CSUM;
290 } else {
291 card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
292 NETIF_F_HW_CSUM);
293 card->options.large_send = QETH_LARGE_SEND_NO;
294 rc = -EOPNOTSUPP;
295 }
296 break;
297 default: /* includes QETH_LARGE_SEND_NO */
298 card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
299 NETIF_F_HW_CSUM);
300 break;
301 }
302 if (card->state == CARD_STATE_UP)
303 netif_wake_queue(card->dev);
304 return rc;
305 }
306 EXPORT_SYMBOL_GPL(qeth_set_large_send);
307
308 static int qeth_issue_next_read(struct qeth_card *card)
309 {
310 int rc;
311 struct qeth_cmd_buffer *iob;
312
313 QETH_DBF_TEXT(TRACE, 5, "issnxrd");
314 if (card->read.state != CH_STATE_UP)
315 return -EIO;
316 iob = qeth_get_buffer(&card->read);
317 if (!iob) {
318 dev_warn(&card->gdev->dev, "The qeth device driver "
319 "failed to recover an error on the device\n");
320 QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob "
321 "available\n", dev_name(&card->gdev->dev));
322 return -ENOMEM;
323 }
324 qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
325 QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
326 rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
327 (addr_t) iob, 0, 0);
328 if (rc) {
329 QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! "
330 "rc=%i\n", dev_name(&card->gdev->dev), rc);
331 atomic_set(&card->read.irq_pending, 0);
332 qeth_schedule_recovery(card);
333 wake_up(&card->wait_q);
334 }
335 return rc;
336 }
337
338 static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
339 {
340 struct qeth_reply *reply;
341
342 reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
343 if (reply) {
344 atomic_set(&reply->refcnt, 1);
345 atomic_set(&reply->received, 0);
346 reply->card = card;
347 };
348 return reply;
349 }
350
351 static void qeth_get_reply(struct qeth_reply *reply)
352 {
353 WARN_ON(atomic_read(&reply->refcnt) <= 0);
354 atomic_inc(&reply->refcnt);
355 }
356
357 static void qeth_put_reply(struct qeth_reply *reply)
358 {
359 WARN_ON(atomic_read(&reply->refcnt) <= 0);
360 if (atomic_dec_and_test(&reply->refcnt))
361 kfree(reply);
362 }
363
364 static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
365 struct qeth_card *card)
366 {
367 char *ipa_name;
368 int com = cmd->hdr.command;
369 ipa_name = qeth_get_ipa_cmd_name(com);
370 if (rc)
371 QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s returned x%X \"%s\"\n",
372 ipa_name, com, QETH_CARD_IFNAME(card),
373 rc, qeth_get_ipa_msg(rc));
374 else
375 QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s succeeded\n",
376 ipa_name, com, QETH_CARD_IFNAME(card));
377 }
378
379 static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
380 struct qeth_cmd_buffer *iob)
381 {
382 struct qeth_ipa_cmd *cmd = NULL;
383
384 QETH_DBF_TEXT(TRACE, 5, "chkipad");
385 if (IS_IPA(iob->data)) {
386 cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
387 if (IS_IPA_REPLY(cmd)) {
388 if (cmd->hdr.command < IPA_CMD_SETCCID ||
389 cmd->hdr.command > IPA_CMD_MODCCID)
390 qeth_issue_ipa_msg(cmd,
391 cmd->hdr.return_code, card);
392 return cmd;
393 } else {
394 switch (cmd->hdr.command) {
395 case IPA_CMD_STOPLAN:
396 dev_warn(&card->gdev->dev,
397 "The link for interface %s on CHPID"
398 " 0x%X failed\n",
399 QETH_CARD_IFNAME(card),
400 card->info.chpid);
401 card->lan_online = 0;
402 if (card->dev && netif_carrier_ok(card->dev))
403 netif_carrier_off(card->dev);
404 return NULL;
405 case IPA_CMD_STARTLAN:
406 dev_info(&card->gdev->dev,
407 "The link for %s on CHPID 0x%X has"
408 " been restored\n",
409 QETH_CARD_IFNAME(card),
410 card->info.chpid);
411 netif_carrier_on(card->dev);
412 card->lan_online = 1;
413 qeth_schedule_recovery(card);
414 return NULL;
415 case IPA_CMD_MODCCID:
416 return cmd;
417 case IPA_CMD_REGISTER_LOCAL_ADDR:
418 QETH_DBF_TEXT(TRACE, 3, "irla");
419 break;
420 case IPA_CMD_UNREGISTER_LOCAL_ADDR:
421 QETH_DBF_TEXT(TRACE, 3, "urla");
422 break;
423 default:
424 QETH_DBF_MESSAGE(2, "Received data is IPA "
425 "but not a reply!\n");
426 break;
427 }
428 }
429 }
430 return cmd;
431 }
432
433 void qeth_clear_ipacmd_list(struct qeth_card *card)
434 {
435 struct qeth_reply *reply, *r;
436 unsigned long flags;
437
438 QETH_DBF_TEXT(TRACE, 4, "clipalst");
439
440 spin_lock_irqsave(&card->lock, flags);
441 list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
442 qeth_get_reply(reply);
443 reply->rc = -EIO;
444 atomic_inc(&reply->received);
445 list_del_init(&reply->list);
446 wake_up(&reply->wait_q);
447 qeth_put_reply(reply);
448 }
449 spin_unlock_irqrestore(&card->lock, flags);
450 }
451 EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
452
453 static int qeth_check_idx_response(unsigned char *buffer)
454 {
455 if (!buffer)
456 return 0;
457
458 QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
459 if ((buffer[2] & 0xc0) == 0xc0) {
460 QETH_DBF_MESSAGE(2, "received an IDX TERMINATE "
461 "with cause code 0x%02x%s\n",
462 buffer[4],
463 ((buffer[4] == 0x22) ?
464 " -- try another portname" : ""));
465 QETH_DBF_TEXT(TRACE, 2, "ckidxres");
466 QETH_DBF_TEXT(TRACE, 2, " idxterm");
467 QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
468 return -EIO;
469 }
470 return 0;
471 }
472
473 static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
474 __u32 len)
475 {
476 struct qeth_card *card;
477
478 QETH_DBF_TEXT(TRACE, 4, "setupccw");
479 card = CARD_FROM_CDEV(channel->ccwdev);
480 if (channel == &card->read)
481 memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
482 else
483 memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
484 channel->ccw.count = len;
485 channel->ccw.cda = (__u32) __pa(iob);
486 }
487
488 static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
489 {
490 __u8 index;
491
492 QETH_DBF_TEXT(TRACE, 6, "getbuff");
493 index = channel->io_buf_no;
494 do {
495 if (channel->iob[index].state == BUF_STATE_FREE) {
496 channel->iob[index].state = BUF_STATE_LOCKED;
497 channel->io_buf_no = (channel->io_buf_no + 1) %
498 QETH_CMD_BUFFER_NO;
499 memset(channel->iob[index].data, 0, QETH_BUFSIZE);
500 return channel->iob + index;
501 }
502 index = (index + 1) % QETH_CMD_BUFFER_NO;
503 } while (index != channel->io_buf_no);
504
505 return NULL;
506 }
507
508 void qeth_release_buffer(struct qeth_channel *channel,
509 struct qeth_cmd_buffer *iob)
510 {
511 unsigned long flags;
512
513 QETH_DBF_TEXT(TRACE, 6, "relbuff");
514 spin_lock_irqsave(&channel->iob_lock, flags);
515 memset(iob->data, 0, QETH_BUFSIZE);
516 iob->state = BUF_STATE_FREE;
517 iob->callback = qeth_send_control_data_cb;
518 iob->rc = 0;
519 spin_unlock_irqrestore(&channel->iob_lock, flags);
520 }
521 EXPORT_SYMBOL_GPL(qeth_release_buffer);
522
523 static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
524 {
525 struct qeth_cmd_buffer *buffer = NULL;
526 unsigned long flags;
527
528 spin_lock_irqsave(&channel->iob_lock, flags);
529 buffer = __qeth_get_buffer(channel);
530 spin_unlock_irqrestore(&channel->iob_lock, flags);
531 return buffer;
532 }
533
534 struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
535 {
536 struct qeth_cmd_buffer *buffer;
537 wait_event(channel->wait_q,
538 ((buffer = qeth_get_buffer(channel)) != NULL));
539 return buffer;
540 }
541 EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
542
543 void qeth_clear_cmd_buffers(struct qeth_channel *channel)
544 {
545 int cnt;
546
547 for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
548 qeth_release_buffer(channel, &channel->iob[cnt]);
549 channel->buf_no = 0;
550 channel->io_buf_no = 0;
551 }
552 EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
553
554 static void qeth_send_control_data_cb(struct qeth_channel *channel,
555 struct qeth_cmd_buffer *iob)
556 {
557 struct qeth_card *card;
558 struct qeth_reply *reply, *r;
559 struct qeth_ipa_cmd *cmd;
560 unsigned long flags;
561 int keep_reply;
562
563 QETH_DBF_TEXT(TRACE, 4, "sndctlcb");
564
565 card = CARD_FROM_CDEV(channel->ccwdev);
566 if (qeth_check_idx_response(iob->data)) {
567 qeth_clear_ipacmd_list(card);
568 if (((iob->data[2] & 0xc0) == 0xc0) && iob->data[4] == 0xf6)
569 dev_err(&card->gdev->dev,
570 "The qeth device is not configured "
571 "for the OSI layer required by z/VM\n");
572 qeth_schedule_recovery(card);
573 goto out;
574 }
575
576 cmd = qeth_check_ipa_data(card, iob);
577 if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
578 goto out;
579 /*in case of OSN : check if cmd is set */
580 if (card->info.type == QETH_CARD_TYPE_OSN &&
581 cmd &&
582 cmd->hdr.command != IPA_CMD_STARTLAN &&
583 card->osn_info.assist_cb != NULL) {
584 card->osn_info.assist_cb(card->dev, cmd);
585 goto out;
586 }
587
588 spin_lock_irqsave(&card->lock, flags);
589 list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
590 if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
591 ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
592 qeth_get_reply(reply);
593 list_del_init(&reply->list);
594 spin_unlock_irqrestore(&card->lock, flags);
595 keep_reply = 0;
596 if (reply->callback != NULL) {
597 if (cmd) {
598 reply->offset = (__u16)((char *)cmd -
599 (char *)iob->data);
600 keep_reply = reply->callback(card,
601 reply,
602 (unsigned long)cmd);
603 } else
604 keep_reply = reply->callback(card,
605 reply,
606 (unsigned long)iob);
607 }
608 if (cmd)
609 reply->rc = (u16) cmd->hdr.return_code;
610 else if (iob->rc)
611 reply->rc = iob->rc;
612 if (keep_reply) {
613 spin_lock_irqsave(&card->lock, flags);
614 list_add_tail(&reply->list,
615 &card->cmd_waiter_list);
616 spin_unlock_irqrestore(&card->lock, flags);
617 } else {
618 atomic_inc(&reply->received);
619 wake_up(&reply->wait_q);
620 }
621 qeth_put_reply(reply);
622 goto out;
623 }
624 }
625 spin_unlock_irqrestore(&card->lock, flags);
626 out:
627 memcpy(&card->seqno.pdu_hdr_ack,
628 QETH_PDU_HEADER_SEQ_NO(iob->data),
629 QETH_SEQ_NO_LENGTH);
630 qeth_release_buffer(channel, iob);
631 }
632
633 static int qeth_setup_channel(struct qeth_channel *channel)
634 {
635 int cnt;
636
637 QETH_DBF_TEXT(SETUP, 2, "setupch");
638 for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
639 channel->iob[cnt].data = (char *)
640 kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
641 if (channel->iob[cnt].data == NULL)
642 break;
643 channel->iob[cnt].state = BUF_STATE_FREE;
644 channel->iob[cnt].channel = channel;
645 channel->iob[cnt].callback = qeth_send_control_data_cb;
646 channel->iob[cnt].rc = 0;
647 }
648 if (cnt < QETH_CMD_BUFFER_NO) {
649 while (cnt-- > 0)
650 kfree(channel->iob[cnt].data);
651 return -ENOMEM;
652 }
653 channel->buf_no = 0;
654 channel->io_buf_no = 0;
655 atomic_set(&channel->irq_pending, 0);
656 spin_lock_init(&channel->iob_lock);
657
658 init_waitqueue_head(&channel->wait_q);
659 return 0;
660 }
661
662 static int qeth_set_thread_start_bit(struct qeth_card *card,
663 unsigned long thread)
664 {
665 unsigned long flags;
666
667 spin_lock_irqsave(&card->thread_mask_lock, flags);
668 if (!(card->thread_allowed_mask & thread) ||
669 (card->thread_start_mask & thread)) {
670 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
671 return -EPERM;
672 }
673 card->thread_start_mask |= thread;
674 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
675 return 0;
676 }
677
678 void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
679 {
680 unsigned long flags;
681
682 spin_lock_irqsave(&card->thread_mask_lock, flags);
683 card->thread_start_mask &= ~thread;
684 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
685 wake_up(&card->wait_q);
686 }
687 EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
688
689 void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
690 {
691 unsigned long flags;
692
693 spin_lock_irqsave(&card->thread_mask_lock, flags);
694 card->thread_running_mask &= ~thread;
695 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
696 wake_up(&card->wait_q);
697 }
698 EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
699
700 static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
701 {
702 unsigned long flags;
703 int rc = 0;
704
705 spin_lock_irqsave(&card->thread_mask_lock, flags);
706 if (card->thread_start_mask & thread) {
707 if ((card->thread_allowed_mask & thread) &&
708 !(card->thread_running_mask & thread)) {
709 rc = 1;
710 card->thread_start_mask &= ~thread;
711 card->thread_running_mask |= thread;
712 } else
713 rc = -EPERM;
714 }
715 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
716 return rc;
717 }
718
719 int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
720 {
721 int rc = 0;
722
723 wait_event(card->wait_q,
724 (rc = __qeth_do_run_thread(card, thread)) >= 0);
725 return rc;
726 }
727 EXPORT_SYMBOL_GPL(qeth_do_run_thread);
728
729 void qeth_schedule_recovery(struct qeth_card *card)
730 {
731 QETH_DBF_TEXT(TRACE, 2, "startrec");
732 if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
733 schedule_work(&card->kernel_thread_starter);
734 }
735 EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
736
737 static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
738 {
739 int dstat, cstat;
740 char *sense;
741
742 sense = (char *) irb->ecw;
743 cstat = irb->scsw.cmd.cstat;
744 dstat = irb->scsw.cmd.dstat;
745
746 if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
747 SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
748 SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
749 QETH_DBF_TEXT(TRACE, 2, "CGENCHK");
750 dev_warn(&cdev->dev, "The qeth device driver "
751 "failed to recover an error on the device\n");
752 QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x ",
753 dev_name(&cdev->dev), dstat, cstat);
754 print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
755 16, 1, irb, 64, 1);
756 return 1;
757 }
758
759 if (dstat & DEV_STAT_UNIT_CHECK) {
760 if (sense[SENSE_RESETTING_EVENT_BYTE] &
761 SENSE_RESETTING_EVENT_FLAG) {
762 QETH_DBF_TEXT(TRACE, 2, "REVIND");
763 return 1;
764 }
765 if (sense[SENSE_COMMAND_REJECT_BYTE] &
766 SENSE_COMMAND_REJECT_FLAG) {
767 QETH_DBF_TEXT(TRACE, 2, "CMDREJi");
768 return 1;
769 }
770 if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
771 QETH_DBF_TEXT(TRACE, 2, "AFFE");
772 return 1;
773 }
774 if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
775 QETH_DBF_TEXT(TRACE, 2, "ZEROSEN");
776 return 0;
777 }
778 QETH_DBF_TEXT(TRACE, 2, "DGENCHK");
779 return 1;
780 }
781 return 0;
782 }
783
784 static long __qeth_check_irb_error(struct ccw_device *cdev,
785 unsigned long intparm, struct irb *irb)
786 {
787 if (!IS_ERR(irb))
788 return 0;
789
790 switch (PTR_ERR(irb)) {
791 case -EIO:
792 QETH_DBF_MESSAGE(2, "%s i/o-error on device\n",
793 dev_name(&cdev->dev));
794 QETH_DBF_TEXT(TRACE, 2, "ckirberr");
795 QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
796 break;
797 case -ETIMEDOUT:
798 dev_warn(&cdev->dev, "A hardware operation timed out"
799 " on the device\n");
800 QETH_DBF_TEXT(TRACE, 2, "ckirberr");
801 QETH_DBF_TEXT_(TRACE, 2, " rc%d", -ETIMEDOUT);
802 if (intparm == QETH_RCD_PARM) {
803 struct qeth_card *card = CARD_FROM_CDEV(cdev);
804
805 if (card && (card->data.ccwdev == cdev)) {
806 card->data.state = CH_STATE_DOWN;
807 wake_up(&card->wait_q);
808 }
809 }
810 break;
811 default:
812 QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n",
813 dev_name(&cdev->dev), PTR_ERR(irb));
814 QETH_DBF_TEXT(TRACE, 2, "ckirberr");
815 QETH_DBF_TEXT(TRACE, 2, " rc???");
816 }
817 return PTR_ERR(irb);
818 }
819
820 static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
821 struct irb *irb)
822 {
823 int rc;
824 int cstat, dstat;
825 struct qeth_cmd_buffer *buffer;
826 struct qeth_channel *channel;
827 struct qeth_card *card;
828 struct qeth_cmd_buffer *iob;
829 __u8 index;
830
831 QETH_DBF_TEXT(TRACE, 5, "irq");
832
833 if (__qeth_check_irb_error(cdev, intparm, irb))
834 return;
835 cstat = irb->scsw.cmd.cstat;
836 dstat = irb->scsw.cmd.dstat;
837
838 card = CARD_FROM_CDEV(cdev);
839 if (!card)
840 return;
841
842 if (card->read.ccwdev == cdev) {
843 channel = &card->read;
844 QETH_DBF_TEXT(TRACE, 5, "read");
845 } else if (card->write.ccwdev == cdev) {
846 channel = &card->write;
847 QETH_DBF_TEXT(TRACE, 5, "write");
848 } else {
849 channel = &card->data;
850 QETH_DBF_TEXT(TRACE, 5, "data");
851 }
852 atomic_set(&channel->irq_pending, 0);
853
854 if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
855 channel->state = CH_STATE_STOPPED;
856
857 if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
858 channel->state = CH_STATE_HALTED;
859
860 /*let's wake up immediately on data channel*/
861 if ((channel == &card->data) && (intparm != 0) &&
862 (intparm != QETH_RCD_PARM))
863 goto out;
864
865 if (intparm == QETH_CLEAR_CHANNEL_PARM) {
866 QETH_DBF_TEXT(TRACE, 6, "clrchpar");
867 /* we don't have to handle this further */
868 intparm = 0;
869 }
870 if (intparm == QETH_HALT_CHANNEL_PARM) {
871 QETH_DBF_TEXT(TRACE, 6, "hltchpar");
872 /* we don't have to handle this further */
873 intparm = 0;
874 }
875 if ((dstat & DEV_STAT_UNIT_EXCEP) ||
876 (dstat & DEV_STAT_UNIT_CHECK) ||
877 (cstat)) {
878 if (irb->esw.esw0.erw.cons) {
879 dev_warn(&channel->ccwdev->dev,
880 "The qeth device driver failed to recover "
881 "an error on the device\n");
882 QETH_DBF_MESSAGE(2, "%s sense data available. cstat "
883 "0x%X dstat 0x%X\n",
884 dev_name(&channel->ccwdev->dev), cstat, dstat);
885 print_hex_dump(KERN_WARNING, "qeth: irb ",
886 DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
887 print_hex_dump(KERN_WARNING, "qeth: sense data ",
888 DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
889 }
890 if (intparm == QETH_RCD_PARM) {
891 channel->state = CH_STATE_DOWN;
892 goto out;
893 }
894 rc = qeth_get_problem(cdev, irb);
895 if (rc) {
896 qeth_clear_ipacmd_list(card);
897 qeth_schedule_recovery(card);
898 goto out;
899 }
900 }
901
902 if (intparm == QETH_RCD_PARM) {
903 channel->state = CH_STATE_RCD_DONE;
904 goto out;
905 }
906 if (intparm) {
907 buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
908 buffer->state = BUF_STATE_PROCESSED;
909 }
910 if (channel == &card->data)
911 return;
912 if (channel == &card->read &&
913 channel->state == CH_STATE_UP)
914 qeth_issue_next_read(card);
915
916 iob = channel->iob;
917 index = channel->buf_no;
918 while (iob[index].state == BUF_STATE_PROCESSED) {
919 if (iob[index].callback != NULL)
920 iob[index].callback(channel, iob + index);
921
922 index = (index + 1) % QETH_CMD_BUFFER_NO;
923 }
924 channel->buf_no = index;
925 out:
926 wake_up(&card->wait_q);
927 return;
928 }
929
930 static void __qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
931 struct qeth_qdio_out_buffer *buf, unsigned int qeth_skip_skb)
932 {
933 int i;
934 struct sk_buff *skb;
935
936 /* is PCI flag set on buffer? */
937 if (buf->buffer->element[0].flags & 0x40)
938 atomic_dec(&queue->set_pci_flags_count);
939
940 if (!qeth_skip_skb) {
941 skb = skb_dequeue(&buf->skb_list);
942 while (skb) {
943 atomic_dec(&skb->users);
944 dev_kfree_skb_any(skb);
945 skb = skb_dequeue(&buf->skb_list);
946 }
947 }
948 for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
949 if (buf->buffer->element[i].addr && buf->is_header[i])
950 kmem_cache_free(qeth_core_header_cache,
951 buf->buffer->element[i].addr);
952 buf->is_header[i] = 0;
953 buf->buffer->element[i].length = 0;
954 buf->buffer->element[i].addr = NULL;
955 buf->buffer->element[i].flags = 0;
956 }
957 buf->buffer->element[15].flags = 0;
958 buf->next_element_to_fill = 0;
959 atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
960 }
961
962 static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
963 struct qeth_qdio_out_buffer *buf)
964 {
965 __qeth_clear_output_buffer(queue, buf, 0);
966 }
967
968 void qeth_clear_qdio_buffers(struct qeth_card *card)
969 {
970 int i, j;
971
972 QETH_DBF_TEXT(TRACE, 2, "clearqdbf");
973 /* clear outbound buffers to free skbs */
974 for (i = 0; i < card->qdio.no_out_queues; ++i)
975 if (card->qdio.out_qs[i]) {
976 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
977 qeth_clear_output_buffer(card->qdio.out_qs[i],
978 &card->qdio.out_qs[i]->bufs[j]);
979 }
980 }
981 EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
982
983 static void qeth_free_buffer_pool(struct qeth_card *card)
984 {
985 struct qeth_buffer_pool_entry *pool_entry, *tmp;
986 int i = 0;
987 QETH_DBF_TEXT(TRACE, 5, "freepool");
988 list_for_each_entry_safe(pool_entry, tmp,
989 &card->qdio.init_pool.entry_list, init_list){
990 for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
991 free_page((unsigned long)pool_entry->elements[i]);
992 list_del(&pool_entry->init_list);
993 kfree(pool_entry);
994 }
995 }
996
997 static void qeth_free_qdio_buffers(struct qeth_card *card)
998 {
999 int i, j;
1000
1001 QETH_DBF_TEXT(TRACE, 2, "freeqdbf");
1002 if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
1003 QETH_QDIO_UNINITIALIZED)
1004 return;
1005 kfree(card->qdio.in_q);
1006 card->qdio.in_q = NULL;
1007 /* inbound buffer pool */
1008 qeth_free_buffer_pool(card);
1009 /* free outbound qdio_qs */
1010 if (card->qdio.out_qs) {
1011 for (i = 0; i < card->qdio.no_out_queues; ++i) {
1012 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
1013 qeth_clear_output_buffer(card->qdio.out_qs[i],
1014 &card->qdio.out_qs[i]->bufs[j]);
1015 kfree(card->qdio.out_qs[i]);
1016 }
1017 kfree(card->qdio.out_qs);
1018 card->qdio.out_qs = NULL;
1019 }
1020 }
1021
1022 static void qeth_clean_channel(struct qeth_channel *channel)
1023 {
1024 int cnt;
1025
1026 QETH_DBF_TEXT(SETUP, 2, "freech");
1027 for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
1028 kfree(channel->iob[cnt].data);
1029 }
1030
1031 static int qeth_is_1920_device(struct qeth_card *card)
1032 {
1033 int single_queue = 0;
1034 struct ccw_device *ccwdev;
1035 struct channelPath_dsc {
1036 u8 flags;
1037 u8 lsn;
1038 u8 desc;
1039 u8 chpid;
1040 u8 swla;
1041 u8 zeroes;
1042 u8 chla;
1043 u8 chpp;
1044 } *chp_dsc;
1045
1046 QETH_DBF_TEXT(SETUP, 2, "chk_1920");
1047
1048 ccwdev = card->data.ccwdev;
1049 chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
1050 if (chp_dsc != NULL) {
1051 /* CHPP field bit 6 == 1 -> single queue */
1052 single_queue = ((chp_dsc->chpp & 0x02) == 0x02);
1053 kfree(chp_dsc);
1054 }
1055 QETH_DBF_TEXT_(SETUP, 2, "rc:%x", single_queue);
1056 return single_queue;
1057 }
1058
1059 static void qeth_init_qdio_info(struct qeth_card *card)
1060 {
1061 QETH_DBF_TEXT(SETUP, 4, "intqdinf");
1062 atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
1063 /* inbound */
1064 card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
1065 card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
1066 card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
1067 INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
1068 INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
1069 }
1070
1071 static void qeth_set_intial_options(struct qeth_card *card)
1072 {
1073 card->options.route4.type = NO_ROUTER;
1074 card->options.route6.type = NO_ROUTER;
1075 card->options.checksum_type = QETH_CHECKSUM_DEFAULT;
1076 card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
1077 card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
1078 card->options.fake_broadcast = 0;
1079 card->options.add_hhlen = DEFAULT_ADD_HHLEN;
1080 card->options.performance_stats = 0;
1081 card->options.rx_sg_cb = QETH_RX_SG_CB;
1082 }
1083
1084 static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
1085 {
1086 unsigned long flags;
1087 int rc = 0;
1088
1089 spin_lock_irqsave(&card->thread_mask_lock, flags);
1090 QETH_DBF_TEXT_(TRACE, 4, " %02x%02x%02x",
1091 (u8) card->thread_start_mask,
1092 (u8) card->thread_allowed_mask,
1093 (u8) card->thread_running_mask);
1094 rc = (card->thread_start_mask & thread);
1095 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
1096 return rc;
1097 }
1098
1099 static void qeth_start_kernel_thread(struct work_struct *work)
1100 {
1101 struct qeth_card *card = container_of(work, struct qeth_card,
1102 kernel_thread_starter);
1103 QETH_DBF_TEXT(TRACE , 2, "strthrd");
1104
1105 if (card->read.state != CH_STATE_UP &&
1106 card->write.state != CH_STATE_UP)
1107 return;
1108 if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
1109 kthread_run(card->discipline.recover, (void *) card,
1110 "qeth_recover");
1111 }
1112
1113 static int qeth_setup_card(struct qeth_card *card)
1114 {
1115
1116 QETH_DBF_TEXT(SETUP, 2, "setupcrd");
1117 QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
1118
1119 card->read.state = CH_STATE_DOWN;
1120 card->write.state = CH_STATE_DOWN;
1121 card->data.state = CH_STATE_DOWN;
1122 card->state = CARD_STATE_DOWN;
1123 card->lan_online = 0;
1124 card->use_hard_stop = 0;
1125 card->dev = NULL;
1126 spin_lock_init(&card->vlanlock);
1127 spin_lock_init(&card->mclock);
1128 card->vlangrp = NULL;
1129 spin_lock_init(&card->lock);
1130 spin_lock_init(&card->ip_lock);
1131 spin_lock_init(&card->thread_mask_lock);
1132 card->thread_start_mask = 0;
1133 card->thread_allowed_mask = 0;
1134 card->thread_running_mask = 0;
1135 INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
1136 INIT_LIST_HEAD(&card->ip_list);
1137 card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
1138 if (!card->ip_tbd_list) {
1139 QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
1140 return -ENOMEM;
1141 }
1142 INIT_LIST_HEAD(card->ip_tbd_list);
1143 INIT_LIST_HEAD(&card->cmd_waiter_list);
1144 init_waitqueue_head(&card->wait_q);
1145 /* intial options */
1146 qeth_set_intial_options(card);
1147 /* IP address takeover */
1148 INIT_LIST_HEAD(&card->ipato.entries);
1149 card->ipato.enabled = 0;
1150 card->ipato.invert4 = 0;
1151 card->ipato.invert6 = 0;
1152 if (card->info.type == QETH_CARD_TYPE_IQD)
1153 card->options.checksum_type = NO_CHECKSUMMING;
1154 /* init QDIO stuff */
1155 qeth_init_qdio_info(card);
1156 return 0;
1157 }
1158
1159 static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
1160 {
1161 struct qeth_card *card = container_of(slr, struct qeth_card,
1162 qeth_service_level);
1163 if (card->info.mcl_level[0])
1164 seq_printf(m, "qeth: %s firmware level %s\n",
1165 CARD_BUS_ID(card), card->info.mcl_level);
1166 }
1167
1168 static struct qeth_card *qeth_alloc_card(void)
1169 {
1170 struct qeth_card *card;
1171
1172 QETH_DBF_TEXT(SETUP, 2, "alloccrd");
1173 card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
1174 if (!card)
1175 return NULL;
1176 QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
1177 if (qeth_setup_channel(&card->read)) {
1178 kfree(card);
1179 return NULL;
1180 }
1181 if (qeth_setup_channel(&card->write)) {
1182 qeth_clean_channel(&card->read);
1183 kfree(card);
1184 return NULL;
1185 }
1186 card->options.layer2 = -1;
1187 card->qeth_service_level.seq_print = qeth_core_sl_print;
1188 register_service_level(&card->qeth_service_level);
1189 return card;
1190 }
1191
1192 static int qeth_determine_card_type(struct qeth_card *card)
1193 {
1194 int i = 0;
1195
1196 QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
1197
1198 card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
1199 card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
1200 while (known_devices[i][4]) {
1201 if ((CARD_RDEV(card)->id.dev_type == known_devices[i][2]) &&
1202 (CARD_RDEV(card)->id.dev_model == known_devices[i][3])) {
1203 card->info.type = known_devices[i][4];
1204 card->qdio.no_out_queues = known_devices[i][8];
1205 card->info.is_multicast_different = known_devices[i][9];
1206 if (qeth_is_1920_device(card)) {
1207 dev_info(&card->gdev->dev,
1208 "Priority Queueing not supported\n");
1209 card->qdio.no_out_queues = 1;
1210 card->qdio.default_out_queue = 0;
1211 }
1212 return 0;
1213 }
1214 i++;
1215 }
1216 card->info.type = QETH_CARD_TYPE_UNKNOWN;
1217 dev_err(&card->gdev->dev, "The adapter hardware is of an "
1218 "unknown type\n");
1219 return -ENOENT;
1220 }
1221
1222 static int qeth_clear_channel(struct qeth_channel *channel)
1223 {
1224 unsigned long flags;
1225 struct qeth_card *card;
1226 int rc;
1227
1228 QETH_DBF_TEXT(TRACE, 3, "clearch");
1229 card = CARD_FROM_CDEV(channel->ccwdev);
1230 spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
1231 rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
1232 spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
1233
1234 if (rc)
1235 return rc;
1236 rc = wait_event_interruptible_timeout(card->wait_q,
1237 channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
1238 if (rc == -ERESTARTSYS)
1239 return rc;
1240 if (channel->state != CH_STATE_STOPPED)
1241 return -ETIME;
1242 channel->state = CH_STATE_DOWN;
1243 return 0;
1244 }
1245
1246 static int qeth_halt_channel(struct qeth_channel *channel)
1247 {
1248 unsigned long flags;
1249 struct qeth_card *card;
1250 int rc;
1251
1252 QETH_DBF_TEXT(TRACE, 3, "haltch");
1253 card = CARD_FROM_CDEV(channel->ccwdev);
1254 spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
1255 rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
1256 spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
1257
1258 if (rc)
1259 return rc;
1260 rc = wait_event_interruptible_timeout(card->wait_q,
1261 channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
1262 if (rc == -ERESTARTSYS)
1263 return rc;
1264 if (channel->state != CH_STATE_HALTED)
1265 return -ETIME;
1266 return 0;
1267 }
1268
1269 static int qeth_halt_channels(struct qeth_card *card)
1270 {
1271 int rc1 = 0, rc2 = 0, rc3 = 0;
1272
1273 QETH_DBF_TEXT(TRACE, 3, "haltchs");
1274 rc1 = qeth_halt_channel(&card->read);
1275 rc2 = qeth_halt_channel(&card->write);
1276 rc3 = qeth_halt_channel(&card->data);
1277 if (rc1)
1278 return rc1;
1279 if (rc2)
1280 return rc2;
1281 return rc3;
1282 }
1283
1284 static int qeth_clear_channels(struct qeth_card *card)
1285 {
1286 int rc1 = 0, rc2 = 0, rc3 = 0;
1287
1288 QETH_DBF_TEXT(TRACE, 3, "clearchs");
1289 rc1 = qeth_clear_channel(&card->read);
1290 rc2 = qeth_clear_channel(&card->write);
1291 rc3 = qeth_clear_channel(&card->data);
1292 if (rc1)
1293 return rc1;
1294 if (rc2)
1295 return rc2;
1296 return rc3;
1297 }
1298
1299 static int qeth_clear_halt_card(struct qeth_card *card, int halt)
1300 {
1301 int rc = 0;
1302
1303 QETH_DBF_TEXT(TRACE, 3, "clhacrd");
1304 QETH_DBF_HEX(TRACE, 3, &card, sizeof(void *));
1305
1306 if (halt)
1307 rc = qeth_halt_channels(card);
1308 if (rc)
1309 return rc;
1310 return qeth_clear_channels(card);
1311 }
1312
1313 int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
1314 {
1315 int rc = 0;
1316
1317 QETH_DBF_TEXT(TRACE, 3, "qdioclr");
1318 switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
1319 QETH_QDIO_CLEANING)) {
1320 case QETH_QDIO_ESTABLISHED:
1321 if (card->info.type == QETH_CARD_TYPE_IQD)
1322 rc = qdio_cleanup(CARD_DDEV(card),
1323 QDIO_FLAG_CLEANUP_USING_HALT);
1324 else
1325 rc = qdio_cleanup(CARD_DDEV(card),
1326 QDIO_FLAG_CLEANUP_USING_CLEAR);
1327 if (rc)
1328 QETH_DBF_TEXT_(TRACE, 3, "1err%d", rc);
1329 atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
1330 break;
1331 case QETH_QDIO_CLEANING:
1332 return rc;
1333 default:
1334 break;
1335 }
1336 rc = qeth_clear_halt_card(card, use_halt);
1337 if (rc)
1338 QETH_DBF_TEXT_(TRACE, 3, "2err%d", rc);
1339 card->state = CARD_STATE_DOWN;
1340 return rc;
1341 }
1342 EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
1343
1344 static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
1345 int *length)
1346 {
1347 struct ciw *ciw;
1348 char *rcd_buf;
1349 int ret;
1350 struct qeth_channel *channel = &card->data;
1351 unsigned long flags;
1352
1353 /*
1354 * scan for RCD command in extended SenseID data
1355 */
1356 ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
1357 if (!ciw || ciw->cmd == 0)
1358 return -EOPNOTSUPP;
1359 rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
1360 if (!rcd_buf)
1361 return -ENOMEM;
1362
1363 channel->ccw.cmd_code = ciw->cmd;
1364 channel->ccw.cda = (__u32) __pa(rcd_buf);
1365 channel->ccw.count = ciw->count;
1366 channel->ccw.flags = CCW_FLAG_SLI;
1367 channel->state = CH_STATE_RCD;
1368 spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
1369 ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
1370 QETH_RCD_PARM, LPM_ANYPATH, 0,
1371 QETH_RCD_TIMEOUT);
1372 spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
1373 if (!ret)
1374 wait_event(card->wait_q,
1375 (channel->state == CH_STATE_RCD_DONE ||
1376 channel->state == CH_STATE_DOWN));
1377 if (channel->state == CH_STATE_DOWN)
1378 ret = -EIO;
1379 else
1380 channel->state = CH_STATE_DOWN;
1381 if (ret) {
1382 kfree(rcd_buf);
1383 *buffer = NULL;
1384 *length = 0;
1385 } else {
1386 *length = ciw->count;
1387 *buffer = rcd_buf;
1388 }
1389 return ret;
1390 }
1391
1392 static int qeth_get_unitaddr(struct qeth_card *card)
1393 {
1394 int length;
1395 char *prcd;
1396 int rc;
1397
1398 QETH_DBF_TEXT(SETUP, 2, "getunit");
1399 rc = qeth_read_conf_data(card, (void **) &prcd, &length);
1400 if (rc) {
1401 QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n",
1402 dev_name(&card->gdev->dev), rc);
1403 return rc;
1404 }
1405 card->info.chpid = prcd[30];
1406 card->info.unit_addr2 = prcd[31];
1407 card->info.cula = prcd[63];
1408 card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
1409 (prcd[0x11] == _ascebc['M']));
1410 kfree(prcd);
1411 return 0;
1412 }
1413
1414 static void qeth_init_tokens(struct qeth_card *card)
1415 {
1416 card->token.issuer_rm_w = 0x00010103UL;
1417 card->token.cm_filter_w = 0x00010108UL;
1418 card->token.cm_connection_w = 0x0001010aUL;
1419 card->token.ulp_filter_w = 0x0001010bUL;
1420 card->token.ulp_connection_w = 0x0001010dUL;
1421 }
1422
1423 static void qeth_init_func_level(struct qeth_card *card)
1424 {
1425 if (card->ipato.enabled) {
1426 if (card->info.type == QETH_CARD_TYPE_IQD)
1427 card->info.func_level =
1428 QETH_IDX_FUNC_LEVEL_IQD_ENA_IPAT;
1429 else
1430 card->info.func_level =
1431 QETH_IDX_FUNC_LEVEL_OSAE_ENA_IPAT;
1432 } else {
1433 if (card->info.type == QETH_CARD_TYPE_IQD)
1434 /*FIXME:why do we have same values for dis and ena for
1435 osae??? */
1436 card->info.func_level =
1437 QETH_IDX_FUNC_LEVEL_IQD_DIS_IPAT;
1438 else
1439 card->info.func_level =
1440 QETH_IDX_FUNC_LEVEL_OSAE_DIS_IPAT;
1441 }
1442 }
1443
1444 static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
1445 void (*idx_reply_cb)(struct qeth_channel *,
1446 struct qeth_cmd_buffer *))
1447 {
1448 struct qeth_cmd_buffer *iob;
1449 unsigned long flags;
1450 int rc;
1451 struct qeth_card *card;
1452
1453 QETH_DBF_TEXT(SETUP, 2, "idxanswr");
1454 card = CARD_FROM_CDEV(channel->ccwdev);
1455 iob = qeth_get_buffer(channel);
1456 iob->callback = idx_reply_cb;
1457 memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
1458 channel->ccw.count = QETH_BUFSIZE;
1459 channel->ccw.cda = (__u32) __pa(iob->data);
1460
1461 wait_event(card->wait_q,
1462 atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
1463 QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
1464 spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
1465 rc = ccw_device_start(channel->ccwdev,
1466 &channel->ccw, (addr_t) iob, 0, 0);
1467 spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
1468
1469 if (rc) {
1470 QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
1471 QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
1472 atomic_set(&channel->irq_pending, 0);
1473 wake_up(&card->wait_q);
1474 return rc;
1475 }
1476 rc = wait_event_interruptible_timeout(card->wait_q,
1477 channel->state == CH_STATE_UP, QETH_TIMEOUT);
1478 if (rc == -ERESTARTSYS)
1479 return rc;
1480 if (channel->state != CH_STATE_UP) {
1481 rc = -ETIME;
1482 QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
1483 qeth_clear_cmd_buffers(channel);
1484 } else
1485 rc = 0;
1486 return rc;
1487 }
1488
1489 static int qeth_idx_activate_channel(struct qeth_channel *channel,
1490 void (*idx_reply_cb)(struct qeth_channel *,
1491 struct qeth_cmd_buffer *))
1492 {
1493 struct qeth_card *card;
1494 struct qeth_cmd_buffer *iob;
1495 unsigned long flags;
1496 __u16 temp;
1497 __u8 tmp;
1498 int rc;
1499 struct ccw_dev_id temp_devid;
1500
1501 card = CARD_FROM_CDEV(channel->ccwdev);
1502
1503 QETH_DBF_TEXT(SETUP, 2, "idxactch");
1504
1505 iob = qeth_get_buffer(channel);
1506 iob->callback = idx_reply_cb;
1507 memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
1508 channel->ccw.count = IDX_ACTIVATE_SIZE;
1509 channel->ccw.cda = (__u32) __pa(iob->data);
1510 if (channel == &card->write) {
1511 memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
1512 memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
1513 &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
1514 card->seqno.trans_hdr++;
1515 } else {
1516 memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
1517 memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
1518 &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
1519 }
1520 tmp = ((__u8)card->info.portno) | 0x80;
1521 memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
1522 memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
1523 &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
1524 memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
1525 &card->info.func_level, sizeof(__u16));
1526 ccw_device_get_id(CARD_DDEV(card), &temp_devid);
1527 memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
1528 temp = (card->info.cula << 8) + card->info.unit_addr2;
1529 memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
1530
1531 wait_event(card->wait_q,
1532 atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
1533 QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
1534 spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
1535 rc = ccw_device_start(channel->ccwdev,
1536 &channel->ccw, (addr_t) iob, 0, 0);
1537 spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
1538
1539 if (rc) {
1540 QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
1541 rc);
1542 QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
1543 atomic_set(&channel->irq_pending, 0);
1544 wake_up(&card->wait_q);
1545 return rc;
1546 }
1547 rc = wait_event_interruptible_timeout(card->wait_q,
1548 channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
1549 if (rc == -ERESTARTSYS)
1550 return rc;
1551 if (channel->state != CH_STATE_ACTIVATING) {
1552 dev_warn(&channel->ccwdev->dev, "The qeth device driver"
1553 " failed to recover an error on the device\n");
1554 QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n",
1555 dev_name(&channel->ccwdev->dev));
1556 QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
1557 qeth_clear_cmd_buffers(channel);
1558 return -ETIME;
1559 }
1560 return qeth_idx_activate_get_answer(channel, idx_reply_cb);
1561 }
1562
1563 static int qeth_peer_func_level(int level)
1564 {
1565 if ((level & 0xff) == 8)
1566 return (level & 0xff) + 0x400;
1567 if (((level >> 8) & 3) == 1)
1568 return (level & 0xff) + 0x200;
1569 return level;
1570 }
1571
1572 static void qeth_idx_write_cb(struct qeth_channel *channel,
1573 struct qeth_cmd_buffer *iob)
1574 {
1575 struct qeth_card *card;
1576 __u16 temp;
1577
1578 QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
1579
1580 if (channel->state == CH_STATE_DOWN) {
1581 channel->state = CH_STATE_ACTIVATING;
1582 goto out;
1583 }
1584 card = CARD_FROM_CDEV(channel->ccwdev);
1585
1586 if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
1587 if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
1588 dev_err(&card->write.ccwdev->dev,
1589 "The adapter is used exclusively by another "
1590 "host\n");
1591 else
1592 QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:"
1593 " negative reply\n",
1594 dev_name(&card->write.ccwdev->dev));
1595 goto out;
1596 }
1597 memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
1598 if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
1599 QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: "
1600 "function level mismatch (sent: 0x%x, received: "
1601 "0x%x)\n", dev_name(&card->write.ccwdev->dev),
1602 card->info.func_level, temp);
1603 goto out;
1604 }
1605 channel->state = CH_STATE_UP;
1606 out:
1607 qeth_release_buffer(channel, iob);
1608 }
1609
1610 static void qeth_idx_read_cb(struct qeth_channel *channel,
1611 struct qeth_cmd_buffer *iob)
1612 {
1613 struct qeth_card *card;
1614 __u16 temp;
1615
1616 QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
1617 if (channel->state == CH_STATE_DOWN) {
1618 channel->state = CH_STATE_ACTIVATING;
1619 goto out;
1620 }
1621
1622 card = CARD_FROM_CDEV(channel->ccwdev);
1623 if (qeth_check_idx_response(iob->data))
1624 goto out;
1625
1626 if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
1627 if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
1628 dev_err(&card->write.ccwdev->dev,
1629 "The adapter is used exclusively by another "
1630 "host\n");
1631 else
1632 QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:"
1633 " negative reply\n",
1634 dev_name(&card->read.ccwdev->dev));
1635 goto out;
1636 }
1637
1638 /**
1639 * temporary fix for microcode bug
1640 * to revert it,replace OR by AND
1641 */
1642 if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
1643 (card->info.type == QETH_CARD_TYPE_OSAE))
1644 card->info.portname_required = 1;
1645
1646 memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
1647 if (temp != qeth_peer_func_level(card->info.func_level)) {
1648 QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function "
1649 "level mismatch (sent: 0x%x, received: 0x%x)\n",
1650 dev_name(&card->read.ccwdev->dev),
1651 card->info.func_level, temp);
1652 goto out;
1653 }
1654 memcpy(&card->token.issuer_rm_r,
1655 QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
1656 QETH_MPC_TOKEN_LENGTH);
1657 memcpy(&card->info.mcl_level[0],
1658 QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
1659 channel->state = CH_STATE_UP;
1660 out:
1661 qeth_release_buffer(channel, iob);
1662 }
1663
1664 void qeth_prepare_control_data(struct qeth_card *card, int len,
1665 struct qeth_cmd_buffer *iob)
1666 {
1667 qeth_setup_ccw(&card->write, iob->data, len);
1668 iob->callback = qeth_release_buffer;
1669
1670 memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
1671 &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
1672 card->seqno.trans_hdr++;
1673 memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
1674 &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
1675 card->seqno.pdu_hdr++;
1676 memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
1677 &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
1678 QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
1679 }
1680 EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
1681
1682 int qeth_send_control_data(struct qeth_card *card, int len,
1683 struct qeth_cmd_buffer *iob,
1684 int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
1685 unsigned long),
1686 void *reply_param)
1687 {
1688 int rc;
1689 unsigned long flags;
1690 struct qeth_reply *reply = NULL;
1691 unsigned long timeout, event_timeout;
1692 struct qeth_ipa_cmd *cmd;
1693
1694 QETH_DBF_TEXT(TRACE, 2, "sendctl");
1695
1696 reply = qeth_alloc_reply(card);
1697 if (!reply) {
1698 return -ENOMEM;
1699 }
1700 reply->callback = reply_cb;
1701 reply->param = reply_param;
1702 if (card->state == CARD_STATE_DOWN)
1703 reply->seqno = QETH_IDX_COMMAND_SEQNO;
1704 else
1705 reply->seqno = card->seqno.ipa++;
1706 init_waitqueue_head(&reply->wait_q);
1707 spin_lock_irqsave(&card->lock, flags);
1708 list_add_tail(&reply->list, &card->cmd_waiter_list);
1709 spin_unlock_irqrestore(&card->lock, flags);
1710 QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
1711
1712 while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
1713 qeth_prepare_control_data(card, len, iob);
1714
1715 if (IS_IPA(iob->data))
1716 event_timeout = QETH_IPA_TIMEOUT;
1717 else
1718 event_timeout = QETH_TIMEOUT;
1719 timeout = jiffies + event_timeout;
1720
1721 QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
1722 spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
1723 rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
1724 (addr_t) iob, 0, 0);
1725 spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
1726 if (rc) {
1727 QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: "
1728 "ccw_device_start rc = %i\n",
1729 dev_name(&card->write.ccwdev->dev), rc);
1730 QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
1731 spin_lock_irqsave(&card->lock, flags);
1732 list_del_init(&reply->list);
1733 qeth_put_reply(reply);
1734 spin_unlock_irqrestore(&card->lock, flags);
1735 qeth_release_buffer(iob->channel, iob);
1736 atomic_set(&card->write.irq_pending, 0);
1737 wake_up(&card->wait_q);
1738 return rc;
1739 }
1740
1741 /* we have only one long running ipassist, since we can ensure
1742 process context of this command we can sleep */
1743 cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
1744 if ((cmd->hdr.command == IPA_CMD_SETIP) &&
1745 (cmd->hdr.prot_version == QETH_PROT_IPV4)) {
1746 if (!wait_event_timeout(reply->wait_q,
1747 atomic_read(&reply->received), event_timeout))
1748 goto time_err;
1749 } else {
1750 while (!atomic_read(&reply->received)) {
1751 if (time_after(jiffies, timeout))
1752 goto time_err;
1753 cpu_relax();
1754 };
1755 }
1756
1757 rc = reply->rc;
1758 qeth_put_reply(reply);
1759 return rc;
1760
1761 time_err:
1762 spin_lock_irqsave(&reply->card->lock, flags);
1763 list_del_init(&reply->list);
1764 spin_unlock_irqrestore(&reply->card->lock, flags);
1765 reply->rc = -ETIME;
1766 atomic_inc(&reply->received);
1767 wake_up(&reply->wait_q);
1768 rc = reply->rc;
1769 qeth_put_reply(reply);
1770 return rc;
1771 }
1772 EXPORT_SYMBOL_GPL(qeth_send_control_data);
1773
1774 static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
1775 unsigned long data)
1776 {
1777 struct qeth_cmd_buffer *iob;
1778
1779 QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
1780
1781 iob = (struct qeth_cmd_buffer *) data;
1782 memcpy(&card->token.cm_filter_r,
1783 QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
1784 QETH_MPC_TOKEN_LENGTH);
1785 QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
1786 return 0;
1787 }
1788
1789 static int qeth_cm_enable(struct qeth_card *card)
1790 {
1791 int rc;
1792 struct qeth_cmd_buffer *iob;
1793
1794 QETH_DBF_TEXT(SETUP, 2, "cmenable");
1795
1796 iob = qeth_wait_for_buffer(&card->write);
1797 memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
1798 memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
1799 &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
1800 memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
1801 &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
1802
1803 rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
1804 qeth_cm_enable_cb, NULL);
1805 return rc;
1806 }
1807
1808 static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
1809 unsigned long data)
1810 {
1811
1812 struct qeth_cmd_buffer *iob;
1813
1814 QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
1815
1816 iob = (struct qeth_cmd_buffer *) data;
1817 memcpy(&card->token.cm_connection_r,
1818 QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
1819 QETH_MPC_TOKEN_LENGTH);
1820 QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
1821 return 0;
1822 }
1823
1824 static int qeth_cm_setup(struct qeth_card *card)
1825 {
1826 int rc;
1827 struct qeth_cmd_buffer *iob;
1828
1829 QETH_DBF_TEXT(SETUP, 2, "cmsetup");
1830
1831 iob = qeth_wait_for_buffer(&card->write);
1832 memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
1833 memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
1834 &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
1835 memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
1836 &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
1837 memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
1838 &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
1839 rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
1840 qeth_cm_setup_cb, NULL);
1841 return rc;
1842
1843 }
1844
1845 static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
1846 {
1847 switch (card->info.type) {
1848 case QETH_CARD_TYPE_UNKNOWN:
1849 return 1500;
1850 case QETH_CARD_TYPE_IQD:
1851 return card->info.max_mtu;
1852 case QETH_CARD_TYPE_OSAE:
1853 switch (card->info.link_type) {
1854 case QETH_LINK_TYPE_HSTR:
1855 case QETH_LINK_TYPE_LANE_TR:
1856 return 2000;
1857 default:
1858 return 1492;
1859 }
1860 default:
1861 return 1500;
1862 }
1863 }
1864
1865 static inline int qeth_get_max_mtu_for_card(int cardtype)
1866 {
1867 switch (cardtype) {
1868
1869 case QETH_CARD_TYPE_UNKNOWN:
1870 case QETH_CARD_TYPE_OSAE:
1871 case QETH_CARD_TYPE_OSN:
1872 return 61440;
1873 case QETH_CARD_TYPE_IQD:
1874 return 57344;
1875 default:
1876 return 1500;
1877 }
1878 }
1879
1880 static inline int qeth_get_mtu_out_of_mpc(int cardtype)
1881 {
1882 switch (cardtype) {
1883 case QETH_CARD_TYPE_IQD:
1884 return 1;
1885 default:
1886 return 0;
1887 }
1888 }
1889
1890 static inline int qeth_get_mtu_outof_framesize(int framesize)
1891 {
1892 switch (framesize) {
1893 case 0x4000:
1894 return 8192;
1895 case 0x6000:
1896 return 16384;
1897 case 0xa000:
1898 return 32768;
1899 case 0xffff:
1900 return 57344;
1901 default:
1902 return 0;
1903 }
1904 }
1905
1906 static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
1907 {
1908 switch (card->info.type) {
1909 case QETH_CARD_TYPE_OSAE:
1910 return ((mtu >= 576) && (mtu <= 61440));
1911 case QETH_CARD_TYPE_IQD:
1912 return ((mtu >= 576) &&
1913 (mtu <= card->info.max_mtu + 4096 - 32));
1914 case QETH_CARD_TYPE_OSN:
1915 case QETH_CARD_TYPE_UNKNOWN:
1916 default:
1917 return 1;
1918 }
1919 }
1920
1921 static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
1922 unsigned long data)
1923 {
1924
1925 __u16 mtu, framesize;
1926 __u16 len;
1927 __u8 link_type;
1928 struct qeth_cmd_buffer *iob;
1929
1930 QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
1931
1932 iob = (struct qeth_cmd_buffer *) data;
1933 memcpy(&card->token.ulp_filter_r,
1934 QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
1935 QETH_MPC_TOKEN_LENGTH);
1936 if (qeth_get_mtu_out_of_mpc(card->info.type)) {
1937 memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
1938 mtu = qeth_get_mtu_outof_framesize(framesize);
1939 if (!mtu) {
1940 iob->rc = -EINVAL;
1941 QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
1942 return 0;
1943 }
1944 card->info.max_mtu = mtu;
1945 card->info.initial_mtu = mtu;
1946 card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
1947 } else {
1948 card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
1949 card->info.max_mtu = qeth_get_max_mtu_for_card(card->info.type);
1950 card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
1951 }
1952
1953 memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
1954 if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
1955 memcpy(&link_type,
1956 QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
1957 card->info.link_type = link_type;
1958 } else
1959 card->info.link_type = 0;
1960 QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
1961 return 0;
1962 }
1963
1964 static int qeth_ulp_enable(struct qeth_card *card)
1965 {
1966 int rc;
1967 char prot_type;
1968 struct qeth_cmd_buffer *iob;
1969
1970 /*FIXME: trace view callbacks*/
1971 QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
1972
1973 iob = qeth_wait_for_buffer(&card->write);
1974 memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
1975
1976 *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
1977 (__u8) card->info.portno;
1978 if (card->options.layer2)
1979 if (card->info.type == QETH_CARD_TYPE_OSN)
1980 prot_type = QETH_PROT_OSN2;
1981 else
1982 prot_type = QETH_PROT_LAYER2;
1983 else
1984 prot_type = QETH_PROT_TCPIP;
1985
1986 memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
1987 memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
1988 &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
1989 memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
1990 &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
1991 memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
1992 card->info.portname, 9);
1993 rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
1994 qeth_ulp_enable_cb, NULL);
1995 return rc;
1996
1997 }
1998
1999 static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
2000 unsigned long data)
2001 {
2002 struct qeth_cmd_buffer *iob;
2003
2004 QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
2005
2006 iob = (struct qeth_cmd_buffer *) data;
2007 memcpy(&card->token.ulp_connection_r,
2008 QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
2009 QETH_MPC_TOKEN_LENGTH);
2010 QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
2011 return 0;
2012 }
2013
2014 static int qeth_ulp_setup(struct qeth_card *card)
2015 {
2016 int rc;
2017 __u16 temp;
2018 struct qeth_cmd_buffer *iob;
2019 struct ccw_dev_id dev_id;
2020
2021 QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
2022
2023 iob = qeth_wait_for_buffer(&card->write);
2024 memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
2025
2026 memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
2027 &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
2028 memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
2029 &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
2030 memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
2031 &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
2032
2033 ccw_device_get_id(CARD_DDEV(card), &dev_id);
2034 memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
2035 temp = (card->info.cula << 8) + card->info.unit_addr2;
2036 memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
2037 rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
2038 qeth_ulp_setup_cb, NULL);
2039 return rc;
2040 }
2041
2042 static int qeth_alloc_qdio_buffers(struct qeth_card *card)
2043 {
2044 int i, j;
2045
2046 QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
2047
2048 if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
2049 QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
2050 return 0;
2051
2052 card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
2053 GFP_KERNEL);
2054 if (!card->qdio.in_q)
2055 goto out_nomem;
2056 QETH_DBF_TEXT(SETUP, 2, "inq");
2057 QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
2058 memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
2059 /* give inbound qeth_qdio_buffers their qdio_buffers */
2060 for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
2061 card->qdio.in_q->bufs[i].buffer =
2062 &card->qdio.in_q->qdio_bufs[i];
2063 /* inbound buffer pool */
2064 if (qeth_alloc_buffer_pool(card))
2065 goto out_freeinq;
2066 /* outbound */
2067 card->qdio.out_qs =
2068 kmalloc(card->qdio.no_out_queues *
2069 sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
2070 if (!card->qdio.out_qs)
2071 goto out_freepool;
2072 for (i = 0; i < card->qdio.no_out_queues; ++i) {
2073 card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
2074 GFP_KERNEL);
2075 if (!card->qdio.out_qs[i])
2076 goto out_freeoutq;
2077 QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
2078 QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
2079 memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
2080 card->qdio.out_qs[i]->queue_no = i;
2081 /* give outbound qeth_qdio_buffers their qdio_buffers */
2082 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
2083 card->qdio.out_qs[i]->bufs[j].buffer =
2084 &card->qdio.out_qs[i]->qdio_bufs[j];
2085 skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
2086 skb_list);
2087 lockdep_set_class(
2088 &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
2089 &qdio_out_skb_queue_key);
2090 INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
2091 }
2092 }
2093 return 0;
2094
2095 out_freeoutq:
2096 while (i > 0)
2097 kfree(card->qdio.out_qs[--i]);
2098 kfree(card->qdio.out_qs);
2099 card->qdio.out_qs = NULL;
2100 out_freepool:
2101 qeth_free_buffer_pool(card);
2102 out_freeinq:
2103 kfree(card->qdio.in_q);
2104 card->qdio.in_q = NULL;
2105 out_nomem:
2106 atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
2107 return -ENOMEM;
2108 }
2109
2110 static void qeth_create_qib_param_field(struct qeth_card *card,
2111 char *param_field)
2112 {
2113
2114 param_field[0] = _ascebc['P'];
2115 param_field[1] = _ascebc['C'];
2116 param_field[2] = _ascebc['I'];
2117 param_field[3] = _ascebc['T'];
2118 *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
2119 *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
2120 *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
2121 }
2122
2123 static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
2124 char *param_field)
2125 {
2126 param_field[16] = _ascebc['B'];
2127 param_field[17] = _ascebc['L'];
2128 param_field[18] = _ascebc['K'];
2129 param_field[19] = _ascebc['T'];
2130 *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
2131 *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
2132 *((unsigned int *) (&param_field[28])) =
2133 card->info.blkt.inter_packet_jumbo;
2134 }
2135
2136 static int qeth_qdio_activate(struct qeth_card *card)
2137 {
2138 QETH_DBF_TEXT(SETUP, 3, "qdioact");
2139 return qdio_activate(CARD_DDEV(card));
2140 }
2141
2142 static int qeth_dm_act(struct qeth_card *card)
2143 {
2144 int rc;
2145 struct qeth_cmd_buffer *iob;
2146
2147 QETH_DBF_TEXT(SETUP, 2, "dmact");
2148
2149 iob = qeth_wait_for_buffer(&card->write);
2150 memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
2151
2152 memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
2153 &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
2154 memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
2155 &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
2156 rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
2157 return rc;
2158 }
2159
2160 static int qeth_mpc_initialize(struct qeth_card *card)
2161 {
2162 int rc;
2163
2164 QETH_DBF_TEXT(SETUP, 2, "mpcinit");
2165
2166 rc = qeth_issue_next_read(card);
2167 if (rc) {
2168 QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
2169 return rc;
2170 }
2171 rc = qeth_cm_enable(card);
2172 if (rc) {
2173 QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
2174 goto out_qdio;
2175 }
2176 rc = qeth_cm_setup(card);
2177 if (rc) {
2178 QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
2179 goto out_qdio;
2180 }
2181 rc = qeth_ulp_enable(card);
2182 if (rc) {
2183 QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
2184 goto out_qdio;
2185 }
2186 rc = qeth_ulp_setup(card);
2187 if (rc) {
2188 QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
2189 goto out_qdio;
2190 }
2191 rc = qeth_alloc_qdio_buffers(card);
2192 if (rc) {
2193 QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
2194 goto out_qdio;
2195 }
2196 rc = qeth_qdio_establish(card);
2197 if (rc) {
2198 QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
2199 qeth_free_qdio_buffers(card);
2200 goto out_qdio;
2201 }
2202 rc = qeth_qdio_activate(card);
2203 if (rc) {
2204 QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
2205 goto out_qdio;
2206 }
2207 rc = qeth_dm_act(card);
2208 if (rc) {
2209 QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
2210 goto out_qdio;
2211 }
2212
2213 return 0;
2214 out_qdio:
2215 qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
2216 return rc;
2217 }
2218
2219 static void qeth_print_status_with_portname(struct qeth_card *card)
2220 {
2221 char dbf_text[15];
2222 int i;
2223
2224 sprintf(dbf_text, "%s", card->info.portname + 1);
2225 for (i = 0; i < 8; i++)
2226 dbf_text[i] =
2227 (char) _ebcasc[(__u8) dbf_text[i]];
2228 dbf_text[8] = 0;
2229 dev_info(&card->gdev->dev, "Device is a%s card%s%s%s\n"
2230 "with link type %s (portname: %s)\n",
2231 qeth_get_cardname(card),
2232 (card->info.mcl_level[0]) ? " (level: " : "",
2233 (card->info.mcl_level[0]) ? card->info.mcl_level : "",
2234 (card->info.mcl_level[0]) ? ")" : "",
2235 qeth_get_cardname_short(card),
2236 dbf_text);
2237
2238 }
2239
2240 static void qeth_print_status_no_portname(struct qeth_card *card)
2241 {
2242 if (card->info.portname[0])
2243 dev_info(&card->gdev->dev, "Device is a%s "
2244 "card%s%s%s\nwith link type %s "
2245 "(no portname needed by interface).\n",
2246 qeth_get_cardname(card),
2247 (card->info.mcl_level[0]) ? " (level: " : "",
2248 (card->info.mcl_level[0]) ? card->info.mcl_level : "",
2249 (card->info.mcl_level[0]) ? ")" : "",
2250 qeth_get_cardname_short(card));
2251 else
2252 dev_info(&card->gdev->dev, "Device is a%s "
2253 "card%s%s%s\nwith link type %s.\n",
2254 qeth_get_cardname(card),
2255 (card->info.mcl_level[0]) ? " (level: " : "",
2256 (card->info.mcl_level[0]) ? card->info.mcl_level : "",
2257 (card->info.mcl_level[0]) ? ")" : "",
2258 qeth_get_cardname_short(card));
2259 }
2260
2261 void qeth_print_status_message(struct qeth_card *card)
2262 {
2263 switch (card->info.type) {
2264 case QETH_CARD_TYPE_OSAE:
2265 /* VM will use a non-zero first character
2266 * to indicate a HiperSockets like reporting
2267 * of the level OSA sets the first character to zero
2268 * */
2269 if (!card->info.mcl_level[0]) {
2270 sprintf(card->info.mcl_level, "%02x%02x",
2271 card->info.mcl_level[2],
2272 card->info.mcl_level[3]);
2273
2274 card->info.mcl_level[QETH_MCL_LENGTH] = 0;
2275 break;
2276 }
2277 /* fallthrough */
2278 case QETH_CARD_TYPE_IQD:
2279 if ((card->info.guestlan) ||
2280 (card->info.mcl_level[0] & 0x80)) {
2281 card->info.mcl_level[0] = (char) _ebcasc[(__u8)
2282 card->info.mcl_level[0]];
2283 card->info.mcl_level[1] = (char) _ebcasc[(__u8)
2284 card->info.mcl_level[1]];
2285 card->info.mcl_level[2] = (char) _ebcasc[(__u8)
2286 card->info.mcl_level[2]];
2287 card->info.mcl_level[3] = (char) _ebcasc[(__u8)
2288 card->info.mcl_level[3]];
2289 card->info.mcl_level[QETH_MCL_LENGTH] = 0;
2290 }
2291 break;
2292 default:
2293 memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
2294 }
2295 if (card->info.portname_required)
2296 qeth_print_status_with_portname(card);
2297 else
2298 qeth_print_status_no_portname(card);
2299 }
2300 EXPORT_SYMBOL_GPL(qeth_print_status_message);
2301
2302 static void qeth_initialize_working_pool_list(struct qeth_card *card)
2303 {
2304 struct qeth_buffer_pool_entry *entry;
2305
2306 QETH_DBF_TEXT(TRACE, 5, "inwrklst");
2307
2308 list_for_each_entry(entry,
2309 &card->qdio.init_pool.entry_list, init_list) {
2310 qeth_put_buffer_pool_entry(card, entry);
2311 }
2312 }
2313
2314 static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
2315 struct qeth_card *card)
2316 {
2317 struct list_head *plh;
2318 struct qeth_buffer_pool_entry *entry;
2319 int i, free;
2320 struct page *page;
2321
2322 if (list_empty(&card->qdio.in_buf_pool.entry_list))
2323 return NULL;
2324
2325 list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
2326 entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
2327 free = 1;
2328 for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
2329 if (page_count(virt_to_page(entry->elements[i])) > 1) {
2330 free = 0;
2331 break;
2332 }
2333 }
2334 if (free) {
2335 list_del_init(&entry->list);
2336 return entry;
2337 }
2338 }
2339
2340 /* no free buffer in pool so take first one and swap pages */
2341 entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
2342 struct qeth_buffer_pool_entry, list);
2343 for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
2344 if (page_count(virt_to_page(entry->elements[i])) > 1) {
2345 page = alloc_page(GFP_ATOMIC);
2346 if (!page) {
2347 return NULL;
2348 } else {
2349 free_page((unsigned long)entry->elements[i]);
2350 entry->elements[i] = page_address(page);
2351 if (card->options.performance_stats)
2352 card->perf_stats.sg_alloc_page_rx++;
2353 }
2354 }
2355 }
2356 list_del_init(&entry->list);
2357 return entry;
2358 }
2359
2360 static int qeth_init_input_buffer(struct qeth_card *card,
2361 struct qeth_qdio_buffer *buf)
2362 {
2363 struct qeth_buffer_pool_entry *pool_entry;
2364 int i;
2365
2366 pool_entry = qeth_find_free_buffer_pool_entry(card);
2367 if (!pool_entry)
2368 return 1;
2369
2370 /*
2371 * since the buffer is accessed only from the input_tasklet
2372 * there shouldn't be a need to synchronize; also, since we use
2373 * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
2374 * buffers
2375 */
2376
2377 buf->pool_entry = pool_entry;
2378 for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
2379 buf->buffer->element[i].length = PAGE_SIZE;
2380 buf->buffer->element[i].addr = pool_entry->elements[i];
2381 if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
2382 buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY;
2383 else
2384 buf->buffer->element[i].flags = 0;
2385 }
2386 return 0;
2387 }
2388
2389 int qeth_init_qdio_queues(struct qeth_card *card)
2390 {
2391 int i, j;
2392 int rc;
2393
2394 QETH_DBF_TEXT(SETUP, 2, "initqdqs");
2395
2396 /* inbound queue */
2397 memset(card->qdio.in_q->qdio_bufs, 0,
2398 QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
2399 qeth_initialize_working_pool_list(card);
2400 /*give only as many buffers to hardware as we have buffer pool entries*/
2401 for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
2402 qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
2403 card->qdio.in_q->next_buf_to_init =
2404 card->qdio.in_buf_pool.buf_count - 1;
2405 rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
2406 card->qdio.in_buf_pool.buf_count - 1);
2407 if (rc) {
2408 QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
2409 return rc;
2410 }
2411 /* outbound queue */
2412 for (i = 0; i < card->qdio.no_out_queues; ++i) {
2413 memset(card->qdio.out_qs[i]->qdio_bufs, 0,
2414 QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
2415 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
2416 qeth_clear_output_buffer(card->qdio.out_qs[i],
2417 &card->qdio.out_qs[i]->bufs[j]);
2418 }
2419 card->qdio.out_qs[i]->card = card;
2420 card->qdio.out_qs[i]->next_buf_to_fill = 0;
2421 card->qdio.out_qs[i]->do_pack = 0;
2422 atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
2423 atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
2424 atomic_set(&card->qdio.out_qs[i]->state,
2425 QETH_OUT_Q_UNLOCKED);
2426 }
2427 return 0;
2428 }
2429 EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
2430
2431 static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
2432 {
2433 switch (link_type) {
2434 case QETH_LINK_TYPE_HSTR:
2435 return 2;
2436 default:
2437 return 1;
2438 }
2439 }
2440
2441 static void qeth_fill_ipacmd_header(struct qeth_card *card,
2442 struct qeth_ipa_cmd *cmd, __u8 command,
2443 enum qeth_prot_versions prot)
2444 {
2445 memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
2446 cmd->hdr.command = command;
2447 cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
2448 cmd->hdr.seqno = card->seqno.ipa;
2449 cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
2450 cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
2451 if (card->options.layer2)
2452 cmd->hdr.prim_version_no = 2;
2453 else
2454 cmd->hdr.prim_version_no = 1;
2455 cmd->hdr.param_count = 1;
2456 cmd->hdr.prot_version = prot;
2457 cmd->hdr.ipa_supported = 0;
2458 cmd->hdr.ipa_enabled = 0;
2459 }
2460
2461 struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
2462 enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
2463 {
2464 struct qeth_cmd_buffer *iob;
2465 struct qeth_ipa_cmd *cmd;
2466
2467 iob = qeth_wait_for_buffer(&card->write);
2468 cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
2469 qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
2470
2471 return iob;
2472 }
2473 EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
2474
2475 void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
2476 char prot_type)
2477 {
2478 memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
2479 memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
2480 memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
2481 &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
2482 }
2483 EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
2484
2485 int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
2486 int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
2487 unsigned long),
2488 void *reply_param)
2489 {
2490 int rc;
2491 char prot_type;
2492
2493 QETH_DBF_TEXT(TRACE, 4, "sendipa");
2494
2495 if (card->options.layer2)
2496 if (card->info.type == QETH_CARD_TYPE_OSN)
2497 prot_type = QETH_PROT_OSN2;
2498 else
2499 prot_type = QETH_PROT_LAYER2;
2500 else
2501 prot_type = QETH_PROT_TCPIP;
2502 qeth_prepare_ipa_cmd(card, iob, prot_type);
2503 rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
2504 iob, reply_cb, reply_param);
2505 return rc;
2506 }
2507 EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
2508
2509 static int qeth_send_startstoplan(struct qeth_card *card,
2510 enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
2511 {
2512 int rc;
2513 struct qeth_cmd_buffer *iob;
2514
2515 iob = qeth_get_ipacmd_buffer(card, ipacmd, prot);
2516 rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
2517
2518 return rc;
2519 }
2520
2521 int qeth_send_startlan(struct qeth_card *card)
2522 {
2523 int rc;
2524
2525 QETH_DBF_TEXT(SETUP, 2, "strtlan");
2526
2527 rc = qeth_send_startstoplan(card, IPA_CMD_STARTLAN, 0);
2528 return rc;
2529 }
2530 EXPORT_SYMBOL_GPL(qeth_send_startlan);
2531
2532 int qeth_send_stoplan(struct qeth_card *card)
2533 {
2534 int rc = 0;
2535
2536 /*
2537 * TODO: according to the IPA format document page 14,
2538 * TCP/IP (we!) never issue a STOPLAN
2539 * is this right ?!?
2540 */
2541 QETH_DBF_TEXT(SETUP, 2, "stoplan");
2542
2543 rc = qeth_send_startstoplan(card, IPA_CMD_STOPLAN, 0);
2544 return rc;
2545 }
2546 EXPORT_SYMBOL_GPL(qeth_send_stoplan);
2547
2548 int qeth_default_setadapterparms_cb(struct qeth_card *card,
2549 struct qeth_reply *reply, unsigned long data)
2550 {
2551 struct qeth_ipa_cmd *cmd;
2552
2553 QETH_DBF_TEXT(TRACE, 4, "defadpcb");
2554
2555 cmd = (struct qeth_ipa_cmd *) data;
2556 if (cmd->hdr.return_code == 0)
2557 cmd->hdr.return_code =
2558 cmd->data.setadapterparms.hdr.return_code;
2559 return 0;
2560 }
2561 EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
2562
2563 static int qeth_query_setadapterparms_cb(struct qeth_card *card,
2564 struct qeth_reply *reply, unsigned long data)
2565 {
2566 struct qeth_ipa_cmd *cmd;
2567
2568 QETH_DBF_TEXT(TRACE, 3, "quyadpcb");
2569
2570 cmd = (struct qeth_ipa_cmd *) data;
2571 if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f)
2572 card->info.link_type =
2573 cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
2574 card->options.adp.supported_funcs =
2575 cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
2576 return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
2577 }
2578
2579 struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
2580 __u32 command, __u32 cmdlen)
2581 {
2582 struct qeth_cmd_buffer *iob;
2583 struct qeth_ipa_cmd *cmd;
2584
2585 iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
2586 QETH_PROT_IPV4);
2587 cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
2588 cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
2589 cmd->data.setadapterparms.hdr.command_code = command;
2590 cmd->data.setadapterparms.hdr.used_total = 1;
2591 cmd->data.setadapterparms.hdr.seq_no = 1;
2592
2593 return iob;
2594 }
2595 EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
2596
2597 int qeth_query_setadapterparms(struct qeth_card *card)
2598 {
2599 int rc;
2600 struct qeth_cmd_buffer *iob;
2601
2602 QETH_DBF_TEXT(TRACE, 3, "queryadp");
2603 iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
2604 sizeof(struct qeth_ipacmd_setadpparms));
2605 rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
2606 return rc;
2607 }
2608 EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
2609
2610 int qeth_check_qdio_errors(struct qdio_buffer *buf, unsigned int qdio_error,
2611 const char *dbftext)
2612 {
2613 if (qdio_error) {
2614 QETH_DBF_TEXT(TRACE, 2, dbftext);
2615 QETH_DBF_TEXT(QERR, 2, dbftext);
2616 QETH_DBF_TEXT_(QERR, 2, " F15=%02X",
2617 buf->element[15].flags & 0xff);
2618 QETH_DBF_TEXT_(QERR, 2, " F14=%02X",
2619 buf->element[14].flags & 0xff);
2620 QETH_DBF_TEXT_(QERR, 2, " qerr=%X", qdio_error);
2621 return 1;
2622 }
2623 return 0;
2624 }
2625 EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
2626
2627 void qeth_queue_input_buffer(struct qeth_card *card, int index)
2628 {
2629 struct qeth_qdio_q *queue = card->qdio.in_q;
2630 int count;
2631 int i;
2632 int rc;
2633 int newcount = 0;
2634
2635 count = (index < queue->next_buf_to_init)?
2636 card->qdio.in_buf_pool.buf_count -
2637 (queue->next_buf_to_init - index) :
2638 card->qdio.in_buf_pool.buf_count -
2639 (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
2640 /* only requeue at a certain threshold to avoid SIGAs */
2641 if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
2642 for (i = queue->next_buf_to_init;
2643 i < queue->next_buf_to_init + count; ++i) {
2644 if (qeth_init_input_buffer(card,
2645 &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
2646 break;
2647 } else {
2648 newcount++;
2649 }
2650 }
2651
2652 if (newcount < count) {
2653 /* we are in memory shortage so we switch back to
2654 traditional skb allocation and drop packages */
2655 atomic_set(&card->force_alloc_skb, 3);
2656 count = newcount;
2657 } else {
2658 atomic_add_unless(&card->force_alloc_skb, -1, 0);
2659 }
2660
2661 /*
2662 * according to old code it should be avoided to requeue all
2663 * 128 buffers in order to benefit from PCI avoidance.
2664 * this function keeps at least one buffer (the buffer at
2665 * 'index') un-requeued -> this buffer is the first buffer that
2666 * will be requeued the next time
2667 */
2668 if (card->options.performance_stats) {
2669 card->perf_stats.inbound_do_qdio_cnt++;
2670 card->perf_stats.inbound_do_qdio_start_time =
2671 qeth_get_micros();
2672 }
2673 rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
2674 queue->next_buf_to_init, count);
2675 if (card->options.performance_stats)
2676 card->perf_stats.inbound_do_qdio_time +=
2677 qeth_get_micros() -
2678 card->perf_stats.inbound_do_qdio_start_time;
2679 if (rc) {
2680 dev_warn(&card->gdev->dev,
2681 "QDIO reported an error, rc=%i\n", rc);
2682 QETH_DBF_TEXT(TRACE, 2, "qinberr");
2683 QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
2684 }
2685 queue->next_buf_to_init = (queue->next_buf_to_init + count) %
2686 QDIO_MAX_BUFFERS_PER_Q;
2687 }
2688 }
2689 EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
2690
2691 static int qeth_handle_send_error(struct qeth_card *card,
2692 struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
2693 {
2694 int sbalf15 = buffer->buffer->element[15].flags & 0xff;
2695
2696 QETH_DBF_TEXT(TRACE, 6, "hdsnderr");
2697 if (card->info.type == QETH_CARD_TYPE_IQD) {
2698 if (sbalf15 == 0) {
2699 qdio_err = 0;
2700 } else {
2701 qdio_err = 1;
2702 }
2703 }
2704 qeth_check_qdio_errors(buffer->buffer, qdio_err, "qouterr");
2705
2706 if (!qdio_err)
2707 return QETH_SEND_ERROR_NONE;
2708
2709 if ((sbalf15 >= 15) && (sbalf15 <= 31))
2710 return QETH_SEND_ERROR_RETRY;
2711
2712 QETH_DBF_TEXT(TRACE, 1, "lnkfail");
2713 QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
2714 QETH_DBF_TEXT_(TRACE, 1, "%04x %02x",
2715 (u16)qdio_err, (u8)sbalf15);
2716 return QETH_SEND_ERROR_LINK_FAILURE;
2717 }
2718
2719 /*
2720 * Switched to packing state if the number of used buffers on a queue
2721 * reaches a certain limit.
2722 */
2723 static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
2724 {
2725 if (!queue->do_pack) {
2726 if (atomic_read(&queue->used_buffers)
2727 >= QETH_HIGH_WATERMARK_PACK){
2728 /* switch non-PACKING -> PACKING */
2729 QETH_DBF_TEXT(TRACE, 6, "np->pack");
2730 if (queue->card->options.performance_stats)
2731 queue->card->perf_stats.sc_dp_p++;
2732 queue->do_pack = 1;
2733 }
2734 }
2735 }
2736
2737 /*
2738 * Switches from packing to non-packing mode. If there is a packing
2739 * buffer on the queue this buffer will be prepared to be flushed.
2740 * In that case 1 is returned to inform the caller. If no buffer
2741 * has to be flushed, zero is returned.
2742 */
2743 static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
2744 {
2745 struct qeth_qdio_out_buffer *buffer;
2746 int flush_count = 0;
2747
2748 if (queue->do_pack) {
2749 if (atomic_read(&queue->used_buffers)
2750 <= QETH_LOW_WATERMARK_PACK) {
2751 /* switch PACKING -> non-PACKING */
2752 QETH_DBF_TEXT(TRACE, 6, "pack->np");
2753 if (queue->card->options.performance_stats)
2754 queue->card->perf_stats.sc_p_dp++;
2755 queue->do_pack = 0;
2756 /* flush packing buffers */
2757 buffer = &queue->bufs[queue->next_buf_to_fill];
2758 if ((atomic_read(&buffer->state) ==
2759 QETH_QDIO_BUF_EMPTY) &&
2760 (buffer->next_element_to_fill > 0)) {
2761 atomic_set(&buffer->state,
2762 QETH_QDIO_BUF_PRIMED);
2763 flush_count++;
2764 queue->next_buf_to_fill =
2765 (queue->next_buf_to_fill + 1) %
2766 QDIO_MAX_BUFFERS_PER_Q;
2767 }
2768 }
2769 }
2770 return flush_count;
2771 }
2772
2773 /*
2774 * Called to flush a packing buffer if no more pci flags are on the queue.
2775 * Checks if there is a packing buffer and prepares it to be flushed.
2776 * In that case returns 1, otherwise zero.
2777 */
2778 static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
2779 {
2780 struct qeth_qdio_out_buffer *buffer;
2781
2782 buffer = &queue->bufs[queue->next_buf_to_fill];
2783 if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
2784 (buffer->next_element_to_fill > 0)) {
2785 /* it's a packing buffer */
2786 atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
2787 queue->next_buf_to_fill =
2788 (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
2789 return 1;
2790 }
2791 return 0;
2792 }
2793
2794 static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
2795 int count)
2796 {
2797 struct qeth_qdio_out_buffer *buf;
2798 int rc;
2799 int i;
2800 unsigned int qdio_flags;
2801
2802 for (i = index; i < index + count; ++i) {
2803 buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
2804 buf->buffer->element[buf->next_element_to_fill - 1].flags |=
2805 SBAL_FLAGS_LAST_ENTRY;
2806
2807 if (queue->card->info.type == QETH_CARD_TYPE_IQD)
2808 continue;
2809
2810 if (!queue->do_pack) {
2811 if ((atomic_read(&queue->used_buffers) >=
2812 (QETH_HIGH_WATERMARK_PACK -
2813 QETH_WATERMARK_PACK_FUZZ)) &&
2814 !atomic_read(&queue->set_pci_flags_count)) {
2815 /* it's likely that we'll go to packing
2816 * mode soon */
2817 atomic_inc(&queue->set_pci_flags_count);
2818 buf->buffer->element[0].flags |= 0x40;
2819 }
2820 } else {
2821 if (!atomic_read(&queue->set_pci_flags_count)) {
2822 /*
2823 * there's no outstanding PCI any more, so we
2824 * have to request a PCI to be sure the the PCI
2825 * will wake at some time in the future then we
2826 * can flush packed buffers that might still be
2827 * hanging around, which can happen if no
2828 * further send was requested by the stack
2829 */
2830 atomic_inc(&queue->set_pci_flags_count);
2831 buf->buffer->element[0].flags |= 0x40;
2832 }
2833 }
2834 }
2835
2836 queue->sync_iqdio_error = 0;
2837 queue->card->dev->trans_start = jiffies;
2838 if (queue->card->options.performance_stats) {
2839 queue->card->perf_stats.outbound_do_qdio_cnt++;
2840 queue->card->perf_stats.outbound_do_qdio_start_time =
2841 qeth_get_micros();
2842 }
2843 qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
2844 if (atomic_read(&queue->set_pci_flags_count))
2845 qdio_flags |= QDIO_FLAG_PCI_OUT;
2846 rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
2847 queue->queue_no, index, count);
2848 if (queue->card->options.performance_stats)
2849 queue->card->perf_stats.outbound_do_qdio_time +=
2850 qeth_get_micros() -
2851 queue->card->perf_stats.outbound_do_qdio_start_time;
2852 if (rc > 0) {
2853 if (!(rc & QDIO_ERROR_SIGA_BUSY))
2854 queue->sync_iqdio_error = rc & 3;
2855 }
2856 if (rc) {
2857 queue->card->stats.tx_errors += count;
2858 /* ignore temporary SIGA errors without busy condition */
2859 if (rc == QDIO_ERROR_SIGA_TARGET)
2860 return;
2861 QETH_DBF_TEXT(TRACE, 2, "flushbuf");
2862 QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
2863 QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_DDEV_ID(queue->card));
2864
2865 /* this must not happen under normal circumstances. if it
2866 * happens something is really wrong -> recover */
2867 qeth_schedule_recovery(queue->card);
2868 return;
2869 }
2870 atomic_add(count, &queue->used_buffers);
2871 if (queue->card->options.performance_stats)
2872 queue->card->perf_stats.bufs_sent += count;
2873 }
2874
2875 static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
2876 {
2877 int index;
2878 int flush_cnt = 0;
2879 int q_was_packing = 0;
2880
2881 /*
2882 * check if weed have to switch to non-packing mode or if
2883 * we have to get a pci flag out on the queue
2884 */
2885 if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
2886 !atomic_read(&queue->set_pci_flags_count)) {
2887 if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
2888 QETH_OUT_Q_UNLOCKED) {
2889 /*
2890 * If we get in here, there was no action in
2891 * do_send_packet. So, we check if there is a
2892 * packing buffer to be flushed here.
2893 */
2894 netif_stop_queue(queue->card->dev);
2895 index = queue->next_buf_to_fill;
2896 q_was_packing = queue->do_pack;
2897 /* queue->do_pack may change */
2898 barrier();
2899 flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
2900 if (!flush_cnt &&
2901 !atomic_read(&queue->set_pci_flags_count))
2902 flush_cnt +=
2903 qeth_flush_buffers_on_no_pci(queue);
2904 if (queue->card->options.performance_stats &&
2905 q_was_packing)
2906 queue->card->perf_stats.bufs_sent_pack +=
2907 flush_cnt;
2908 if (flush_cnt)
2909 qeth_flush_buffers(queue, index, flush_cnt);
2910 atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
2911 }
2912 }
2913 }
2914
2915 void qeth_qdio_output_handler(struct ccw_device *ccwdev,
2916 unsigned int qdio_error, int __queue, int first_element,
2917 int count, unsigned long card_ptr)
2918 {
2919 struct qeth_card *card = (struct qeth_card *) card_ptr;
2920 struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
2921 struct qeth_qdio_out_buffer *buffer;
2922 int i;
2923 unsigned qeth_send_err;
2924
2925 QETH_DBF_TEXT(TRACE, 6, "qdouhdl");
2926 if (qdio_error & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) {
2927 QETH_DBF_TEXT(TRACE, 2, "achkcond");
2928 QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
2929 netif_stop_queue(card->dev);
2930 qeth_schedule_recovery(card);
2931 return;
2932 }
2933 if (card->options.performance_stats) {
2934 card->perf_stats.outbound_handler_cnt++;
2935 card->perf_stats.outbound_handler_start_time =
2936 qeth_get_micros();
2937 }
2938 for (i = first_element; i < (first_element + count); ++i) {
2939 buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
2940 qeth_send_err = qeth_handle_send_error(card, buffer, qdio_error);
2941 __qeth_clear_output_buffer(queue, buffer,
2942 (qeth_send_err == QETH_SEND_ERROR_RETRY) ? 1 : 0);
2943 }
2944 atomic_sub(count, &queue->used_buffers);
2945 /* check if we need to do something on this outbound queue */
2946 if (card->info.type != QETH_CARD_TYPE_IQD)
2947 qeth_check_outbound_queue(queue);
2948
2949 netif_wake_queue(queue->card->dev);
2950 if (card->options.performance_stats)
2951 card->perf_stats.outbound_handler_time += qeth_get_micros() -
2952 card->perf_stats.outbound_handler_start_time;
2953 }
2954 EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
2955
2956 int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
2957 int ipv, int cast_type)
2958 {
2959 if (!ipv && (card->info.type == QETH_CARD_TYPE_OSAE))
2960 return card->qdio.default_out_queue;
2961 switch (card->qdio.no_out_queues) {
2962 case 4:
2963 if (cast_type && card->info.is_multicast_different)
2964 return card->info.is_multicast_different &
2965 (card->qdio.no_out_queues - 1);
2966 if (card->qdio.do_prio_queueing && (ipv == 4)) {
2967 const u8 tos = ip_hdr(skb)->tos;
2968
2969 if (card->qdio.do_prio_queueing ==
2970 QETH_PRIO_Q_ING_TOS) {
2971 if (tos & IP_TOS_NOTIMPORTANT)
2972 return 3;
2973 if (tos & IP_TOS_HIGHRELIABILITY)
2974 return 2;
2975 if (tos & IP_TOS_HIGHTHROUGHPUT)
2976 return 1;
2977 if (tos & IP_TOS_LOWDELAY)
2978 return 0;
2979 }
2980 if (card->qdio.do_prio_queueing ==
2981 QETH_PRIO_Q_ING_PREC)
2982 return 3 - (tos >> 6);
2983 } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
2984 /* TODO: IPv6!!! */
2985 }
2986 return card->qdio.default_out_queue;
2987 case 1: /* fallthrough for single-out-queue 1920-device */
2988 default:
2989 return card->qdio.default_out_queue;
2990 }
2991 }
2992 EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
2993
2994 int qeth_get_elements_no(struct qeth_card *card, void *hdr,
2995 struct sk_buff *skb, int elems)
2996 {
2997 int elements_needed = 0;
2998
2999 if (skb_shinfo(skb)->nr_frags > 0)
3000 elements_needed = (skb_shinfo(skb)->nr_frags + 1);
3001 if (elements_needed == 0)
3002 elements_needed = 1 + (((((unsigned long) skb->data) %
3003 PAGE_SIZE) + skb->len) >> PAGE_SHIFT);
3004 if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
3005 QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
3006 "(Number=%d / Length=%d). Discarded.\n",
3007 (elements_needed+elems), skb->len);
3008 return 0;
3009 }
3010 return elements_needed;
3011 }
3012 EXPORT_SYMBOL_GPL(qeth_get_elements_no);
3013
3014 static inline void __qeth_fill_buffer(struct sk_buff *skb,
3015 struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
3016 int offset)
3017 {
3018 int length = skb->len;
3019 int length_here;
3020 int element;
3021 char *data;
3022 int first_lap ;
3023
3024 element = *next_element_to_fill;
3025 data = skb->data;
3026 first_lap = (is_tso == 0 ? 1 : 0);
3027
3028 if (offset >= 0) {
3029 data = skb->data + offset;
3030 length -= offset;
3031 first_lap = 0;
3032 }
3033
3034 while (length > 0) {
3035 /* length_here is the remaining amount of data in this page */
3036 length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
3037 if (length < length_here)
3038 length_here = length;
3039
3040 buffer->element[element].addr = data;
3041 buffer->element[element].length = length_here;
3042 length -= length_here;
3043 if (!length) {
3044 if (first_lap)
3045 buffer->element[element].flags = 0;
3046 else
3047 buffer->element[element].flags =
3048 SBAL_FLAGS_LAST_FRAG;
3049 } else {
3050 if (first_lap)
3051 buffer->element[element].flags =
3052 SBAL_FLAGS_FIRST_FRAG;
3053 else
3054 buffer->element[element].flags =
3055 SBAL_FLAGS_MIDDLE_FRAG;
3056 }
3057 data += length_here;
3058 element++;
3059 first_lap = 0;
3060 }
3061 *next_element_to_fill = element;
3062 }
3063
3064 static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
3065 struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
3066 struct qeth_hdr *hdr, int offset, int hd_len)
3067 {
3068 struct qdio_buffer *buffer;
3069 int flush_cnt = 0, hdr_len, large_send = 0;
3070
3071 buffer = buf->buffer;
3072 atomic_inc(&skb->users);
3073 skb_queue_tail(&buf->skb_list, skb);
3074
3075 /*check first on TSO ....*/
3076 if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
3077 int element = buf->next_element_to_fill;
3078
3079 hdr_len = sizeof(struct qeth_hdr_tso) +
3080 ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
3081 /*fill first buffer entry only with header information */
3082 buffer->element[element].addr = skb->data;
3083 buffer->element[element].length = hdr_len;
3084 buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
3085 buf->next_element_to_fill++;
3086 skb->data += hdr_len;
3087 skb->len -= hdr_len;
3088 large_send = 1;
3089 }
3090
3091 if (offset >= 0) {
3092 int element = buf->next_element_to_fill;
3093 buffer->element[element].addr = hdr;
3094 buffer->element[element].length = sizeof(struct qeth_hdr) +
3095 hd_len;
3096 buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
3097 buf->is_header[element] = 1;
3098 buf->next_element_to_fill++;
3099 }
3100
3101 if (skb_shinfo(skb)->nr_frags == 0)
3102 __qeth_fill_buffer(skb, buffer, large_send,
3103 (int *)&buf->next_element_to_fill, offset);
3104 else
3105 __qeth_fill_buffer_frag(skb, buffer, large_send,
3106 (int *)&buf->next_element_to_fill);
3107
3108 if (!queue->do_pack) {
3109 QETH_DBF_TEXT(TRACE, 6, "fillbfnp");
3110 /* set state to PRIMED -> will be flushed */
3111 atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
3112 flush_cnt = 1;
3113 } else {
3114 QETH_DBF_TEXT(TRACE, 6, "fillbfpa");
3115 if (queue->card->options.performance_stats)
3116 queue->card->perf_stats.skbs_sent_pack++;
3117 if (buf->next_element_to_fill >=
3118 QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
3119 /*
3120 * packed buffer if full -> set state PRIMED
3121 * -> will be flushed
3122 */
3123 atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
3124 flush_cnt = 1;
3125 }
3126 }
3127 return flush_cnt;
3128 }
3129
3130 int qeth_do_send_packet_fast(struct qeth_card *card,
3131 struct qeth_qdio_out_q *queue, struct sk_buff *skb,
3132 struct qeth_hdr *hdr, int elements_needed,
3133 int offset, int hd_len)
3134 {
3135 struct qeth_qdio_out_buffer *buffer;
3136 struct sk_buff *skb1;
3137 struct qeth_skb_data *retry_ctrl;
3138 int index;
3139 int rc;
3140
3141 /* spin until we get the queue ... */
3142 while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
3143 QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
3144 /* ... now we've got the queue */
3145 index = queue->next_buf_to_fill;
3146 buffer = &queue->bufs[queue->next_buf_to_fill];
3147 /*
3148 * check if buffer is empty to make sure that we do not 'overtake'
3149 * ourselves and try to fill a buffer that is already primed
3150 */
3151 if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
3152 goto out;
3153 queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
3154 QDIO_MAX_BUFFERS_PER_Q;
3155 atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
3156 qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
3157 qeth_flush_buffers(queue, index, 1);
3158 if (queue->sync_iqdio_error == 2) {
3159 skb1 = skb_dequeue(&buffer->skb_list);
3160 while (skb1) {
3161 atomic_dec(&skb1->users);
3162 skb1 = skb_dequeue(&buffer->skb_list);
3163 }
3164 retry_ctrl = (struct qeth_skb_data *) &skb->cb[16];
3165 if (retry_ctrl->magic != QETH_SKB_MAGIC) {
3166 retry_ctrl->magic = QETH_SKB_MAGIC;
3167 retry_ctrl->count = 0;
3168 }
3169 if (retry_ctrl->count < QETH_SIGA_CC2_RETRIES) {
3170 retry_ctrl->count++;
3171 rc = dev_queue_xmit(skb);
3172 } else {
3173 dev_kfree_skb_any(skb);
3174 QETH_DBF_TEXT(QERR, 2, "qrdrop");
3175 }
3176 }
3177 return 0;
3178 out:
3179 atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
3180 return -EBUSY;
3181 }
3182 EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
3183
3184 int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
3185 struct sk_buff *skb, struct qeth_hdr *hdr,
3186 int elements_needed)
3187 {
3188 struct qeth_qdio_out_buffer *buffer;
3189 int start_index;
3190 int flush_count = 0;
3191 int do_pack = 0;
3192 int tmp;
3193 int rc = 0;
3194
3195 /* spin until we get the queue ... */
3196 while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
3197 QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
3198 start_index = queue->next_buf_to_fill;
3199 buffer = &queue->bufs[queue->next_buf_to_fill];
3200 /*
3201 * check if buffer is empty to make sure that we do not 'overtake'
3202 * ourselves and try to fill a buffer that is already primed
3203 */
3204 if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
3205 atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
3206 return -EBUSY;
3207 }
3208 /* check if we need to switch packing state of this queue */
3209 qeth_switch_to_packing_if_needed(queue);
3210 if (queue->do_pack) {
3211 do_pack = 1;
3212 /* does packet fit in current buffer? */
3213 if ((QETH_MAX_BUFFER_ELEMENTS(card) -
3214 buffer->next_element_to_fill) < elements_needed) {
3215 /* ... no -> set state PRIMED */
3216 atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
3217 flush_count++;
3218 queue->next_buf_to_fill =
3219 (queue->next_buf_to_fill + 1) %
3220 QDIO_MAX_BUFFERS_PER_Q;
3221 buffer = &queue->bufs[queue->next_buf_to_fill];
3222 /* we did a step forward, so check buffer state
3223 * again */
3224 if (atomic_read(&buffer->state) !=
3225 QETH_QDIO_BUF_EMPTY) {
3226 qeth_flush_buffers(queue, start_index,
3227 flush_count);
3228 atomic_set(&queue->state,
3229 QETH_OUT_Q_UNLOCKED);
3230 return -EBUSY;
3231 }
3232 }
3233 }
3234 tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
3235 queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
3236 QDIO_MAX_BUFFERS_PER_Q;
3237 flush_count += tmp;
3238 if (flush_count)
3239 qeth_flush_buffers(queue, start_index, flush_count);
3240 else if (!atomic_read(&queue->set_pci_flags_count))
3241 atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
3242 /*
3243 * queue->state will go from LOCKED -> UNLOCKED or from
3244 * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
3245 * (switch packing state or flush buffer to get another pci flag out).
3246 * In that case we will enter this loop
3247 */
3248 while (atomic_dec_return(&queue->state)) {
3249 flush_count = 0;
3250 start_index = queue->next_buf_to_fill;
3251 /* check if we can go back to non-packing state */
3252 flush_count += qeth_switch_to_nonpacking_if_needed(queue);
3253 /*
3254 * check if we need to flush a packing buffer to get a pci
3255 * flag out on the queue
3256 */
3257 if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
3258 flush_count += qeth_flush_buffers_on_no_pci(queue);
3259 if (flush_count)
3260 qeth_flush_buffers(queue, start_index, flush_count);
3261 }
3262 /* at this point the queue is UNLOCKED again */
3263 if (queue->card->options.performance_stats && do_pack)
3264 queue->card->perf_stats.bufs_sent_pack += flush_count;
3265
3266 return rc;
3267 }
3268 EXPORT_SYMBOL_GPL(qeth_do_send_packet);
3269
3270 static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
3271 struct qeth_reply *reply, unsigned long data)
3272 {
3273 struct qeth_ipa_cmd *cmd;
3274 struct qeth_ipacmd_setadpparms *setparms;
3275
3276 QETH_DBF_TEXT(TRACE, 4, "prmadpcb");
3277
3278 cmd = (struct qeth_ipa_cmd *) data;
3279 setparms = &(cmd->data.setadapterparms);
3280
3281 qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
3282 if (cmd->hdr.return_code) {
3283 QETH_DBF_TEXT_(TRACE, 4, "prmrc%2.2x", cmd->hdr.return_code);
3284 setparms->data.mode = SET_PROMISC_MODE_OFF;
3285 }
3286 card->info.promisc_mode = setparms->data.mode;
3287 return 0;
3288 }
3289
3290 void qeth_setadp_promisc_mode(struct qeth_card *card)
3291 {
3292 enum qeth_ipa_promisc_modes mode;
3293 struct net_device *dev = card->dev;
3294 struct qeth_cmd_buffer *iob;
3295 struct qeth_ipa_cmd *cmd;
3296
3297 QETH_DBF_TEXT(TRACE, 4, "setprom");
3298
3299 if (((dev->flags & IFF_PROMISC) &&
3300 (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
3301 (!(dev->flags & IFF_PROMISC) &&
3302 (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
3303 return;
3304 mode = SET_PROMISC_MODE_OFF;
3305 if (dev->flags & IFF_PROMISC)
3306 mode = SET_PROMISC_MODE_ON;
3307 QETH_DBF_TEXT_(TRACE, 4, "mode:%x", mode);
3308
3309 iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
3310 sizeof(struct qeth_ipacmd_setadpparms));
3311 cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
3312 cmd->data.setadapterparms.data.mode = mode;
3313 qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
3314 }
3315 EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
3316
3317 int qeth_change_mtu(struct net_device *dev, int new_mtu)
3318 {
3319 struct qeth_card *card;
3320 char dbf_text[15];
3321
3322 card = dev->ml_priv;
3323
3324 QETH_DBF_TEXT(TRACE, 4, "chgmtu");
3325 sprintf(dbf_text, "%8x", new_mtu);
3326 QETH_DBF_TEXT(TRACE, 4, dbf_text);
3327
3328 if (new_mtu < 64)
3329 return -EINVAL;
3330 if (new_mtu > 65535)
3331 return -EINVAL;
3332 if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
3333 (!qeth_mtu_is_valid(card, new_mtu)))
3334 return -EINVAL;
3335 dev->mtu = new_mtu;
3336 return 0;
3337 }
3338 EXPORT_SYMBOL_GPL(qeth_change_mtu);
3339
3340 struct net_device_stats *qeth_get_stats(struct net_device *dev)
3341 {
3342 struct qeth_card *card;
3343
3344 card = dev->ml_priv;
3345
3346 QETH_DBF_TEXT(TRACE, 5, "getstat");
3347
3348 return &card->stats;
3349 }
3350 EXPORT_SYMBOL_GPL(qeth_get_stats);
3351
3352 static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
3353 struct qeth_reply *reply, unsigned long data)
3354 {
3355 struct qeth_ipa_cmd *cmd;
3356
3357 QETH_DBF_TEXT(TRACE, 4, "chgmaccb");
3358
3359 cmd = (struct qeth_ipa_cmd *) data;
3360 if (!card->options.layer2 ||
3361 !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
3362 memcpy(card->dev->dev_addr,
3363 &cmd->data.setadapterparms.data.change_addr.addr,
3364 OSA_ADDR_LEN);
3365 card->info.mac_bits |= QETH_LAYER2_MAC_READ;
3366 }
3367 qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
3368 return 0;
3369 }
3370
3371 int qeth_setadpparms_change_macaddr(struct qeth_card *card)
3372 {
3373 int rc;
3374 struct qeth_cmd_buffer *iob;
3375 struct qeth_ipa_cmd *cmd;
3376
3377 QETH_DBF_TEXT(TRACE, 4, "chgmac");
3378
3379 iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
3380 sizeof(struct qeth_ipacmd_setadpparms));
3381 cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
3382 cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
3383 cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
3384 memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
3385 card->dev->dev_addr, OSA_ADDR_LEN);
3386 rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
3387 NULL);
3388 return rc;
3389 }
3390 EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
3391
3392 void qeth_tx_timeout(struct net_device *dev)
3393 {
3394 struct qeth_card *card;
3395
3396 card = dev->ml_priv;
3397 card->stats.tx_errors++;
3398 qeth_schedule_recovery(card);
3399 }
3400 EXPORT_SYMBOL_GPL(qeth_tx_timeout);
3401
3402 int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
3403 {
3404 struct qeth_card *card = dev->ml_priv;
3405 int rc = 0;
3406
3407 switch (regnum) {
3408 case MII_BMCR: /* Basic mode control register */
3409 rc = BMCR_FULLDPLX;
3410 if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
3411 (card->info.link_type != QETH_LINK_TYPE_OSN) &&
3412 (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
3413 rc |= BMCR_SPEED100;
3414 break;
3415 case MII_BMSR: /* Basic mode status register */
3416 rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
3417 BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
3418 BMSR_100BASE4;
3419 break;
3420 case MII_PHYSID1: /* PHYS ID 1 */
3421 rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
3422 dev->dev_addr[2];
3423 rc = (rc >> 5) & 0xFFFF;
3424 break;
3425 case MII_PHYSID2: /* PHYS ID 2 */
3426 rc = (dev->dev_addr[2] << 10) & 0xFFFF;
3427 break;
3428 case MII_ADVERTISE: /* Advertisement control reg */
3429 rc = ADVERTISE_ALL;
3430 break;
3431 case MII_LPA: /* Link partner ability reg */
3432 rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
3433 LPA_100BASE4 | LPA_LPACK;
3434 break;
3435 case MII_EXPANSION: /* Expansion register */
3436 break;
3437 case MII_DCOUNTER: /* disconnect counter */
3438 break;
3439 case MII_FCSCOUNTER: /* false carrier counter */
3440 break;
3441 case MII_NWAYTEST: /* N-way auto-neg test register */
3442 break;
3443 case MII_RERRCOUNTER: /* rx error counter */
3444 rc = card->stats.rx_errors;
3445 break;
3446 case MII_SREVISION: /* silicon revision */
3447 break;
3448 case MII_RESV1: /* reserved 1 */
3449 break;
3450 case MII_LBRERROR: /* loopback, rx, bypass error */
3451 break;
3452 case MII_PHYADDR: /* physical address */
3453 break;
3454 case MII_RESV2: /* reserved 2 */
3455 break;
3456 case MII_TPISTATUS: /* TPI status for 10mbps */
3457 break;
3458 case MII_NCONFIG: /* network interface config */
3459 break;
3460 default:
3461 break;
3462 }
3463 return rc;
3464 }
3465 EXPORT_SYMBOL_GPL(qeth_mdio_read);
3466
3467 static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
3468 struct qeth_cmd_buffer *iob, int len,
3469 int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
3470 unsigned long),
3471 void *reply_param)
3472 {
3473 u16 s1, s2;
3474
3475 QETH_DBF_TEXT(TRACE, 4, "sendsnmp");
3476
3477 memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
3478 memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
3479 &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
3480 /* adjust PDU length fields in IPA_PDU_HEADER */
3481 s1 = (u32) IPA_PDU_HEADER_SIZE + len;
3482 s2 = (u32) len;
3483 memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
3484 memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
3485 memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
3486 memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
3487 return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
3488 reply_cb, reply_param);
3489 }
3490
3491 static int qeth_snmp_command_cb(struct qeth_card *card,
3492 struct qeth_reply *reply, unsigned long sdata)
3493 {
3494 struct qeth_ipa_cmd *cmd;
3495 struct qeth_arp_query_info *qinfo;
3496 struct qeth_snmp_cmd *snmp;
3497 unsigned char *data;
3498 __u16 data_len;
3499
3500 QETH_DBF_TEXT(TRACE, 3, "snpcmdcb");
3501
3502 cmd = (struct qeth_ipa_cmd *) sdata;
3503 data = (unsigned char *)((char *)cmd - reply->offset);
3504 qinfo = (struct qeth_arp_query_info *) reply->param;
3505 snmp = &cmd->data.setadapterparms.data.snmp;
3506
3507 if (cmd->hdr.return_code) {
3508 QETH_DBF_TEXT_(TRACE, 4, "scer1%i", cmd->hdr.return_code);
3509 return 0;
3510 }
3511 if (cmd->data.setadapterparms.hdr.return_code) {
3512 cmd->hdr.return_code =
3513 cmd->data.setadapterparms.hdr.return_code;
3514 QETH_DBF_TEXT_(TRACE, 4, "scer2%i", cmd->hdr.return_code);
3515 return 0;
3516 }
3517 data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
3518 if (cmd->data.setadapterparms.hdr.seq_no == 1)
3519 data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
3520 else
3521 data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
3522
3523 /* check if there is enough room in userspace */
3524 if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
3525 QETH_DBF_TEXT_(TRACE, 4, "scer3%i", -ENOMEM);
3526 cmd->hdr.return_code = -ENOMEM;
3527 return 0;
3528 }
3529 QETH_DBF_TEXT_(TRACE, 4, "snore%i",
3530 cmd->data.setadapterparms.hdr.used_total);
3531 QETH_DBF_TEXT_(TRACE, 4, "sseqn%i",
3532 cmd->data.setadapterparms.hdr.seq_no);
3533 /*copy entries to user buffer*/
3534 if (cmd->data.setadapterparms.hdr.seq_no == 1) {
3535 memcpy(qinfo->udata + qinfo->udata_offset,
3536 (char *)snmp,
3537 data_len + offsetof(struct qeth_snmp_cmd, data));
3538 qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
3539 } else {
3540 memcpy(qinfo->udata + qinfo->udata_offset,
3541 (char *)&snmp->request, data_len);
3542 }
3543 qinfo->udata_offset += data_len;
3544 /* check if all replies received ... */
3545 QETH_DBF_TEXT_(TRACE, 4, "srtot%i",
3546 cmd->data.setadapterparms.hdr.used_total);
3547 QETH_DBF_TEXT_(TRACE, 4, "srseq%i",
3548 cmd->data.setadapterparms.hdr.seq_no);
3549 if (cmd->data.setadapterparms.hdr.seq_no <
3550 cmd->data.setadapterparms.hdr.used_total)
3551 return 1;
3552 return 0;
3553 }
3554
3555 int qeth_snmp_command(struct qeth_card *card, char __user *udata)
3556 {
3557 struct qeth_cmd_buffer *iob;
3558 struct qeth_ipa_cmd *cmd;
3559 struct qeth_snmp_ureq *ureq;
3560 int req_len;
3561 struct qeth_arp_query_info qinfo = {0, };
3562 int rc = 0;
3563
3564 QETH_DBF_TEXT(TRACE, 3, "snmpcmd");
3565
3566 if (card->info.guestlan)
3567 return -EOPNOTSUPP;
3568
3569 if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
3570 (!card->options.layer2)) {
3571 return -EOPNOTSUPP;
3572 }
3573 /* skip 4 bytes (data_len struct member) to get req_len */
3574 if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
3575 return -EFAULT;
3576 ureq = kmalloc(req_len+sizeof(struct qeth_snmp_ureq_hdr), GFP_KERNEL);
3577 if (!ureq) {
3578 QETH_DBF_TEXT(TRACE, 2, "snmpnome");
3579 return -ENOMEM;
3580 }
3581 if (copy_from_user(ureq, udata,
3582 req_len + sizeof(struct qeth_snmp_ureq_hdr))) {
3583 kfree(ureq);
3584 return -EFAULT;
3585 }
3586 qinfo.udata_len = ureq->hdr.data_len;
3587 qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
3588 if (!qinfo.udata) {
3589 kfree(ureq);
3590 return -ENOMEM;
3591 }
3592 qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
3593
3594 iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
3595 QETH_SNMP_SETADP_CMDLENGTH + req_len);
3596 cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
3597 memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
3598 rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
3599 qeth_snmp_command_cb, (void *)&qinfo);
3600 if (rc)
3601 QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
3602 QETH_CARD_IFNAME(card), rc);
3603 else {
3604 if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
3605 rc = -EFAULT;
3606 }
3607
3608 kfree(ureq);
3609 kfree(qinfo.udata);
3610 return rc;
3611 }
3612 EXPORT_SYMBOL_GPL(qeth_snmp_command);
3613
3614 static inline int qeth_get_qdio_q_format(struct qeth_card *card)
3615 {
3616 switch (card->info.type) {
3617 case QETH_CARD_TYPE_IQD:
3618 return 2;
3619 default:
3620 return 0;
3621 }
3622 }
3623
3624 static int qeth_qdio_establish(struct qeth_card *card)
3625 {
3626 struct qdio_initialize init_data;
3627 char *qib_param_field;
3628 struct qdio_buffer **in_sbal_ptrs;
3629 struct qdio_buffer **out_sbal_ptrs;
3630 int i, j, k;
3631 int rc = 0;
3632
3633 QETH_DBF_TEXT(SETUP, 2, "qdioest");
3634
3635 qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
3636 GFP_KERNEL);
3637 if (!qib_param_field)
3638 return -ENOMEM;
3639
3640 qeth_create_qib_param_field(card, qib_param_field);
3641 qeth_create_qib_param_field_blkt(card, qib_param_field);
3642
3643 in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
3644 GFP_KERNEL);
3645 if (!in_sbal_ptrs) {
3646 kfree(qib_param_field);
3647 return -ENOMEM;
3648 }
3649 for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
3650 in_sbal_ptrs[i] = (struct qdio_buffer *)
3651 virt_to_phys(card->qdio.in_q->bufs[i].buffer);
3652
3653 out_sbal_ptrs =
3654 kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
3655 sizeof(void *), GFP_KERNEL);
3656 if (!out_sbal_ptrs) {
3657 kfree(in_sbal_ptrs);
3658 kfree(qib_param_field);
3659 return -ENOMEM;
3660 }
3661 for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
3662 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
3663 out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
3664 card->qdio.out_qs[i]->bufs[j].buffer);
3665 }
3666
3667 memset(&init_data, 0, sizeof(struct qdio_initialize));
3668 init_data.cdev = CARD_DDEV(card);
3669 init_data.q_format = qeth_get_qdio_q_format(card);
3670 init_data.qib_param_field_format = 0;
3671 init_data.qib_param_field = qib_param_field;
3672 init_data.no_input_qs = 1;
3673 init_data.no_output_qs = card->qdio.no_out_queues;
3674 init_data.input_handler = card->discipline.input_handler;
3675 init_data.output_handler = card->discipline.output_handler;
3676 init_data.int_parm = (unsigned long) card;
3677 init_data.flags = QDIO_INBOUND_0COPY_SBALS |
3678 QDIO_OUTBOUND_0COPY_SBALS |
3679 QDIO_USE_OUTBOUND_PCIS;
3680 init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
3681 init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
3682
3683 if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
3684 QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
3685 rc = qdio_initialize(&init_data);
3686 if (rc)
3687 atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
3688 }
3689 kfree(out_sbal_ptrs);
3690 kfree(in_sbal_ptrs);
3691 kfree(qib_param_field);
3692 return rc;
3693 }
3694
3695 static void qeth_core_free_card(struct qeth_card *card)
3696 {
3697
3698 QETH_DBF_TEXT(SETUP, 2, "freecrd");
3699 QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
3700 qeth_clean_channel(&card->read);
3701 qeth_clean_channel(&card->write);
3702 if (card->dev)
3703 free_netdev(card->dev);
3704 kfree(card->ip_tbd_list);
3705 qeth_free_qdio_buffers(card);
3706 unregister_service_level(&card->qeth_service_level);
3707 kfree(card);
3708 }
3709
3710 static struct ccw_device_id qeth_ids[] = {
3711 {CCW_DEVICE(0x1731, 0x01), .driver_info = QETH_CARD_TYPE_OSAE},
3712 {CCW_DEVICE(0x1731, 0x05), .driver_info = QETH_CARD_TYPE_IQD},
3713 {CCW_DEVICE(0x1731, 0x06), .driver_info = QETH_CARD_TYPE_OSN},
3714 {},
3715 };
3716 MODULE_DEVICE_TABLE(ccw, qeth_ids);
3717
3718 static struct ccw_driver qeth_ccw_driver = {
3719 .name = "qeth",
3720 .ids = qeth_ids,
3721 .probe = ccwgroup_probe_ccwdev,
3722 .remove = ccwgroup_remove_ccwdev,
3723 };
3724
3725 static int qeth_core_driver_group(const char *buf, struct device *root_dev,
3726 unsigned long driver_id)
3727 {
3728 return ccwgroup_create_from_string(root_dev, driver_id,
3729 &qeth_ccw_driver, 3, buf);
3730 }
3731
3732 int qeth_core_hardsetup_card(struct qeth_card *card)
3733 {
3734 struct qdio_ssqd_desc *ssqd;
3735 int retries = 3;
3736 int mpno = 0;
3737 int rc;
3738
3739 QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
3740 atomic_set(&card->force_alloc_skb, 0);
3741 retry:
3742 if (retries < 3) {
3743 QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n",
3744 dev_name(&card->gdev->dev));
3745 ccw_device_set_offline(CARD_DDEV(card));
3746 ccw_device_set_offline(CARD_WDEV(card));
3747 ccw_device_set_offline(CARD_RDEV(card));
3748 ccw_device_set_online(CARD_RDEV(card));
3749 ccw_device_set_online(CARD_WDEV(card));
3750 ccw_device_set_online(CARD_DDEV(card));
3751 }
3752 rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
3753 if (rc == -ERESTARTSYS) {
3754 QETH_DBF_TEXT(SETUP, 2, "break1");
3755 return rc;
3756 } else if (rc) {
3757 QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
3758 if (--retries < 0)
3759 goto out;
3760 else
3761 goto retry;
3762 }
3763
3764 rc = qeth_get_unitaddr(card);
3765 if (rc) {
3766 QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
3767 return rc;
3768 }
3769
3770 ssqd = kmalloc(sizeof(struct qdio_ssqd_desc), GFP_KERNEL);
3771 if (!ssqd) {
3772 rc = -ENOMEM;
3773 goto out;
3774 }
3775 rc = qdio_get_ssqd_desc(CARD_DDEV(card), ssqd);
3776 if (rc == 0)
3777 mpno = ssqd->pcnt;
3778 kfree(ssqd);
3779
3780 if (mpno)
3781 mpno = min(mpno - 1, QETH_MAX_PORTNO);
3782 if (card->info.portno > mpno) {
3783 QETH_DBF_MESSAGE(2, "Device %s does not offer port number %d"
3784 "\n.", CARD_BUS_ID(card), card->info.portno);
3785 rc = -ENODEV;
3786 goto out;
3787 }
3788 qeth_init_tokens(card);
3789 qeth_init_func_level(card);
3790 rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
3791 if (rc == -ERESTARTSYS) {
3792 QETH_DBF_TEXT(SETUP, 2, "break2");
3793 return rc;
3794 } else if (rc) {
3795 QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
3796 if (--retries < 0)
3797 goto out;
3798 else
3799 goto retry;
3800 }
3801 rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
3802 if (rc == -ERESTARTSYS) {
3803 QETH_DBF_TEXT(SETUP, 2, "break3");
3804 return rc;
3805 } else if (rc) {
3806 QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
3807 if (--retries < 0)
3808 goto out;
3809 else
3810 goto retry;
3811 }
3812 rc = qeth_mpc_initialize(card);
3813 if (rc) {
3814 QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
3815 goto out;
3816 }
3817 return 0;
3818 out:
3819 dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "
3820 "an error on the device\n");
3821 QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n",
3822 dev_name(&card->gdev->dev), rc);
3823 return rc;
3824 }
3825 EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
3826
3827 static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
3828 struct sk_buff **pskb, int offset, int *pfrag, int data_len)
3829 {
3830 struct page *page = virt_to_page(element->addr);
3831 if (*pskb == NULL) {
3832 /* the upper protocol layers assume that there is data in the
3833 * skb itself. Copy a small amount (64 bytes) to make them
3834 * happy. */
3835 *pskb = dev_alloc_skb(64 + ETH_HLEN);
3836 if (!(*pskb))
3837 return -ENOMEM;
3838 skb_reserve(*pskb, ETH_HLEN);
3839 if (data_len <= 64) {
3840 memcpy(skb_put(*pskb, data_len), element->addr + offset,
3841 data_len);
3842 } else {
3843 get_page(page);
3844 memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
3845 skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
3846 data_len - 64);
3847 (*pskb)->data_len += data_len - 64;
3848 (*pskb)->len += data_len - 64;
3849 (*pskb)->truesize += data_len - 64;
3850 (*pfrag)++;
3851 }
3852 } else {
3853 get_page(page);
3854 skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
3855 (*pskb)->data_len += data_len;
3856 (*pskb)->len += data_len;
3857 (*pskb)->truesize += data_len;
3858 (*pfrag)++;
3859 }
3860 return 0;
3861 }
3862
3863 struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
3864 struct qdio_buffer *buffer,
3865 struct qdio_buffer_element **__element, int *__offset,
3866 struct qeth_hdr **hdr)
3867 {
3868 struct qdio_buffer_element *element = *__element;
3869 int offset = *__offset;
3870 struct sk_buff *skb = NULL;
3871 int skb_len;
3872 void *data_ptr;
3873 int data_len;
3874 int headroom = 0;
3875 int use_rx_sg = 0;
3876 int frag = 0;
3877
3878 /* qeth_hdr must not cross element boundaries */
3879 if (element->length < offset + sizeof(struct qeth_hdr)) {
3880 if (qeth_is_last_sbale(element))
3881 return NULL;
3882 element++;
3883 offset = 0;
3884 if (element->length < sizeof(struct qeth_hdr))
3885 return NULL;
3886 }
3887 *hdr = element->addr + offset;
3888
3889 offset += sizeof(struct qeth_hdr);
3890 if (card->options.layer2) {
3891 if (card->info.type == QETH_CARD_TYPE_OSN) {
3892 skb_len = (*hdr)->hdr.osn.pdu_length;
3893 headroom = sizeof(struct qeth_hdr);
3894 } else {
3895 skb_len = (*hdr)->hdr.l2.pkt_length;
3896 }
3897 } else {
3898 skb_len = (*hdr)->hdr.l3.length;
3899 if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
3900 (card->info.link_type == QETH_LINK_TYPE_HSTR))
3901 headroom = TR_HLEN;
3902 else
3903 headroom = ETH_HLEN;
3904 }
3905
3906 if (!skb_len)
3907 return NULL;
3908
3909 if ((skb_len >= card->options.rx_sg_cb) &&
3910 (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
3911 (!atomic_read(&card->force_alloc_skb))) {
3912 use_rx_sg = 1;
3913 } else {
3914 skb = dev_alloc_skb(skb_len + headroom);
3915 if (!skb)
3916 goto no_mem;
3917 if (headroom)
3918 skb_reserve(skb, headroom);
3919 }
3920
3921 data_ptr = element->addr + offset;
3922 while (skb_len) {
3923 data_len = min(skb_len, (int)(element->length - offset));
3924 if (data_len) {
3925 if (use_rx_sg) {
3926 if (qeth_create_skb_frag(element, &skb, offset,
3927 &frag, data_len))
3928 goto no_mem;
3929 } else {
3930 memcpy(skb_put(skb, data_len), data_ptr,
3931 data_len);
3932 }
3933 }
3934 skb_len -= data_len;
3935 if (skb_len) {
3936 if (qeth_is_last_sbale(element)) {
3937 QETH_DBF_TEXT(TRACE, 4, "unexeob");
3938 QETH_DBF_TEXT_(TRACE, 4, "%s",
3939 CARD_BUS_ID(card));
3940 QETH_DBF_TEXT(QERR, 2, "unexeob");
3941 QETH_DBF_TEXT_(QERR, 2, "%s",
3942 CARD_BUS_ID(card));
3943 QETH_DBF_HEX(MISC, 4, buffer, sizeof(*buffer));
3944 dev_kfree_skb_any(skb);
3945 card->stats.rx_errors++;
3946 return NULL;
3947 }
3948 element++;
3949 offset = 0;
3950 data_ptr = element->addr;
3951 } else {
3952 offset += data_len;
3953 }
3954 }
3955 *__element = element;
3956 *__offset = offset;
3957 if (use_rx_sg && card->options.performance_stats) {
3958 card->perf_stats.sg_skbs_rx++;
3959 card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
3960 }
3961 return skb;
3962 no_mem:
3963 if (net_ratelimit()) {
3964 QETH_DBF_TEXT(TRACE, 2, "noskbmem");
3965 QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
3966 }
3967 card->stats.rx_dropped++;
3968 return NULL;
3969 }
3970 EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
3971
3972 static void qeth_unregister_dbf_views(void)
3973 {
3974 int x;
3975 for (x = 0; x < QETH_DBF_INFOS; x++) {
3976 debug_unregister(qeth_dbf[x].id);
3977 qeth_dbf[x].id = NULL;
3978 }
3979 }
3980
3981 void qeth_dbf_longtext(enum qeth_dbf_names dbf_nix, int level, char *fmt, ...)
3982 {
3983 char dbf_txt_buf[32];
3984 va_list args;
3985
3986 if (level > (qeth_dbf[dbf_nix].id)->level)
3987 return;
3988 va_start(args, fmt);
3989 vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
3990 va_end(args);
3991 debug_text_event(qeth_dbf[dbf_nix].id, level, dbf_txt_buf);
3992 }
3993 EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
3994
3995 static int qeth_register_dbf_views(void)
3996 {
3997 int ret;
3998 int x;
3999
4000 for (x = 0; x < QETH_DBF_INFOS; x++) {
4001 /* register the areas */
4002 qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
4003 qeth_dbf[x].pages,
4004 qeth_dbf[x].areas,
4005 qeth_dbf[x].len);
4006 if (qeth_dbf[x].id == NULL) {
4007 qeth_unregister_dbf_views();
4008 return -ENOMEM;
4009 }
4010
4011 /* register a view */
4012 ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
4013 if (ret) {
4014 qeth_unregister_dbf_views();
4015 return ret;
4016 }
4017
4018 /* set a passing level */
4019 debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
4020 }
4021
4022 return 0;
4023 }
4024
4025 int qeth_core_load_discipline(struct qeth_card *card,
4026 enum qeth_discipline_id discipline)
4027 {
4028 int rc = 0;
4029 switch (discipline) {
4030 case QETH_DISCIPLINE_LAYER3:
4031 card->discipline.ccwgdriver = try_then_request_module(
4032 symbol_get(qeth_l3_ccwgroup_driver),
4033 "qeth_l3");
4034 break;
4035 case QETH_DISCIPLINE_LAYER2:
4036 card->discipline.ccwgdriver = try_then_request_module(
4037 symbol_get(qeth_l2_ccwgroup_driver),
4038 "qeth_l2");
4039 break;
4040 }
4041 if (!card->discipline.ccwgdriver) {
4042 dev_err(&card->gdev->dev, "There is no kernel module to "
4043 "support discipline %d\n", discipline);
4044 rc = -EINVAL;
4045 }
4046 return rc;
4047 }
4048
4049 void qeth_core_free_discipline(struct qeth_card *card)
4050 {
4051 if (card->options.layer2)
4052 symbol_put(qeth_l2_ccwgroup_driver);
4053 else
4054 symbol_put(qeth_l3_ccwgroup_driver);
4055 card->discipline.ccwgdriver = NULL;
4056 }
4057
4058 static int qeth_core_probe_device(struct ccwgroup_device *gdev)
4059 {
4060 struct qeth_card *card;
4061 struct device *dev;
4062 int rc;
4063 unsigned long flags;
4064
4065 QETH_DBF_TEXT(SETUP, 2, "probedev");
4066
4067 dev = &gdev->dev;
4068 if (!get_device(dev))
4069 return -ENODEV;
4070
4071 QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
4072
4073 card = qeth_alloc_card();
4074 if (!card) {
4075 QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
4076 rc = -ENOMEM;
4077 goto err_dev;
4078 }
4079 card->read.ccwdev = gdev->cdev[0];
4080 card->write.ccwdev = gdev->cdev[1];
4081 card->data.ccwdev = gdev->cdev[2];
4082 dev_set_drvdata(&gdev->dev, card);
4083 card->gdev = gdev;
4084 gdev->cdev[0]->handler = qeth_irq;
4085 gdev->cdev[1]->handler = qeth_irq;
4086 gdev->cdev[2]->handler = qeth_irq;
4087
4088 rc = qeth_determine_card_type(card);
4089 if (rc) {
4090 QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
4091 goto err_card;
4092 }
4093 rc = qeth_setup_card(card);
4094 if (rc) {
4095 QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
4096 goto err_card;
4097 }
4098
4099 if (card->info.type == QETH_CARD_TYPE_OSN) {
4100 rc = qeth_core_create_osn_attributes(dev);
4101 if (rc)
4102 goto err_card;
4103 rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
4104 if (rc) {
4105 qeth_core_remove_osn_attributes(dev);
4106 goto err_card;
4107 }
4108 rc = card->discipline.ccwgdriver->probe(card->gdev);
4109 if (rc) {
4110 qeth_core_free_discipline(card);
4111 qeth_core_remove_osn_attributes(dev);
4112 goto err_card;
4113 }
4114 } else {
4115 rc = qeth_core_create_device_attributes(dev);
4116 if (rc)
4117 goto err_card;
4118 }
4119
4120 write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
4121 list_add_tail(&card->list, &qeth_core_card_list.list);
4122 write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
4123 return 0;
4124
4125 err_card:
4126 qeth_core_free_card(card);
4127 err_dev:
4128 put_device(dev);
4129 return rc;
4130 }
4131
4132 static void qeth_core_remove_device(struct ccwgroup_device *gdev)
4133 {
4134 unsigned long flags;
4135 struct qeth_card *card = dev_get_drvdata(&gdev->dev);
4136
4137 QETH_DBF_TEXT(SETUP, 2, "removedv");
4138 if (card->discipline.ccwgdriver) {
4139 card->discipline.ccwgdriver->remove(gdev);
4140 qeth_core_free_discipline(card);
4141 }
4142
4143 if (card->info.type == QETH_CARD_TYPE_OSN) {
4144 qeth_core_remove_osn_attributes(&gdev->dev);
4145 } else {
4146 qeth_core_remove_device_attributes(&gdev->dev);
4147 }
4148 write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
4149 list_del(&card->list);
4150 write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
4151 qeth_core_free_card(card);
4152 dev_set_drvdata(&gdev->dev, NULL);
4153 put_device(&gdev->dev);
4154 return;
4155 }
4156
4157 static int qeth_core_set_online(struct ccwgroup_device *gdev)
4158 {
4159 struct qeth_card *card = dev_get_drvdata(&gdev->dev);
4160 int rc = 0;
4161 int def_discipline;
4162
4163 if (!card->discipline.ccwgdriver) {
4164 if (card->info.type == QETH_CARD_TYPE_IQD)
4165 def_discipline = QETH_DISCIPLINE_LAYER3;
4166 else
4167 def_discipline = QETH_DISCIPLINE_LAYER2;
4168 rc = qeth_core_load_discipline(card, def_discipline);
4169 if (rc)
4170 goto err;
4171 rc = card->discipline.ccwgdriver->probe(card->gdev);
4172 if (rc)
4173 goto err;
4174 }
4175 rc = card->discipline.ccwgdriver->set_online(gdev);
4176 err:
4177 return rc;
4178 }
4179
4180 static int qeth_core_set_offline(struct ccwgroup_device *gdev)
4181 {
4182 struct qeth_card *card = dev_get_drvdata(&gdev->dev);
4183 return card->discipline.ccwgdriver->set_offline(gdev);
4184 }
4185
4186 static void qeth_core_shutdown(struct ccwgroup_device *gdev)
4187 {
4188 struct qeth_card *card = dev_get_drvdata(&gdev->dev);
4189 if (card->discipline.ccwgdriver &&
4190 card->discipline.ccwgdriver->shutdown)
4191 card->discipline.ccwgdriver->shutdown(gdev);
4192 }
4193
4194 static int qeth_core_prepare(struct ccwgroup_device *gdev)
4195 {
4196 struct qeth_card *card = dev_get_drvdata(&gdev->dev);
4197 if (card->discipline.ccwgdriver &&
4198 card->discipline.ccwgdriver->prepare)
4199 return card->discipline.ccwgdriver->prepare(gdev);
4200 return 0;
4201 }
4202
4203 static void qeth_core_complete(struct ccwgroup_device *gdev)
4204 {
4205 struct qeth_card *card = dev_get_drvdata(&gdev->dev);
4206 if (card->discipline.ccwgdriver &&
4207 card->discipline.ccwgdriver->complete)
4208 card->discipline.ccwgdriver->complete(gdev);
4209 }
4210
4211 static int qeth_core_freeze(struct ccwgroup_device *gdev)
4212 {
4213 struct qeth_card *card = dev_get_drvdata(&gdev->dev);
4214 if (card->discipline.ccwgdriver &&
4215 card->discipline.ccwgdriver->freeze)
4216 return card->discipline.ccwgdriver->freeze(gdev);
4217 return 0;
4218 }
4219
4220 static int qeth_core_thaw(struct ccwgroup_device *gdev)
4221 {
4222 struct qeth_card *card = dev_get_drvdata(&gdev->dev);
4223 if (card->discipline.ccwgdriver &&
4224 card->discipline.ccwgdriver->thaw)
4225 return card->discipline.ccwgdriver->thaw(gdev);
4226 return 0;
4227 }
4228
4229 static int qeth_core_restore(struct ccwgroup_device *gdev)
4230 {
4231 struct qeth_card *card = dev_get_drvdata(&gdev->dev);
4232 if (card->discipline.ccwgdriver &&
4233 card->discipline.ccwgdriver->restore)
4234 return card->discipline.ccwgdriver->restore(gdev);
4235 return 0;
4236 }
4237
4238 static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
4239 .owner = THIS_MODULE,
4240 .name = "qeth",
4241 .driver_id = 0xD8C5E3C8,
4242 .probe = qeth_core_probe_device,
4243 .remove = qeth_core_remove_device,
4244 .set_online = qeth_core_set_online,
4245 .set_offline = qeth_core_set_offline,
4246 .shutdown = qeth_core_shutdown,
4247 .prepare = qeth_core_prepare,
4248 .complete = qeth_core_complete,
4249 .freeze = qeth_core_freeze,
4250 .thaw = qeth_core_thaw,
4251 .restore = qeth_core_restore,
4252 };
4253
4254 static ssize_t
4255 qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
4256 size_t count)
4257 {
4258 int err;
4259 err = qeth_core_driver_group(buf, qeth_core_root_dev,
4260 qeth_core_ccwgroup_driver.driver_id);
4261 if (err)
4262 return err;
4263 else
4264 return count;
4265 }
4266
4267 static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
4268
4269 static struct {
4270 const char str[ETH_GSTRING_LEN];
4271 } qeth_ethtool_stats_keys[] = {
4272 /* 0 */{"rx skbs"},
4273 {"rx buffers"},
4274 {"tx skbs"},
4275 {"tx buffers"},
4276 {"tx skbs no packing"},
4277 {"tx buffers no packing"},
4278 {"tx skbs packing"},
4279 {"tx buffers packing"},
4280 {"tx sg skbs"},
4281 {"tx sg frags"},
4282 /* 10 */{"rx sg skbs"},
4283 {"rx sg frags"},
4284 {"rx sg page allocs"},
4285 {"tx large kbytes"},
4286 {"tx large count"},
4287 {"tx pk state ch n->p"},
4288 {"tx pk state ch p->n"},
4289 {"tx pk watermark low"},
4290 {"tx pk watermark high"},
4291 {"queue 0 buffer usage"},
4292 /* 20 */{"queue 1 buffer usage"},
4293 {"queue 2 buffer usage"},
4294 {"queue 3 buffer usage"},
4295 {"rx handler time"},
4296 {"rx handler count"},
4297 {"rx do_QDIO time"},
4298 {"rx do_QDIO count"},
4299 {"tx handler time"},
4300 {"tx handler count"},
4301 {"tx time"},
4302 /* 30 */{"tx count"},
4303 {"tx do_QDIO time"},
4304 {"tx do_QDIO count"},
4305 {"tx csum"},
4306 };
4307
4308 int qeth_core_get_stats_count(struct net_device *dev)
4309 {
4310 return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
4311 }
4312 EXPORT_SYMBOL_GPL(qeth_core_get_stats_count);
4313
4314 void qeth_core_get_ethtool_stats(struct net_device *dev,
4315 struct ethtool_stats *stats, u64 *data)
4316 {
4317 struct qeth_card *card = dev->ml_priv;
4318 data[0] = card->stats.rx_packets -
4319 card->perf_stats.initial_rx_packets;
4320 data[1] = card->perf_stats.bufs_rec;
4321 data[2] = card->stats.tx_packets -
4322 card->perf_stats.initial_tx_packets;
4323 data[3] = card->perf_stats.bufs_sent;
4324 data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
4325 - card->perf_stats.skbs_sent_pack;
4326 data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
4327 data[6] = card->perf_stats.skbs_sent_pack;
4328 data[7] = card->perf_stats.bufs_sent_pack;
4329 data[8] = card->perf_stats.sg_skbs_sent;
4330 data[9] = card->perf_stats.sg_frags_sent;
4331 data[10] = card->perf_stats.sg_skbs_rx;
4332 data[11] = card->perf_stats.sg_frags_rx;
4333 data[12] = card->perf_stats.sg_alloc_page_rx;
4334 data[13] = (card->perf_stats.large_send_bytes >> 10);
4335 data[14] = card->perf_stats.large_send_cnt;
4336 data[15] = card->perf_stats.sc_dp_p;
4337 data[16] = card->perf_stats.sc_p_dp;
4338 data[17] = QETH_LOW_WATERMARK_PACK;
4339 data[18] = QETH_HIGH_WATERMARK_PACK;
4340 data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
4341 data[20] = (card->qdio.no_out_queues > 1) ?
4342 atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
4343 data[21] = (card->qdio.no_out_queues > 2) ?
4344 atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
4345 data[22] = (card->qdio.no_out_queues > 3) ?
4346 atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
4347 data[23] = card->perf_stats.inbound_time;
4348 data[24] = card->perf_stats.inbound_cnt;
4349 data[25] = card->perf_stats.inbound_do_qdio_time;
4350 data[26] = card->perf_stats.inbound_do_qdio_cnt;
4351 data[27] = card->perf_stats.outbound_handler_time;
4352 data[28] = card->perf_stats.outbound_handler_cnt;
4353 data[29] = card->perf_stats.outbound_time;
4354 data[30] = card->perf_stats.outbound_cnt;
4355 data[31] = card->perf_stats.outbound_do_qdio_time;
4356 data[32] = card->perf_stats.outbound_do_qdio_cnt;
4357 data[33] = card->perf_stats.tx_csum;
4358 }
4359 EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
4360
4361 void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4362 {
4363 switch (stringset) {
4364 case ETH_SS_STATS:
4365 memcpy(data, &qeth_ethtool_stats_keys,
4366 sizeof(qeth_ethtool_stats_keys));
4367 break;
4368 default:
4369 WARN_ON(1);
4370 break;
4371 }
4372 }
4373 EXPORT_SYMBOL_GPL(qeth_core_get_strings);
4374
4375 void qeth_core_get_drvinfo(struct net_device *dev,
4376 struct ethtool_drvinfo *info)
4377 {
4378 struct qeth_card *card = dev->ml_priv;
4379 if (card->options.layer2)
4380 strcpy(info->driver, "qeth_l2");
4381 else
4382 strcpy(info->driver, "qeth_l3");
4383
4384 strcpy(info->version, "1.0");
4385 strcpy(info->fw_version, card->info.mcl_level);
4386 sprintf(info->bus_info, "%s/%s/%s",
4387 CARD_RDEV_ID(card),
4388 CARD_WDEV_ID(card),
4389 CARD_DDEV_ID(card));
4390 }
4391 EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
4392
4393 int qeth_core_ethtool_get_settings(struct net_device *netdev,
4394 struct ethtool_cmd *ecmd)
4395 {
4396 struct qeth_card *card = netdev->ml_priv;
4397 enum qeth_link_types link_type;
4398
4399 if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
4400 link_type = QETH_LINK_TYPE_10GBIT_ETH;
4401 else
4402 link_type = card->info.link_type;
4403
4404 ecmd->transceiver = XCVR_INTERNAL;
4405 ecmd->supported = SUPPORTED_Autoneg;
4406 ecmd->advertising = ADVERTISED_Autoneg;
4407 ecmd->duplex = DUPLEX_FULL;
4408 ecmd->autoneg = AUTONEG_ENABLE;
4409
4410 switch (link_type) {
4411 case QETH_LINK_TYPE_FAST_ETH:
4412 case QETH_LINK_TYPE_LANE_ETH100:
4413 ecmd->supported |= SUPPORTED_10baseT_Half |
4414 SUPPORTED_10baseT_Full |
4415 SUPPORTED_100baseT_Half |
4416 SUPPORTED_100baseT_Full |
4417 SUPPORTED_TP;
4418 ecmd->advertising |= ADVERTISED_10baseT_Half |
4419 ADVERTISED_10baseT_Full |
4420 ADVERTISED_100baseT_Half |
4421 ADVERTISED_100baseT_Full |
4422 ADVERTISED_TP;
4423 ecmd->speed = SPEED_100;
4424 ecmd->port = PORT_TP;
4425 break;
4426
4427 case QETH_LINK_TYPE_GBIT_ETH:
4428 case QETH_LINK_TYPE_LANE_ETH1000:
4429 ecmd->supported |= SUPPORTED_10baseT_Half |
4430 SUPPORTED_10baseT_Full |
4431 SUPPORTED_100baseT_Half |
4432 SUPPORTED_100baseT_Full |
4433 SUPPORTED_1000baseT_Half |
4434 SUPPORTED_1000baseT_Full |
4435 SUPPORTED_FIBRE;
4436 ecmd->advertising |= ADVERTISED_10baseT_Half |
4437 ADVERTISED_10baseT_Full |
4438 ADVERTISED_100baseT_Half |
4439 ADVERTISED_100baseT_Full |
4440 ADVERTISED_1000baseT_Half |
4441 ADVERTISED_1000baseT_Full |
4442 ADVERTISED_FIBRE;
4443 ecmd->speed = SPEED_1000;
4444 ecmd->port = PORT_FIBRE;
4445 break;
4446
4447 case QETH_LINK_TYPE_10GBIT_ETH:
4448 ecmd->supported |= SUPPORTED_10baseT_Half |
4449 SUPPORTED_10baseT_Full |
4450 SUPPORTED_100baseT_Half |
4451 SUPPORTED_100baseT_Full |
4452 SUPPORTED_1000baseT_Half |
4453 SUPPORTED_1000baseT_Full |
4454 SUPPORTED_10000baseT_Full |
4455 SUPPORTED_FIBRE;
4456 ecmd->advertising |= ADVERTISED_10baseT_Half |
4457 ADVERTISED_10baseT_Full |
4458 ADVERTISED_100baseT_Half |
4459 ADVERTISED_100baseT_Full |
4460 ADVERTISED_1000baseT_Half |
4461 ADVERTISED_1000baseT_Full |
4462 ADVERTISED_10000baseT_Full |
4463 ADVERTISED_FIBRE;
4464 ecmd->speed = SPEED_10000;
4465 ecmd->port = PORT_FIBRE;
4466 break;
4467
4468 default:
4469 ecmd->supported |= SUPPORTED_10baseT_Half |
4470 SUPPORTED_10baseT_Full |
4471 SUPPORTED_TP;
4472 ecmd->advertising |= ADVERTISED_10baseT_Half |
4473 ADVERTISED_10baseT_Full |
4474 ADVERTISED_TP;
4475 ecmd->speed = SPEED_10;
4476 ecmd->port = PORT_TP;
4477 }
4478
4479 return 0;
4480 }
4481 EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
4482
4483 static int __init qeth_core_init(void)
4484 {
4485 int rc;
4486
4487 pr_info("loading core functions\n");
4488 INIT_LIST_HEAD(&qeth_core_card_list.list);
4489 rwlock_init(&qeth_core_card_list.rwlock);
4490
4491 rc = qeth_register_dbf_views();
4492 if (rc)
4493 goto out_err;
4494 rc = ccw_driver_register(&qeth_ccw_driver);
4495 if (rc)
4496 goto ccw_err;
4497 rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
4498 if (rc)
4499 goto ccwgroup_err;
4500 rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
4501 &driver_attr_group);
4502 if (rc)
4503 goto driver_err;
4504 qeth_core_root_dev = root_device_register("qeth");
4505 rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
4506 if (rc)
4507 goto register_err;
4508
4509 qeth_core_header_cache = kmem_cache_create("qeth_hdr",
4510 sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
4511 if (!qeth_core_header_cache) {
4512 rc = -ENOMEM;
4513 goto slab_err;
4514 }
4515
4516 return 0;
4517 slab_err:
4518 root_device_unregister(qeth_core_root_dev);
4519 register_err:
4520 driver_remove_file(&qeth_core_ccwgroup_driver.driver,
4521 &driver_attr_group);
4522 driver_err:
4523 ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
4524 ccwgroup_err:
4525 ccw_driver_unregister(&qeth_ccw_driver);
4526 ccw_err:
4527 QETH_DBF_MESSAGE(2, "Initialization failed with code %d\n", rc);
4528 qeth_unregister_dbf_views();
4529 out_err:
4530 pr_err("Initializing the qeth device driver failed\n");
4531 return rc;
4532 }
4533
4534 static void __exit qeth_core_exit(void)
4535 {
4536 root_device_unregister(qeth_core_root_dev);
4537 driver_remove_file(&qeth_core_ccwgroup_driver.driver,
4538 &driver_attr_group);
4539 ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
4540 ccw_driver_unregister(&qeth_ccw_driver);
4541 kmem_cache_destroy(qeth_core_header_cache);
4542 qeth_unregister_dbf_views();
4543 pr_info("core functions removed\n");
4544 }
4545
4546 module_init(qeth_core_init);
4547 module_exit(qeth_core_exit);
4548 MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
4549 MODULE_DESCRIPTION("qeth core functions");
4550 MODULE_LICENSE("GPL");
Support for the Chinese Samsung S3C2440 based development boards