2 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 #include <linux/config.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/linkage.h>
22 #include <linux/interrupt.h>
23 #include <linux/spinlock.h>
24 #include <linux/smp.h>
26 #include <linux/slab.h>
27 #include <linux/kernel_stat.h>
29 #include <asm/errno.h>
30 #include <asm/signal.h>
31 #include <asm/system.h>
32 #include <asm/ptrace.h>
35 #include <asm/sibyte/sb1250_regs.h>
36 #include <asm/sibyte/sb1250_int.h>
37 #include <asm/sibyte/sb1250_uart.h>
38 #include <asm/sibyte/sb1250_scd.h>
39 #include <asm/sibyte/sb1250.h>
42 * These are the routines that handle all the low level interrupt stuff.
43 * Actions handled here are: initialization of the interrupt map, requesting of
44 * interrupt lines by handlers, dispatching if interrupts to handlers, probing
49 #define shutdown_sb1250_irq disable_sb1250_irq
50 static void end_sb1250_irq(unsigned int irq
);
51 static void enable_sb1250_irq(unsigned int irq
);
52 static void disable_sb1250_irq(unsigned int irq
);
53 static unsigned int startup_sb1250_irq(unsigned int irq
);
54 static void ack_sb1250_irq(unsigned int irq
);
56 static void sb1250_set_affinity(unsigned int irq
, cpumask_t mask
);
59 #ifdef CONFIG_SIBYTE_HAS_LDT
60 extern unsigned long ldt_eoi_space
;
66 /* Default to UART1 */
68 #ifdef CONFIG_SIBYTE_SB1250_DUART
69 extern char sb1250_duart_present
[];
73 static struct hw_interrupt_type sb1250_irq_type
= {
74 .typename
= "SB1250-IMR",
75 .startup
= startup_sb1250_irq
,
76 .shutdown
= shutdown_sb1250_irq
,
77 .enable
= enable_sb1250_irq
,
78 .disable
= disable_sb1250_irq
,
79 .ack
= ack_sb1250_irq
,
80 .end
= end_sb1250_irq
,
82 .set_affinity
= sb1250_set_affinity
86 /* Store the CPU id (not the logical number) */
87 int sb1250_irq_owner
[SB1250_NR_IRQS
];
89 DEFINE_SPINLOCK(sb1250_imr_lock
);
91 void sb1250_mask_irq(int cpu
, int irq
)
96 spin_lock_irqsave(&sb1250_imr_lock
, flags
);
97 cur_ints
= ____raw_readq(IOADDR(A_IMR_MAPPER(cpu
) +
98 R_IMR_INTERRUPT_MASK
));
99 cur_ints
|= (((u64
) 1) << irq
);
100 ____raw_writeq(cur_ints
, IOADDR(A_IMR_MAPPER(cpu
) +
101 R_IMR_INTERRUPT_MASK
));
102 spin_unlock_irqrestore(&sb1250_imr_lock
, flags
);
105 void sb1250_unmask_irq(int cpu
, int irq
)
110 spin_lock_irqsave(&sb1250_imr_lock
, flags
);
111 cur_ints
= ____raw_readq(IOADDR(A_IMR_MAPPER(cpu
) +
112 R_IMR_INTERRUPT_MASK
));
113 cur_ints
&= ~(((u64
) 1) << irq
);
114 ____raw_writeq(cur_ints
, IOADDR(A_IMR_MAPPER(cpu
) +
115 R_IMR_INTERRUPT_MASK
));
116 spin_unlock_irqrestore(&sb1250_imr_lock
, flags
);
120 static void sb1250_set_affinity(unsigned int irq
, cpumask_t mask
)
122 int i
= 0, old_cpu
, cpu
, int_on
;
124 irq_desc_t
*desc
= irq_desc
+ irq
;
129 if (cpus_weight(mask
) > 1) {
130 printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq
);
134 /* Convert logical CPU to physical CPU */
135 cpu
= cpu_logical_map(i
);
137 /* Protect against other affinity changers and IMR manipulation */
138 spin_lock_irqsave(&desc
->lock
, flags
);
139 spin_lock(&sb1250_imr_lock
);
141 /* Swizzle each CPU's IMR (but leave the IP selection alone) */
142 old_cpu
= sb1250_irq_owner
[irq
];
143 cur_ints
= ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu
) +
144 R_IMR_INTERRUPT_MASK
));
145 int_on
= !(cur_ints
& (((u64
) 1) << irq
));
147 /* If it was on, mask it */
148 cur_ints
|= (((u64
) 1) << irq
);
149 ____raw_writeq(cur_ints
, IOADDR(A_IMR_MAPPER(old_cpu
) +
150 R_IMR_INTERRUPT_MASK
));
152 sb1250_irq_owner
[irq
] = cpu
;
154 /* unmask for the new CPU */
155 cur_ints
= ____raw_readq(IOADDR(A_IMR_MAPPER(cpu
) +
156 R_IMR_INTERRUPT_MASK
));
157 cur_ints
&= ~(((u64
) 1) << irq
);
158 ____raw_writeq(cur_ints
, IOADDR(A_IMR_MAPPER(cpu
) +
159 R_IMR_INTERRUPT_MASK
));
161 spin_unlock(&sb1250_imr_lock
);
162 spin_unlock_irqrestore(&desc
->lock
, flags
);
166 /*****************************************************************************/
168 static unsigned int startup_sb1250_irq(unsigned int irq
)
170 sb1250_unmask_irq(sb1250_irq_owner
[irq
], irq
);
172 return 0; /* never anything pending */
176 static void disable_sb1250_irq(unsigned int irq
)
178 sb1250_mask_irq(sb1250_irq_owner
[irq
], irq
);
181 static void enable_sb1250_irq(unsigned int irq
)
183 sb1250_unmask_irq(sb1250_irq_owner
[irq
], irq
);
187 static void ack_sb1250_irq(unsigned int irq
)
189 #ifdef CONFIG_SIBYTE_HAS_LDT
193 * If the interrupt was an HT interrupt, now is the time to
194 * clear it. NOTE: we assume the HT bridge was set up to
195 * deliver the interrupts to all CPUs (which makes affinity
196 * changing easier for us)
198 pending
= __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner
[irq
],
199 R_IMR_LDT_INTERRUPT
)));
200 pending
&= ((u64
)1 << (irq
));
203 for (i
=0; i
<NR_CPUS
; i
++) {
206 cpu
= cpu_logical_map(i
);
211 * Clear for all CPUs so an affinity switch
212 * doesn't find an old status
214 __raw_writeq(pending
,
215 IOADDR(A_IMR_REGISTER(cpu
,
216 R_IMR_LDT_INTERRUPT_CLR
)));
220 * Generate EOI. For Pass 1 parts, EOI is a nop. For
221 * Pass 2, the LDT world may be edge-triggered, but
222 * this EOI shouldn't hurt. If they are
223 * level-sensitive, the EOI is required.
225 *(uint32_t *)(ldt_eoi_space
+(irq
<<16)+(7<<2)) = 0;
228 sb1250_mask_irq(sb1250_irq_owner
[irq
], irq
);
232 static void end_sb1250_irq(unsigned int irq
)
234 if (!(irq_desc
[irq
].status
& (IRQ_DISABLED
| IRQ_INPROGRESS
))) {
235 sb1250_unmask_irq(sb1250_irq_owner
[irq
], irq
);
240 void __init
init_sb1250_irqs(void)
244 for (i
= 0; i
< NR_IRQS
; i
++) {
245 irq_desc
[i
].status
= IRQ_DISABLED
;
246 irq_desc
[i
].action
= 0;
247 irq_desc
[i
].depth
= 1;
248 if (i
< SB1250_NR_IRQS
) {
249 irq_desc
[i
].handler
= &sb1250_irq_type
;
250 sb1250_irq_owner
[i
] = 0;
252 irq_desc
[i
].handler
= &no_irq_type
;
258 static irqreturn_t
sb1250_dummy_handler(int irq
, void *dev_id
,
259 struct pt_regs
*regs
)
264 static struct irqaction sb1250_dummy_action
= {
265 .handler
= sb1250_dummy_handler
,
267 .mask
= CPU_MASK_NONE
,
268 .name
= "sb1250-private",
273 int sb1250_steal_irq(int irq
)
275 irq_desc_t
*desc
= irq_desc
+ irq
;
279 if (irq
>= SB1250_NR_IRQS
)
282 spin_lock_irqsave(&desc
->lock
,flags
);
283 /* Don't allow sharing at all for these */
284 if (desc
->action
!= NULL
)
287 desc
->action
= &sb1250_dummy_action
;
290 spin_unlock_irqrestore(&desc
->lock
,flags
);
295 * arch_init_irq is called early in the boot sequence from init/main.c via
296 * init_IRQ. It is responsible for setting up the interrupt mapper and
297 * installing the handler that will be responsible for dispatching interrupts
298 * to the "right" place.
301 * For now, map all interrupts to IP[2]. We could save
302 * some cycles by parceling out system interrupts to different
303 * IP lines, but keep it simple for bringup. We'll also direct
304 * all interrupts to a single CPU; we should probably route
305 * PCI and LDT to one cpu and everything else to the other
306 * to balance the load a bit.
308 * On the second cpu, everything is set to IP5, which is
309 * ignored, EXCEPT the mailbox interrupt. That one is
310 * set to IP[2] so it is handled. This is needed so we
311 * can do cross-cpu function calls, as requred by SMP
314 #define IMR_IP2_VAL K_INT_MAP_I0
315 #define IMR_IP3_VAL K_INT_MAP_I1
316 #define IMR_IP4_VAL K_INT_MAP_I2
317 #define IMR_IP5_VAL K_INT_MAP_I3
318 #define IMR_IP6_VAL K_INT_MAP_I4
320 void __init
arch_init_irq(void)
325 unsigned int imask
= STATUSF_IP4
| STATUSF_IP3
| STATUSF_IP2
|
326 STATUSF_IP1
| STATUSF_IP0
;
328 /* Default everything to IP2 */
329 for (i
= 0; i
< SB1250_NR_IRQS
; i
++) { /* was I0 */
330 __raw_writeq(IMR_IP2_VAL
,
331 IOADDR(A_IMR_REGISTER(0,
332 R_IMR_INTERRUPT_MAP_BASE
) +
334 __raw_writeq(IMR_IP2_VAL
,
335 IOADDR(A_IMR_REGISTER(1,
336 R_IMR_INTERRUPT_MAP_BASE
) +
343 * Map the high 16 bits of the mailbox registers to IP[3], for
347 __raw_writeq(IMR_IP3_VAL
,
348 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE
) +
349 (K_INT_MBOX_0
<< 3)));
350 __raw_writeq(IMR_IP3_VAL
,
351 IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE
) +
352 (K_INT_MBOX_0
<< 3)));
354 /* Clear the mailboxes. The firmware may leave them dirty */
355 __raw_writeq(0xffffffffffffffffULL
,
356 IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU
)));
357 __raw_writeq(0xffffffffffffffffULL
,
358 IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU
)));
360 /* Mask everything except the mailbox registers for both cpus */
361 tmp
= ~((u64
) 0) ^ (((u64
) 1) << K_INT_MBOX_0
);
362 __raw_writeq(tmp
, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK
)));
363 __raw_writeq(tmp
, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK
)));
365 sb1250_steal_irq(K_INT_MBOX_0
);
368 * Note that the timer interrupts are also mapped, but this is
369 * done in sb1250_time_init(). Also, the profiling driver
370 * does its own management of IP7.
374 imask
|= STATUSF_IP6
;
376 /* Enable necessary IPs, disable the rest */
377 change_c0_status(ST0_IM
, imask
);
381 kgdb_irq
= K_INT_UART_0
+ kgdb_port
;
383 #ifdef CONFIG_SIBYTE_SB1250_DUART
384 sb1250_duart_present
[kgdb_port
] = 0;
386 /* Setup uart 1 settings, mapper */
387 __raw_writeq(M_DUART_IMR_BRK
,
388 IOADDR(A_DUART_IMRREG(kgdb_port
)));
390 sb1250_steal_irq(kgdb_irq
);
391 __raw_writeq(IMR_IP6_VAL
,
392 IOADDR(A_IMR_REGISTER(0,
393 R_IMR_INTERRUPT_MAP_BASE
) +
395 sb1250_unmask_irq(0, kgdb_irq
);
402 #include <linux/delay.h>
404 #define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
405 #define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
407 static void sb1250_kgdb_interrupt(struct pt_regs
*regs
)
410 * Clear break-change status (allow some time for the remote
411 * host to stop the break, since we would see another
412 * interrupt on the end-of-break too)
414 kstat_this_cpu
.irqs
[kgdb_irq
]++;
416 duart_out(R_DUART_CMD
, V_DUART_MISC_CMD_RESET_BREAK_INT
|
417 M_DUART_RX_EN
| M_DUART_TX_EN
);
418 set_async_breakpoint(®s
->cp0_epc
);
421 #endif /* CONFIG_KGDB */
423 static inline int dclz(unsigned long long x
)
438 asmlinkage
void plat_irq_dispatch(struct pt_regs
*regs
)
440 unsigned int pending
;
442 #ifdef CONFIG_SIBYTE_SB1250_PROF
443 /* Set compare to count to silence count/compare timer interrupts */
444 write_c0_count(read_c0_count());
448 * What a pain. We have to be really careful saving the upper 32 bits
449 * of any * register across function calls if we don't want them
450 * trashed--since were running in -o32, the calling routing never saves
451 * the full 64 bits of a register across a function call. Being the
452 * interrupt handler, we're guaranteed that interrupts are disabled
453 * during this code so we don't have to worry about random interrupts
454 * blasting the high 32 bits.
457 pending
= read_c0_cause();
459 #ifdef CONFIG_SIBYTE_SB1250_PROF
460 if (pending
& CAUSEF_IP7
) { /* Cpu performance counter interrupt */
461 sbprof_cpu_intr(exception_epc(regs
));
465 if (pending
& CAUSEF_IP4
)
466 sb1250_timer_interrupt(regs
);
469 if (pending
& CAUSEF_IP3
)
470 sb1250_mailbox_interrupt(regs
);
474 if (pending
& CAUSEF_IP6
) /* KGDB (uart 1) */
475 sb1250_kgdb_interrupt(regs
);
478 if (pending
& CAUSEF_IP2
) {
479 unsigned long long mask
;
482 * Default...we've hit an IP[2] interrupt, which means we've
483 * got to check the 1250 interrupt registers to figure out what
484 * to do. Need to detect which CPU we're on, now that
485 ~ smp_affinity is supported.
487 mask
= __raw_readq(IOADDR(A_IMR_REGISTER(smp_processor_id(),
488 R_IMR_INTERRUPT_STATUS_BASE
)));
490 do_IRQ(63 - dclz(mask
), regs
);