arch/mips/jmr3927/rbhma3100/irq.c

   1 /*
   2  * Copyright 2001 MontaVista Software Inc.
   3  * Author: MontaVista Software, Inc.
   4  *              ahennessy@mvista.com
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  *
  10  * Copyright (C) 2000-2001 Toshiba Corporation
  11  *
  12  *  This program is free software; you can redistribute  it and/or modify it
  13  *  under  the terms of  the GNU General  Public License as published by the
  14  *  Free Software Foundation;  either version 2 of the  License, or (at your
  15  *  option) any later version.
  16  *
  17  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  18  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  19  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  20  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  21  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  23  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  24  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  25  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  *  You should have received a copy of the  GNU General Public License along
  29  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  30  *  675 Mass Ave, Cambridge, MA 02139, USA.
  31  */
  32 #include <linux/config.h>
  33 #include <linux/init.h>
  34
  35 #include <linux/errno.h>
  36 #include <linux/irq.h>
  37 #include <linux/kernel_stat.h>
  38 #include <linux/signal.h>
  39 #include <linux/sched.h>
  40 #include <linux/types.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/ioport.h>
  43 #include <linux/timex.h>
  44 #include <linux/slab.h>
  45 #include <linux/random.h>
  46 #include <linux/smp.h>
  47 #include <linux/smp_lock.h>
  48 #include <linux/bitops.h>
  49
  50 #include <asm/io.h>
  51 #include <asm/mipsregs.h>
  52 #include <asm/system.h>
  53
  54 #include <asm/ptrace.h>
  55 #include <asm/processor.h>
  56 #include <asm/jmr3927/irq.h>
  57 #include <asm/debug.h>
  58 #include <asm/jmr3927/jmr3927.h>
  59
  60 #if JMR3927_IRQ_END > NR_IRQS
  61 #error JMR3927_IRQ_END > NR_IRQS
  62 #endif
  63
  64 struct tb_irq_space* tb_irq_spaces;
  65
  66 static int jmr3927_irq_base = -1;
  67
  68 #ifdef CONFIG_PCI
  69 static int jmr3927_gen_iack(void)
  70 {
  71         /* generate ACK cycle */
  72 #ifdef __BIG_ENDIAN
  73         return (tx3927_pcicptr->iiadp >> 24) & 0xff;
  74 #else
  75         return tx3927_pcicptr->iiadp & 0xff;
  76 #endif
  77 }
  78 #endif
  79
  80 #define irc_dlevel      0
  81 #define irc_elevel      1
  82
  83 static unsigned char irc_level[TX3927_NUM_IR] = {
  84         5, 5, 5, 5, 5, 5,       /* INT[5:0] */
  85         7, 7,                   /* SIO */
  86         5, 5, 5, 0, 0,          /* DMA, PIO, PCI */
  87         6, 6, 6                 /* TMR */
  88 };
  89
  90 static void jmr3927_irq_disable(unsigned int irq_nr);
  91 static void jmr3927_irq_enable(unsigned int irq_nr);
  92
  93 static DEFINE_SPINLOCK(jmr3927_irq_lock);
  94
  95 static unsigned int jmr3927_irq_startup(unsigned int irq)
  96 {
  97         jmr3927_irq_enable(irq);
  98
  99         return 0;
 100 }
 101
 102 #define jmr3927_irq_shutdown    jmr3927_irq_disable
 103
 104 static void jmr3927_irq_ack(unsigned int irq)
 105 {
 106         if (irq == JMR3927_IRQ_IRC_TMR0)
 107                 jmr3927_tmrptr->tisr = 0;       /* ack interrupt */
 108
 109         jmr3927_irq_disable(irq);
 110 }
 111
 112 static void jmr3927_irq_end(unsigned int irq)
 113 {
 114         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
 115                 jmr3927_irq_enable(irq);
 116 }
 117
 118 static void jmr3927_irq_disable(unsigned int irq_nr)
 119 {
 120         struct tb_irq_space* sp;
 121         unsigned long flags;
 122
 123         spin_lock_irqsave(&jmr3927_irq_lock, flags);
 124         for (sp = tb_irq_spaces; sp; sp = sp->next) {
 125                 if (sp->start_irqno <= irq_nr &&
 126                     irq_nr < sp->start_irqno + sp->nr_irqs) {
 127                         if (sp->mask_func)
 128                                 sp->mask_func(irq_nr - sp->start_irqno,
 129                                               sp->space_id);
 130                         break;
 131                 }
 132         }
 133         spin_unlock_irqrestore(&jmr3927_irq_lock, flags);
 134 }
 135
 136 static void jmr3927_irq_enable(unsigned int irq_nr)
 137 {
 138         struct tb_irq_space* sp;
 139         unsigned long flags;
 140
 141         spin_lock_irqsave(&jmr3927_irq_lock, flags);
 142         for (sp = tb_irq_spaces; sp; sp = sp->next) {
 143                 if (sp->start_irqno <= irq_nr &&
 144                     irq_nr < sp->start_irqno + sp->nr_irqs) {
 145                         if (sp->unmask_func)
 146                                 sp->unmask_func(irq_nr - sp->start_irqno,
 147                                                 sp->space_id);
 148                         break;
 149                 }
 150         }
 151         spin_unlock_irqrestore(&jmr3927_irq_lock, flags);
 152 }
 153
 154 /*
 155  * CP0_STATUS is a thread's resource (saved/restored on context switch).
 156  * So disable_irq/enable_irq MUST handle IOC/ISAC/IRC registers.
 157  */
 158 static void mask_irq_isac(int irq_nr, int space_id)
 159 {
 160         /* 0: mask */
 161         unsigned char imask =
 162                 jmr3927_isac_reg_in(JMR3927_ISAC_INTM_ADDR);
 163         unsigned int bit  = 1 << irq_nr;
 164         jmr3927_isac_reg_out(imask & ~bit, JMR3927_ISAC_INTM_ADDR);
 165         /* flush write buffer */
 166         (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
 167 }
 168 static void unmask_irq_isac(int irq_nr, int space_id)
 169 {
 170         /* 0: mask */
 171         unsigned char imask = jmr3927_isac_reg_in(JMR3927_ISAC_INTM_ADDR);
 172         unsigned int bit  = 1 << irq_nr;
 173         jmr3927_isac_reg_out(imask | bit, JMR3927_ISAC_INTM_ADDR);
 174         /* flush write buffer */
 175         (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
 176 }
 177
 178 static void mask_irq_ioc(int irq_nr, int space_id)
 179 {
 180         /* 0: mask */
 181         unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
 182         unsigned int bit = 1 << irq_nr;
 183         jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR);
 184         /* flush write buffer */
 185         (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
 186 }
 187 static void unmask_irq_ioc(int irq_nr, int space_id)
 188 {
 189         /* 0: mask */
 190         unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
 191         unsigned int bit = 1 << irq_nr;
 192         jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR);
 193         /* flush write buffer */
 194         (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
 195 }
 196
 197 static void mask_irq_irc(int irq_nr, int space_id)
 198 {
 199         volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2];
 200         if (irq_nr & 1)
 201                 *ilrp = (*ilrp & 0x00ff) | (irc_dlevel << 8);
 202         else
 203                 *ilrp = (*ilrp & 0xff00) | irc_dlevel;
 204         /* update IRCSR */
 205         tx3927_ircptr->imr = 0;
 206         tx3927_ircptr->imr = irc_elevel;
 207         /* flush write buffer */
 208         (void)tx3927_ircptr->ssr;
 209 }
 210
 211 static void unmask_irq_irc(int irq_nr, int space_id)
 212 {
 213         volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2];
 214         if (irq_nr & 1)
 215                 *ilrp = (*ilrp & 0x00ff) | (irc_level[irq_nr] << 8);
 216         else
 217                 *ilrp = (*ilrp & 0xff00) | irc_level[irq_nr];
 218         /* update IRCSR */
 219         tx3927_ircptr->imr = 0;
 220         tx3927_ircptr->imr = irc_elevel;
 221 }
 222
 223 struct tb_irq_space jmr3927_isac_irqspace = {
 224         .next = NULL,
 225         .start_irqno = JMR3927_IRQ_ISAC,
 226         nr_irqs : JMR3927_NR_IRQ_ISAC,
 227         .mask_func = mask_irq_isac,
 228         .unmask_func = unmask_irq_isac,
 229         .name = "ISAC",
 230         .space_id = 0,
 231         can_share : 0
 232 };
 233 struct tb_irq_space jmr3927_ioc_irqspace = {
 234         .next = NULL,
 235         .start_irqno = JMR3927_IRQ_IOC,
 236         nr_irqs : JMR3927_NR_IRQ_IOC,
 237         .mask_func = mask_irq_ioc,
 238         .unmask_func = unmask_irq_ioc,
 239         .name = "IOC",
 240         .space_id = 0,
 241         can_share : 1
 242 };
 243 struct tb_irq_space jmr3927_irc_irqspace = {
 244         .next = NULL,
 245         .start_irqno = JMR3927_IRQ_IRC,
 246         nr_irqs : JMR3927_NR_IRQ_IRC,
 247         .mask_func = mask_irq_irc,
 248         .unmask_func = unmask_irq_irc,
 249         .name = "on-chip",
 250         .space_id = 0,
 251         can_share : 0
 252 };
 253
 254 void jmr3927_spurious(struct pt_regs *regs)
 255 {
 256 #ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
 257         tx_branch_likely_bug_fixup(regs);
 258 #endif
 259         printk(KERN_WARNING "spurious interrupt (cause 0x%lx, pc 0x%lx, ra 0x%lx).\n",
 260                regs->cp0_cause, regs->cp0_epc, regs->regs[31]);
 261 }
 262
 263 asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
 264 {
 265         int irq;
 266
 267 #ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
 268         tx_branch_likely_bug_fixup(regs);
 269 #endif
 270         if ((regs->cp0_cause & CAUSEF_IP7) == 0) {
 271 #if 0
 272                 jmr3927_spurious(regs);
 273 #endif
 274                 return;
 275         }
 276         irq = (regs->cp0_cause >> CAUSEB_IP2) & 0x0f;
 277
 278         do_IRQ(irq + JMR3927_IRQ_IRC, regs);
 279 }
 280
 281 static irqreturn_t jmr3927_ioc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 282 {
 283         unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR);
 284         int i;
 285
 286         for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) {
 287                 if (istat & (1 << i)) {
 288                         irq = JMR3927_IRQ_IOC + i;
 289                         do_IRQ(irq, regs);
 290                 }
 291         }
 292         return IRQ_HANDLED;
 293 }
 294
 295 static struct irqaction ioc_action = {
 296         jmr3927_ioc_interrupt, 0, CPU_MASK_NONE, "IOC", NULL, NULL,
 297 };
 298
 299 static irqreturn_t jmr3927_isac_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 300 {
 301         unsigned char istat = jmr3927_isac_reg_in(JMR3927_ISAC_INTS2_ADDR);
 302         int i;
 303
 304         for (i = 0; i < JMR3927_NR_IRQ_ISAC; i++) {
 305                 if (istat & (1 << i)) {
 306                         irq = JMR3927_IRQ_ISAC + i;
 307                         do_IRQ(irq, regs);
 308                 }
 309         }
 310         return IRQ_HANDLED;
 311 }
 312
 313 static struct irqaction isac_action = {
 314         jmr3927_isac_interrupt, 0, CPU_MASK_NONE, "ISAC", NULL, NULL,
 315 };
 316
 317
 318 static irqreturn_t jmr3927_isaerr_interrupt(int irq, void * dev_id, struct pt_regs * regs)
 319 {
 320         printk(KERN_WARNING "ISA error interrupt (irq 0x%x).\n", irq);
 321
 322         return IRQ_HANDLED;
 323 }
 324 static struct irqaction isaerr_action = {
 325         jmr3927_isaerr_interrupt, 0, CPU_MASK_NONE, "ISA error", NULL, NULL,
 326 };
 327
 328 static irqreturn_t jmr3927_pcierr_interrupt(int irq, void * dev_id, struct pt_regs * regs)
 329 {
 330         printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq);
 331         printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n",
 332                tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat);
 333
 334         return IRQ_HANDLED;
 335 }
 336 static struct irqaction pcierr_action = {
 337         jmr3927_pcierr_interrupt, 0, CPU_MASK_NONE, "PCI error", NULL, NULL,
 338 };
 339
 340 int jmr3927_ether1_irq = 0;
 341
 342 void jmr3927_irq_init(u32 irq_base);
 343
 344 void __init arch_init_irq(void)
 345 {
 346         /* look for io board's presence */
 347         int have_isac = jmr3927_have_isac();
 348
 349         /* Now, interrupt control disabled, */
 350         /* all IRC interrupts are masked, */
 351         /* all IRC interrupt mode are Low Active. */
 352
 353         if (have_isac) {
 354
 355                 /* ETHER1 (NE2000 compatible 10M-Ether) parameter setup */
 356                 /* temporary enable interrupt control */
 357                 tx3927_ircptr->cer = 1;
 358                 /* ETHER1 Int. Is High-Active. */
 359                 if (tx3927_ircptr->ssr & (1 << 0))
 360                         jmr3927_ether1_irq = JMR3927_IRQ_IRC_INT0;
 361 #if 0   /* INT3 may be asserted by ether0 (even after reboot...) */
 362                 else if (tx3927_ircptr->ssr & (1 << 3))
 363                         jmr3927_ether1_irq = JMR3927_IRQ_IRC_INT3;
 364 #endif
 365                 /* disable interrupt control */
 366                 tx3927_ircptr->cer = 0;
 367
 368                 /* Ether1: High Active */
 369                 if (jmr3927_ether1_irq) {
 370                         int ether1_irc = jmr3927_ether1_irq - JMR3927_IRQ_IRC;
 371                         tx3927_ircptr->cr[ether1_irc / 8] |=
 372                                 TX3927_IRCR_HIGH << ((ether1_irc % 8) * 2);
 373                 }
 374         }
 375
 376         /* mask all IOC interrupts */
 377         jmr3927_ioc_reg_out(0, JMR3927_IOC_INTM_ADDR);
 378         /* setup IOC interrupt mode (SOFT:High Active, Others:Low Active) */
 379         jmr3927_ioc_reg_out(JMR3927_IOC_INTF_SOFT, JMR3927_IOC_INTP_ADDR);
 380
 381         if (have_isac) {
 382                 /* mask all ISAC interrupts */
 383                 jmr3927_isac_reg_out(0, JMR3927_ISAC_INTM_ADDR);
 384                 /* setup ISAC interrupt mode (ISAIRQ3,ISAIRQ5:Low Active ???) */
 385                 jmr3927_isac_reg_out(JMR3927_ISAC_INTF_IRQ3|JMR3927_ISAC_INTF_IRQ5, JMR3927_ISAC_INTP_ADDR);
 386         }
 387
 388         /* clear PCI Soft interrupts */
 389         jmr3927_ioc_reg_out(0, JMR3927_IOC_INTS1_ADDR);
 390         /* clear PCI Reset interrupts */
 391         jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 392
 393         /* enable interrupt control */
 394         tx3927_ircptr->cer = TX3927_IRCER_ICE;
 395         tx3927_ircptr->imr = irc_elevel;
 396
 397         jmr3927_irq_init(NR_ISA_IRQS);
 398
 399         /* setup irq space */
 400         add_tb_irq_space(&jmr3927_isac_irqspace);
 401         add_tb_irq_space(&jmr3927_ioc_irqspace);
 402         add_tb_irq_space(&jmr3927_irc_irqspace);
 403
 404         /* setup IOC interrupt 1 (PCI, MODEM) */
 405         setup_irq(JMR3927_IRQ_IOCINT, &ioc_action);
 406
 407         if (have_isac) {
 408                 setup_irq(JMR3927_IRQ_ISACINT, &isac_action);
 409                 setup_irq(JMR3927_IRQ_ISAC_ISAER, &isaerr_action);
 410         }
 411
 412 #ifdef CONFIG_PCI
 413         setup_irq(JMR3927_IRQ_IRC_PCI, &pcierr_action);
 414 #endif
 415
 416         /* enable all CPU interrupt bits. */
 417         set_c0_status(ST0_IM);  /* IE bit is still 0. */
 418 }
 419
 420 static hw_irq_controller jmr3927_irq_controller = {
 421         .typename = "jmr3927_irq",
 422         .startup = jmr3927_irq_startup,
 423         .shutdown = jmr3927_irq_shutdown,
 424         .enable = jmr3927_irq_enable,
 425         .disable = jmr3927_irq_disable,
 426         .ack = jmr3927_irq_ack,
 427         .end = jmr3927_irq_end,
 428 };
 429
 430 void jmr3927_irq_init(u32 irq_base)
 431 {
 432         u32 i;
 433
 434         for (i= irq_base; i< irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC; i++) {
 435                 irq_desc[i].status = IRQ_DISABLED;
 436                 irq_desc[i].action = NULL;
 437                 irq_desc[i].depth = 1;
 438                 irq_desc[i].handler = &jmr3927_irq_controller;
 439         }
 440
 441         jmr3927_irq_base = irq_base;
 442 }
 443
 444 #ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
 445 static int tx_branch_likely_bug_count = 0;
 446 static int have_tx_branch_likely_bug = 0;
 447 void tx_branch_likely_bug_fixup(struct pt_regs *regs)
 448 {
 449         /* TX39/49-BUG: Under this condition, the insn in delay slot
 450            of the branch likely insn is executed (not nullified) even
 451            the branch condition is false. */
 452         if (!have_tx_branch_likely_bug)
 453                 return;
 454         if ((regs->cp0_epc & 0xfff) == 0xffc &&
 455             KSEGX(regs->cp0_epc) != KSEG0 &&
 456             KSEGX(regs->cp0_epc) != KSEG1) {
 457                 unsigned int insn = *(unsigned int*)(regs->cp0_epc - 4);
 458                 /* beql,bnel,blezl,bgtzl */
 459                 /* bltzl,bgezl,blezall,bgezall */
 460                 /* bczfl, bcztl */
 461                 if ((insn & 0xf0000000) == 0x50000000 ||
 462                     (insn & 0xfc0e0000) == 0x04020000 ||
 463                     (insn & 0xf3fe0000) == 0x41020000) {
 464                         regs->cp0_epc -= 4;
 465                         tx_branch_likely_bug_count++;
 466                         printk(KERN_INFO
 467                                "fix branch-likery bug in %s (insn %08x)\n",
 468                                current->comm, insn);
 469                 }
 470         }
 471 }
 472 #endif