drivers/ide/au1xxx-ide.c

   1 /*
   2  * BRIEF MODULE DESCRIPTION
   3  * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
   4  *
   5  * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
   6  *
   7  * This program is free software; you can redistribute it and/or modify it under
   8  * the terms of the GNU General Public License as published by the Free Software
   9  * Foundation; either version 2 of the License, or (at your option) any later
  10  * version.
  11  *
  12  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
  13  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
  14  * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
  15  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  16  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  17  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  18  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  19  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  20  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  21  * POSSIBILITY OF SUCH DAMAGE.
  22  *
  23  * You should have received a copy of the GNU General Public License along with
  24  * this program; if not, write to the Free Software Foundation, Inc.,
  25  * 675 Mass Ave, Cambridge, MA 02139, USA.
  26  *
  27  * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
  28  *       Interface and Linux Device Driver" Application Note.
  29  */
  30 #include <linux/types.h>
  31 #include <linux/module.h>
  32 #include <linux/kernel.h>
  33 #include <linux/delay.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/init.h>
  36 #include <linux/ide.h>
  37 #include <linux/scatterlist.h>
  38
  39 #include <asm/mach-au1x00/au1xxx.h>
  40 #include <asm/mach-au1x00/au1xxx_dbdma.h>
  41 #include <asm/mach-au1x00/au1xxx_ide.h>
  42
  43 #define DRV_NAME        "au1200-ide"
  44 #define DRV_AUTHOR      "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>"
  45
  46 /* enable the burstmode in the dbdma */
  47 #define IDE_AU1XXX_BURSTMODE    1
  48
  49 static _auide_hwif auide_hwif;
  50
  51 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
  52
  53 static inline void auide_insw(unsigned long port, void *addr, u32 count)
  54 {
  55         _auide_hwif *ahwif = &auide_hwif;
  56         chan_tab_t *ctp;
  57         au1x_ddma_desc_t *dp;
  58
  59         if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1,
  60                            DDMA_FLAGS_NOIE)) {
  61                 printk(KERN_ERR "%s failed %d\n", __func__, __LINE__);
  62                 return;
  63         }
  64         ctp = *((chan_tab_t **)ahwif->rx_chan);
  65         dp = ctp->cur_ptr;
  66         while (dp->dscr_cmd0 & DSCR_CMD0_V)
  67                 ;
  68         ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
  69 }
  70
  71 static inline void auide_outsw(unsigned long port, void *addr, u32 count)
  72 {
  73         _auide_hwif *ahwif = &auide_hwif;
  74         chan_tab_t *ctp;
  75         au1x_ddma_desc_t *dp;
  76
  77         if(!put_source_flags(ahwif->tx_chan, (void*)addr,
  78                              count << 1, DDMA_FLAGS_NOIE)) {
  79                 printk(KERN_ERR "%s failed %d\n", __func__, __LINE__);
  80                 return;
  81         }
  82         ctp = *((chan_tab_t **)ahwif->tx_chan);
  83         dp = ctp->cur_ptr;
  84         while (dp->dscr_cmd0 & DSCR_CMD0_V)
  85                 ;
  86         ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
  87 }
  88
  89 static void au1xxx_input_data(ide_drive_t *drive, struct ide_cmd *cmd,
  90                               void *buf, unsigned int len)
  91 {
  92         auide_insw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
  93 }
  94
  95 static void au1xxx_output_data(ide_drive_t *drive, struct ide_cmd *cmd,
  96                                void *buf, unsigned int len)
  97 {
  98         auide_outsw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
  99 }
 100 #endif
 101
 102 static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio)
 103 {
 104         int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
 105
 106         /* set pio mode! */
 107         switch(pio) {
 108         case 0:
 109                 mem_sttime = SBC_IDE_TIMING(PIO0);
 110
 111                 /* set configuration for RCS2# */
 112                 mem_stcfg |= TS_MASK;
 113                 mem_stcfg &= ~TCSOE_MASK;
 114                 mem_stcfg &= ~TOECS_MASK;
 115                 mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS;
 116                 break;
 117
 118         case 1:
 119                 mem_sttime = SBC_IDE_TIMING(PIO1);
 120
 121                 /* set configuration for RCS2# */
 122                 mem_stcfg |= TS_MASK;
 123                 mem_stcfg &= ~TCSOE_MASK;
 124                 mem_stcfg &= ~TOECS_MASK;
 125                 mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS;
 126                 break;
 127
 128         case 2:
 129                 mem_sttime = SBC_IDE_TIMING(PIO2);
 130
 131                 /* set configuration for RCS2# */
 132                 mem_stcfg &= ~TS_MASK;
 133                 mem_stcfg &= ~TCSOE_MASK;
 134                 mem_stcfg &= ~TOECS_MASK;
 135                 mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS;
 136                 break;
 137
 138         case 3:
 139                 mem_sttime = SBC_IDE_TIMING(PIO3);
 140
 141                 /* set configuration for RCS2# */
 142                 mem_stcfg &= ~TS_MASK;
 143                 mem_stcfg &= ~TCSOE_MASK;
 144                 mem_stcfg &= ~TOECS_MASK;
 145                 mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS;
 146
 147                 break;
 148
 149         case 4:
 150                 mem_sttime = SBC_IDE_TIMING(PIO4);
 151
 152                 /* set configuration for RCS2# */
 153                 mem_stcfg &= ~TS_MASK;
 154                 mem_stcfg &= ~TCSOE_MASK;
 155                 mem_stcfg &= ~TOECS_MASK;
 156                 mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS;
 157                 break;
 158         }
 159
 160         au_writel(mem_sttime,MEM_STTIME2);
 161         au_writel(mem_stcfg,MEM_STCFG2);
 162 }
 163
 164 static void auide_set_dma_mode(ide_drive_t *drive, const u8 speed)
 165 {
 166         int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
 167
 168         switch(speed) {
 169 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 170         case XFER_MW_DMA_2:
 171                 mem_sttime = SBC_IDE_TIMING(MDMA2);
 172
 173                 /* set configuration for RCS2# */
 174                 mem_stcfg &= ~TS_MASK;
 175                 mem_stcfg &= ~TCSOE_MASK;
 176                 mem_stcfg &= ~TOECS_MASK;
 177                 mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS;
 178
 179                 break;
 180         case XFER_MW_DMA_1:
 181                 mem_sttime = SBC_IDE_TIMING(MDMA1);
 182
 183                 /* set configuration for RCS2# */
 184                 mem_stcfg &= ~TS_MASK;
 185                 mem_stcfg &= ~TCSOE_MASK;
 186                 mem_stcfg &= ~TOECS_MASK;
 187                 mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS;
 188
 189                 break;
 190         case XFER_MW_DMA_0:
 191                 mem_sttime = SBC_IDE_TIMING(MDMA0);
 192
 193                 /* set configuration for RCS2# */
 194                 mem_stcfg |= TS_MASK;
 195                 mem_stcfg &= ~TCSOE_MASK;
 196                 mem_stcfg &= ~TOECS_MASK;
 197                 mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS;
 198
 199                 break;
 200 #endif
 201         }
 202
 203         au_writel(mem_sttime,MEM_STTIME2);
 204         au_writel(mem_stcfg,MEM_STCFG2);
 205 }
 206
 207 /*
 208  * Multi-Word DMA + DbDMA functions
 209  */
 210
 211 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 212 static int auide_build_dmatable(ide_drive_t *drive, struct ide_cmd *cmd)
 213 {
 214         ide_hwif_t *hwif = drive->hwif;
 215         _auide_hwif *ahwif = &auide_hwif;
 216         struct scatterlist *sg;
 217         int i = cmd->sg_nents, count = 0;
 218         int iswrite = !!(cmd->tf_flags & IDE_TFLAG_WRITE);
 219
 220         /* Save for interrupt context */
 221         ahwif->drive = drive;
 222
 223         /* fill the descriptors */
 224         sg = hwif->sg_table;
 225         while (i && sg_dma_len(sg)) {
 226                 u32 cur_addr;
 227                 u32 cur_len;
 228
 229                 cur_addr = sg_dma_address(sg);
 230                 cur_len = sg_dma_len(sg);
 231
 232                 while (cur_len) {
 233                         u32 flags = DDMA_FLAGS_NOIE;
 234                         unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
 235
 236                         if (++count >= PRD_ENTRIES) {
 237                                 printk(KERN_WARNING "%s: DMA table too small\n",
 238                                        drive->name);
 239                                 return 0;
 240                         }
 241
 242                         /* Lets enable intr for the last descriptor only */
 243                         if (1==i)
 244                                 flags = DDMA_FLAGS_IE;
 245                         else
 246                                 flags = DDMA_FLAGS_NOIE;
 247
 248                         if (iswrite) {
 249                                 if(!put_source_flags(ahwif->tx_chan,
 250                                                      (void*) sg_virt(sg),
 251                                                      tc, flags)) {
 252                                         printk(KERN_ERR "%s failed %d\n",
 253                                                __func__, __LINE__);
 254                                 }
 255                         } else
 256                         {
 257                                 if(!put_dest_flags(ahwif->rx_chan,
 258                                                    (void*) sg_virt(sg),
 259                                                    tc, flags)) {
 260                                         printk(KERN_ERR "%s failed %d\n",
 261                                                __func__, __LINE__);
 262                                 }
 263                         }
 264
 265                         cur_addr += tc;
 266                         cur_len -= tc;
 267                 }
 268                 sg = sg_next(sg);
 269                 i--;
 270         }
 271
 272         if (count)
 273                 return 1;
 274
 275         return 0; /* revert to PIO for this request */
 276 }
 277
 278 static int auide_dma_end(ide_drive_t *drive)
 279 {
 280         return 0;
 281 }
 282
 283 static void auide_dma_start(ide_drive_t *drive )
 284 {
 285 }
 286
 287
 288 static int auide_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
 289 {
 290         if (auide_build_dmatable(drive, cmd) == 0)
 291                 return 1;
 292
 293         return 0;
 294 }
 295
 296 static int auide_dma_test_irq(ide_drive_t *drive)
 297 {
 298         /* If dbdma didn't execute the STOP command yet, the
 299          * active bit is still set
 300          */
 301         drive->waiting_for_dma++;
 302         if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) {
 303                 printk(KERN_WARNING "%s: timeout waiting for ddma to \
 304                                      complete\n", drive->name);
 305                 return 1;
 306         }
 307         udelay(10);
 308         return 0;
 309 }
 310
 311 static void auide_dma_host_set(ide_drive_t *drive, int on)
 312 {
 313 }
 314
 315 static void auide_ddma_tx_callback(int irq, void *param)
 316 {
 317 }
 318
 319 static void auide_ddma_rx_callback(int irq, void *param)
 320 {
 321 }
 322 #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
 323
 324 static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags)
 325 {
 326         dev->dev_id          = dev_id;
 327         dev->dev_physaddr    = (u32)IDE_PHYS_ADDR;
 328         dev->dev_intlevel    = 0;
 329         dev->dev_intpolarity = 0;
 330         dev->dev_tsize       = tsize;
 331         dev->dev_devwidth    = devwidth;
 332         dev->dev_flags       = flags;
 333 }
 334
 335 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 336 static const struct ide_dma_ops au1xxx_dma_ops = {
 337         .dma_host_set           = auide_dma_host_set,
 338         .dma_setup              = auide_dma_setup,
 339         .dma_start              = auide_dma_start,
 340         .dma_end                = auide_dma_end,
 341         .dma_test_irq           = auide_dma_test_irq,
 342         .dma_lost_irq           = ide_dma_lost_irq,
 343 };
 344
 345 static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
 346 {
 347         _auide_hwif *auide = &auide_hwif;
 348         dbdev_tab_t source_dev_tab, target_dev_tab;
 349         u32 dev_id, tsize, devwidth, flags;
 350
 351         dev_id   = IDE_DDMA_REQ;
 352
 353         tsize    =  8; /*  1 */
 354         devwidth = 32; /* 16 */
 355
 356 #ifdef IDE_AU1XXX_BURSTMODE
 357         flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
 358 #else
 359         flags = DEV_FLAGS_SYNC;
 360 #endif
 361
 362         /* setup dev_tab for tx channel */
 363         auide_init_dbdma_dev( &source_dev_tab,
 364                               dev_id,
 365                               tsize, devwidth, DEV_FLAGS_OUT | flags);
 366         auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 367
 368         auide_init_dbdma_dev( &source_dev_tab,
 369                               dev_id,
 370                               tsize, devwidth, DEV_FLAGS_IN | flags);
 371         auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 372
 373         /* We also need to add a target device for the DMA */
 374         auide_init_dbdma_dev( &target_dev_tab,
 375                               (u32)DSCR_CMD0_ALWAYS,
 376                               tsize, devwidth, DEV_FLAGS_ANYUSE);
 377         auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab);
 378
 379         /* Get a channel for TX */
 380         auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id,
 381                                                  auide->tx_dev_id,
 382                                                  auide_ddma_tx_callback,
 383                                                  (void*)auide);
 384
 385         /* Get a channel for RX */
 386         auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
 387                                                  auide->target_dev_id,
 388                                                  auide_ddma_rx_callback,
 389                                                  (void*)auide);
 390
 391         auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
 392                                                              NUM_DESCRIPTORS);
 393         auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
 394                                                              NUM_DESCRIPTORS);
 395
 396         /* FIXME: check return value */
 397         (void)ide_allocate_dma_engine(hwif);
 398
 399         au1xxx_dbdma_start( auide->tx_chan );
 400         au1xxx_dbdma_start( auide->rx_chan );
 401
 402         return 0;
 403 }
 404 #else
 405 static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
 406 {
 407         _auide_hwif *auide = &auide_hwif;
 408         dbdev_tab_t source_dev_tab;
 409         int flags;
 410
 411 #ifdef IDE_AU1XXX_BURSTMODE
 412         flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
 413 #else
 414         flags = DEV_FLAGS_SYNC;
 415 #endif
 416
 417         /* setup dev_tab for tx channel */
 418         auide_init_dbdma_dev( &source_dev_tab,
 419                               (u32)DSCR_CMD0_ALWAYS,
 420                               8, 32, DEV_FLAGS_OUT | flags);
 421         auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 422
 423         auide_init_dbdma_dev( &source_dev_tab,
 424                               (u32)DSCR_CMD0_ALWAYS,
 425                               8, 32, DEV_FLAGS_IN | flags);
 426         auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 427
 428         /* Get a channel for TX */
 429         auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
 430                                                  auide->tx_dev_id,
 431                                                  NULL,
 432                                                  (void*)auide);
 433
 434         /* Get a channel for RX */
 435         auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
 436                                                  DSCR_CMD0_ALWAYS,
 437                                                  NULL,
 438                                                  (void*)auide);
 439
 440         auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
 441                                                              NUM_DESCRIPTORS);
 442         auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
 443                                                              NUM_DESCRIPTORS);
 444
 445         au1xxx_dbdma_start( auide->tx_chan );
 446         au1xxx_dbdma_start( auide->rx_chan );
 447
 448         return 0;
 449 }
 450 #endif
 451
 452 static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif)
 453 {
 454         int i;
 455         unsigned long *ata_regs = hw->io_ports_array;
 456
 457         /* FIXME? */
 458         for (i = 0; i < 8; i++)
 459                 *ata_regs++ = ahwif->regbase + (i << IDE_REG_SHIFT);
 460
 461         /* set the Alternative Status register */
 462         *ata_regs = ahwif->regbase + (14 << IDE_REG_SHIFT);
 463 }
 464
 465 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
 466 static const struct ide_tp_ops au1xxx_tp_ops = {
 467         .exec_command           = ide_exec_command,
 468         .read_status            = ide_read_status,
 469         .read_altstatus         = ide_read_altstatus,
 470         .write_devctl           = ide_write_devctl,
 471
 472         .dev_select             = ide_dev_select,
 473         .tf_load                = ide_tf_load,
 474         .tf_read                = ide_tf_read,
 475
 476         .input_data             = au1xxx_input_data,
 477         .output_data            = au1xxx_output_data,
 478 };
 479 #endif
 480
 481 static const struct ide_port_ops au1xxx_port_ops = {
 482         .set_pio_mode           = au1xxx_set_pio_mode,
 483         .set_dma_mode           = auide_set_dma_mode,
 484 };
 485
 486 static const struct ide_port_info au1xxx_port_info = {
 487         .init_dma               = auide_ddma_init,
 488 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
 489         .tp_ops                 = &au1xxx_tp_ops,
 490 #endif
 491         .port_ops               = &au1xxx_port_ops,
 492 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 493         .dma_ops                = &au1xxx_dma_ops,
 494 #endif
 495         .host_flags             = IDE_HFLAG_POST_SET_MODE |
 496                                   IDE_HFLAG_NO_IO_32BIT |
 497                                   IDE_HFLAG_UNMASK_IRQS,
 498         .pio_mask               = ATA_PIO4,
 499 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 500         .mwdma_mask             = ATA_MWDMA2,
 501 #endif
 502 };
 503
 504 static int au_ide_probe(struct platform_device *dev)
 505 {
 506         _auide_hwif *ahwif = &auide_hwif;
 507         struct resource *res;
 508         struct ide_host *host;
 509         int ret = 0;
 510         hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
 511
 512 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
 513         char *mode = "MWDMA2";
 514 #elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
 515         char *mode = "PIO+DDMA(offload)";
 516 #endif
 517
 518         memset(&auide_hwif, 0, sizeof(_auide_hwif));
 519         ahwif->irq = platform_get_irq(dev, 0);
 520
 521         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 522
 523         if (res == NULL) {
 524                 pr_debug("%s %d: no base address\n", DRV_NAME, dev->id);
 525                 ret = -ENODEV;
 526                 goto out;
 527         }
 528         if (ahwif->irq < 0) {
 529                 pr_debug("%s %d: no IRQ\n", DRV_NAME, dev->id);
 530                 ret = -ENODEV;
 531                 goto out;
 532         }
 533
 534         if (!request_mem_region(res->start, res->end - res->start + 1,
 535                                 dev->name)) {
 536                 pr_debug("%s: request_mem_region failed\n", DRV_NAME);
 537                 ret =  -EBUSY;
 538                 goto out;
 539         }
 540
 541         ahwif->regbase = (u32)ioremap(res->start, res->end - res->start + 1);
 542         if (ahwif->regbase == 0) {
 543                 ret = -ENOMEM;
 544                 goto out;
 545         }
 546
 547         memset(&hw, 0, sizeof(hw));
 548         auide_setup_ports(&hw, ahwif);
 549         hw.irq = ahwif->irq;
 550         hw.dev = &dev->dev;
 551         hw.chipset = ide_au1xxx;
 552
 553         ret = ide_host_add(&au1xxx_port_info, hws, &host);
 554         if (ret)
 555                 goto out;
 556
 557         auide_hwif.hwif = host->ports[0];
 558
 559         platform_set_drvdata(dev, host);
 560
 561         printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode );
 562
 563  out:
 564         return ret;
 565 }
 566
 567 static int au_ide_remove(struct platform_device *dev)
 568 {
 569         struct resource *res;
 570         struct ide_host *host = platform_get_drvdata(dev);
 571         _auide_hwif *ahwif = &auide_hwif;
 572
 573         ide_host_remove(host);
 574
 575         iounmap((void *)ahwif->regbase);
 576
 577         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 578         release_mem_region(res->start, res->end - res->start + 1);
 579
 580         return 0;
 581 }
 582
 583 static struct platform_driver au1200_ide_driver = {
 584         .driver = {
 585                 .name           = "au1200-ide",
 586                 .owner          = THIS_MODULE,
 587         },
 588         .probe          = au_ide_probe,
 589         .remove         = au_ide_remove,
 590 };
 591
 592 static int __init au_ide_init(void)
 593 {
 594         return platform_driver_register(&au1200_ide_driver);
 595 }
 596
 597 static void __exit au_ide_exit(void)
 598 {
 599         platform_driver_unregister(&au1200_ide_driver);
 600 }
 601
 602 MODULE_LICENSE("GPL");
 603 MODULE_DESCRIPTION("AU1200 IDE driver");
 604
 605 module_init(au_ide_init);
 606 module_exit(au_ide_exit);