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sata_mv: fis irq register fixes
[linux-2.6/mini2440.git] / drivers / ata / sata_mv.c
blob2a23d7ae4769717471afc3c038388befa91bb0e8
1 /*
2 * sata_mv.c - Marvell SATA support
3 *
4 * Copyright 2008: Marvell Corporation, all rights reserved.
5 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Copyright 2005 Red Hat, Inc. All rights reserved.
7 *
8 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25 /*
26 * sata_mv TODO list:
27 *
28 * --> Errata workaround for NCQ device errors.
29 *
30 * --> More errata workarounds for PCI-X.
31 *
32 * --> Complete a full errata audit for all chipsets to identify others.
33 *
34 * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it).
35 *
36 * --> Investigate problems with PCI Message Signalled Interrupts (MSI).
37 *
38 * --> Cache frequently-accessed registers in mv_port_priv to reduce overhead.
39 *
40 * --> Develop a low-power-consumption strategy, and implement it.
41 *
42 * --> [Experiment, low priority] Investigate interrupt coalescing.
43 * Quite often, especially with PCI Message Signalled Interrupts (MSI),
44 * the overhead reduced by interrupt mitigation is quite often not
45 * worth the latency cost.
46 *
47 * --> [Experiment, Marvell value added] Is it possible to use target
48 * mode to cross-connect two Linux boxes with Marvell cards? If so,
49 * creating LibATA target mode support would be very interesting.
50 *
51 * Target mode, for those without docs, is the ability to directly
52 * connect two SATA ports.
53 */
54
55 #include <linux/kernel.h>
56 #include <linux/module.h>
57 #include <linux/pci.h>
58 #include <linux/init.h>
59 #include <linux/blkdev.h>
60 #include <linux/delay.h>
61 #include <linux/interrupt.h>
62 #include <linux/dmapool.h>
63 #include <linux/dma-mapping.h>
64 #include <linux/device.h>
65 #include <linux/platform_device.h>
66 #include <linux/ata_platform.h>
67 #include <linux/mbus.h>
68 #include <linux/bitops.h>
69 #include <scsi/scsi_host.h>
70 #include <scsi/scsi_cmnd.h>
71 #include <scsi/scsi_device.h>
72 #include <linux/libata.h>
73
74 #define DRV_NAME "sata_mv"
75 #define DRV_VERSION "1.20"
76
77 enum {
78 /* BAR's are enumerated in terms of pci_resource_start() terms */
79 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
80 MV_IO_BAR = 2, /* offset 0x18: IO space */
81 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
82
83 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
84 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
85
86 MV_PCI_REG_BASE = 0,
87 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
88 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
89 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
90 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
91 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
92 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
93
94 MV_SATAHC0_REG_BASE = 0x20000,
95 MV_FLASH_CTL_OFS = 0x1046c,
96 MV_GPIO_PORT_CTL_OFS = 0x104f0,
97 MV_RESET_CFG_OFS = 0x180d8,
98
99 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
100 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
101 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
102 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
103
104 MV_MAX_Q_DEPTH = 32,
105 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
106
107 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
108 * CRPB needs alignment on a 256B boundary. Size == 256B
109 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
110 */
111 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
112 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
113 MV_MAX_SG_CT = 256,
114 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
115
116 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
117 MV_PORT_HC_SHIFT = 2,
118 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
119 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
120 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
121
122 /* Host Flags */
123 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
124 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
125 /* SoC integrated controllers, no PCI interface */
126 MV_FLAG_SOC = (1 << 28),
127
128 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
129 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
130 ATA_FLAG_PIO_POLLING,
131 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
132
133 CRQB_FLAG_READ = (1 << 0),
134 CRQB_TAG_SHIFT = 1,
135 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
136 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
137 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
138 CRQB_CMD_ADDR_SHIFT = 8,
139 CRQB_CMD_CS = (0x2 << 11),
140 CRQB_CMD_LAST = (1 << 15),
141
142 CRPB_FLAG_STATUS_SHIFT = 8,
143 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
144 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
145
146 EPRD_FLAG_END_OF_TBL = (1 << 31),
147
148 /* PCI interface registers */
149
150 PCI_COMMAND_OFS = 0xc00,
151 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
152
153 PCI_MAIN_CMD_STS_OFS = 0xd30,
154 STOP_PCI_MASTER = (1 << 2),
155 PCI_MASTER_EMPTY = (1 << 3),
156 GLOB_SFT_RST = (1 << 4),
157
158 MV_PCI_MODE_OFS = 0xd00,
159 MV_PCI_MODE_MASK = 0x30,
160
161 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
162 MV_PCI_DISC_TIMER = 0xd04,
163 MV_PCI_MSI_TRIGGER = 0xc38,
164 MV_PCI_SERR_MASK = 0xc28,
165 MV_PCI_XBAR_TMOUT_OFS = 0x1d04,
166 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
167 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
168 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
169 MV_PCI_ERR_COMMAND = 0x1d50,
170
171 PCI_IRQ_CAUSE_OFS = 0x1d58,
172 PCI_IRQ_MASK_OFS = 0x1d5c,
173 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
174
175 PCIE_IRQ_CAUSE_OFS = 0x1900,
176 PCIE_IRQ_MASK_OFS = 0x1910,
177 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
178
179 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
180 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
181 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
182 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
183 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
184 ERR_IRQ = (1 << 0), /* shift by port # */
185 DONE_IRQ = (1 << 1), /* shift by port # */
186 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
187 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
188 PCI_ERR = (1 << 18),
189 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
190 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
191 PORTS_0_3_COAL_DONE = (1 << 8),
192 PORTS_4_7_COAL_DONE = (1 << 17),
193 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
194 GPIO_INT = (1 << 22),
195 SELF_INT = (1 << 23),
196 TWSI_INT = (1 << 24),
197 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
198 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
199 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
200 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
201 PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
202 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
203 HC_MAIN_RSVD),
204 HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
205 HC_MAIN_RSVD_5),
206 HC_MAIN_MASKED_IRQS_SOC = (PORTS_0_3_COAL_DONE | HC_MAIN_RSVD_SOC),
207
208 /* SATAHC registers */
209 HC_CFG_OFS = 0,
210
211 HC_IRQ_CAUSE_OFS = 0x14,
212 DMA_IRQ = (1 << 0), /* shift by port # */
213 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
214 DEV_IRQ = (1 << 8), /* shift by port # */
215
216 /* Shadow block registers */
217 SHD_BLK_OFS = 0x100,
218 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
219
220 /* SATA registers */
221 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
222 SATA_ACTIVE_OFS = 0x350,
223 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
224
225 LTMODE_OFS = 0x30c,
226 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
227
228 PHY_MODE3 = 0x310,
229 PHY_MODE4 = 0x314,
230 PHY_MODE2 = 0x330,
231 SATA_IFCTL_OFS = 0x344,
232 SATA_TESTCTL_OFS = 0x348,
233 SATA_IFSTAT_OFS = 0x34c,
234 VENDOR_UNIQUE_FIS_OFS = 0x35c,
235
236 FISCFG_OFS = 0x360,
237 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
238 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
239
240 MV5_PHY_MODE = 0x74,
241 MV5_LTMODE_OFS = 0x30,
242 MV5_PHY_CTL_OFS = 0x0C,
243 SATA_INTERFACE_CFG_OFS = 0x050,
244
245 MV_M2_PREAMP_MASK = 0x7e0,
246
247 /* Port registers */
248 EDMA_CFG_OFS = 0,
249 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
250 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
251 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
252 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
253 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
254 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
255 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
256
257 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
258 EDMA_ERR_IRQ_MASK_OFS = 0xc,
259 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
260 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
261 EDMA_ERR_DEV = (1 << 2), /* device error */
262 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
263 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
264 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
265 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
266 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
267 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
268 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
269 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
270 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
271 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
272 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
273
274 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
275 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
276 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
277 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
278 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
279
280 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
281
282 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
283 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
284 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
285 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
286 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
287 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
288
289 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
290
291 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
292 EDMA_ERR_OVERRUN_5 = (1 << 5),
293 EDMA_ERR_UNDERRUN_5 = (1 << 6),
294
295 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
296 EDMA_ERR_LNK_CTRL_RX_1 |
297 EDMA_ERR_LNK_CTRL_RX_3 |
298 EDMA_ERR_LNK_CTRL_TX,
299
300 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
301 EDMA_ERR_PRD_PAR |
302 EDMA_ERR_DEV_DCON |
303 EDMA_ERR_DEV_CON |
304 EDMA_ERR_SERR |
305 EDMA_ERR_SELF_DIS |
306 EDMA_ERR_CRQB_PAR |
307 EDMA_ERR_CRPB_PAR |
308 EDMA_ERR_INTRL_PAR |
309 EDMA_ERR_IORDY |
310 EDMA_ERR_LNK_CTRL_RX_2 |
311 EDMA_ERR_LNK_DATA_RX |
312 EDMA_ERR_LNK_DATA_TX |
313 EDMA_ERR_TRANS_PROTO,
314
315 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
316 EDMA_ERR_PRD_PAR |
317 EDMA_ERR_DEV_DCON |
318 EDMA_ERR_DEV_CON |
319 EDMA_ERR_OVERRUN_5 |
320 EDMA_ERR_UNDERRUN_5 |
321 EDMA_ERR_SELF_DIS_5 |
322 EDMA_ERR_CRQB_PAR |
323 EDMA_ERR_CRPB_PAR |
324 EDMA_ERR_INTRL_PAR |
325 EDMA_ERR_IORDY,
326
327 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
328 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
329
330 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
331 EDMA_REQ_Q_PTR_SHIFT = 5,
332
333 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
334 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
335 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
336 EDMA_RSP_Q_PTR_SHIFT = 3,
337
338 EDMA_CMD_OFS = 0x28, /* EDMA command register */
339 EDMA_EN = (1 << 0), /* enable EDMA */
340 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
341 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
342
343 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */
344 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
345 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
346
347 EDMA_IORDY_TMOUT_OFS = 0x34,
348 EDMA_ARB_CFG_OFS = 0x38,
349
350 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
351
352 GEN_II_NCQ_MAX_SECTORS = 256, /* max sects/io on Gen2 w/NCQ */
353
354 /* Host private flags (hp_flags) */
355 MV_HP_FLAG_MSI = (1 << 0),
356 MV_HP_ERRATA_50XXB0 = (1 << 1),
357 MV_HP_ERRATA_50XXB2 = (1 << 2),
358 MV_HP_ERRATA_60X1B2 = (1 << 3),
359 MV_HP_ERRATA_60X1C0 = (1 << 4),
360 MV_HP_ERRATA_XX42A0 = (1 << 5),
361 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
362 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
363 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
364 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
365 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
366
367 /* Port private flags (pp_flags) */
368 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
369 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
370 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
371 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
372 };
373
374 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
375 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
376 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
377 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
378 #define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC))
379
380 #define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
381 #define WINDOW_BASE(i) (0x20034 + ((i) << 4))
382
383 enum {
384 /* DMA boundary 0xffff is required by the s/g splitting
385 * we need on /length/ in mv_fill-sg().
386 */
387 MV_DMA_BOUNDARY = 0xffffU,
388
389 /* mask of register bits containing lower 32 bits
390 * of EDMA request queue DMA address
391 */
392 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
393
394 /* ditto, for response queue */
395 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
396 };
397
398 enum chip_type {
399 chip_504x,
400 chip_508x,
401 chip_5080,
402 chip_604x,
403 chip_608x,
404 chip_6042,
405 chip_7042,
406 chip_soc,
407 };
408
409 /* Command ReQuest Block: 32B */
410 struct mv_crqb {
411 __le32 sg_addr;
412 __le32 sg_addr_hi;
413 __le16 ctrl_flags;
414 __le16 ata_cmd[11];
415 };
416
417 struct mv_crqb_iie {
418 __le32 addr;
419 __le32 addr_hi;
420 __le32 flags;
421 __le32 len;
422 __le32 ata_cmd[4];
423 };
424
425 /* Command ResPonse Block: 8B */
426 struct mv_crpb {
427 __le16 id;
428 __le16 flags;
429 __le32 tmstmp;
430 };
431
432 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
433 struct mv_sg {
434 __le32 addr;
435 __le32 flags_size;
436 __le32 addr_hi;
437 __le32 reserved;
438 };
439
440 struct mv_port_priv {
441 struct mv_crqb *crqb;
442 dma_addr_t crqb_dma;
443 struct mv_crpb *crpb;
444 dma_addr_t crpb_dma;
445 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
446 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
447
448 unsigned int req_idx;
449 unsigned int resp_idx;
450
451 u32 pp_flags;
452 unsigned int delayed_eh_pmp_map;
453 };
454
455 struct mv_port_signal {
456 u32 amps;
457 u32 pre;
458 };
459
460 struct mv_host_priv {
461 u32 hp_flags;
462 struct mv_port_signal signal[8];
463 const struct mv_hw_ops *ops;
464 int n_ports;
465 void __iomem *base;
466 void __iomem *main_irq_cause_addr;
467 void __iomem *main_irq_mask_addr;
468 u32 irq_cause_ofs;
469 u32 irq_mask_ofs;
470 u32 unmask_all_irqs;
471 /*
472 * These consistent DMA memory pools give us guaranteed
473 * alignment for hardware-accessed data structures,
474 * and less memory waste in accomplishing the alignment.
475 */
476 struct dma_pool *crqb_pool;
477 struct dma_pool *crpb_pool;
478 struct dma_pool *sg_tbl_pool;
479 };
480
481 struct mv_hw_ops {
482 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
483 unsigned int port);
484 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
485 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
486 void __iomem *mmio);
487 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
488 unsigned int n_hc);
489 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
490 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
491 };
492
493 static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
494 static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
495 static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
496 static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
497 static int mv_port_start(struct ata_port *ap);
498 static void mv_port_stop(struct ata_port *ap);
499 static int mv_qc_defer(struct ata_queued_cmd *qc);
500 static void mv_qc_prep(struct ata_queued_cmd *qc);
501 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
502 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
503 static int mv_hardreset(struct ata_link *link, unsigned int *class,
504 unsigned long deadline);
505 static void mv_eh_freeze(struct ata_port *ap);
506 static void mv_eh_thaw(struct ata_port *ap);
507 static void mv6_dev_config(struct ata_device *dev);
508
509 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
510 unsigned int port);
511 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
512 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
513 void __iomem *mmio);
514 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
515 unsigned int n_hc);
516 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
517 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
518
519 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
520 unsigned int port);
521 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
522 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
523 void __iomem *mmio);
524 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
525 unsigned int n_hc);
526 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
527 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
528 void __iomem *mmio);
529 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
530 void __iomem *mmio);
531 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
532 void __iomem *mmio, unsigned int n_hc);
533 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
534 void __iomem *mmio);
535 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
536 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
537 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
538 unsigned int port_no);
539 static int mv_stop_edma(struct ata_port *ap);
540 static int mv_stop_edma_engine(void __iomem *port_mmio);
541 static void mv_edma_cfg(struct ata_port *ap, int want_ncq);
542
543 static void mv_pmp_select(struct ata_port *ap, int pmp);
544 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
545 unsigned long deadline);
546 static int mv_softreset(struct ata_link *link, unsigned int *class,
547 unsigned long deadline);
548 static void mv_pmp_error_handler(struct ata_port *ap);
549 static void mv_process_crpb_entries(struct ata_port *ap,
550 struct mv_port_priv *pp);
551
552 /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
553 * because we have to allow room for worst case splitting of
554 * PRDs for 64K boundaries in mv_fill_sg().
555 */
556 static struct scsi_host_template mv5_sht = {
557 ATA_BASE_SHT(DRV_NAME),
558 .sg_tablesize = MV_MAX_SG_CT / 2,
559 .dma_boundary = MV_DMA_BOUNDARY,
560 };
561
562 static struct scsi_host_template mv6_sht = {
563 ATA_NCQ_SHT(DRV_NAME),
564 .can_queue = MV_MAX_Q_DEPTH - 1,
565 .sg_tablesize = MV_MAX_SG_CT / 2,
566 .dma_boundary = MV_DMA_BOUNDARY,
567 };
568
569 static struct ata_port_operations mv5_ops = {
570 .inherits = &ata_sff_port_ops,
571
572 .qc_defer = mv_qc_defer,
573 .qc_prep = mv_qc_prep,
574 .qc_issue = mv_qc_issue,
575
576 .freeze = mv_eh_freeze,
577 .thaw = mv_eh_thaw,
578 .hardreset = mv_hardreset,
579 .error_handler = ata_std_error_handler, /* avoid SFF EH */
580 .post_internal_cmd = ATA_OP_NULL,
581
582 .scr_read = mv5_scr_read,
583 .scr_write = mv5_scr_write,
584
585 .port_start = mv_port_start,
586 .port_stop = mv_port_stop,
587 };
588
589 static struct ata_port_operations mv6_ops = {
590 .inherits = &mv5_ops,
591 .dev_config = mv6_dev_config,
592 .scr_read = mv_scr_read,
593 .scr_write = mv_scr_write,
594
595 .pmp_hardreset = mv_pmp_hardreset,
596 .pmp_softreset = mv_softreset,
597 .softreset = mv_softreset,
598 .error_handler = mv_pmp_error_handler,
599 };
600
601 static struct ata_port_operations mv_iie_ops = {
602 .inherits = &mv6_ops,
603 .dev_config = ATA_OP_NULL,
604 .qc_prep = mv_qc_prep_iie,
605 };
606
607 static const struct ata_port_info mv_port_info[] = {
608 { /* chip_504x */
609 .flags = MV_COMMON_FLAGS,
610 .pio_mask = 0x1f, /* pio0-4 */
611 .udma_mask = ATA_UDMA6,
612 .port_ops = &mv5_ops,
613 },
614 { /* chip_508x */
615 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
616 .pio_mask = 0x1f, /* pio0-4 */
617 .udma_mask = ATA_UDMA6,
618 .port_ops = &mv5_ops,
619 },
620 { /* chip_5080 */
621 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
622 .pio_mask = 0x1f, /* pio0-4 */
623 .udma_mask = ATA_UDMA6,
624 .port_ops = &mv5_ops,
625 },
626 { /* chip_604x */
627 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
628 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
629 ATA_FLAG_NCQ,
630 .pio_mask = 0x1f, /* pio0-4 */
631 .udma_mask = ATA_UDMA6,
632 .port_ops = &mv6_ops,
633 },
634 { /* chip_608x */
635 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
636 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
637 ATA_FLAG_NCQ | MV_FLAG_DUAL_HC,
638 .pio_mask = 0x1f, /* pio0-4 */
639 .udma_mask = ATA_UDMA6,
640 .port_ops = &mv6_ops,
641 },
642 { /* chip_6042 */
643 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
644 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
645 ATA_FLAG_NCQ,
646 .pio_mask = 0x1f, /* pio0-4 */
647 .udma_mask = ATA_UDMA6,
648 .port_ops = &mv_iie_ops,
649 },
650 { /* chip_7042 */
651 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
652 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
653 ATA_FLAG_NCQ,
654 .pio_mask = 0x1f, /* pio0-4 */
655 .udma_mask = ATA_UDMA6,
656 .port_ops = &mv_iie_ops,
657 },
658 { /* chip_soc */
659 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
660 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
661 ATA_FLAG_NCQ | MV_FLAG_SOC,
662 .pio_mask = 0x1f, /* pio0-4 */
663 .udma_mask = ATA_UDMA6,
664 .port_ops = &mv_iie_ops,
665 },
666 };
667
668 static const struct pci_device_id mv_pci_tbl[] = {
669 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
670 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
671 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
672 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
673 /* RocketRAID 1740/174x have different identifiers */
674 { PCI_VDEVICE(TTI, 0x1740), chip_508x },
675 { PCI_VDEVICE(TTI, 0x1742), chip_508x },
676
677 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
678 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
679 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
680 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
681 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
682
683 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
684
685 /* Adaptec 1430SA */
686 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
687
688 /* Marvell 7042 support */
689 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
690
691 /* Highpoint RocketRAID PCIe series */
692 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
693 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
694
695 { } /* terminate list */
696 };
697
698 static const struct mv_hw_ops mv5xxx_ops = {
699 .phy_errata = mv5_phy_errata,
700 .enable_leds = mv5_enable_leds,
701 .read_preamp = mv5_read_preamp,
702 .reset_hc = mv5_reset_hc,
703 .reset_flash = mv5_reset_flash,
704 .reset_bus = mv5_reset_bus,
705 };
706
707 static const struct mv_hw_ops mv6xxx_ops = {
708 .phy_errata = mv6_phy_errata,
709 .enable_leds = mv6_enable_leds,
710 .read_preamp = mv6_read_preamp,
711 .reset_hc = mv6_reset_hc,
712 .reset_flash = mv6_reset_flash,
713 .reset_bus = mv_reset_pci_bus,
714 };
715
716 static const struct mv_hw_ops mv_soc_ops = {
717 .phy_errata = mv6_phy_errata,
718 .enable_leds = mv_soc_enable_leds,
719 .read_preamp = mv_soc_read_preamp,
720 .reset_hc = mv_soc_reset_hc,
721 .reset_flash = mv_soc_reset_flash,
722 .reset_bus = mv_soc_reset_bus,
723 };
724
725 /*
726 * Functions
727 */
728
729 static inline void writelfl(unsigned long data, void __iomem *addr)
730 {
731 writel(data, addr);
732 (void) readl(addr); /* flush to avoid PCI posted write */
733 }
734
735 static inline unsigned int mv_hc_from_port(unsigned int port)
736 {
737 return port >> MV_PORT_HC_SHIFT;
738 }
739
740 static inline unsigned int mv_hardport_from_port(unsigned int port)
741 {
742 return port & MV_PORT_MASK;
743 }
744
745 /*
746 * Consolidate some rather tricky bit shift calculations.
747 * This is hot-path stuff, so not a function.
748 * Simple code, with two return values, so macro rather than inline.
749 *
750 * port is the sole input, in range 0..7.
751 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
752 * hardport is the other output, in range 0..3.
753 *
754 * Note that port and hardport may be the same variable in some cases.
755 */
756 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
757 { \
758 shift = mv_hc_from_port(port) * HC_SHIFT; \
759 hardport = mv_hardport_from_port(port); \
760 shift += hardport * 2; \
761 }
762
763 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
764 {
765 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
766 }
767
768 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
769 unsigned int port)
770 {
771 return mv_hc_base(base, mv_hc_from_port(port));
772 }
773
774 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
775 {
776 return mv_hc_base_from_port(base, port) +
777 MV_SATAHC_ARBTR_REG_SZ +
778 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
779 }
780
781 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
782 {
783 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
784 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
785
786 return hc_mmio + ofs;
787 }
788
789 static inline void __iomem *mv_host_base(struct ata_host *host)
790 {
791 struct mv_host_priv *hpriv = host->private_data;
792 return hpriv->base;
793 }
794
795 static inline void __iomem *mv_ap_base(struct ata_port *ap)
796 {
797 return mv_port_base(mv_host_base(ap->host), ap->port_no);
798 }
799
800 static inline int mv_get_hc_count(unsigned long port_flags)
801 {
802 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
803 }
804
805 static void mv_set_edma_ptrs(void __iomem *port_mmio,
806 struct mv_host_priv *hpriv,
807 struct mv_port_priv *pp)
808 {
809 u32 index;
810
811 /*
812 * initialize request queue
813 */
814 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
815 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
816
817 WARN_ON(pp->crqb_dma & 0x3ff);
818 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
819 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
820 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
821
822 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
823 writelfl((pp->crqb_dma & 0xffffffff) | index,
824 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
825 else
826 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
827
828 /*
829 * initialize response queue
830 */
831 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
832 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
833
834 WARN_ON(pp->crpb_dma & 0xff);
835 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
836
837 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
838 writelfl((pp->crpb_dma & 0xffffffff) | index,
839 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
840 else
841 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
842
843 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
844 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
845 }
846
847 /**
848 * mv_start_dma - Enable eDMA engine
849 * @base: port base address
850 * @pp: port private data
851 *
852 * Verify the local cache of the eDMA state is accurate with a
853 * WARN_ON.
854 *
855 * LOCKING:
856 * Inherited from caller.
857 */
858 static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio,
859 struct mv_port_priv *pp, u8 protocol)
860 {
861 int want_ncq = (protocol == ATA_PROT_NCQ);
862
863 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
864 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
865 if (want_ncq != using_ncq)
866 mv_stop_edma(ap);
867 }
868 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
869 struct mv_host_priv *hpriv = ap->host->private_data;
870 int hardport = mv_hardport_from_port(ap->port_no);
871 void __iomem *hc_mmio = mv_hc_base_from_port(
872 mv_host_base(ap->host), hardport);
873 u32 hc_irq_cause, ipending;
874
875 /* clear EDMA event indicators, if any */
876 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
877
878 /* clear EDMA interrupt indicator, if any */
879 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
880 ipending = (DEV_IRQ | DMA_IRQ) << hardport;
881 if (hc_irq_cause & ipending) {
882 writelfl(hc_irq_cause & ~ipending,
883 hc_mmio + HC_IRQ_CAUSE_OFS);
884 }
885
886 mv_edma_cfg(ap, want_ncq);
887
888 /* clear FIS IRQ Cause */
889 if (IS_GEN_IIE(hpriv))
890 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
891
892 mv_set_edma_ptrs(port_mmio, hpriv, pp);
893
894 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
895 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
896 }
897 }
898
899 static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
900 {
901 void __iomem *port_mmio = mv_ap_base(ap);
902 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
903 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
904 int i;
905
906 /*
907 * Wait for the EDMA engine to finish transactions in progress.
908 * No idea what a good "timeout" value might be, but measurements
909 * indicate that it often requires hundreds of microseconds
910 * with two drives in-use. So we use the 15msec value above
911 * as a rough guess at what even more drives might require.
912 */
913 for (i = 0; i < timeout; ++i) {
914 u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS);
915 if ((edma_stat & empty_idle) == empty_idle)
916 break;
917 udelay(per_loop);
918 }
919 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
920 }
921
922 /**
923 * mv_stop_edma_engine - Disable eDMA engine
924 * @port_mmio: io base address
925 *
926 * LOCKING:
927 * Inherited from caller.
928 */
929 static int mv_stop_edma_engine(void __iomem *port_mmio)
930 {
931 int i;
932
933 /* Disable eDMA. The disable bit auto clears. */
934 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
935
936 /* Wait for the chip to confirm eDMA is off. */
937 for (i = 10000; i > 0; i--) {
938 u32 reg = readl(port_mmio + EDMA_CMD_OFS);
939 if (!(reg & EDMA_EN))
940 return 0;
941 udelay(10);
942 }
943 return -EIO;
944 }
945
946 static int mv_stop_edma(struct ata_port *ap)
947 {
948 void __iomem *port_mmio = mv_ap_base(ap);
949 struct mv_port_priv *pp = ap->private_data;
950
951 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
952 return 0;
953 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
954 mv_wait_for_edma_empty_idle(ap);
955 if (mv_stop_edma_engine(port_mmio)) {
956 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
957 return -EIO;
958 }
959 return 0;
960 }
961
962 #ifdef ATA_DEBUG
963 static void mv_dump_mem(void __iomem *start, unsigned bytes)
964 {
965 int b, w;
966 for (b = 0; b < bytes; ) {
967 DPRINTK("%p: ", start + b);
968 for (w = 0; b < bytes && w < 4; w++) {
969 printk("%08x ", readl(start + b));
970 b += sizeof(u32);
971 }
972 printk("\n");
973 }
974 }
975 #endif
976
977 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
978 {
979 #ifdef ATA_DEBUG
980 int b, w;
981 u32 dw;
982 for (b = 0; b < bytes; ) {
983 DPRINTK("%02x: ", b);
984 for (w = 0; b < bytes && w < 4; w++) {
985 (void) pci_read_config_dword(pdev, b, &dw);
986 printk("%08x ", dw);
987 b += sizeof(u32);
988 }
989 printk("\n");
990 }
991 #endif
992 }
993 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
994 struct pci_dev *pdev)
995 {
996 #ifdef ATA_DEBUG
997 void __iomem *hc_base = mv_hc_base(mmio_base,
998 port >> MV_PORT_HC_SHIFT);
999 void __iomem *port_base;
1000 int start_port, num_ports, p, start_hc, num_hcs, hc;
1001
1002 if (0 > port) {
1003 start_hc = start_port = 0;
1004 num_ports = 8; /* shld be benign for 4 port devs */
1005 num_hcs = 2;
1006 } else {
1007 start_hc = port >> MV_PORT_HC_SHIFT;
1008 start_port = port;
1009 num_ports = num_hcs = 1;
1010 }
1011 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
1012 num_ports > 1 ? num_ports - 1 : start_port);
1013
1014 if (NULL != pdev) {
1015 DPRINTK("PCI config space regs:\n");
1016 mv_dump_pci_cfg(pdev, 0x68);
1017 }
1018 DPRINTK("PCI regs:\n");
1019 mv_dump_mem(mmio_base+0xc00, 0x3c);
1020 mv_dump_mem(mmio_base+0xd00, 0x34);
1021 mv_dump_mem(mmio_base+0xf00, 0x4);
1022 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1023 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
1024 hc_base = mv_hc_base(mmio_base, hc);
1025 DPRINTK("HC regs (HC %i):\n", hc);
1026 mv_dump_mem(hc_base, 0x1c);
1027 }
1028 for (p = start_port; p < start_port + num_ports; p++) {
1029 port_base = mv_port_base(mmio_base, p);
1030 DPRINTK("EDMA regs (port %i):\n", p);
1031 mv_dump_mem(port_base, 0x54);
1032 DPRINTK("SATA regs (port %i):\n", p);
1033 mv_dump_mem(port_base+0x300, 0x60);
1034 }
1035 #endif
1036 }
1037
1038 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1039 {
1040 unsigned int ofs;
1041
1042 switch (sc_reg_in) {
1043 case SCR_STATUS:
1044 case SCR_CONTROL:
1045 case SCR_ERROR:
1046 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1047 break;
1048 case SCR_ACTIVE:
1049 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1050 break;
1051 default:
1052 ofs = 0xffffffffU;
1053 break;
1054 }
1055 return ofs;
1056 }
1057
1058 static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
1059 {
1060 unsigned int ofs = mv_scr_offset(sc_reg_in);
1061
1062 if (ofs != 0xffffffffU) {
1063 *val = readl(mv_ap_base(ap) + ofs);
1064 return 0;
1065 } else
1066 return -EINVAL;
1067 }
1068
1069 static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1070 {
1071 unsigned int ofs = mv_scr_offset(sc_reg_in);
1072
1073 if (ofs != 0xffffffffU) {
1074 writelfl(val, mv_ap_base(ap) + ofs);
1075 return 0;
1076 } else
1077 return -EINVAL;
1078 }
1079
1080 static void mv6_dev_config(struct ata_device *adev)
1081 {
1082 /*
1083 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1084 *
1085 * Gen-II does not support NCQ over a port multiplier
1086 * (no FIS-based switching).
1087 *
1088 * We don't have hob_nsect when doing NCQ commands on Gen-II.
1089 * See mv_qc_prep() for more info.
1090 */
1091 if (adev->flags & ATA_DFLAG_NCQ) {
1092 if (sata_pmp_attached(adev->link->ap)) {
1093 adev->flags &= ~ATA_DFLAG_NCQ;
1094 ata_dev_printk(adev, KERN_INFO,
1095 "NCQ disabled for command-based switching\n");
1096 } else if (adev->max_sectors > GEN_II_NCQ_MAX_SECTORS) {
1097 adev->max_sectors = GEN_II_NCQ_MAX_SECTORS;
1098 ata_dev_printk(adev, KERN_INFO,
1099 "max_sectors limited to %u for NCQ\n",
1100 adev->max_sectors);
1101 }
1102 }
1103 }
1104
1105 static int mv_qc_defer(struct ata_queued_cmd *qc)
1106 {
1107 struct ata_link *link = qc->dev->link;
1108 struct ata_port *ap = link->ap;
1109 struct mv_port_priv *pp = ap->private_data;
1110
1111 /*
1112 * Don't allow new commands if we're in a delayed EH state
1113 * for NCQ and/or FIS-based switching.
1114 */
1115 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1116 return ATA_DEFER_PORT;
1117 /*
1118 * If the port is completely idle, then allow the new qc.
1119 */
1120 if (ap->nr_active_links == 0)
1121 return 0;
1122
1123 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1124 /*
1125 * The port is operating in host queuing mode (EDMA).
1126 * It can accomodate a new qc if the qc protocol
1127 * is compatible with the current host queue mode.
1128 */
1129 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
1130 /*
1131 * The host queue (EDMA) is in NCQ mode.
1132 * If the new qc is also an NCQ command,
1133 * then allow the new qc.
1134 */
1135 if (qc->tf.protocol == ATA_PROT_NCQ)
1136 return 0;
1137 } else {
1138 /*
1139 * The host queue (EDMA) is in non-NCQ, DMA mode.
1140 * If the new qc is also a non-NCQ, DMA command,
1141 * then allow the new qc.
1142 */
1143 if (qc->tf.protocol == ATA_PROT_DMA)
1144 return 0;
1145 }
1146 }
1147 return ATA_DEFER_PORT;
1148 }
1149
1150 static void mv_config_fbs(void __iomem *port_mmio, int want_ncq, int want_fbs)
1151 {
1152 u32 new_fiscfg, old_fiscfg;
1153 u32 new_ltmode, old_ltmode;
1154 u32 new_haltcond, old_haltcond;
1155
1156 old_fiscfg = readl(port_mmio + FISCFG_OFS);
1157 old_ltmode = readl(port_mmio + LTMODE_OFS);
1158 old_haltcond = readl(port_mmio + EDMA_HALTCOND_OFS);
1159
1160 new_fiscfg = old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1161 new_ltmode = old_ltmode & ~LTMODE_BIT8;
1162 new_haltcond = old_haltcond | EDMA_ERR_DEV;
1163
1164 if (want_fbs) {
1165 new_fiscfg = old_fiscfg | FISCFG_SINGLE_SYNC;
1166 new_ltmode = old_ltmode | LTMODE_BIT8;
1167 if (want_ncq)
1168 new_haltcond &= ~EDMA_ERR_DEV;
1169 else
1170 new_fiscfg |= FISCFG_WAIT_DEV_ERR;
1171 }
1172
1173 if (new_fiscfg != old_fiscfg)
1174 writelfl(new_fiscfg, port_mmio + FISCFG_OFS);
1175 if (new_ltmode != old_ltmode)
1176 writelfl(new_ltmode, port_mmio + LTMODE_OFS);
1177 if (new_haltcond != old_haltcond)
1178 writelfl(new_haltcond, port_mmio + EDMA_HALTCOND_OFS);
1179 }
1180
1181 static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1182 {
1183 struct mv_host_priv *hpriv = ap->host->private_data;
1184 u32 old, new;
1185
1186 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1187 old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS);
1188 if (want_ncq)
1189 new = old | (1 << 22);
1190 else
1191 new = old & ~(1 << 22);
1192 if (new != old)
1193 writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS);
1194 }
1195
1196 static void mv_edma_cfg(struct ata_port *ap, int want_ncq)
1197 {
1198 u32 cfg;
1199 struct mv_port_priv *pp = ap->private_data;
1200 struct mv_host_priv *hpriv = ap->host->private_data;
1201 void __iomem *port_mmio = mv_ap_base(ap);
1202
1203 /* set up non-NCQ EDMA configuration */
1204 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
1205 pp->pp_flags &= ~MV_PP_FLAG_FBS_EN;
1206
1207 if (IS_GEN_I(hpriv))
1208 cfg |= (1 << 8); /* enab config burst size mask */
1209
1210 else if (IS_GEN_II(hpriv)) {
1211 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
1212 mv_60x1_errata_sata25(ap, want_ncq);
1213
1214 } else if (IS_GEN_IIE(hpriv)) {
1215 int want_fbs = sata_pmp_attached(ap);
1216 /*
1217 * Possible future enhancement:
1218 *
1219 * The chip can use FBS with non-NCQ, if we allow it,
1220 * But first we need to have the error handling in place
1221 * for this mode (datasheet section 7.3.15.4.2.3).
1222 * So disallow non-NCQ FBS for now.
1223 */
1224 want_fbs &= want_ncq;
1225
1226 mv_config_fbs(port_mmio, want_ncq, want_fbs);
1227
1228 if (want_fbs) {
1229 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1230 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1231 }
1232
1233 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1234 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1235 if (HAS_PCI(ap->host))
1236 cfg |= (1 << 18); /* enab early completion */
1237 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1238 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
1239 }
1240
1241 if (want_ncq) {
1242 cfg |= EDMA_CFG_NCQ;
1243 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1244 } else
1245 pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN;
1246
1247 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1248 }
1249
1250 static void mv_port_free_dma_mem(struct ata_port *ap)
1251 {
1252 struct mv_host_priv *hpriv = ap->host->private_data;
1253 struct mv_port_priv *pp = ap->private_data;
1254 int tag;
1255
1256 if (pp->crqb) {
1257 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1258 pp->crqb = NULL;
1259 }
1260 if (pp->crpb) {
1261 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1262 pp->crpb = NULL;
1263 }
1264 /*
1265 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1266 * For later hardware, we have one unique sg_tbl per NCQ tag.
1267 */
1268 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1269 if (pp->sg_tbl[tag]) {
1270 if (tag == 0 || !IS_GEN_I(hpriv))
1271 dma_pool_free(hpriv->sg_tbl_pool,
1272 pp->sg_tbl[tag],
1273 pp->sg_tbl_dma[tag]);
1274 pp->sg_tbl[tag] = NULL;
1275 }
1276 }
1277 }
1278
1279 /**
1280 * mv_port_start - Port specific init/start routine.
1281 * @ap: ATA channel to manipulate
1282 *
1283 * Allocate and point to DMA memory, init port private memory,
1284 * zero indices.
1285 *
1286 * LOCKING:
1287 * Inherited from caller.
1288 */
1289 static int mv_port_start(struct ata_port *ap)
1290 {
1291 struct device *dev = ap->host->dev;
1292 struct mv_host_priv *hpriv = ap->host->private_data;
1293 struct mv_port_priv *pp;
1294 int tag;
1295
1296 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1297 if (!pp)
1298 return -ENOMEM;
1299 ap->private_data = pp;
1300
1301 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1302 if (!pp->crqb)
1303 return -ENOMEM;
1304 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
1305
1306 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1307 if (!pp->crpb)
1308 goto out_port_free_dma_mem;
1309 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
1310
1311 /*
1312 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1313 * For later hardware, we need one unique sg_tbl per NCQ tag.
1314 */
1315 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1316 if (tag == 0 || !IS_GEN_I(hpriv)) {
1317 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1318 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1319 if (!pp->sg_tbl[tag])
1320 goto out_port_free_dma_mem;
1321 } else {
1322 pp->sg_tbl[tag] = pp->sg_tbl[0];
1323 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1324 }
1325 }
1326 return 0;
1327
1328 out_port_free_dma_mem:
1329 mv_port_free_dma_mem(ap);
1330 return -ENOMEM;
1331 }
1332
1333 /**
1334 * mv_port_stop - Port specific cleanup/stop routine.
1335 * @ap: ATA channel to manipulate
1336 *
1337 * Stop DMA, cleanup port memory.
1338 *
1339 * LOCKING:
1340 * This routine uses the host lock to protect the DMA stop.
1341 */
1342 static void mv_port_stop(struct ata_port *ap)
1343 {
1344 mv_stop_edma(ap);
1345 mv_port_free_dma_mem(ap);
1346 }
1347
1348 /**
1349 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1350 * @qc: queued command whose SG list to source from
1351 *
1352 * Populate the SG list and mark the last entry.
1353 *
1354 * LOCKING:
1355 * Inherited from caller.
1356 */
1357 static void mv_fill_sg(struct ata_queued_cmd *qc)
1358 {
1359 struct mv_port_priv *pp = qc->ap->private_data;
1360 struct scatterlist *sg;
1361 struct mv_sg *mv_sg, *last_sg = NULL;
1362 unsigned int si;
1363
1364 mv_sg = pp->sg_tbl[qc->tag];
1365 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1366 dma_addr_t addr = sg_dma_address(sg);
1367 u32 sg_len = sg_dma_len(sg);
1368
1369 while (sg_len) {
1370 u32 offset = addr & 0xffff;
1371 u32 len = sg_len;
1372
1373 if ((offset + sg_len > 0x10000))
1374 len = 0x10000 - offset;
1375
1376 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1377 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1378 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
1379
1380 sg_len -= len;
1381 addr += len;
1382
1383 last_sg = mv_sg;
1384 mv_sg++;
1385 }
1386 }
1387
1388 if (likely(last_sg))
1389 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1390 }
1391
1392 static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
1393 {
1394 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1395 (last ? CRQB_CMD_LAST : 0);
1396 *cmdw = cpu_to_le16(tmp);
1397 }
1398
1399 /**
1400 * mv_qc_prep - Host specific command preparation.
1401 * @qc: queued command to prepare
1402 *
1403 * This routine simply redirects to the general purpose routine
1404 * if command is not DMA. Else, it handles prep of the CRQB
1405 * (command request block), does some sanity checking, and calls
1406 * the SG load routine.
1407 *
1408 * LOCKING:
1409 * Inherited from caller.
1410 */
1411 static void mv_qc_prep(struct ata_queued_cmd *qc)
1412 {
1413 struct ata_port *ap = qc->ap;
1414 struct mv_port_priv *pp = ap->private_data;
1415 __le16 *cw;
1416 struct ata_taskfile *tf;
1417 u16 flags = 0;
1418 unsigned in_index;
1419
1420 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1421 (qc->tf.protocol != ATA_PROT_NCQ))
1422 return;
1423
1424 /* Fill in command request block
1425 */
1426 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1427 flags |= CRQB_FLAG_READ;
1428 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1429 flags |= qc->tag << CRQB_TAG_SHIFT;
1430 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
1431
1432 /* get current queue index from software */
1433 in_index = pp->req_idx;
1434
1435 pp->crqb[in_index].sg_addr =
1436 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1437 pp->crqb[in_index].sg_addr_hi =
1438 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
1439 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
1440
1441 cw = &pp->crqb[in_index].ata_cmd[0];
1442 tf = &qc->tf;
1443
1444 /* Sadly, the CRQB cannot accomodate all registers--there are
1445 * only 11 bytes...so we must pick and choose required
1446 * registers based on the command. So, we drop feature and
1447 * hob_feature for [RW] DMA commands, but they are needed for
1448 * NCQ. NCQ will drop hob_nsect.
1449 */
1450 switch (tf->command) {
1451 case ATA_CMD_READ:
1452 case ATA_CMD_READ_EXT:
1453 case ATA_CMD_WRITE:
1454 case ATA_CMD_WRITE_EXT:
1455 case ATA_CMD_WRITE_FUA_EXT:
1456 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1457 break;
1458 case ATA_CMD_FPDMA_READ:
1459 case ATA_CMD_FPDMA_WRITE:
1460 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
1461 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1462 break;
1463 default:
1464 /* The only other commands EDMA supports in non-queued and
1465 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1466 * of which are defined/used by Linux. If we get here, this
1467 * driver needs work.
1468 *
1469 * FIXME: modify libata to give qc_prep a return value and
1470 * return error here.
1471 */
1472 BUG_ON(tf->command);
1473 break;
1474 }
1475 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1476 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1477 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1478 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1479 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1480 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1481 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1482 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1483 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1484
1485 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1486 return;
1487 mv_fill_sg(qc);
1488 }
1489
1490 /**
1491 * mv_qc_prep_iie - Host specific command preparation.
1492 * @qc: queued command to prepare
1493 *
1494 * This routine simply redirects to the general purpose routine
1495 * if command is not DMA. Else, it handles prep of the CRQB
1496 * (command request block), does some sanity checking, and calls
1497 * the SG load routine.
1498 *
1499 * LOCKING:
1500 * Inherited from caller.
1501 */
1502 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1503 {
1504 struct ata_port *ap = qc->ap;
1505 struct mv_port_priv *pp = ap->private_data;
1506 struct mv_crqb_iie *crqb;
1507 struct ata_taskfile *tf;
1508 unsigned in_index;
1509 u32 flags = 0;
1510
1511 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1512 (qc->tf.protocol != ATA_PROT_NCQ))
1513 return;
1514
1515 /* Fill in Gen IIE command request block */
1516 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1517 flags |= CRQB_FLAG_READ;
1518
1519 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1520 flags |= qc->tag << CRQB_TAG_SHIFT;
1521 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
1522 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
1523
1524 /* get current queue index from software */
1525 in_index = pp->req_idx;
1526
1527 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
1528 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1529 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
1530 crqb->flags = cpu_to_le32(flags);
1531
1532 tf = &qc->tf;
1533 crqb->ata_cmd[0] = cpu_to_le32(
1534 (tf->command << 16) |
1535 (tf->feature << 24)
1536 );
1537 crqb->ata_cmd[1] = cpu_to_le32(
1538 (tf->lbal << 0) |
1539 (tf->lbam << 8) |
1540 (tf->lbah << 16) |
1541 (tf->device << 24)
1542 );
1543 crqb->ata_cmd[2] = cpu_to_le32(
1544 (tf->hob_lbal << 0) |
1545 (tf->hob_lbam << 8) |
1546 (tf->hob_lbah << 16) |
1547 (tf->hob_feature << 24)
1548 );
1549 crqb->ata_cmd[3] = cpu_to_le32(
1550 (tf->nsect << 0) |
1551 (tf->hob_nsect << 8)
1552 );
1553
1554 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1555 return;
1556 mv_fill_sg(qc);
1557 }
1558
1559 /**
1560 * mv_qc_issue - Initiate a command to the host
1561 * @qc: queued command to start
1562 *
1563 * This routine simply redirects to the general purpose routine
1564 * if command is not DMA. Else, it sanity checks our local
1565 * caches of the request producer/consumer indices then enables
1566 * DMA and bumps the request producer index.
1567 *
1568 * LOCKING:
1569 * Inherited from caller.
1570 */
1571 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
1572 {
1573 struct ata_port *ap = qc->ap;
1574 void __iomem *port_mmio = mv_ap_base(ap);
1575 struct mv_port_priv *pp = ap->private_data;
1576 u32 in_index;
1577
1578 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1579 (qc->tf.protocol != ATA_PROT_NCQ)) {
1580 /*
1581 * We're about to send a non-EDMA capable command to the
1582 * port. Turn off EDMA so there won't be problems accessing
1583 * shadow block, etc registers.
1584 */
1585 mv_stop_edma(ap);
1586 mv_pmp_select(ap, qc->dev->link->pmp);
1587 return ata_sff_qc_issue(qc);
1588 }
1589
1590 mv_start_dma(ap, port_mmio, pp, qc->tf.protocol);
1591
1592 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1593 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
1594
1595 /* and write the request in pointer to kick the EDMA to life */
1596 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
1597 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1598
1599 return 0;
1600 }
1601
1602 static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
1603 {
1604 struct mv_port_priv *pp = ap->private_data;
1605 struct ata_queued_cmd *qc;
1606
1607 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1608 return NULL;
1609 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1610 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1611 qc = NULL;
1612 return qc;
1613 }
1614
1615 static void mv_pmp_error_handler(struct ata_port *ap)
1616 {
1617 unsigned int pmp, pmp_map;
1618 struct mv_port_priv *pp = ap->private_data;
1619
1620 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
1621 /*
1622 * Perform NCQ error analysis on failed PMPs
1623 * before we freeze the port entirely.
1624 *
1625 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
1626 */
1627 pmp_map = pp->delayed_eh_pmp_map;
1628 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
1629 for (pmp = 0; pmp_map != 0; pmp++) {
1630 unsigned int this_pmp = (1 << pmp);
1631 if (pmp_map & this_pmp) {
1632 struct ata_link *link = &ap->pmp_link[pmp];
1633 pmp_map &= ~this_pmp;
1634 ata_eh_analyze_ncq_error(link);
1635 }
1636 }
1637 ata_port_freeze(ap);
1638 }
1639 sata_pmp_error_handler(ap);
1640 }
1641
1642 static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
1643 {
1644 void __iomem *port_mmio = mv_ap_base(ap);
1645
1646 return readl(port_mmio + SATA_TESTCTL_OFS) >> 16;
1647 }
1648
1649 static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
1650 {
1651 struct ata_eh_info *ehi;
1652 unsigned int pmp;
1653
1654 /*
1655 * Initialize EH info for PMPs which saw device errors
1656 */
1657 ehi = &ap->link.eh_info;
1658 for (pmp = 0; pmp_map != 0; pmp++) {
1659 unsigned int this_pmp = (1 << pmp);
1660 if (pmp_map & this_pmp) {
1661 struct ata_link *link = &ap->pmp_link[pmp];
1662
1663 pmp_map &= ~this_pmp;
1664 ehi = &link->eh_info;
1665 ata_ehi_clear_desc(ehi);
1666 ata_ehi_push_desc(ehi, "dev err");
1667 ehi->err_mask |= AC_ERR_DEV;
1668 ehi->action |= ATA_EH_RESET;
1669 ata_link_abort(link);
1670 }
1671 }
1672 }
1673
1674 static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
1675 {
1676 struct mv_port_priv *pp = ap->private_data;
1677 int failed_links;
1678 unsigned int old_map, new_map;
1679
1680 /*
1681 * Device error during FBS+NCQ operation:
1682 *
1683 * Set a port flag to prevent further I/O being enqueued.
1684 * Leave the EDMA running to drain outstanding commands from this port.
1685 * Perform the post-mortem/EH only when all responses are complete.
1686 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
1687 */
1688 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
1689 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
1690 pp->delayed_eh_pmp_map = 0;
1691 }
1692 old_map = pp->delayed_eh_pmp_map;
1693 new_map = old_map | mv_get_err_pmp_map(ap);
1694
1695 if (old_map != new_map) {
1696 pp->delayed_eh_pmp_map = new_map;
1697 mv_pmp_eh_prep(ap, new_map & ~old_map);
1698 }
1699 failed_links = hweight16(new_map);
1700
1701 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
1702 "failed_links=%d nr_active_links=%d\n",
1703 __func__, pp->delayed_eh_pmp_map,
1704 ap->qc_active, failed_links,
1705 ap->nr_active_links);
1706
1707 if (ap->nr_active_links <= failed_links) {
1708 mv_process_crpb_entries(ap, pp);
1709 mv_stop_edma(ap);
1710 mv_eh_freeze(ap);
1711 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
1712 return 1; /* handled */
1713 }
1714 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
1715 return 1; /* handled */
1716 }
1717
1718 static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
1719 {
1720 /*
1721 * Possible future enhancement:
1722 *
1723 * FBS+non-NCQ operation is not yet implemented.
1724 * See related notes in mv_edma_cfg().
1725 *
1726 * Device error during FBS+non-NCQ operation:
1727 *
1728 * We need to snapshot the shadow registers for each failed command.
1729 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
1730 */
1731 return 0; /* not handled */
1732 }
1733
1734 static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
1735 {
1736 struct mv_port_priv *pp = ap->private_data;
1737
1738 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1739 return 0; /* EDMA was not active: not handled */
1740 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
1741 return 0; /* FBS was not active: not handled */
1742
1743 if (!(edma_err_cause & EDMA_ERR_DEV))
1744 return 0; /* non DEV error: not handled */
1745 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
1746 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
1747 return 0; /* other problems: not handled */
1748
1749 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
1750 /*
1751 * EDMA should NOT have self-disabled for this case.
1752 * If it did, then something is wrong elsewhere,
1753 * and we cannot handle it here.
1754 */
1755 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
1756 ata_port_printk(ap, KERN_WARNING,
1757 "%s: err_cause=0x%x pp_flags=0x%x\n",
1758 __func__, edma_err_cause, pp->pp_flags);
1759 return 0; /* not handled */
1760 }
1761 return mv_handle_fbs_ncq_dev_err(ap);
1762 } else {
1763 /*
1764 * EDMA should have self-disabled for this case.
1765 * If it did not, then something is wrong elsewhere,
1766 * and we cannot handle it here.
1767 */
1768 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
1769 ata_port_printk(ap, KERN_WARNING,
1770 "%s: err_cause=0x%x pp_flags=0x%x\n",
1771 __func__, edma_err_cause, pp->pp_flags);
1772 return 0; /* not handled */
1773 }
1774 return mv_handle_fbs_non_ncq_dev_err(ap);
1775 }
1776 return 0; /* not handled */
1777 }
1778
1779 static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
1780 {
1781 struct ata_eh_info *ehi = &ap->link.eh_info;
1782 char *when = "idle";
1783
1784 ata_ehi_clear_desc(ehi);
1785 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
1786 when = "disabled";
1787 } else if (edma_was_enabled) {
1788 when = "EDMA enabled";
1789 } else {
1790 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
1791 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1792 when = "polling";
1793 }
1794 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
1795 ehi->err_mask |= AC_ERR_OTHER;
1796 ehi->action |= ATA_EH_RESET;
1797 ata_port_freeze(ap);
1798 }
1799
1800 /**
1801 * mv_err_intr - Handle error interrupts on the port
1802 * @ap: ATA channel to manipulate
1803 * @qc: affected command (non-NCQ), or NULL
1804 *
1805 * Most cases require a full reset of the chip's state machine,
1806 * which also performs a COMRESET.
1807 * Also, if the port disabled DMA, update our cached copy to match.
1808 *
1809 * LOCKING:
1810 * Inherited from caller.
1811 */
1812 static void mv_err_intr(struct ata_port *ap)
1813 {
1814 void __iomem *port_mmio = mv_ap_base(ap);
1815 u32 edma_err_cause, eh_freeze_mask, serr = 0;
1816 u32 fis_cause = 0;
1817 struct mv_port_priv *pp = ap->private_data;
1818 struct mv_host_priv *hpriv = ap->host->private_data;
1819 unsigned int action = 0, err_mask = 0;
1820 struct ata_eh_info *ehi = &ap->link.eh_info;
1821 struct ata_queued_cmd *qc;
1822 int abort = 0;
1823
1824 /*
1825 * Read and clear the SError and err_cause bits.
1826 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
1827 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
1828 */
1829 sata_scr_read(&ap->link, SCR_ERROR, &serr);
1830 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
1831
1832 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1833 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
1834 fis_cause = readl(port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1835 writelfl(~fis_cause, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1836 }
1837 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1838
1839 if (edma_err_cause & EDMA_ERR_DEV) {
1840 /*
1841 * Device errors during FIS-based switching operation
1842 * require special handling.
1843 */
1844 if (mv_handle_dev_err(ap, edma_err_cause))
1845 return;
1846 }
1847
1848 qc = mv_get_active_qc(ap);
1849 ata_ehi_clear_desc(ehi);
1850 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
1851 edma_err_cause, pp->pp_flags);
1852
1853 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7))
1854 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
1855 /*
1856 * All generations share these EDMA error cause bits:
1857 */
1858 if (edma_err_cause & EDMA_ERR_DEV) {
1859 err_mask |= AC_ERR_DEV;
1860 action |= ATA_EH_RESET;
1861 ata_ehi_push_desc(ehi, "dev error");
1862 }
1863 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
1864 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
1865 EDMA_ERR_INTRL_PAR)) {
1866 err_mask |= AC_ERR_ATA_BUS;
1867 action |= ATA_EH_RESET;
1868 ata_ehi_push_desc(ehi, "parity error");
1869 }
1870 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
1871 ata_ehi_hotplugged(ehi);
1872 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
1873 "dev disconnect" : "dev connect");
1874 action |= ATA_EH_RESET;
1875 }
1876
1877 /*
1878 * Gen-I has a different SELF_DIS bit,
1879 * different FREEZE bits, and no SERR bit:
1880 */
1881 if (IS_GEN_I(hpriv)) {
1882 eh_freeze_mask = EDMA_EH_FREEZE_5;
1883 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
1884 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1885 ata_ehi_push_desc(ehi, "EDMA self-disable");
1886 }
1887 } else {
1888 eh_freeze_mask = EDMA_EH_FREEZE;
1889 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
1890 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1891 ata_ehi_push_desc(ehi, "EDMA self-disable");
1892 }
1893 if (edma_err_cause & EDMA_ERR_SERR) {
1894 ata_ehi_push_desc(ehi, "SError=%08x", serr);
1895 err_mask |= AC_ERR_ATA_BUS;
1896 action |= ATA_EH_RESET;
1897 }
1898 }
1899
1900 if (!err_mask) {
1901 err_mask = AC_ERR_OTHER;
1902 action |= ATA_EH_RESET;
1903 }
1904
1905 ehi->serror |= serr;
1906 ehi->action |= action;
1907
1908 if (qc)
1909 qc->err_mask |= err_mask;
1910 else
1911 ehi->err_mask |= err_mask;
1912
1913 if (err_mask == AC_ERR_DEV) {
1914 /*
1915 * Cannot do ata_port_freeze() here,
1916 * because it would kill PIO access,
1917 * which is needed for further diagnosis.
1918 */
1919 mv_eh_freeze(ap);
1920 abort = 1;
1921 } else if (edma_err_cause & eh_freeze_mask) {
1922 /*
1923 * Note to self: ata_port_freeze() calls ata_port_abort()
1924 */
1925 ata_port_freeze(ap);
1926 } else {
1927 abort = 1;
1928 }
1929
1930 if (abort) {
1931 if (qc)
1932 ata_link_abort(qc->dev->link);
1933 else
1934 ata_port_abort(ap);
1935 }
1936 }
1937
1938 static void mv_process_crpb_response(struct ata_port *ap,
1939 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
1940 {
1941 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
1942
1943 if (qc) {
1944 u8 ata_status;
1945 u16 edma_status = le16_to_cpu(response->flags);
1946 /*
1947 * edma_status from a response queue entry:
1948 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
1949 * MSB is saved ATA status from command completion.
1950 */
1951 if (!ncq_enabled) {
1952 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
1953 if (err_cause) {
1954 /*
1955 * Error will be seen/handled by mv_err_intr().
1956 * So do nothing at all here.
1957 */
1958 return;
1959 }
1960 }
1961 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
1962 if (!ac_err_mask(ata_status))
1963 ata_qc_complete(qc);
1964 /* else: leave it for mv_err_intr() */
1965 } else {
1966 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
1967 __func__, tag);
1968 }
1969 }
1970
1971 static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
1972 {
1973 void __iomem *port_mmio = mv_ap_base(ap);
1974 struct mv_host_priv *hpriv = ap->host->private_data;
1975 u32 in_index;
1976 bool work_done = false;
1977 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
1978
1979 /* Get the hardware queue position index */
1980 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
1981 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1982
1983 /* Process new responses from since the last time we looked */
1984 while (in_index != pp->resp_idx) {
1985 unsigned int tag;
1986 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
1987
1988 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1989
1990 if (IS_GEN_I(hpriv)) {
1991 /* 50xx: no NCQ, only one command active at a time */
1992 tag = ap->link.active_tag;
1993 } else {
1994 /* Gen II/IIE: get command tag from CRPB entry */
1995 tag = le16_to_cpu(response->id) & 0x1f;
1996 }
1997 mv_process_crpb_response(ap, response, tag, ncq_enabled);
1998 work_done = true;
1999 }
2000
2001 /* Update the software queue position index in hardware */
2002 if (work_done)
2003 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
2004 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
2005 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
2006 }
2007
2008 static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2009 {
2010 struct mv_port_priv *pp;
2011 int edma_was_enabled;
2012
2013 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2014 mv_unexpected_intr(ap, 0);
2015 return;
2016 }
2017 /*
2018 * Grab a snapshot of the EDMA_EN flag setting,
2019 * so that we have a consistent view for this port,
2020 * even if something we call of our routines changes it.
2021 */
2022 pp = ap->private_data;
2023 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2024 /*
2025 * Process completed CRPB response(s) before other events.
2026 */
2027 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2028 mv_process_crpb_entries(ap, pp);
2029 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2030 mv_handle_fbs_ncq_dev_err(ap);
2031 }
2032 /*
2033 * Handle chip-reported errors, or continue on to handle PIO.
2034 */
2035 if (unlikely(port_cause & ERR_IRQ)) {
2036 mv_err_intr(ap);
2037 } else if (!edma_was_enabled) {
2038 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2039 if (qc)
2040 ata_sff_host_intr(ap, qc);
2041 else
2042 mv_unexpected_intr(ap, edma_was_enabled);
2043 }
2044 }
2045
2046 /**
2047 * mv_host_intr - Handle all interrupts on the given host controller
2048 * @host: host specific structure
2049 * @main_irq_cause: Main interrupt cause register for the chip.
2050 *
2051 * LOCKING:
2052 * Inherited from caller.
2053 */
2054 static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
2055 {
2056 struct mv_host_priv *hpriv = host->private_data;
2057 void __iomem *mmio = hpriv->base, *hc_mmio;
2058 unsigned int handled = 0, port;
2059
2060 for (port = 0; port < hpriv->n_ports; port++) {
2061 struct ata_port *ap = host->ports[port];
2062 unsigned int p, shift, hardport, port_cause;
2063
2064 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2065 /*
2066 * Each hc within the host has its own hc_irq_cause register,
2067 * where the interrupting ports bits get ack'd.
2068 */
2069 if (hardport == 0) { /* first port on this hc ? */
2070 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2071 u32 port_mask, ack_irqs;
2072 /*
2073 * Skip this entire hc if nothing pending for any ports
2074 */
2075 if (!hc_cause) {
2076 port += MV_PORTS_PER_HC - 1;
2077 continue;
2078 }
2079 /*
2080 * We don't need/want to read the hc_irq_cause register,
2081 * because doing so hurts performance, and
2082 * main_irq_cause already gives us everything we need.
2083 *
2084 * But we do have to *write* to the hc_irq_cause to ack
2085 * the ports that we are handling this time through.
2086 *
2087 * This requires that we create a bitmap for those
2088 * ports which interrupted us, and use that bitmap
2089 * to ack (only) those ports via hc_irq_cause.
2090 */
2091 ack_irqs = 0;
2092 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2093 if ((port + p) >= hpriv->n_ports)
2094 break;
2095 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2096 if (hc_cause & port_mask)
2097 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2098 }
2099 hc_mmio = mv_hc_base_from_port(mmio, port);
2100 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS);
2101 handled = 1;
2102 }
2103 /*
2104 * Handle interrupts signalled for this port:
2105 */
2106 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2107 if (port_cause)
2108 mv_port_intr(ap, port_cause);
2109 }
2110 return handled;
2111 }
2112
2113 static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
2114 {
2115 struct mv_host_priv *hpriv = host->private_data;
2116 struct ata_port *ap;
2117 struct ata_queued_cmd *qc;
2118 struct ata_eh_info *ehi;
2119 unsigned int i, err_mask, printed = 0;
2120 u32 err_cause;
2121
2122 err_cause = readl(mmio + hpriv->irq_cause_ofs);
2123
2124 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2125 err_cause);
2126
2127 DPRINTK("All regs @ PCI error\n");
2128 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2129
2130 writelfl(0, mmio + hpriv->irq_cause_ofs);
2131
2132 for (i = 0; i < host->n_ports; i++) {
2133 ap = host->ports[i];
2134 if (!ata_link_offline(&ap->link)) {
2135 ehi = &ap->link.eh_info;
2136 ata_ehi_clear_desc(ehi);
2137 if (!printed++)
2138 ata_ehi_push_desc(ehi,
2139 "PCI err cause 0x%08x", err_cause);
2140 err_mask = AC_ERR_HOST_BUS;
2141 ehi->action = ATA_EH_RESET;
2142 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2143 if (qc)
2144 qc->err_mask |= err_mask;
2145 else
2146 ehi->err_mask |= err_mask;
2147
2148 ata_port_freeze(ap);
2149 }
2150 }
2151 return 1; /* handled */
2152 }
2153
2154 /**
2155 * mv_interrupt - Main interrupt event handler
2156 * @irq: unused
2157 * @dev_instance: private data; in this case the host structure
2158 *
2159 * Read the read only register to determine if any host
2160 * controllers have pending interrupts. If so, call lower level
2161 * routine to handle. Also check for PCI errors which are only
2162 * reported here.
2163 *
2164 * LOCKING:
2165 * This routine holds the host lock while processing pending
2166 * interrupts.
2167 */
2168 static irqreturn_t mv_interrupt(int irq, void *dev_instance)
2169 {
2170 struct ata_host *host = dev_instance;
2171 struct mv_host_priv *hpriv = host->private_data;
2172 unsigned int handled = 0;
2173 u32 main_irq_cause, main_irq_mask;
2174
2175 spin_lock(&host->lock);
2176 main_irq_cause = readl(hpriv->main_irq_cause_addr);
2177 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2178 /*
2179 * Deal with cases where we either have nothing pending, or have read
2180 * a bogus register value which can indicate HW removal or PCI fault.
2181 */
2182 if ((main_irq_cause & main_irq_mask) && (main_irq_cause != 0xffffffffU)) {
2183 if (unlikely((main_irq_cause & PCI_ERR) && HAS_PCI(host)))
2184 handled = mv_pci_error(host, hpriv->base);
2185 else
2186 handled = mv_host_intr(host, main_irq_cause);
2187 }
2188 spin_unlock(&host->lock);
2189 return IRQ_RETVAL(handled);
2190 }
2191
2192 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2193 {
2194 unsigned int ofs;
2195
2196 switch (sc_reg_in) {
2197 case SCR_STATUS:
2198 case SCR_ERROR:
2199 case SCR_CONTROL:
2200 ofs = sc_reg_in * sizeof(u32);
2201 break;
2202 default:
2203 ofs = 0xffffffffU;
2204 break;
2205 }
2206 return ofs;
2207 }
2208
2209 static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
2210 {
2211 struct mv_host_priv *hpriv = ap->host->private_data;
2212 void __iomem *mmio = hpriv->base;
2213 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
2214 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2215
2216 if (ofs != 0xffffffffU) {
2217 *val = readl(addr + ofs);
2218 return 0;
2219 } else
2220 return -EINVAL;
2221 }
2222
2223 static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
2224 {
2225 struct mv_host_priv *hpriv = ap->host->private_data;
2226 void __iomem *mmio = hpriv->base;
2227 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
2228 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2229
2230 if (ofs != 0xffffffffU) {
2231 writelfl(val, addr + ofs);
2232 return 0;
2233 } else
2234 return -EINVAL;
2235 }
2236
2237 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
2238 {
2239 struct pci_dev *pdev = to_pci_dev(host->dev);
2240 int early_5080;
2241
2242 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
2243
2244 if (!early_5080) {
2245 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2246 tmp |= (1 << 0);
2247 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2248 }
2249
2250 mv_reset_pci_bus(host, mmio);
2251 }
2252
2253 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2254 {
2255 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS);
2256 }
2257
2258 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
2259 void __iomem *mmio)
2260 {
2261 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
2262 u32 tmp;
2263
2264 tmp = readl(phy_mmio + MV5_PHY_MODE);
2265
2266 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
2267 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
2268 }
2269
2270 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
2271 {
2272 u32 tmp;
2273
2274 writel(0, mmio + MV_GPIO_PORT_CTL_OFS);
2275
2276 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
2277
2278 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2279 tmp |= ~(1 << 0);
2280 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2281 }
2282
2283 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2284 unsigned int port)
2285 {
2286 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
2287 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
2288 u32 tmp;
2289 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
2290
2291 if (fix_apm_sq) {
2292 tmp = readl(phy_mmio + MV5_LTMODE_OFS);
2293 tmp |= (1 << 19);
2294 writel(tmp, phy_mmio + MV5_LTMODE_OFS);
2295
2296 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS);
2297 tmp &= ~0x3;
2298 tmp |= 0x1;
2299 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS);
2300 }
2301
2302 tmp = readl(phy_mmio + MV5_PHY_MODE);
2303 tmp &= ~mask;
2304 tmp |= hpriv->signal[port].pre;
2305 tmp |= hpriv->signal[port].amps;
2306 writel(tmp, phy_mmio + MV5_PHY_MODE);
2307 }
2308
2309
2310 #undef ZERO
2311 #define ZERO(reg) writel(0, port_mmio + (reg))
2312 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
2313 unsigned int port)
2314 {
2315 void __iomem *port_mmio = mv_port_base(mmio, port);
2316
2317 mv_reset_channel(hpriv, mmio, port);
2318
2319 ZERO(0x028); /* command */
2320 writel(0x11f, port_mmio + EDMA_CFG_OFS);
2321 ZERO(0x004); /* timer */
2322 ZERO(0x008); /* irq err cause */
2323 ZERO(0x00c); /* irq err mask */
2324 ZERO(0x010); /* rq bah */
2325 ZERO(0x014); /* rq inp */
2326 ZERO(0x018); /* rq outp */
2327 ZERO(0x01c); /* respq bah */
2328 ZERO(0x024); /* respq outp */
2329 ZERO(0x020); /* respq inp */
2330 ZERO(0x02c); /* test control */
2331 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
2332 }
2333 #undef ZERO
2334
2335 #define ZERO(reg) writel(0, hc_mmio + (reg))
2336 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2337 unsigned int hc)
2338 {
2339 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2340 u32 tmp;
2341
2342 ZERO(0x00c);
2343 ZERO(0x010);
2344 ZERO(0x014);
2345 ZERO(0x018);
2346
2347 tmp = readl(hc_mmio + 0x20);
2348 tmp &= 0x1c1c1c1c;
2349 tmp |= 0x03030303;
2350 writel(tmp, hc_mmio + 0x20);
2351 }
2352 #undef ZERO
2353
2354 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2355 unsigned int n_hc)
2356 {
2357 unsigned int hc, port;
2358
2359 for (hc = 0; hc < n_hc; hc++) {
2360 for (port = 0; port < MV_PORTS_PER_HC; port++)
2361 mv5_reset_hc_port(hpriv, mmio,
2362 (hc * MV_PORTS_PER_HC) + port);
2363
2364 mv5_reset_one_hc(hpriv, mmio, hc);
2365 }
2366
2367 return 0;
2368 }
2369
2370 #undef ZERO
2371 #define ZERO(reg) writel(0, mmio + (reg))
2372 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
2373 {
2374 struct mv_host_priv *hpriv = host->private_data;
2375 u32 tmp;
2376
2377 tmp = readl(mmio + MV_PCI_MODE_OFS);
2378 tmp &= 0xff00ffff;
2379 writel(tmp, mmio + MV_PCI_MODE_OFS);
2380
2381 ZERO(MV_PCI_DISC_TIMER);
2382 ZERO(MV_PCI_MSI_TRIGGER);
2383 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
2384 ZERO(PCI_HC_MAIN_IRQ_MASK_OFS);
2385 ZERO(MV_PCI_SERR_MASK);
2386 ZERO(hpriv->irq_cause_ofs);
2387 ZERO(hpriv->irq_mask_ofs);
2388 ZERO(MV_PCI_ERR_LOW_ADDRESS);
2389 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
2390 ZERO(MV_PCI_ERR_ATTRIBUTE);
2391 ZERO(MV_PCI_ERR_COMMAND);
2392 }
2393 #undef ZERO
2394
2395 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2396 {
2397 u32 tmp;
2398
2399 mv5_reset_flash(hpriv, mmio);
2400
2401 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS);
2402 tmp &= 0x3;
2403 tmp |= (1 << 5) | (1 << 6);
2404 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS);
2405 }
2406
2407 /**
2408 * mv6_reset_hc - Perform the 6xxx global soft reset
2409 * @mmio: base address of the HBA
2410 *
2411 * This routine only applies to 6xxx parts.
2412 *
2413 * LOCKING:
2414 * Inherited from caller.
2415 */
2416 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2417 unsigned int n_hc)
2418 {
2419 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
2420 int i, rc = 0;
2421 u32 t;
2422
2423 /* Following procedure defined in PCI "main command and status
2424 * register" table.
2425 */
2426 t = readl(reg);
2427 writel(t | STOP_PCI_MASTER, reg);
2428
2429 for (i = 0; i < 1000; i++) {
2430 udelay(1);
2431 t = readl(reg);
2432 if (PCI_MASTER_EMPTY & t)
2433 break;
2434 }
2435 if (!(PCI_MASTER_EMPTY & t)) {
2436 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
2437 rc = 1;
2438 goto done;
2439 }
2440
2441 /* set reset */
2442 i = 5;
2443 do {
2444 writel(t | GLOB_SFT_RST, reg);
2445 t = readl(reg);
2446 udelay(1);
2447 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
2448
2449 if (!(GLOB_SFT_RST & t)) {
2450 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
2451 rc = 1;
2452 goto done;
2453 }
2454
2455 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
2456 i = 5;
2457 do {
2458 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
2459 t = readl(reg);
2460 udelay(1);
2461 } while ((GLOB_SFT_RST & t) && (i-- > 0));
2462
2463 if (GLOB_SFT_RST & t) {
2464 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
2465 rc = 1;
2466 }
2467 done:
2468 return rc;
2469 }
2470
2471 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
2472 void __iomem *mmio)
2473 {
2474 void __iomem *port_mmio;
2475 u32 tmp;
2476
2477 tmp = readl(mmio + MV_RESET_CFG_OFS);
2478 if ((tmp & (1 << 0)) == 0) {
2479 hpriv->signal[idx].amps = 0x7 << 8;
2480 hpriv->signal[idx].pre = 0x1 << 5;
2481 return;
2482 }
2483
2484 port_mmio = mv_port_base(mmio, idx);
2485 tmp = readl(port_mmio + PHY_MODE2);
2486
2487 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2488 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2489 }
2490
2491 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
2492 {
2493 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS);
2494 }
2495
2496 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2497 unsigned int port)
2498 {
2499 void __iomem *port_mmio = mv_port_base(mmio, port);
2500
2501 u32 hp_flags = hpriv->hp_flags;
2502 int fix_phy_mode2 =
2503 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2504 int fix_phy_mode4 =
2505 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2506 u32 m2, tmp;
2507
2508 if (fix_phy_mode2) {
2509 m2 = readl(port_mmio + PHY_MODE2);
2510 m2 &= ~(1 << 16);
2511 m2 |= (1 << 31);
2512 writel(m2, port_mmio + PHY_MODE2);
2513
2514 udelay(200);
2515
2516 m2 = readl(port_mmio + PHY_MODE2);
2517 m2 &= ~((1 << 16) | (1 << 31));
2518 writel(m2, port_mmio + PHY_MODE2);
2519
2520 udelay(200);
2521 }
2522
2523 /* who knows what this magic does */
2524 tmp = readl(port_mmio + PHY_MODE3);
2525 tmp &= ~0x7F800000;
2526 tmp |= 0x2A800000;
2527 writel(tmp, port_mmio + PHY_MODE3);
2528
2529 if (fix_phy_mode4) {
2530 u32 m4;
2531
2532 m4 = readl(port_mmio + PHY_MODE4);
2533
2534 if (hp_flags & MV_HP_ERRATA_60X1B2)
2535 tmp = readl(port_mmio + PHY_MODE3);
2536
2537 /* workaround for errata FEr SATA#10 (part 1) */
2538 m4 = (m4 & ~(1 << 1)) | (1 << 0);
2539
2540 writel(m4, port_mmio + PHY_MODE4);
2541
2542 if (hp_flags & MV_HP_ERRATA_60X1B2)
2543 writel(tmp, port_mmio + PHY_MODE3);
2544 }
2545
2546 /* Revert values of pre-emphasis and signal amps to the saved ones */
2547 m2 = readl(port_mmio + PHY_MODE2);
2548
2549 m2 &= ~MV_M2_PREAMP_MASK;
2550 m2 |= hpriv->signal[port].amps;
2551 m2 |= hpriv->signal[port].pre;
2552 m2 &= ~(1 << 16);
2553
2554 /* according to mvSata 3.6.1, some IIE values are fixed */
2555 if (IS_GEN_IIE(hpriv)) {
2556 m2 &= ~0xC30FF01F;
2557 m2 |= 0x0000900F;
2558 }
2559
2560 writel(m2, port_mmio + PHY_MODE2);
2561 }
2562
2563 /* TODO: use the generic LED interface to configure the SATA Presence */
2564 /* & Acitivy LEDs on the board */
2565 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
2566 void __iomem *mmio)
2567 {
2568 return;
2569 }
2570
2571 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
2572 void __iomem *mmio)
2573 {
2574 void __iomem *port_mmio;
2575 u32 tmp;
2576
2577 port_mmio = mv_port_base(mmio, idx);
2578 tmp = readl(port_mmio + PHY_MODE2);
2579
2580 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2581 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2582 }
2583
2584 #undef ZERO
2585 #define ZERO(reg) writel(0, port_mmio + (reg))
2586 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
2587 void __iomem *mmio, unsigned int port)
2588 {
2589 void __iomem *port_mmio = mv_port_base(mmio, port);
2590
2591 mv_reset_channel(hpriv, mmio, port);
2592
2593 ZERO(0x028); /* command */
2594 writel(0x101f, port_mmio + EDMA_CFG_OFS);
2595 ZERO(0x004); /* timer */
2596 ZERO(0x008); /* irq err cause */
2597 ZERO(0x00c); /* irq err mask */
2598 ZERO(0x010); /* rq bah */
2599 ZERO(0x014); /* rq inp */
2600 ZERO(0x018); /* rq outp */
2601 ZERO(0x01c); /* respq bah */
2602 ZERO(0x024); /* respq outp */
2603 ZERO(0x020); /* respq inp */
2604 ZERO(0x02c); /* test control */
2605 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
2606 }
2607
2608 #undef ZERO
2609
2610 #define ZERO(reg) writel(0, hc_mmio + (reg))
2611 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
2612 void __iomem *mmio)
2613 {
2614 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
2615
2616 ZERO(0x00c);
2617 ZERO(0x010);
2618 ZERO(0x014);
2619
2620 }
2621
2622 #undef ZERO
2623
2624 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
2625 void __iomem *mmio, unsigned int n_hc)
2626 {
2627 unsigned int port;
2628
2629 for (port = 0; port < hpriv->n_ports; port++)
2630 mv_soc_reset_hc_port(hpriv, mmio, port);
2631
2632 mv_soc_reset_one_hc(hpriv, mmio);
2633
2634 return 0;
2635 }
2636
2637 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
2638 void __iomem *mmio)
2639 {
2640 return;
2641 }
2642
2643 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
2644 {
2645 return;
2646 }
2647
2648 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
2649 {
2650 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
2651
2652 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
2653 if (want_gen2i)
2654 ifcfg |= (1 << 7); /* enable gen2i speed */
2655 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS);
2656 }
2657
2658 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
2659 unsigned int port_no)
2660 {
2661 void __iomem *port_mmio = mv_port_base(mmio, port_no);
2662
2663 /*
2664 * The datasheet warns against setting EDMA_RESET when EDMA is active
2665 * (but doesn't say what the problem might be). So we first try
2666 * to disable the EDMA engine before doing the EDMA_RESET operation.
2667 */
2668 mv_stop_edma_engine(port_mmio);
2669 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
2670
2671 if (!IS_GEN_I(hpriv)) {
2672 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
2673 mv_setup_ifcfg(port_mmio, 1);
2674 }
2675 /*
2676 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
2677 * link, and physical layers. It resets all SATA interface registers
2678 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
2679 */
2680 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
2681 udelay(25); /* allow reset propagation */
2682 writelfl(0, port_mmio + EDMA_CMD_OFS);
2683
2684 hpriv->ops->phy_errata(hpriv, mmio, port_no);
2685
2686 if (IS_GEN_I(hpriv))
2687 mdelay(1);
2688 }
2689
2690 static void mv_pmp_select(struct ata_port *ap, int pmp)
2691 {
2692 if (sata_pmp_supported(ap)) {
2693 void __iomem *port_mmio = mv_ap_base(ap);
2694 u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
2695 int old = reg & 0xf;
2696
2697 if (old != pmp) {
2698 reg = (reg & ~0xf) | pmp;
2699 writelfl(reg, port_mmio + SATA_IFCTL_OFS);
2700 }
2701 }
2702 }
2703
2704 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
2705 unsigned long deadline)
2706 {
2707 mv_pmp_select(link->ap, sata_srst_pmp(link));
2708 return sata_std_hardreset(link, class, deadline);
2709 }
2710
2711 static int mv_softreset(struct ata_link *link, unsigned int *class,
2712 unsigned long deadline)
2713 {
2714 mv_pmp_select(link->ap, sata_srst_pmp(link));
2715 return ata_sff_softreset(link, class, deadline);
2716 }
2717
2718 static int mv_hardreset(struct ata_link *link, unsigned int *class,
2719 unsigned long deadline)
2720 {
2721 struct ata_port *ap = link->ap;
2722 struct mv_host_priv *hpriv = ap->host->private_data;
2723 struct mv_port_priv *pp = ap->private_data;
2724 void __iomem *mmio = hpriv->base;
2725 int rc, attempts = 0, extra = 0;
2726 u32 sstatus;
2727 bool online;
2728
2729 mv_reset_channel(hpriv, mmio, ap->port_no);
2730 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2731
2732 /* Workaround for errata FEr SATA#10 (part 2) */
2733 do {
2734 const unsigned long *timing =
2735 sata_ehc_deb_timing(&link->eh_context);
2736
2737 rc = sata_link_hardreset(link, timing, deadline + extra,
2738 &online, NULL);
2739 rc = online ? -EAGAIN : rc;
2740 if (rc)
2741 return rc;
2742 sata_scr_read(link, SCR_STATUS, &sstatus);
2743 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
2744 /* Force 1.5gb/s link speed and try again */
2745 mv_setup_ifcfg(mv_ap_base(ap), 0);
2746 if (time_after(jiffies + HZ, deadline))
2747 extra = HZ; /* only extend it once, max */
2748 }
2749 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
2750
2751 return rc;
2752 }
2753
2754 static void mv_eh_freeze(struct ata_port *ap)
2755 {
2756 struct mv_host_priv *hpriv = ap->host->private_data;
2757 unsigned int shift, hardport, port = ap->port_no;
2758 u32 main_irq_mask;
2759
2760 /* FIXME: handle coalescing completion events properly */
2761
2762 mv_stop_edma(ap);
2763 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2764
2765 /* disable assertion of portN err, done events */
2766 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2767 main_irq_mask &= ~((DONE_IRQ | ERR_IRQ) << shift);
2768 writelfl(main_irq_mask, hpriv->main_irq_mask_addr);
2769 }
2770
2771 static void mv_eh_thaw(struct ata_port *ap)
2772 {
2773 struct mv_host_priv *hpriv = ap->host->private_data;
2774 unsigned int shift, hardport, port = ap->port_no;
2775 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
2776 void __iomem *port_mmio = mv_ap_base(ap);
2777 u32 main_irq_mask, hc_irq_cause;
2778
2779 /* FIXME: handle coalescing completion events properly */
2780
2781 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2782
2783 /* clear EDMA errors on this port */
2784 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2785
2786 /* clear pending irq events */
2787 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
2788 hc_irq_cause &= ~((DEV_IRQ | DMA_IRQ) << hardport);
2789 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
2790
2791 /* enable assertion of portN err, done events */
2792 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2793 main_irq_mask |= ((DONE_IRQ | ERR_IRQ) << shift);
2794 writelfl(main_irq_mask, hpriv->main_irq_mask_addr);
2795 }
2796
2797 /**
2798 * mv_port_init - Perform some early initialization on a single port.
2799 * @port: libata data structure storing shadow register addresses
2800 * @port_mmio: base address of the port
2801 *
2802 * Initialize shadow register mmio addresses, clear outstanding
2803 * interrupts on the port, and unmask interrupts for the future
2804 * start of the port.
2805 *
2806 * LOCKING:
2807 * Inherited from caller.
2808 */
2809 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
2810 {
2811 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
2812 unsigned serr_ofs;
2813
2814 /* PIO related setup
2815 */
2816 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
2817 port->error_addr =
2818 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2819 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2820 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2821 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2822 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2823 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
2824 port->status_addr =
2825 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2826 /* special case: control/altstatus doesn't have ATA_REG_ address */
2827 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2828
2829 /* unused: */
2830 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
2831
2832 /* Clear any currently outstanding port interrupt conditions */
2833 serr_ofs = mv_scr_offset(SCR_ERROR);
2834 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2835 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2836
2837 /* unmask all non-transient EDMA error interrupts */
2838 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
2839
2840 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
2841 readl(port_mmio + EDMA_CFG_OFS),
2842 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2843 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
2844 }
2845
2846 static unsigned int mv_in_pcix_mode(struct ata_host *host)
2847 {
2848 struct mv_host_priv *hpriv = host->private_data;
2849 void __iomem *mmio = hpriv->base;
2850 u32 reg;
2851
2852 if (!HAS_PCI(host) || !IS_PCIE(hpriv))
2853 return 0; /* not PCI-X capable */
2854 reg = readl(mmio + MV_PCI_MODE_OFS);
2855 if ((reg & MV_PCI_MODE_MASK) == 0)
2856 return 0; /* conventional PCI mode */
2857 return 1; /* chip is in PCI-X mode */
2858 }
2859
2860 static int mv_pci_cut_through_okay(struct ata_host *host)
2861 {
2862 struct mv_host_priv *hpriv = host->private_data;
2863 void __iomem *mmio = hpriv->base;
2864 u32 reg;
2865
2866 if (!mv_in_pcix_mode(host)) {
2867 reg = readl(mmio + PCI_COMMAND_OFS);
2868 if (reg & PCI_COMMAND_MRDTRIG)
2869 return 0; /* not okay */
2870 }
2871 return 1; /* okay */
2872 }
2873
2874 static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
2875 {
2876 struct pci_dev *pdev = to_pci_dev(host->dev);
2877 struct mv_host_priv *hpriv = host->private_data;
2878 u32 hp_flags = hpriv->hp_flags;
2879
2880 switch (board_idx) {
2881 case chip_5080:
2882 hpriv->ops = &mv5xxx_ops;
2883 hp_flags |= MV_HP_GEN_I;
2884
2885 switch (pdev->revision) {
2886 case 0x1:
2887 hp_flags |= MV_HP_ERRATA_50XXB0;
2888 break;
2889 case 0x3:
2890 hp_flags |= MV_HP_ERRATA_50XXB2;
2891 break;
2892 default:
2893 dev_printk(KERN_WARNING, &pdev->dev,
2894 "Applying 50XXB2 workarounds to unknown rev\n");
2895 hp_flags |= MV_HP_ERRATA_50XXB2;
2896 break;
2897 }
2898 break;
2899
2900 case chip_504x:
2901 case chip_508x:
2902 hpriv->ops = &mv5xxx_ops;
2903 hp_flags |= MV_HP_GEN_I;
2904
2905 switch (pdev->revision) {
2906 case 0x0:
2907 hp_flags |= MV_HP_ERRATA_50XXB0;
2908 break;
2909 case 0x3:
2910 hp_flags |= MV_HP_ERRATA_50XXB2;
2911 break;
2912 default:
2913 dev_printk(KERN_WARNING, &pdev->dev,
2914 "Applying B2 workarounds to unknown rev\n");
2915 hp_flags |= MV_HP_ERRATA_50XXB2;
2916 break;
2917 }
2918 break;
2919
2920 case chip_604x:
2921 case chip_608x:
2922 hpriv->ops = &mv6xxx_ops;
2923 hp_flags |= MV_HP_GEN_II;
2924
2925 switch (pdev->revision) {
2926 case 0x7:
2927 hp_flags |= MV_HP_ERRATA_60X1B2;
2928 break;
2929 case 0x9:
2930 hp_flags |= MV_HP_ERRATA_60X1C0;
2931 break;
2932 default:
2933 dev_printk(KERN_WARNING, &pdev->dev,
2934 "Applying B2 workarounds to unknown rev\n");
2935 hp_flags |= MV_HP_ERRATA_60X1B2;
2936 break;
2937 }
2938 break;
2939
2940 case chip_7042:
2941 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
2942 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
2943 (pdev->device == 0x2300 || pdev->device == 0x2310))
2944 {
2945 /*
2946 * Highpoint RocketRAID PCIe 23xx series cards:
2947 *
2948 * Unconfigured drives are treated as "Legacy"
2949 * by the BIOS, and it overwrites sector 8 with
2950 * a "Lgcy" metadata block prior to Linux boot.
2951 *
2952 * Configured drives (RAID or JBOD) leave sector 8
2953 * alone, but instead overwrite a high numbered
2954 * sector for the RAID metadata. This sector can
2955 * be determined exactly, by truncating the physical
2956 * drive capacity to a nice even GB value.
2957 *
2958 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
2959 *
2960 * Warn the user, lest they think we're just buggy.
2961 */
2962 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
2963 " BIOS CORRUPTS DATA on all attached drives,"
2964 " regardless of if/how they are configured."
2965 " BEWARE!\n");
2966 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
2967 " use sectors 8-9 on \"Legacy\" drives,"
2968 " and avoid the final two gigabytes on"
2969 " all RocketRAID BIOS initialized drives.\n");
2970 }
2971 /* drop through */
2972 case chip_6042:
2973 hpriv->ops = &mv6xxx_ops;
2974 hp_flags |= MV_HP_GEN_IIE;
2975 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
2976 hp_flags |= MV_HP_CUT_THROUGH;
2977
2978 switch (pdev->revision) {
2979 case 0x0:
2980 hp_flags |= MV_HP_ERRATA_XX42A0;
2981 break;
2982 case 0x1:
2983 hp_flags |= MV_HP_ERRATA_60X1C0;
2984 break;
2985 default:
2986 dev_printk(KERN_WARNING, &pdev->dev,
2987 "Applying 60X1C0 workarounds to unknown rev\n");
2988 hp_flags |= MV_HP_ERRATA_60X1C0;
2989 break;
2990 }
2991 break;
2992 case chip_soc:
2993 hpriv->ops = &mv_soc_ops;
2994 hp_flags |= MV_HP_ERRATA_60X1C0;
2995 break;
2996
2997 default:
2998 dev_printk(KERN_ERR, host->dev,
2999 "BUG: invalid board index %u\n", board_idx);
3000 return 1;
3001 }
3002
3003 hpriv->hp_flags = hp_flags;
3004 if (hp_flags & MV_HP_PCIE) {
3005 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
3006 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
3007 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3008 } else {
3009 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
3010 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
3011 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3012 }
3013
3014 return 0;
3015 }
3016
3017 /**
3018 * mv_init_host - Perform some early initialization of the host.
3019 * @host: ATA host to initialize
3020 * @board_idx: controller index
3021 *
3022 * If possible, do an early global reset of the host. Then do
3023 * our port init and clear/unmask all/relevant host interrupts.
3024 *
3025 * LOCKING:
3026 * Inherited from caller.
3027 */
3028 static int mv_init_host(struct ata_host *host, unsigned int board_idx)
3029 {
3030 int rc = 0, n_hc, port, hc;
3031 struct mv_host_priv *hpriv = host->private_data;
3032 void __iomem *mmio = hpriv->base;
3033
3034 rc = mv_chip_id(host, board_idx);
3035 if (rc)
3036 goto done;
3037
3038 if (HAS_PCI(host)) {
3039 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
3040 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
3041 } else {
3042 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
3043 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
3044 }
3045
3046 /* global interrupt mask: 0 == mask everything */
3047 writel(0, hpriv->main_irq_mask_addr);
3048
3049 n_hc = mv_get_hc_count(host->ports[0]->flags);
3050
3051 for (port = 0; port < host->n_ports; port++)
3052 hpriv->ops->read_preamp(hpriv, port, mmio);
3053
3054 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
3055 if (rc)
3056 goto done;
3057
3058 hpriv->ops->reset_flash(hpriv, mmio);
3059 hpriv->ops->reset_bus(host, mmio);
3060 hpriv->ops->enable_leds(hpriv, mmio);
3061
3062 for (port = 0; port < host->n_ports; port++) {
3063 struct ata_port *ap = host->ports[port];
3064 void __iomem *port_mmio = mv_port_base(mmio, port);
3065
3066 mv_port_init(&ap->ioaddr, port_mmio);
3067
3068 #ifdef CONFIG_PCI
3069 if (HAS_PCI(host)) {
3070 unsigned int offset = port_mmio - mmio;
3071 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
3072 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
3073 }
3074 #endif
3075 }
3076
3077 for (hc = 0; hc < n_hc; hc++) {
3078 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3079
3080 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3081 "(before clear)=0x%08x\n", hc,
3082 readl(hc_mmio + HC_CFG_OFS),
3083 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
3084
3085 /* Clear any currently outstanding hc interrupt conditions */
3086 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
3087 }
3088
3089 if (HAS_PCI(host)) {
3090 /* Clear any currently outstanding host interrupt conditions */
3091 writelfl(0, mmio + hpriv->irq_cause_ofs);
3092
3093 /* and unmask interrupt generation for host regs */
3094 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
3095 if (IS_GEN_I(hpriv))
3096 writelfl(~HC_MAIN_MASKED_IRQS_5,
3097 hpriv->main_irq_mask_addr);
3098 else
3099 writelfl(~HC_MAIN_MASKED_IRQS,
3100 hpriv->main_irq_mask_addr);
3101
3102 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
3103 "PCI int cause/mask=0x%08x/0x%08x\n",
3104 readl(hpriv->main_irq_cause_addr),
3105 readl(hpriv->main_irq_mask_addr),
3106 readl(mmio + hpriv->irq_cause_ofs),
3107 readl(mmio + hpriv->irq_mask_ofs));
3108 } else {
3109 writelfl(~HC_MAIN_MASKED_IRQS_SOC,
3110 hpriv->main_irq_mask_addr);
3111 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x\n",
3112 readl(hpriv->main_irq_cause_addr),
3113 readl(hpriv->main_irq_mask_addr));
3114 }
3115 done:
3116 return rc;
3117 }
3118
3119 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3120 {
3121 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3122 MV_CRQB_Q_SZ, 0);
3123 if (!hpriv->crqb_pool)
3124 return -ENOMEM;
3125
3126 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3127 MV_CRPB_Q_SZ, 0);
3128 if (!hpriv->crpb_pool)
3129 return -ENOMEM;
3130
3131 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3132 MV_SG_TBL_SZ, 0);
3133 if (!hpriv->sg_tbl_pool)
3134 return -ENOMEM;
3135
3136 return 0;
3137 }
3138
3139 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3140 struct mbus_dram_target_info *dram)
3141 {
3142 int i;
3143
3144 for (i = 0; i < 4; i++) {
3145 writel(0, hpriv->base + WINDOW_CTRL(i));
3146 writel(0, hpriv->base + WINDOW_BASE(i));
3147 }
3148
3149 for (i = 0; i < dram->num_cs; i++) {
3150 struct mbus_dram_window *cs = dram->cs + i;
3151
3152 writel(((cs->size - 1) & 0xffff0000) |
3153 (cs->mbus_attr << 8) |
3154 (dram->mbus_dram_target_id << 4) | 1,
3155 hpriv->base + WINDOW_CTRL(i));
3156 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3157 }
3158 }
3159
3160 /**
3161 * mv_platform_probe - handle a positive probe of an soc Marvell
3162 * host
3163 * @pdev: platform device found
3164 *
3165 * LOCKING:
3166 * Inherited from caller.
3167 */
3168 static int mv_platform_probe(struct platform_device *pdev)
3169 {
3170 static int printed_version;
3171 const struct mv_sata_platform_data *mv_platform_data;
3172 const struct ata_port_info *ppi[] =
3173 { &mv_port_info[chip_soc], NULL };
3174 struct ata_host *host;
3175 struct mv_host_priv *hpriv;
3176 struct resource *res;
3177 int n_ports, rc;
3178
3179 if (!printed_version++)
3180 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
3181
3182 /*
3183 * Simple resource validation ..
3184 */
3185 if (unlikely(pdev->num_resources != 2)) {
3186 dev_err(&pdev->dev, "invalid number of resources\n");
3187 return -EINVAL;
3188 }
3189
3190 /*
3191 * Get the register base first
3192 */
3193 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3194 if (res == NULL)
3195 return -EINVAL;
3196
3197 /* allocate host */
3198 mv_platform_data = pdev->dev.platform_data;
3199 n_ports = mv_platform_data->n_ports;
3200
3201 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3202 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3203
3204 if (!host || !hpriv)
3205 return -ENOMEM;
3206 host->private_data = hpriv;
3207 hpriv->n_ports = n_ports;
3208
3209 host->iomap = NULL;
3210 hpriv->base = devm_ioremap(&pdev->dev, res->start,
3211 res->end - res->start + 1);
3212 hpriv->base -= MV_SATAHC0_REG_BASE;
3213
3214 /*
3215 * (Re-)program MBUS remapping windows if we are asked to.
3216 */
3217 if (mv_platform_data->dram != NULL)
3218 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
3219
3220 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3221 if (rc)
3222 return rc;
3223
3224 /* initialize adapter */
3225 rc = mv_init_host(host, chip_soc);
3226 if (rc)
3227 return rc;
3228
3229 dev_printk(KERN_INFO, &pdev->dev,
3230 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
3231 host->n_ports);
3232
3233 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
3234 IRQF_SHARED, &mv6_sht);
3235 }
3236
3237 /*
3238 *
3239 * mv_platform_remove - unplug a platform interface
3240 * @pdev: platform device
3241 *
3242 * A platform bus SATA device has been unplugged. Perform the needed
3243 * cleanup. Also called on module unload for any active devices.
3244 */
3245 static int __devexit mv_platform_remove(struct platform_device *pdev)
3246 {
3247 struct device *dev = &pdev->dev;
3248 struct ata_host *host = dev_get_drvdata(dev);
3249
3250 ata_host_detach(host);
3251 return 0;
3252 }
3253
3254 static struct platform_driver mv_platform_driver = {
3255 .probe = mv_platform_probe,
3256 .remove = __devexit_p(mv_platform_remove),
3257 .driver = {
3258 .name = DRV_NAME,
3259 .owner = THIS_MODULE,
3260 },
3261 };
3262
3263
3264 #ifdef CONFIG_PCI
3265 static int mv_pci_init_one(struct pci_dev *pdev,
3266 const struct pci_device_id *ent);
3267
3268
3269 static struct pci_driver mv_pci_driver = {
3270 .name = DRV_NAME,
3271 .id_table = mv_pci_tbl,
3272 .probe = mv_pci_init_one,
3273 .remove = ata_pci_remove_one,
3274 };
3275
3276 /*
3277 * module options
3278 */
3279 static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
3280
3281
3282 /* move to PCI layer or libata core? */
3283 static int pci_go_64(struct pci_dev *pdev)
3284 {
3285 int rc;
3286
3287 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3288 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3289 if (rc) {
3290 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3291 if (rc) {
3292 dev_printk(KERN_ERR, &pdev->dev,
3293 "64-bit DMA enable failed\n");
3294 return rc;
3295 }
3296 }
3297 } else {
3298 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3299 if (rc) {
3300 dev_printk(KERN_ERR, &pdev->dev,
3301 "32-bit DMA enable failed\n");
3302 return rc;
3303 }
3304 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3305 if (rc) {
3306 dev_printk(KERN_ERR, &pdev->dev,
3307 "32-bit consistent DMA enable failed\n");
3308 return rc;
3309 }
3310 }
3311
3312 return rc;
3313 }
3314
3315 /**
3316 * mv_print_info - Dump key info to kernel log for perusal.
3317 * @host: ATA host to print info about
3318 *
3319 * FIXME: complete this.
3320 *
3321 * LOCKING:
3322 * Inherited from caller.
3323 */
3324 static void mv_print_info(struct ata_host *host)
3325 {
3326 struct pci_dev *pdev = to_pci_dev(host->dev);
3327 struct mv_host_priv *hpriv = host->private_data;
3328 u8 scc;
3329 const char *scc_s, *gen;
3330
3331 /* Use this to determine the HW stepping of the chip so we know
3332 * what errata to workaround
3333 */
3334 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
3335 if (scc == 0)
3336 scc_s = "SCSI";
3337 else if (scc == 0x01)
3338 scc_s = "RAID";
3339 else
3340 scc_s = "?";
3341
3342 if (IS_GEN_I(hpriv))
3343 gen = "I";
3344 else if (IS_GEN_II(hpriv))
3345 gen = "II";
3346 else if (IS_GEN_IIE(hpriv))
3347 gen = "IIE";
3348 else
3349 gen = "?";
3350
3351 dev_printk(KERN_INFO, &pdev->dev,
3352 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
3353 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
3354 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
3355 }
3356
3357 /**
3358 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
3359 * @pdev: PCI device found
3360 * @ent: PCI device ID entry for the matched host
3361 *
3362 * LOCKING:
3363 * Inherited from caller.
3364 */
3365 static int mv_pci_init_one(struct pci_dev *pdev,
3366 const struct pci_device_id *ent)
3367 {
3368 static int printed_version;
3369 unsigned int board_idx = (unsigned int)ent->driver_data;
3370 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
3371 struct ata_host *host;
3372 struct mv_host_priv *hpriv;
3373 int n_ports, rc;
3374
3375 if (!printed_version++)
3376 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
3377
3378 /* allocate host */
3379 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
3380
3381 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3382 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3383 if (!host || !hpriv)
3384 return -ENOMEM;
3385 host->private_data = hpriv;
3386 hpriv->n_ports = n_ports;
3387
3388 /* acquire resources */
3389 rc = pcim_enable_device(pdev);
3390 if (rc)
3391 return rc;
3392
3393 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
3394 if (rc == -EBUSY)
3395 pcim_pin_device(pdev);
3396 if (rc)
3397 return rc;
3398 host->iomap = pcim_iomap_table(pdev);
3399 hpriv->base = host->iomap[MV_PRIMARY_BAR];
3400
3401 rc = pci_go_64(pdev);
3402 if (rc)
3403 return rc;
3404
3405 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3406 if (rc)
3407 return rc;
3408
3409 /* initialize adapter */
3410 rc = mv_init_host(host, board_idx);
3411 if (rc)
3412 return rc;
3413
3414 /* Enable interrupts */
3415 if (msi && pci_enable_msi(pdev))
3416 pci_intx(pdev, 1);
3417
3418 mv_dump_pci_cfg(pdev, 0x68);
3419 mv_print_info(host);
3420
3421 pci_set_master(pdev);
3422 pci_try_set_mwi(pdev);
3423 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
3424 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
3425 }
3426 #endif
3427
3428 static int mv_platform_probe(struct platform_device *pdev);
3429 static int __devexit mv_platform_remove(struct platform_device *pdev);
3430
3431 static int __init mv_init(void)
3432 {
3433 int rc = -ENODEV;
3434 #ifdef CONFIG_PCI
3435 rc = pci_register_driver(&mv_pci_driver);
3436 if (rc < 0)
3437 return rc;
3438 #endif
3439 rc = platform_driver_register(&mv_platform_driver);
3440
3441 #ifdef CONFIG_PCI
3442 if (rc < 0)
3443 pci_unregister_driver(&mv_pci_driver);
3444 #endif
3445 return rc;
3446 }
3447
3448 static void __exit mv_exit(void)
3449 {
3450 #ifdef CONFIG_PCI
3451 pci_unregister_driver(&mv_pci_driver);
3452 #endif
3453 platform_driver_unregister(&mv_platform_driver);
3454 }
3455
3456 MODULE_AUTHOR("Brett Russ");
3457 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
3458 MODULE_LICENSE("GPL");
3459 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
3460 MODULE_VERSION(DRV_VERSION);
3461 MODULE_ALIAS("platform:" DRV_NAME);
3462
3463 #ifdef CONFIG_PCI
3464 module_param(msi, int, 0444);
3465 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
3466 #endif
3467
3468 module_init(mv_init);
3469 module_exit(mv_exit);
Support for the Chinese Samsung S3C2440 based development boards