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V4L/DVB (11992): Add missing __devexit_p()
[linux-2.6/mini2440.git] / drivers / media / video / pxa_camera.c
blobf60de40fd21f79d17274dc0fe3769a84639d9f6a
1 /*
2 * V4L2 Driver for PXA camera host
3 *
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/io.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/errno.h>
19 #include <linux/fs.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/mm.h>
23 #include <linux/moduleparam.h>
24 #include <linux/time.h>
25 #include <linux/version.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
29
30 #include <media/v4l2-common.h>
31 #include <media/v4l2-dev.h>
32 #include <media/videobuf-dma-sg.h>
33 #include <media/soc_camera.h>
34
35 #include <linux/videodev2.h>
36
37 #include <mach/dma.h>
38 #include <mach/camera.h>
39
40 #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
41 #define PXA_CAM_DRV_NAME "pxa27x-camera"
42
43 /* Camera Interface */
44 #define CICR0 0x0000
45 #define CICR1 0x0004
46 #define CICR2 0x0008
47 #define CICR3 0x000C
48 #define CICR4 0x0010
49 #define CISR 0x0014
50 #define CIFR 0x0018
51 #define CITOR 0x001C
52 #define CIBR0 0x0028
53 #define CIBR1 0x0030
54 #define CIBR2 0x0038
55
56 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
57 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
58 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
59 #define CICR0_ENB (1 << 28) /* Camera interface enable */
60 #define CICR0_DIS (1 << 27) /* Camera interface disable */
61 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
62 #define CICR0_TOM (1 << 9) /* Time-out mask */
63 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
64 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
65 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
66 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
67 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
68 #define CICR0_CDM (1 << 3) /* Disable-done mask */
69 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
70 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
71 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
72
73 #define CICR1_TBIT (1 << 31) /* Transparency bit */
74 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
75 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
76 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
77 #define CICR1_RGB_F (1 << 11) /* RGB format */
78 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
79 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
80 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
81 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
82 #define CICR1_DW (0x7 << 0) /* Data width mask */
83
84 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
85 wait count mask */
86 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
87 wait count mask */
88 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
89 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
90 wait count mask */
91 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
92 wait count mask */
93
94 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
95 wait count mask */
96 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
97 wait count mask */
98 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
99 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
100 wait count mask */
101 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
102
103 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
104 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
105 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
106 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
107 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
108 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
109 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
110 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
111
112 #define CISR_FTO (1 << 15) /* FIFO time-out */
113 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
114 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
115 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
116 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
117 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
118 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
119 #define CISR_EOL (1 << 8) /* End of line */
120 #define CISR_PAR_ERR (1 << 7) /* Parity error */
121 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
122 #define CISR_CDD (1 << 5) /* Camera interface disable done */
123 #define CISR_SOF (1 << 4) /* Start of frame */
124 #define CISR_EOF (1 << 3) /* End of frame */
125 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
126 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
127 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
128
129 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
130 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
131 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
132 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
133 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
134 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
135 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
136 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
137
138 #define CICR0_SIM_MP (0 << 24)
139 #define CICR0_SIM_SP (1 << 24)
140 #define CICR0_SIM_MS (2 << 24)
141 #define CICR0_SIM_EP (3 << 24)
142 #define CICR0_SIM_ES (4 << 24)
143
144 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
145 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
146 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
147 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
148 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
149
150 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
151 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
152 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
153 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
154 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
155
156 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
157 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
158 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
159 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
160
161 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
162 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
163 CICR0_EOFM | CICR0_FOM)
164
165 /*
166 * YUV422P picture size should be a multiple of 16, so the heuristic aligns
167 * height, width on 4 byte boundaries to reach the 16 multiple for the size.
168 */
169 #define YUV422P_X_Y_ALIGN 4
170 #define YUV422P_SIZE_ALIGN YUV422P_X_Y_ALIGN * YUV422P_X_Y_ALIGN
171
172 /*
173 * Structures
174 */
175 enum pxa_camera_active_dma {
176 DMA_Y = 0x1,
177 DMA_U = 0x2,
178 DMA_V = 0x4,
179 };
180
181 /* descriptor needed for the PXA DMA engine */
182 struct pxa_cam_dma {
183 dma_addr_t sg_dma;
184 struct pxa_dma_desc *sg_cpu;
185 size_t sg_size;
186 int sglen;
187 };
188
189 /* buffer for one video frame */
190 struct pxa_buffer {
191 /* common v4l buffer stuff -- must be first */
192 struct videobuf_buffer vb;
193
194 const struct soc_camera_data_format *fmt;
195
196 /* our descriptor lists for Y, U and V channels */
197 struct pxa_cam_dma dmas[3];
198
199 int inwork;
200
201 enum pxa_camera_active_dma active_dma;
202 };
203
204 struct pxa_camera_dev {
205 struct soc_camera_host soc_host;
206 /* PXA27x is only supposed to handle one camera on its Quick Capture
207 * interface. If anyone ever builds hardware to enable more than
208 * one camera, they will have to modify this driver too */
209 struct soc_camera_device *icd;
210 struct clk *clk;
211
212 unsigned int irq;
213 void __iomem *base;
214
215 int channels;
216 unsigned int dma_chans[3];
217
218 struct pxacamera_platform_data *pdata;
219 struct resource *res;
220 unsigned long platform_flags;
221 unsigned long ciclk;
222 unsigned long mclk;
223 u32 mclk_divisor;
224
225 struct list_head capture;
226
227 spinlock_t lock;
228
229 struct pxa_buffer *active;
230 struct pxa_dma_desc *sg_tail[3];
231
232 u32 save_cicr[5];
233 };
234
235 static const char *pxa_cam_driver_description = "PXA_Camera";
236
237 static unsigned int vid_limit = 16; /* Video memory limit, in Mb */
238
239 /*
240 * Videobuf operations
241 */
242 static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
243 unsigned int *size)
244 {
245 struct soc_camera_device *icd = vq->priv_data;
246
247 dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size);
248
249 *size = roundup(icd->width * icd->height *
250 ((icd->current_fmt->depth + 7) >> 3), 8);
251
252 if (0 == *count)
253 *count = 32;
254 while (*size * *count > vid_limit * 1024 * 1024)
255 (*count)--;
256
257 return 0;
258 }
259
260 static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf)
261 {
262 struct soc_camera_device *icd = vq->priv_data;
263 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
264 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
265 int i;
266
267 BUG_ON(in_interrupt());
268
269 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
270 &buf->vb, buf->vb.baddr, buf->vb.bsize);
271
272 /* This waits until this buffer is out of danger, i.e., until it is no
273 * longer in STATE_QUEUED or STATE_ACTIVE */
274 videobuf_waiton(&buf->vb, 0, 0);
275 videobuf_dma_unmap(vq, dma);
276 videobuf_dma_free(dma);
277
278 for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) {
279 if (buf->dmas[i].sg_cpu)
280 dma_free_coherent(ici->dev, buf->dmas[i].sg_size,
281 buf->dmas[i].sg_cpu,
282 buf->dmas[i].sg_dma);
283 buf->dmas[i].sg_cpu = NULL;
284 }
285
286 buf->vb.state = VIDEOBUF_NEEDS_INIT;
287 }
288
289 static int calculate_dma_sglen(struct scatterlist *sglist, int sglen,
290 int sg_first_ofs, int size)
291 {
292 int i, offset, dma_len, xfer_len;
293 struct scatterlist *sg;
294
295 offset = sg_first_ofs;
296 for_each_sg(sglist, sg, sglen, i) {
297 dma_len = sg_dma_len(sg);
298
299 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
300 xfer_len = roundup(min(dma_len - offset, size), 8);
301
302 size = max(0, size - xfer_len);
303 offset = 0;
304 if (size == 0)
305 break;
306 }
307
308 BUG_ON(size != 0);
309 return i + 1;
310 }
311
312 /**
313 * pxa_init_dma_channel - init dma descriptors
314 * @pcdev: pxa camera device
315 * @buf: pxa buffer to find pxa dma channel
316 * @dma: dma video buffer
317 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
318 * @cibr: camera Receive Buffer Register
319 * @size: bytes to transfer
320 * @sg_first: first element of sg_list
321 * @sg_first_ofs: offset in first element of sg_list
322 *
323 * Prepares the pxa dma descriptors to transfer one camera channel.
324 * Beware sg_first and sg_first_ofs are both input and output parameters.
325 *
326 * Returns 0 or -ENOMEM if no coherent memory is available
327 */
328 static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
329 struct pxa_buffer *buf,
330 struct videobuf_dmabuf *dma, int channel,
331 int cibr, int size,
332 struct scatterlist **sg_first, int *sg_first_ofs)
333 {
334 struct pxa_cam_dma *pxa_dma = &buf->dmas[channel];
335 struct scatterlist *sg;
336 int i, offset, sglen;
337 int dma_len = 0, xfer_len = 0;
338
339 if (pxa_dma->sg_cpu)
340 dma_free_coherent(pcdev->soc_host.dev, pxa_dma->sg_size,
341 pxa_dma->sg_cpu, pxa_dma->sg_dma);
342
343 sglen = calculate_dma_sglen(*sg_first, dma->sglen,
344 *sg_first_ofs, size);
345
346 pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc);
347 pxa_dma->sg_cpu = dma_alloc_coherent(pcdev->soc_host.dev, pxa_dma->sg_size,
348 &pxa_dma->sg_dma, GFP_KERNEL);
349 if (!pxa_dma->sg_cpu)
350 return -ENOMEM;
351
352 pxa_dma->sglen = sglen;
353 offset = *sg_first_ofs;
354
355 dev_dbg(pcdev->soc_host.dev, "DMA: sg_first=%p, sglen=%d, ofs=%d, dma.desc=%x\n",
356 *sg_first, sglen, *sg_first_ofs, pxa_dma->sg_dma);
357
358
359 for_each_sg(*sg_first, sg, sglen, i) {
360 dma_len = sg_dma_len(sg);
361
362 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
363 xfer_len = roundup(min(dma_len - offset, size), 8);
364
365 size = max(0, size - xfer_len);
366
367 pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr;
368 pxa_dma->sg_cpu[i].dtadr = sg_dma_address(sg) + offset;
369 pxa_dma->sg_cpu[i].dcmd =
370 DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len;
371 #ifdef DEBUG
372 if (!i)
373 pxa_dma->sg_cpu[i].dcmd |= DCMD_STARTIRQEN;
374 #endif
375 pxa_dma->sg_cpu[i].ddadr =
376 pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc);
377
378 dev_vdbg(pcdev->soc_host.dev, "DMA: desc.%08x->@phys=0x%08x, len=%d\n",
379 pxa_dma->sg_dma + i * sizeof(struct pxa_dma_desc),
380 sg_dma_address(sg) + offset, xfer_len);
381 offset = 0;
382
383 if (size == 0)
384 break;
385 }
386
387 pxa_dma->sg_cpu[sglen].ddadr = DDADR_STOP;
388 pxa_dma->sg_cpu[sglen].dcmd = DCMD_FLOWSRC | DCMD_BURST8 | DCMD_ENDIRQEN;
389
390 /*
391 * Handle 1 special case :
392 * - in 3 planes (YUV422P format), we might finish with xfer_len equal
393 * to dma_len (end on PAGE boundary). In this case, the sg element
394 * for next plane should be the next after the last used to store the
395 * last scatter gather RAM page
396 */
397 if (xfer_len >= dma_len) {
398 *sg_first_ofs = xfer_len - dma_len;
399 *sg_first = sg_next(sg);
400 } else {
401 *sg_first_ofs = xfer_len;
402 *sg_first = sg;
403 }
404
405 return 0;
406 }
407
408 static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev,
409 struct pxa_buffer *buf)
410 {
411 buf->active_dma = DMA_Y;
412 if (pcdev->channels == 3)
413 buf->active_dma |= DMA_U | DMA_V;
414 }
415
416 /*
417 * Please check the DMA prepared buffer structure in :
418 * Documentation/video4linux/pxa_camera.txt
419 * Please check also in pxa_camera_check_link_miss() to understand why DMA chain
420 * modification while DMA chain is running will work anyway.
421 */
422 static int pxa_videobuf_prepare(struct videobuf_queue *vq,
423 struct videobuf_buffer *vb, enum v4l2_field field)
424 {
425 struct soc_camera_device *icd = vq->priv_data;
426 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
427 struct pxa_camera_dev *pcdev = ici->priv;
428 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
429 int ret;
430 int size_y, size_u = 0, size_v = 0;
431
432 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
433 vb, vb->baddr, vb->bsize);
434
435 /* Added list head initialization on alloc */
436 WARN_ON(!list_empty(&vb->queue));
437
438 #ifdef DEBUG
439 /* This can be useful if you want to see if we actually fill
440 * the buffer with something */
441 memset((void *)vb->baddr, 0xaa, vb->bsize);
442 #endif
443
444 BUG_ON(NULL == icd->current_fmt);
445
446 /* I think, in buf_prepare you only have to protect global data,
447 * the actual buffer is yours */
448 buf->inwork = 1;
449
450 if (buf->fmt != icd->current_fmt ||
451 vb->width != icd->width ||
452 vb->height != icd->height ||
453 vb->field != field) {
454 buf->fmt = icd->current_fmt;
455 vb->width = icd->width;
456 vb->height = icd->height;
457 vb->field = field;
458 vb->state = VIDEOBUF_NEEDS_INIT;
459 }
460
461 vb->size = vb->width * vb->height * ((buf->fmt->depth + 7) >> 3);
462 if (0 != vb->baddr && vb->bsize < vb->size) {
463 ret = -EINVAL;
464 goto out;
465 }
466
467 if (vb->state == VIDEOBUF_NEEDS_INIT) {
468 int size = vb->size;
469 int next_ofs = 0;
470 struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
471 struct scatterlist *sg;
472
473 ret = videobuf_iolock(vq, vb, NULL);
474 if (ret)
475 goto fail;
476
477 if (pcdev->channels == 3) {
478 size_y = size / 2;
479 size_u = size_v = size / 4;
480 } else {
481 size_y = size;
482 }
483
484 sg = dma->sglist;
485
486 /* init DMA for Y channel */
487 ret = pxa_init_dma_channel(pcdev, buf, dma, 0, CIBR0, size_y,
488 &sg, &next_ofs);
489 if (ret) {
490 dev_err(pcdev->soc_host.dev,
491 "DMA initialization for Y/RGB failed\n");
492 goto fail;
493 }
494
495 /* init DMA for U channel */
496 if (size_u)
497 ret = pxa_init_dma_channel(pcdev, buf, dma, 1, CIBR1,
498 size_u, &sg, &next_ofs);
499 if (ret) {
500 dev_err(pcdev->soc_host.dev,
501 "DMA initialization for U failed\n");
502 goto fail_u;
503 }
504
505 /* init DMA for V channel */
506 if (size_v)
507 ret = pxa_init_dma_channel(pcdev, buf, dma, 2, CIBR2,
508 size_v, &sg, &next_ofs);
509 if (ret) {
510 dev_err(pcdev->soc_host.dev,
511 "DMA initialization for V failed\n");
512 goto fail_v;
513 }
514
515 vb->state = VIDEOBUF_PREPARED;
516 }
517
518 buf->inwork = 0;
519 pxa_videobuf_set_actdma(pcdev, buf);
520
521 return 0;
522
523 fail_v:
524 dma_free_coherent(pcdev->soc_host.dev, buf->dmas[1].sg_size,
525 buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma);
526 fail_u:
527 dma_free_coherent(pcdev->soc_host.dev, buf->dmas[0].sg_size,
528 buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma);
529 fail:
530 free_buffer(vq, buf);
531 out:
532 buf->inwork = 0;
533 return ret;
534 }
535
536 /**
537 * pxa_dma_start_channels - start DMA channel for active buffer
538 * @pcdev: pxa camera device
539 *
540 * Initialize DMA channels to the beginning of the active video buffer, and
541 * start these channels.
542 */
543 static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
544 {
545 int i;
546 struct pxa_buffer *active;
547
548 active = pcdev->active;
549
550 for (i = 0; i < pcdev->channels; i++) {
551 dev_dbg(pcdev->soc_host.dev, "%s (channel=%d) ddadr=%08x\n", __func__,
552 i, active->dmas[i].sg_dma);
553 DDADR(pcdev->dma_chans[i]) = active->dmas[i].sg_dma;
554 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
555 }
556 }
557
558 static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
559 {
560 int i;
561
562 for (i = 0; i < pcdev->channels; i++) {
563 dev_dbg(pcdev->soc_host.dev, "%s (channel=%d)\n", __func__, i);
564 DCSR(pcdev->dma_chans[i]) = 0;
565 }
566 }
567
568 static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
569 struct pxa_buffer *buf)
570 {
571 int i;
572 struct pxa_dma_desc *buf_last_desc;
573
574 for (i = 0; i < pcdev->channels; i++) {
575 buf_last_desc = buf->dmas[i].sg_cpu + buf->dmas[i].sglen;
576 buf_last_desc->ddadr = DDADR_STOP;
577
578 if (pcdev->sg_tail[i])
579 /* Link the new buffer to the old tail */
580 pcdev->sg_tail[i]->ddadr = buf->dmas[i].sg_dma;
581
582 /* Update the channel tail */
583 pcdev->sg_tail[i] = buf_last_desc;
584 }
585 }
586
587 /**
588 * pxa_camera_start_capture - start video capturing
589 * @pcdev: camera device
590 *
591 * Launch capturing. DMA channels should not be active yet. They should get
592 * activated at the end of frame interrupt, to capture only whole frames, and
593 * never begin the capture of a partial frame.
594 */
595 static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
596 {
597 unsigned long cicr0, cifr;
598
599 dev_dbg(pcdev->soc_host.dev, "%s\n", __func__);
600 /* Reset the FIFOs */
601 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
602 __raw_writel(cifr, pcdev->base + CIFR);
603 /* Enable End-Of-Frame Interrupt */
604 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
605 cicr0 &= ~CICR0_EOFM;
606 __raw_writel(cicr0, pcdev->base + CICR0);
607 }
608
609 static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
610 {
611 unsigned long cicr0;
612
613 pxa_dma_stop_channels(pcdev);
614
615 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
616 __raw_writel(cicr0, pcdev->base + CICR0);
617
618 pcdev->active = NULL;
619 dev_dbg(pcdev->soc_host.dev, "%s\n", __func__);
620 }
621
622 static void pxa_videobuf_queue(struct videobuf_queue *vq,
623 struct videobuf_buffer *vb)
624 {
625 struct soc_camera_device *icd = vq->priv_data;
626 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
627 struct pxa_camera_dev *pcdev = ici->priv;
628 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
629 unsigned long flags;
630
631 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d active=%p\n", __func__,
632 vb, vb->baddr, vb->bsize, pcdev->active);
633
634 spin_lock_irqsave(&pcdev->lock, flags);
635
636 list_add_tail(&vb->queue, &pcdev->capture);
637
638 vb->state = VIDEOBUF_ACTIVE;
639 pxa_dma_add_tail_buf(pcdev, buf);
640
641 if (!pcdev->active)
642 pxa_camera_start_capture(pcdev);
643
644 spin_unlock_irqrestore(&pcdev->lock, flags);
645 }
646
647 static void pxa_videobuf_release(struct videobuf_queue *vq,
648 struct videobuf_buffer *vb)
649 {
650 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
651 #ifdef DEBUG
652 struct soc_camera_device *icd = vq->priv_data;
653
654 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
655 vb, vb->baddr, vb->bsize);
656
657 switch (vb->state) {
658 case VIDEOBUF_ACTIVE:
659 dev_dbg(&icd->dev, "%s (active)\n", __func__);
660 break;
661 case VIDEOBUF_QUEUED:
662 dev_dbg(&icd->dev, "%s (queued)\n", __func__);
663 break;
664 case VIDEOBUF_PREPARED:
665 dev_dbg(&icd->dev, "%s (prepared)\n", __func__);
666 break;
667 default:
668 dev_dbg(&icd->dev, "%s (unknown)\n", __func__);
669 break;
670 }
671 #endif
672
673 free_buffer(vq, buf);
674 }
675
676 static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
677 struct videobuf_buffer *vb,
678 struct pxa_buffer *buf)
679 {
680 int i;
681
682 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
683 list_del_init(&vb->queue);
684 vb->state = VIDEOBUF_DONE;
685 do_gettimeofday(&vb->ts);
686 vb->field_count++;
687 wake_up(&vb->done);
688 dev_dbg(pcdev->soc_host.dev, "%s dequeud buffer (vb=0x%p)\n", __func__, vb);
689
690 if (list_empty(&pcdev->capture)) {
691 pxa_camera_stop_capture(pcdev);
692 for (i = 0; i < pcdev->channels; i++)
693 pcdev->sg_tail[i] = NULL;
694 return;
695 }
696
697 pcdev->active = list_entry(pcdev->capture.next,
698 struct pxa_buffer, vb.queue);
699 }
700
701 /**
702 * pxa_camera_check_link_miss - check missed DMA linking
703 * @pcdev: camera device
704 *
705 * The DMA chaining is done with DMA running. This means a tiny temporal window
706 * remains, where a buffer is queued on the chain, while the chain is already
707 * stopped. This means the tailed buffer would never be transfered by DMA.
708 * This function restarts the capture for this corner case, where :
709 * - DADR() == DADDR_STOP
710 * - a videobuffer is queued on the pcdev->capture list
711 *
712 * Please check the "DMA hot chaining timeslice issue" in
713 * Documentation/video4linux/pxa_camera.txt
714 *
715 * Context: should only be called within the dma irq handler
716 */
717 static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev)
718 {
719 int i, is_dma_stopped = 1;
720
721 for (i = 0; i < pcdev->channels; i++)
722 if (DDADR(pcdev->dma_chans[i]) != DDADR_STOP)
723 is_dma_stopped = 0;
724 dev_dbg(pcdev->soc_host.dev, "%s : top queued buffer=%p, dma_stopped=%d\n",
725 __func__, pcdev->active, is_dma_stopped);
726 if (pcdev->active && is_dma_stopped)
727 pxa_camera_start_capture(pcdev);
728 }
729
730 static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev,
731 enum pxa_camera_active_dma act_dma)
732 {
733 struct pxa_buffer *buf;
734 unsigned long flags;
735 u32 status, camera_status, overrun;
736 struct videobuf_buffer *vb;
737
738 spin_lock_irqsave(&pcdev->lock, flags);
739
740 status = DCSR(channel);
741 DCSR(channel) = status;
742
743 camera_status = __raw_readl(pcdev->base + CISR);
744 overrun = CISR_IFO_0;
745 if (pcdev->channels == 3)
746 overrun |= CISR_IFO_1 | CISR_IFO_2;
747
748 if (status & DCSR_BUSERR) {
749 dev_err(pcdev->soc_host.dev, "DMA Bus Error IRQ!\n");
750 goto out;
751 }
752
753 if (!(status & (DCSR_ENDINTR | DCSR_STARTINTR))) {
754 dev_err(pcdev->soc_host.dev, "Unknown DMA IRQ source, "
755 "status: 0x%08x\n", status);
756 goto out;
757 }
758
759 /*
760 * pcdev->active should not be NULL in DMA irq handler.
761 *
762 * But there is one corner case : if capture was stopped due to an
763 * overrun of channel 1, and at that same channel 2 was completed.
764 *
765 * When handling the overrun in DMA irq for channel 1, we'll stop the
766 * capture and restart it (and thus set pcdev->active to NULL). But the
767 * DMA irq handler will already be pending for channel 2. So on entering
768 * the DMA irq handler for channel 2 there will be no active buffer, yet
769 * that is normal.
770 */
771 if (!pcdev->active)
772 goto out;
773
774 vb = &pcdev->active->vb;
775 buf = container_of(vb, struct pxa_buffer, vb);
776 WARN_ON(buf->inwork || list_empty(&vb->queue));
777
778 dev_dbg(pcdev->soc_host.dev, "%s channel=%d %s%s(vb=0x%p) dma.desc=%x\n",
779 __func__, channel, status & DCSR_STARTINTR ? "SOF " : "",
780 status & DCSR_ENDINTR ? "EOF " : "", vb, DDADR(channel));
781
782 if (status & DCSR_ENDINTR) {
783 /*
784 * It's normal if the last frame creates an overrun, as there
785 * are no more DMA descriptors to fetch from QCI fifos
786 */
787 if (camera_status & overrun &&
788 !list_is_last(pcdev->capture.next, &pcdev->capture)) {
789 dev_dbg(pcdev->soc_host.dev, "FIFO overrun! CISR: %x\n",
790 camera_status);
791 pxa_camera_stop_capture(pcdev);
792 pxa_camera_start_capture(pcdev);
793 goto out;
794 }
795 buf->active_dma &= ~act_dma;
796 if (!buf->active_dma) {
797 pxa_camera_wakeup(pcdev, vb, buf);
798 pxa_camera_check_link_miss(pcdev);
799 }
800 }
801
802 out:
803 spin_unlock_irqrestore(&pcdev->lock, flags);
804 }
805
806 static void pxa_camera_dma_irq_y(int channel, void *data)
807 {
808 struct pxa_camera_dev *pcdev = data;
809 pxa_camera_dma_irq(channel, pcdev, DMA_Y);
810 }
811
812 static void pxa_camera_dma_irq_u(int channel, void *data)
813 {
814 struct pxa_camera_dev *pcdev = data;
815 pxa_camera_dma_irq(channel, pcdev, DMA_U);
816 }
817
818 static void pxa_camera_dma_irq_v(int channel, void *data)
819 {
820 struct pxa_camera_dev *pcdev = data;
821 pxa_camera_dma_irq(channel, pcdev, DMA_V);
822 }
823
824 static struct videobuf_queue_ops pxa_videobuf_ops = {
825 .buf_setup = pxa_videobuf_setup,
826 .buf_prepare = pxa_videobuf_prepare,
827 .buf_queue = pxa_videobuf_queue,
828 .buf_release = pxa_videobuf_release,
829 };
830
831 static void pxa_camera_init_videobuf(struct videobuf_queue *q,
832 struct soc_camera_device *icd)
833 {
834 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
835 struct pxa_camera_dev *pcdev = ici->priv;
836
837 /* We must pass NULL as dev pointer, then all pci_* dma operations
838 * transform to normal dma_* ones. */
839 videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock,
840 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE,
841 sizeof(struct pxa_buffer), icd);
842 }
843
844 static u32 mclk_get_divisor(struct pxa_camera_dev *pcdev)
845 {
846 unsigned long mclk = pcdev->mclk;
847 u32 div;
848 unsigned long lcdclk;
849
850 lcdclk = clk_get_rate(pcdev->clk);
851 pcdev->ciclk = lcdclk;
852
853 /* mclk <= ciclk / 4 (27.4.2) */
854 if (mclk > lcdclk / 4) {
855 mclk = lcdclk / 4;
856 dev_warn(pcdev->soc_host.dev, "Limiting master clock to %lu\n", mclk);
857 }
858
859 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
860 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
861
862 /* If we're not supplying MCLK, leave it at 0 */
863 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
864 pcdev->mclk = lcdclk / (2 * (div + 1));
865
866 dev_dbg(pcdev->soc_host.dev, "LCD clock %luHz, target freq %luHz, "
867 "divisor %u\n", lcdclk, mclk, div);
868
869 return div;
870 }
871
872 static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
873 unsigned long pclk)
874 {
875 /* We want a timeout > 1 pixel time, not ">=" */
876 u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
877
878 __raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
879 }
880
881 static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
882 {
883 struct pxacamera_platform_data *pdata = pcdev->pdata;
884 u32 cicr4 = 0;
885
886 dev_dbg(pcdev->soc_host.dev, "Registered platform device at %p data %p\n",
887 pcdev, pdata);
888
889 if (pdata && pdata->init) {
890 dev_dbg(pcdev->soc_host.dev, "%s: Init gpios\n", __func__);
891 pdata->init(pcdev->soc_host.dev);
892 }
893
894 /* disable all interrupts */
895 __raw_writel(0x3ff, pcdev->base + CICR0);
896
897 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
898 cicr4 |= CICR4_PCLK_EN;
899 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
900 cicr4 |= CICR4_MCLK_EN;
901 if (pcdev->platform_flags & PXA_CAMERA_PCP)
902 cicr4 |= CICR4_PCP;
903 if (pcdev->platform_flags & PXA_CAMERA_HSP)
904 cicr4 |= CICR4_HSP;
905 if (pcdev->platform_flags & PXA_CAMERA_VSP)
906 cicr4 |= CICR4_VSP;
907
908 __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
909
910 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
911 /* Initialise the timeout under the assumption pclk = mclk */
912 recalculate_fifo_timeout(pcdev, pcdev->mclk);
913 else
914 /* "Safe default" - 13MHz */
915 recalculate_fifo_timeout(pcdev, 13000000);
916
917 clk_enable(pcdev->clk);
918 }
919
920 static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
921 {
922 clk_disable(pcdev->clk);
923 }
924
925 static irqreturn_t pxa_camera_irq(int irq, void *data)
926 {
927 struct pxa_camera_dev *pcdev = data;
928 unsigned long status, cicr0;
929 struct pxa_buffer *buf;
930 struct videobuf_buffer *vb;
931
932 status = __raw_readl(pcdev->base + CISR);
933 dev_dbg(pcdev->soc_host.dev, "Camera interrupt status 0x%lx\n", status);
934
935 if (!status)
936 return IRQ_NONE;
937
938 __raw_writel(status, pcdev->base + CISR);
939
940 if (status & CISR_EOF) {
941 pcdev->active = list_first_entry(&pcdev->capture,
942 struct pxa_buffer, vb.queue);
943 vb = &pcdev->active->vb;
944 buf = container_of(vb, struct pxa_buffer, vb);
945 pxa_videobuf_set_actdma(pcdev, buf);
946
947 pxa_dma_start_channels(pcdev);
948
949 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
950 __raw_writel(cicr0, pcdev->base + CICR0);
951 }
952
953 return IRQ_HANDLED;
954 }
955
956 /*
957 * The following two functions absolutely depend on the fact, that
958 * there can be only one camera on PXA quick capture interface
959 * Called with .video_lock held
960 */
961 static int pxa_camera_add_device(struct soc_camera_device *icd)
962 {
963 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
964 struct pxa_camera_dev *pcdev = ici->priv;
965 int ret;
966
967 if (pcdev->icd) {
968 ret = -EBUSY;
969 goto ebusy;
970 }
971
972 dev_info(&icd->dev, "PXA Camera driver attached to camera %d\n",
973 icd->devnum);
974
975 pxa_camera_activate(pcdev);
976 ret = icd->ops->init(icd);
977
978 if (!ret)
979 pcdev->icd = icd;
980
981 ebusy:
982 return ret;
983 }
984
985 /* Called with .video_lock held */
986 static void pxa_camera_remove_device(struct soc_camera_device *icd)
987 {
988 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
989 struct pxa_camera_dev *pcdev = ici->priv;
990
991 BUG_ON(icd != pcdev->icd);
992
993 dev_info(&icd->dev, "PXA Camera driver detached from camera %d\n",
994 icd->devnum);
995
996 /* disable capture, disable interrupts */
997 __raw_writel(0x3ff, pcdev->base + CICR0);
998
999 /* Stop DMA engine */
1000 DCSR(pcdev->dma_chans[0]) = 0;
1001 DCSR(pcdev->dma_chans[1]) = 0;
1002 DCSR(pcdev->dma_chans[2]) = 0;
1003
1004 icd->ops->release(icd);
1005
1006 pxa_camera_deactivate(pcdev);
1007
1008 pcdev->icd = NULL;
1009 }
1010
1011 static int test_platform_param(struct pxa_camera_dev *pcdev,
1012 unsigned char buswidth, unsigned long *flags)
1013 {
1014 /*
1015 * Platform specified synchronization and pixel clock polarities are
1016 * only a recommendation and are only used during probing. The PXA270
1017 * quick capture interface supports both.
1018 */
1019 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1020 SOCAM_MASTER : SOCAM_SLAVE) |
1021 SOCAM_HSYNC_ACTIVE_HIGH |
1022 SOCAM_HSYNC_ACTIVE_LOW |
1023 SOCAM_VSYNC_ACTIVE_HIGH |
1024 SOCAM_VSYNC_ACTIVE_LOW |
1025 SOCAM_DATA_ACTIVE_HIGH |
1026 SOCAM_PCLK_SAMPLE_RISING |
1027 SOCAM_PCLK_SAMPLE_FALLING;
1028
1029 /* If requested data width is supported by the platform, use it */
1030 switch (buswidth) {
1031 case 10:
1032 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10))
1033 return -EINVAL;
1034 *flags |= SOCAM_DATAWIDTH_10;
1035 break;
1036 case 9:
1037 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9))
1038 return -EINVAL;
1039 *flags |= SOCAM_DATAWIDTH_9;
1040 break;
1041 case 8:
1042 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8))
1043 return -EINVAL;
1044 *flags |= SOCAM_DATAWIDTH_8;
1045 break;
1046 default:
1047 return -EINVAL;
1048 }
1049
1050 return 0;
1051 }
1052
1053 static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
1054 {
1055 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1056 struct pxa_camera_dev *pcdev = ici->priv;
1057 unsigned long dw, bpp, bus_flags, camera_flags, common_flags;
1058 u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0;
1059 int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags);
1060
1061 if (ret < 0)
1062 return ret;
1063
1064 camera_flags = icd->ops->query_bus_param(icd);
1065
1066 common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags);
1067 if (!common_flags)
1068 return -EINVAL;
1069
1070 pcdev->channels = 1;
1071
1072 /* Make choises, based on platform preferences */
1073 if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) &&
1074 (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) {
1075 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1076 common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH;
1077 else
1078 common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW;
1079 }
1080
1081 if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) &&
1082 (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) {
1083 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1084 common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH;
1085 else
1086 common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW;
1087 }
1088
1089 if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
1090 (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
1091 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1092 common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
1093 else
1094 common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
1095 }
1096
1097 ret = icd->ops->set_bus_param(icd, common_flags);
1098 if (ret < 0)
1099 return ret;
1100
1101 /* Datawidth is now guaranteed to be equal to one of the three values.
1102 * We fix bit-per-pixel equal to data-width... */
1103 switch (common_flags & SOCAM_DATAWIDTH_MASK) {
1104 case SOCAM_DATAWIDTH_10:
1105 dw = 4;
1106 bpp = 0x40;
1107 break;
1108 case SOCAM_DATAWIDTH_9:
1109 dw = 3;
1110 bpp = 0x20;
1111 break;
1112 default:
1113 /* Actually it can only be 8 now,
1114 * default is just to silence compiler warnings */
1115 case SOCAM_DATAWIDTH_8:
1116 dw = 2;
1117 bpp = 0;
1118 }
1119
1120 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1121 cicr4 |= CICR4_PCLK_EN;
1122 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1123 cicr4 |= CICR4_MCLK_EN;
1124 if (common_flags & SOCAM_PCLK_SAMPLE_FALLING)
1125 cicr4 |= CICR4_PCP;
1126 if (common_flags & SOCAM_HSYNC_ACTIVE_LOW)
1127 cicr4 |= CICR4_HSP;
1128 if (common_flags & SOCAM_VSYNC_ACTIVE_LOW)
1129 cicr4 |= CICR4_VSP;
1130
1131 cicr0 = __raw_readl(pcdev->base + CICR0);
1132 if (cicr0 & CICR0_ENB)
1133 __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
1134
1135 cicr1 = CICR1_PPL_VAL(icd->width - 1) | bpp | dw;
1136
1137 switch (pixfmt) {
1138 case V4L2_PIX_FMT_YUV422P:
1139 pcdev->channels = 3;
1140 cicr1 |= CICR1_YCBCR_F;
1141 /*
1142 * Normally, pxa bus wants as input UYVY format. We allow all
1143 * reorderings of the YUV422 format, as no processing is done,
1144 * and the YUV stream is just passed through without any
1145 * transformation. Note that UYVY is the only format that
1146 * should be used if pxa framebuffer Overlay2 is used.
1147 */
1148 case V4L2_PIX_FMT_UYVY:
1149 case V4L2_PIX_FMT_VYUY:
1150 case V4L2_PIX_FMT_YUYV:
1151 case V4L2_PIX_FMT_YVYU:
1152 cicr1 |= CICR1_COLOR_SP_VAL(2);
1153 break;
1154 case V4L2_PIX_FMT_RGB555:
1155 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1156 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
1157 break;
1158 case V4L2_PIX_FMT_RGB565:
1159 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1160 break;
1161 }
1162
1163 cicr2 = 0;
1164 cicr3 = CICR3_LPF_VAL(icd->height - 1) |
1165 CICR3_BFW_VAL(min((unsigned short)255, icd->y_skip_top));
1166 cicr4 |= pcdev->mclk_divisor;
1167
1168 __raw_writel(cicr1, pcdev->base + CICR1);
1169 __raw_writel(cicr2, pcdev->base + CICR2);
1170 __raw_writel(cicr3, pcdev->base + CICR3);
1171 __raw_writel(cicr4, pcdev->base + CICR4);
1172
1173 /* CIF interrupts are not used, only DMA */
1174 cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1175 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
1176 cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1177 __raw_writel(cicr0, pcdev->base + CICR0);
1178
1179 return 0;
1180 }
1181
1182 static int pxa_camera_try_bus_param(struct soc_camera_device *icd,
1183 unsigned char buswidth)
1184 {
1185 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1186 struct pxa_camera_dev *pcdev = ici->priv;
1187 unsigned long bus_flags, camera_flags;
1188 int ret = test_platform_param(pcdev, buswidth, &bus_flags);
1189
1190 if (ret < 0)
1191 return ret;
1192
1193 camera_flags = icd->ops->query_bus_param(icd);
1194
1195 return soc_camera_bus_param_compatible(camera_flags, bus_flags) ? 0 : -EINVAL;
1196 }
1197
1198 static const struct soc_camera_data_format pxa_camera_formats[] = {
1199 {
1200 .name = "Planar YUV422 16 bit",
1201 .depth = 16,
1202 .fourcc = V4L2_PIX_FMT_YUV422P,
1203 .colorspace = V4L2_COLORSPACE_JPEG,
1204 },
1205 };
1206
1207 static bool buswidth_supported(struct soc_camera_device *icd, int depth)
1208 {
1209 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1210 struct pxa_camera_dev *pcdev = ici->priv;
1211
1212 switch (depth) {
1213 case 8:
1214 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8);
1215 case 9:
1216 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9);
1217 case 10:
1218 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10);
1219 }
1220 return false;
1221 }
1222
1223 static int required_buswidth(const struct soc_camera_data_format *fmt)
1224 {
1225 switch (fmt->fourcc) {
1226 case V4L2_PIX_FMT_UYVY:
1227 case V4L2_PIX_FMT_VYUY:
1228 case V4L2_PIX_FMT_YUYV:
1229 case V4L2_PIX_FMT_YVYU:
1230 case V4L2_PIX_FMT_RGB565:
1231 case V4L2_PIX_FMT_RGB555:
1232 return 8;
1233 default:
1234 return fmt->depth;
1235 }
1236 }
1237
1238 static int pxa_camera_get_formats(struct soc_camera_device *icd, int idx,
1239 struct soc_camera_format_xlate *xlate)
1240 {
1241 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1242 int formats = 0, buswidth, ret;
1243
1244 buswidth = required_buswidth(icd->formats + idx);
1245
1246 if (!buswidth_supported(icd, buswidth))
1247 return 0;
1248
1249 ret = pxa_camera_try_bus_param(icd, buswidth);
1250 if (ret < 0)
1251 return 0;
1252
1253 switch (icd->formats[idx].fourcc) {
1254 case V4L2_PIX_FMT_UYVY:
1255 formats++;
1256 if (xlate) {
1257 xlate->host_fmt = &pxa_camera_formats[0];
1258 xlate->cam_fmt = icd->formats + idx;
1259 xlate->buswidth = buswidth;
1260 xlate++;
1261 dev_dbg(ici->dev, "Providing format %s using %s\n",
1262 pxa_camera_formats[0].name,
1263 icd->formats[idx].name);
1264 }
1265 case V4L2_PIX_FMT_VYUY:
1266 case V4L2_PIX_FMT_YUYV:
1267 case V4L2_PIX_FMT_YVYU:
1268 case V4L2_PIX_FMT_RGB565:
1269 case V4L2_PIX_FMT_RGB555:
1270 formats++;
1271 if (xlate) {
1272 xlate->host_fmt = icd->formats + idx;
1273 xlate->cam_fmt = icd->formats + idx;
1274 xlate->buswidth = buswidth;
1275 xlate++;
1276 dev_dbg(ici->dev, "Providing format %s packed\n",
1277 icd->formats[idx].name);
1278 }
1279 break;
1280 default:
1281 /* Generic pass-through */
1282 formats++;
1283 if (xlate) {
1284 xlate->host_fmt = icd->formats + idx;
1285 xlate->cam_fmt = icd->formats + idx;
1286 xlate->buswidth = icd->formats[idx].depth;
1287 xlate++;
1288 dev_dbg(ici->dev,
1289 "Providing format %s in pass-through mode\n",
1290 icd->formats[idx].name);
1291 }
1292 }
1293
1294 return formats;
1295 }
1296
1297 static int pxa_camera_set_crop(struct soc_camera_device *icd,
1298 struct v4l2_rect *rect)
1299 {
1300 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1301 struct pxa_camera_dev *pcdev = ici->priv;
1302 struct soc_camera_sense sense = {
1303 .master_clock = pcdev->mclk,
1304 .pixel_clock_max = pcdev->ciclk / 4,
1305 };
1306 int ret;
1307
1308 /* If PCLK is used to latch data from the sensor, check sense */
1309 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1310 icd->sense = &sense;
1311
1312 ret = icd->ops->set_crop(icd, rect);
1313
1314 icd->sense = NULL;
1315
1316 if (ret < 0) {
1317 dev_warn(ici->dev, "Failed to crop to %ux%u@%u:%u\n",
1318 rect->width, rect->height, rect->left, rect->top);
1319 } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1320 if (sense.pixel_clock > sense.pixel_clock_max) {
1321 dev_err(ici->dev,
1322 "pixel clock %lu set by the camera too high!",
1323 sense.pixel_clock);
1324 return -EIO;
1325 }
1326 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1327 }
1328
1329 return ret;
1330 }
1331
1332 static int pxa_camera_set_fmt(struct soc_camera_device *icd,
1333 struct v4l2_format *f)
1334 {
1335 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1336 struct pxa_camera_dev *pcdev = ici->priv;
1337 const struct soc_camera_data_format *cam_fmt = NULL;
1338 const struct soc_camera_format_xlate *xlate = NULL;
1339 struct soc_camera_sense sense = {
1340 .master_clock = pcdev->mclk,
1341 .pixel_clock_max = pcdev->ciclk / 4,
1342 };
1343 struct v4l2_pix_format *pix = &f->fmt.pix;
1344 struct v4l2_format cam_f = *f;
1345 int ret;
1346
1347 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1348 if (!xlate) {
1349 dev_warn(ici->dev, "Format %x not found\n", pix->pixelformat);
1350 return -EINVAL;
1351 }
1352
1353 cam_fmt = xlate->cam_fmt;
1354
1355 /* If PCLK is used to latch data from the sensor, check sense */
1356 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1357 icd->sense = &sense;
1358
1359 cam_f.fmt.pix.pixelformat = cam_fmt->fourcc;
1360 ret = icd->ops->set_fmt(icd, &cam_f);
1361
1362 icd->sense = NULL;
1363
1364 if (ret < 0) {
1365 dev_warn(ici->dev, "Failed to configure for format %x\n",
1366 pix->pixelformat);
1367 } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1368 if (sense.pixel_clock > sense.pixel_clock_max) {
1369 dev_err(ici->dev,
1370 "pixel clock %lu set by the camera too high!",
1371 sense.pixel_clock);
1372 return -EIO;
1373 }
1374 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1375 }
1376
1377 if (!ret) {
1378 icd->buswidth = xlate->buswidth;
1379 icd->current_fmt = xlate->host_fmt;
1380 }
1381
1382 return ret;
1383 }
1384
1385 static int pxa_camera_try_fmt(struct soc_camera_device *icd,
1386 struct v4l2_format *f)
1387 {
1388 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1389 const struct soc_camera_format_xlate *xlate;
1390 struct v4l2_pix_format *pix = &f->fmt.pix;
1391 __u32 pixfmt = pix->pixelformat;
1392 enum v4l2_field field;
1393 int ret;
1394
1395 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1396 if (!xlate) {
1397 dev_warn(ici->dev, "Format %x not found\n", pixfmt);
1398 return -EINVAL;
1399 }
1400
1401 /* limit to pxa hardware capabilities */
1402 if (pix->height < 32)
1403 pix->height = 32;
1404 if (pix->height > 2048)
1405 pix->height = 2048;
1406 if (pix->width < 48)
1407 pix->width = 48;
1408 if (pix->width > 2048)
1409 pix->width = 2048;
1410 pix->width &= ~0x01;
1411
1412 /*
1413 * YUV422P planar format requires images size to be a 16 bytes
1414 * multiple. If not, zeros will be inserted between Y and U planes, and
1415 * U and V planes, and YUV422P standard would be violated.
1416 */
1417 if (xlate->host_fmt->fourcc == V4L2_PIX_FMT_YUV422P) {
1418 if (!IS_ALIGNED(pix->width * pix->height, YUV422P_SIZE_ALIGN))
1419 pix->height = ALIGN(pix->height, YUV422P_X_Y_ALIGN);
1420 if (!IS_ALIGNED(pix->width * pix->height, YUV422P_SIZE_ALIGN))
1421 pix->width = ALIGN(pix->width, YUV422P_X_Y_ALIGN);
1422 }
1423
1424 pix->bytesperline = pix->width *
1425 DIV_ROUND_UP(xlate->host_fmt->depth, 8);
1426 pix->sizeimage = pix->height * pix->bytesperline;
1427
1428 /* camera has to see its format, but the user the original one */
1429 pix->pixelformat = xlate->cam_fmt->fourcc;
1430 /* limit to sensor capabilities */
1431 ret = icd->ops->try_fmt(icd, f);
1432 pix->pixelformat = xlate->host_fmt->fourcc;
1433
1434 field = pix->field;
1435
1436 if (field == V4L2_FIELD_ANY) {
1437 pix->field = V4L2_FIELD_NONE;
1438 } else if (field != V4L2_FIELD_NONE) {
1439 dev_err(&icd->dev, "Field type %d unsupported.\n", field);
1440 return -EINVAL;
1441 }
1442
1443 return ret;
1444 }
1445
1446 static int pxa_camera_reqbufs(struct soc_camera_file *icf,
1447 struct v4l2_requestbuffers *p)
1448 {
1449 int i;
1450
1451 /* This is for locking debugging only. I removed spinlocks and now I
1452 * check whether .prepare is ever called on a linked buffer, or whether
1453 * a dma IRQ can occur for an in-work or unlinked buffer. Until now
1454 * it hadn't triggered */
1455 for (i = 0; i < p->count; i++) {
1456 struct pxa_buffer *buf = container_of(icf->vb_vidq.bufs[i],
1457 struct pxa_buffer, vb);
1458 buf->inwork = 0;
1459 INIT_LIST_HEAD(&buf->vb.queue);
1460 }
1461
1462 return 0;
1463 }
1464
1465 static unsigned int pxa_camera_poll(struct file *file, poll_table *pt)
1466 {
1467 struct soc_camera_file *icf = file->private_data;
1468 struct pxa_buffer *buf;
1469
1470 buf = list_entry(icf->vb_vidq.stream.next, struct pxa_buffer,
1471 vb.stream);
1472
1473 poll_wait(file, &buf->vb.done, pt);
1474
1475 if (buf->vb.state == VIDEOBUF_DONE ||
1476 buf->vb.state == VIDEOBUF_ERROR)
1477 return POLLIN|POLLRDNORM;
1478
1479 return 0;
1480 }
1481
1482 static int pxa_camera_querycap(struct soc_camera_host *ici,
1483 struct v4l2_capability *cap)
1484 {
1485 /* cap->name is set by the firendly caller:-> */
1486 strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
1487 cap->version = PXA_CAM_VERSION_CODE;
1488 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1489
1490 return 0;
1491 }
1492
1493 static int pxa_camera_suspend(struct soc_camera_device *icd, pm_message_t state)
1494 {
1495 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1496 struct pxa_camera_dev *pcdev = ici->priv;
1497 int i = 0, ret = 0;
1498
1499 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
1500 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
1501 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
1502 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
1503 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
1504
1505 if ((pcdev->icd) && (pcdev->icd->ops->suspend))
1506 ret = pcdev->icd->ops->suspend(pcdev->icd, state);
1507
1508 return ret;
1509 }
1510
1511 static int pxa_camera_resume(struct soc_camera_device *icd)
1512 {
1513 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1514 struct pxa_camera_dev *pcdev = ici->priv;
1515 int i = 0, ret = 0;
1516
1517 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1518 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1519 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1520
1521 __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
1522 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
1523 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
1524 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
1525 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
1526
1527 if ((pcdev->icd) && (pcdev->icd->ops->resume))
1528 ret = pcdev->icd->ops->resume(pcdev->icd);
1529
1530 /* Restart frame capture if active buffer exists */
1531 if (!ret && pcdev->active)
1532 pxa_camera_start_capture(pcdev);
1533
1534 return ret;
1535 }
1536
1537 static struct soc_camera_host_ops pxa_soc_camera_host_ops = {
1538 .owner = THIS_MODULE,
1539 .add = pxa_camera_add_device,
1540 .remove = pxa_camera_remove_device,
1541 .suspend = pxa_camera_suspend,
1542 .resume = pxa_camera_resume,
1543 .set_crop = pxa_camera_set_crop,
1544 .get_formats = pxa_camera_get_formats,
1545 .set_fmt = pxa_camera_set_fmt,
1546 .try_fmt = pxa_camera_try_fmt,
1547 .init_videobuf = pxa_camera_init_videobuf,
1548 .reqbufs = pxa_camera_reqbufs,
1549 .poll = pxa_camera_poll,
1550 .querycap = pxa_camera_querycap,
1551 .set_bus_param = pxa_camera_set_bus_param,
1552 };
1553
1554 static int __devinit pxa_camera_probe(struct platform_device *pdev)
1555 {
1556 struct pxa_camera_dev *pcdev;
1557 struct resource *res;
1558 void __iomem *base;
1559 int irq;
1560 int err = 0;
1561
1562 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1563 irq = platform_get_irq(pdev, 0);
1564 if (!res || irq < 0) {
1565 err = -ENODEV;
1566 goto exit;
1567 }
1568
1569 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
1570 if (!pcdev) {
1571 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1572 err = -ENOMEM;
1573 goto exit;
1574 }
1575
1576 pcdev->clk = clk_get(&pdev->dev, NULL);
1577 if (IS_ERR(pcdev->clk)) {
1578 err = PTR_ERR(pcdev->clk);
1579 goto exit_kfree;
1580 }
1581
1582 pcdev->res = res;
1583
1584 pcdev->pdata = pdev->dev.platform_data;
1585 pcdev->platform_flags = pcdev->pdata->flags;
1586 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
1587 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
1588 /* Platform hasn't set available data widths. This is bad.
1589 * Warn and use a default. */
1590 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
1591 "data widths, using default 10 bit\n");
1592 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
1593 }
1594 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
1595 if (!pcdev->mclk) {
1596 dev_warn(&pdev->dev,
1597 "mclk == 0! Please, fix your platform data. "
1598 "Using default 20MHz\n");
1599 pcdev->mclk = 20000000;
1600 }
1601
1602 pcdev->mclk_divisor = mclk_get_divisor(pcdev);
1603
1604 INIT_LIST_HEAD(&pcdev->capture);
1605 spin_lock_init(&pcdev->lock);
1606
1607 /*
1608 * Request the regions.
1609 */
1610 if (!request_mem_region(res->start, resource_size(res),
1611 PXA_CAM_DRV_NAME)) {
1612 err = -EBUSY;
1613 goto exit_clk;
1614 }
1615
1616 base = ioremap(res->start, resource_size(res));
1617 if (!base) {
1618 err = -ENOMEM;
1619 goto exit_release;
1620 }
1621 pcdev->irq = irq;
1622 pcdev->base = base;
1623
1624 /* request dma */
1625 err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH,
1626 pxa_camera_dma_irq_y, pcdev);
1627 if (err < 0) {
1628 dev_err(&pdev->dev, "Can't request DMA for Y\n");
1629 goto exit_iounmap;
1630 }
1631 pcdev->dma_chans[0] = err;
1632 dev_dbg(&pdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]);
1633
1634 err = pxa_request_dma("CI_U", DMA_PRIO_HIGH,
1635 pxa_camera_dma_irq_u, pcdev);
1636 if (err < 0) {
1637 dev_err(&pdev->dev, "Can't request DMA for U\n");
1638 goto exit_free_dma_y;
1639 }
1640 pcdev->dma_chans[1] = err;
1641 dev_dbg(&pdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]);
1642
1643 err = pxa_request_dma("CI_V", DMA_PRIO_HIGH,
1644 pxa_camera_dma_irq_v, pcdev);
1645 if (err < 0) {
1646 dev_err(&pdev->dev, "Can't request DMA for V\n");
1647 goto exit_free_dma_u;
1648 }
1649 pcdev->dma_chans[2] = err;
1650 dev_dbg(&pdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]);
1651
1652 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1653 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1654 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1655
1656 /* request irq */
1657 err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME,
1658 pcdev);
1659 if (err) {
1660 dev_err(&pdev->dev, "Camera interrupt register failed \n");
1661 goto exit_free_dma;
1662 }
1663
1664 pcdev->soc_host.drv_name = PXA_CAM_DRV_NAME;
1665 pcdev->soc_host.ops = &pxa_soc_camera_host_ops;
1666 pcdev->soc_host.priv = pcdev;
1667 pcdev->soc_host.dev = &pdev->dev;
1668 pcdev->soc_host.nr = pdev->id;
1669
1670 err = soc_camera_host_register(&pcdev->soc_host);
1671 if (err)
1672 goto exit_free_irq;
1673
1674 return 0;
1675
1676 exit_free_irq:
1677 free_irq(pcdev->irq, pcdev);
1678 exit_free_dma:
1679 pxa_free_dma(pcdev->dma_chans[2]);
1680 exit_free_dma_u:
1681 pxa_free_dma(pcdev->dma_chans[1]);
1682 exit_free_dma_y:
1683 pxa_free_dma(pcdev->dma_chans[0]);
1684 exit_iounmap:
1685 iounmap(base);
1686 exit_release:
1687 release_mem_region(res->start, resource_size(res));
1688 exit_clk:
1689 clk_put(pcdev->clk);
1690 exit_kfree:
1691 kfree(pcdev);
1692 exit:
1693 return err;
1694 }
1695
1696 static int __devexit pxa_camera_remove(struct platform_device *pdev)
1697 {
1698 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1699 struct pxa_camera_dev *pcdev = container_of(soc_host,
1700 struct pxa_camera_dev, soc_host);
1701 struct resource *res;
1702
1703 clk_put(pcdev->clk);
1704
1705 pxa_free_dma(pcdev->dma_chans[0]);
1706 pxa_free_dma(pcdev->dma_chans[1]);
1707 pxa_free_dma(pcdev->dma_chans[2]);
1708 free_irq(pcdev->irq, pcdev);
1709
1710 soc_camera_host_unregister(soc_host);
1711
1712 iounmap(pcdev->base);
1713
1714 res = pcdev->res;
1715 release_mem_region(res->start, resource_size(res));
1716
1717 kfree(pcdev);
1718
1719 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
1720
1721 return 0;
1722 }
1723
1724 static struct platform_driver pxa_camera_driver = {
1725 .driver = {
1726 .name = PXA_CAM_DRV_NAME,
1727 },
1728 .probe = pxa_camera_probe,
1729 .remove = __devexit_p(pxa_camera_remove),
1730 };
1731
1732
1733 static int __init pxa_camera_init(void)
1734 {
1735 return platform_driver_register(&pxa_camera_driver);
1736 }
1737
1738 static void __exit pxa_camera_exit(void)
1739 {
1740 platform_driver_unregister(&pxa_camera_driver);
1741 }
1742
1743 module_init(pxa_camera_init);
1744 module_exit(pxa_camera_exit);
1745
1746 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1747 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1748 MODULE_LICENSE("GPL");
Support for the Chinese Samsung S3C2440 based development boards