drivers/misc/hpilo.h

   1 /*
   2  * linux/drivers/char/hpilo.h
   3  *
   4  * Copyright (C) 2008 Hewlett-Packard Development Company, L.P.
   5  *      David Altobelli <david.altobelli@hp.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11 #ifndef __HPILO_H
  12 #define __HPILO_H
  13
  14 #define ILO_NAME "hpilo"
  15
  16 /* max number of open channel control blocks per device, hw limited to 32 */
  17 #define MAX_CCB         8
  18 /* max number of supported devices */
  19 #define MAX_ILO_DEV     1
  20 /* max number of files */
  21 #define MAX_OPEN        (MAX_CCB * MAX_ILO_DEV)
  22 /* spin counter for open/close delay */
  23 #define MAX_WAIT        10000
  24
  25 /*
  26  * Per device, used to track global memory allocations.
  27  */
  28 struct ilo_hwinfo {
  29         /* mmio registers on device */
  30         char __iomem *mmio_vaddr;
  31
  32         /* doorbell registers on device */
  33         char __iomem *db_vaddr;
  34
  35         /* shared memory on device used for channel control blocks */
  36         char __iomem *ram_vaddr;
  37
  38         /* files corresponding to this device */
  39         struct ccb_data *ccb_alloc[MAX_CCB];
  40
  41         struct pci_dev *ilo_dev;
  42
  43         spinlock_t alloc_lock;
  44         spinlock_t fifo_lock;
  45
  46         struct cdev cdev;
  47 };
  48
  49 /* offset from mmio_vaddr */
  50 #define DB_OUT          0xD4
  51 /* DB_OUT reset bit */
  52 #define DB_RESET        26
  53
  54 /*
  55  * Channel control block. Used to manage hardware queues.
  56  * The format must match hw's version.  The hw ccb is 128 bytes,
  57  * but the context area shouldn't be touched by the driver.
  58  */
  59 #define ILOSW_CCB_SZ    64
  60 #define ILOHW_CCB_SZ    128
  61 struct ccb {
  62         union {
  63                 char *send_fifobar;
  64                 u64 padding1;
  65         } ccb_u1;
  66         union {
  67                 char *send_desc;
  68                 u64 padding2;
  69         } ccb_u2;
  70         u64 send_ctrl;
  71
  72         union {
  73                 char *recv_fifobar;
  74                 u64 padding3;
  75         } ccb_u3;
  76         union {
  77                 char *recv_desc;
  78                 u64 padding4;
  79         } ccb_u4;
  80         u64 recv_ctrl;
  81
  82         union {
  83                 char __iomem *db_base;
  84                 u64 padding5;
  85         } ccb_u5;
  86
  87         u64 channel;
  88
  89         /* unused context area (64 bytes) */
  90 };
  91
  92 /* ccb queue parameters */
  93 #define SENDQ           1
  94 #define RECVQ           2
  95 #define NR_QENTRY       4
  96 #define L2_QENTRY_SZ    12
  97
  98 /* ccb ctrl bitfields */
  99 #define CTRL_BITPOS_L2SZ             0
 100 #define CTRL_BITPOS_FIFOINDEXMASK    4
 101 #define CTRL_BITPOS_DESCLIMIT        18
 102 #define CTRL_BITPOS_A                30
 103 #define CTRL_BITPOS_G                31
 104
 105 /* ccb doorbell macros */
 106 #define L2_DB_SIZE              14
 107 #define ONE_DB_SIZE             (1 << L2_DB_SIZE)
 108
 109 /*
 110  * Per fd structure used to track the ccb allocated to that dev file.
 111  */
 112 struct ccb_data {
 113         /* software version of ccb, using virtual addrs */
 114         struct ccb  driver_ccb;
 115
 116         /* hardware version of ccb, using physical addrs */
 117         struct ccb  ilo_ccb;
 118
 119         /* hardware ccb is written to this shared mapped device memory */
 120         struct ccb __iomem *mapped_ccb;
 121
 122         /* dma'able memory used for send/recv queues */
 123         void       *dma_va;
 124         dma_addr_t  dma_pa;
 125         size_t      dma_size;
 126
 127         /* pointer to hardware device info */
 128         struct ilo_hwinfo *ilo_hw;
 129
 130         /* usage count, to allow for shared ccb's */
 131         int         ccb_cnt;
 132
 133         /* open wanted exclusive access to this ccb */
 134         int         ccb_excl;
 135 };
 136
 137 /*
 138  * FIFO queue structure, shared with hw.
 139  */
 140 #define ILO_START_ALIGN 4096
 141 #define ILO_CACHE_SZ     128
 142 struct fifo {
 143     u64 nrents; /* user requested number of fifo entries */
 144     u64 imask;  /* mask to extract valid fifo index */
 145     u64 merge;  /*  O/C bits to merge in during enqueue operation */
 146     u64 reset;  /* set to non-zero when the target device resets */
 147     u8  pad_0[ILO_CACHE_SZ - (sizeof(u64) * 4)];
 148
 149     u64 head;
 150     u8  pad_1[ILO_CACHE_SZ - (sizeof(u64))];
 151
 152     u64 tail;
 153     u8  pad_2[ILO_CACHE_SZ - (sizeof(u64))];
 154
 155     u64 fifobar[1];
 156 };
 157
 158 /* convert between struct fifo, and the fifobar, which is saved in the ccb */
 159 #define FIFOHANDLESIZE (sizeof(struct fifo) - sizeof(u64))
 160 #define FIFOBARTOHANDLE(_fifo) \
 161         ((struct fifo *)(((char *)(_fifo)) - FIFOHANDLESIZE))
 162
 163 /* the number of qwords to consume from the entry descriptor */
 164 #define ENTRY_BITPOS_QWORDS      0
 165 /* descriptor index number (within a specified queue) */
 166 #define ENTRY_BITPOS_DESCRIPTOR  10
 167 /* state bit, fifo entry consumed by consumer */
 168 #define ENTRY_BITPOS_C           22
 169 /* state bit, fifo entry is occupied */
 170 #define ENTRY_BITPOS_O           23
 171
 172 #define ENTRY_BITS_QWORDS        10
 173 #define ENTRY_BITS_DESCRIPTOR    12
 174 #define ENTRY_BITS_C             1
 175 #define ENTRY_BITS_O             1
 176 #define ENTRY_BITS_TOTAL        \
 177         (ENTRY_BITS_C + ENTRY_BITS_O + \
 178          ENTRY_BITS_QWORDS + ENTRY_BITS_DESCRIPTOR)
 179
 180 /* extract various entry fields */
 181 #define ENTRY_MASK ((1 << ENTRY_BITS_TOTAL) - 1)
 182 #define ENTRY_MASK_C (((1 << ENTRY_BITS_C) - 1) << ENTRY_BITPOS_C)
 183 #define ENTRY_MASK_O (((1 << ENTRY_BITS_O) - 1) << ENTRY_BITPOS_O)
 184 #define ENTRY_MASK_QWORDS \
 185         (((1 << ENTRY_BITS_QWORDS) - 1) << ENTRY_BITPOS_QWORDS)
 186 #define ENTRY_MASK_DESCRIPTOR \
 187         (((1 << ENTRY_BITS_DESCRIPTOR) - 1) << ENTRY_BITPOS_DESCRIPTOR)
 188
 189 #define ENTRY_MASK_NOSTATE (ENTRY_MASK >> (ENTRY_BITS_C + ENTRY_BITS_O))
 190
 191 #endif /* __HPILO_H */