arch/arm/mach-ixp4xx/common.c

   1 /*
   2  * arch/arm/mach-ixp4xx/common.c
   3  *
   4  * Generic code shared across all IXP4XX platforms
   5  *
   6  * Maintainer: Deepak Saxena <dsaxena@plexity.net>
   7  *
   8  * Copyright 2002 (c) Intel Corporation
   9  * Copyright 2003-2004 (c) MontaVista, Software, Inc.
  10  *
  11  * This file is licensed under  the terms of the GNU General Public
  12  * License version 2. This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/mm.h>
  18 #include <linux/init.h>
  19 #include <linux/serial.h>
  20 #include <linux/sched.h>
  21 #include <linux/tty.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/serial_core.h>
  24 #include <linux/bootmem.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/bitops.h>
  27 #include <linux/time.h>
  28 #include <linux/timex.h>
  29 #include <linux/clocksource.h>
  30 #include <linux/clockchips.h>
  31
  32 #include <asm/arch/udc.h>
  33 #include <asm/hardware.h>
  34 #include <asm/uaccess.h>
  35 #include <asm/io.h>
  36 #include <asm/pgtable.h>
  37 #include <asm/page.h>
  38 #include <asm/irq.h>
  39
  40 #include <asm/mach/map.h>
  41 #include <asm/mach/irq.h>
  42 #include <asm/mach/time.h>
  43
  44 static int __init ixp4xx_clocksource_init(void);
  45 static int __init ixp4xx_clockevent_init(void);
  46 static struct clock_event_device clockevent_ixp4xx;
  47
  48 /*************************************************************************
  49  * IXP4xx chipset I/O mapping
  50  *************************************************************************/
  51 static struct map_desc ixp4xx_io_desc[] __initdata = {
  52         {       /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
  53                 .virtual        = IXP4XX_PERIPHERAL_BASE_VIRT,
  54                 .pfn            = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
  55                 .length         = IXP4XX_PERIPHERAL_REGION_SIZE,
  56                 .type           = MT_DEVICE
  57         }, {    /* Expansion Bus Config Registers */
  58                 .virtual        = IXP4XX_EXP_CFG_BASE_VIRT,
  59                 .pfn            = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
  60                 .length         = IXP4XX_EXP_CFG_REGION_SIZE,
  61                 .type           = MT_DEVICE
  62         }, {    /* PCI Registers */
  63                 .virtual        = IXP4XX_PCI_CFG_BASE_VIRT,
  64                 .pfn            = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
  65                 .length         = IXP4XX_PCI_CFG_REGION_SIZE,
  66                 .type           = MT_DEVICE
  67         },
  68 #ifdef CONFIG_DEBUG_LL
  69         {       /* Debug UART mapping */
  70                 .virtual        = IXP4XX_DEBUG_UART_BASE_VIRT,
  71                 .pfn            = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS),
  72                 .length         = IXP4XX_DEBUG_UART_REGION_SIZE,
  73                 .type           = MT_DEVICE
  74         }
  75 #endif
  76 };
  77
  78 void __init ixp4xx_map_io(void)
  79 {
  80         iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
  81 }
  82
  83
  84 /*************************************************************************
  85  * IXP4xx chipset IRQ handling
  86  *
  87  * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
  88  *       (be it PCI or something else) configures that GPIO line
  89  *       as an IRQ.
  90  **************************************************************************/
  91 enum ixp4xx_irq_type {
  92         IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
  93 };
  94
  95 /* Each bit represents an IRQ: 1: edge-triggered, 0: level triggered */
  96 static unsigned long long ixp4xx_irq_edge = 0;
  97
  98 /*
  99  * IRQ -> GPIO mapping table
 100  */
 101 static signed char irq2gpio[32] = {
 102         -1, -1, -1, -1, -1, -1,  0,  1,
 103         -1, -1, -1, -1, -1, -1, -1, -1,
 104         -1, -1, -1,  2,  3,  4,  5,  6,
 105          7,  8,  9, 10, 11, 12, -1, -1,
 106 };
 107
 108 static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
 109 {
 110         int line = irq2gpio[irq];
 111         u32 int_style;
 112         enum ixp4xx_irq_type irq_type;
 113         volatile u32 *int_reg;
 114
 115         /*
 116          * Only for GPIO IRQs
 117          */
 118         if (line < 0)
 119                 return -EINVAL;
 120
 121         switch (type){
 122         case IRQT_BOTHEDGE:
 123                 int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
 124                 irq_type = IXP4XX_IRQ_EDGE;
 125                 break;
 126         case IRQT_RISING:
 127                 int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
 128                 irq_type = IXP4XX_IRQ_EDGE;
 129                 break;
 130         case IRQT_FALLING:
 131                 int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
 132                 irq_type = IXP4XX_IRQ_EDGE;
 133                 break;
 134         case IRQT_HIGH:
 135                 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
 136                 irq_type = IXP4XX_IRQ_LEVEL;
 137                 break;
 138         case IRQT_LOW:
 139                 int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
 140                 irq_type = IXP4XX_IRQ_LEVEL;
 141                 break;
 142         default:
 143                 return -EINVAL;
 144         }
 145
 146         if (irq_type == IXP4XX_IRQ_EDGE)
 147                 ixp4xx_irq_edge |= (1 << irq);
 148         else
 149                 ixp4xx_irq_edge &= ~(1 << irq);
 150
 151         if (line >= 8) {        /* pins 8-15 */
 152                 line -= 8;
 153                 int_reg = IXP4XX_GPIO_GPIT2R;
 154         } else {                /* pins 0-7 */
 155                 int_reg = IXP4XX_GPIO_GPIT1R;
 156         }
 157
 158         /* Clear the style for the appropriate pin */
 159         *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
 160                         (line * IXP4XX_GPIO_STYLE_SIZE));
 161
 162         *IXP4XX_GPIO_GPISR = (1 << line);
 163
 164         /* Set the new style */
 165         *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
 166
 167         /* Configure the line as an input */
 168         gpio_line_config(line, IXP4XX_GPIO_IN);
 169
 170         return 0;
 171 }
 172
 173 static void ixp4xx_irq_mask(unsigned int irq)
 174 {
 175         if (cpu_is_ixp46x() && irq >= 32)
 176                 *IXP4XX_ICMR2 &= ~(1 << (irq - 32));
 177         else
 178                 *IXP4XX_ICMR &= ~(1 << irq);
 179 }
 180
 181 static void ixp4xx_irq_ack(unsigned int irq)
 182 {
 183         int line = (irq < 32) ? irq2gpio[irq] : -1;
 184
 185         if (line >= 0)
 186                 *IXP4XX_GPIO_GPISR = (1 << line);
 187 }
 188
 189 /*
 190  * Level triggered interrupts on GPIO lines can only be cleared when the
 191  * interrupt condition disappears.
 192  */
 193 static void ixp4xx_irq_unmask(unsigned int irq)
 194 {
 195         if (!(ixp4xx_irq_edge & (1 << irq)))
 196                 ixp4xx_irq_ack(irq);
 197
 198         if (cpu_is_ixp46x() && irq >= 32)
 199                 *IXP4XX_ICMR2 |= (1 << (irq - 32));
 200         else
 201                 *IXP4XX_ICMR |= (1 << irq);
 202 }
 203
 204 static struct irq_chip ixp4xx_irq_chip = {
 205         .name           = "IXP4xx",
 206         .ack            = ixp4xx_irq_ack,
 207         .mask           = ixp4xx_irq_mask,
 208         .unmask         = ixp4xx_irq_unmask,
 209         .set_type       = ixp4xx_set_irq_type,
 210 };
 211
 212 void __init ixp4xx_init_irq(void)
 213 {
 214         int i = 0;
 215
 216         /* Route all sources to IRQ instead of FIQ */
 217         *IXP4XX_ICLR = 0x0;
 218
 219         /* Disable all interrupt */
 220         *IXP4XX_ICMR = 0x0;
 221
 222         if (cpu_is_ixp46x()) {
 223                 /* Route upper 32 sources to IRQ instead of FIQ */
 224                 *IXP4XX_ICLR2 = 0x00;
 225
 226                 /* Disable upper 32 interrupts */
 227                 *IXP4XX_ICMR2 = 0x00;
 228         }
 229
 230         /* Default to all level triggered */
 231         for(i = 0; i < NR_IRQS; i++) {
 232                 set_irq_chip(i, &ixp4xx_irq_chip);
 233                 set_irq_handler(i, handle_level_irq);
 234                 set_irq_flags(i, IRQF_VALID);
 235         }
 236 }
 237
 238
 239 /*************************************************************************
 240  * IXP4xx timer tick
 241  * We use OS timer1 on the CPU for the timer tick and the timestamp
 242  * counter as a source of real clock ticks to account for missed jiffies.
 243  *************************************************************************/
 244
 245 static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
 246 {
 247         struct clock_event_device *evt = &clockevent_ixp4xx;
 248
 249         /* Clear Pending Interrupt by writing '1' to it */
 250         *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
 251
 252         evt->event_handler(evt);
 253
 254         return IRQ_HANDLED;
 255 }
 256
 257 static struct irqaction ixp4xx_timer_irq = {
 258         .name           = "timer1",
 259         .flags          = IRQF_DISABLED | IRQF_TIMER,
 260         .handler        = ixp4xx_timer_interrupt,
 261 };
 262
 263 static void __init ixp4xx_timer_init(void)
 264 {
 265         /* Reset/disable counter */
 266         *IXP4XX_OSRT1 = 0;
 267
 268         /* Clear Pending Interrupt by writing '1' to it */
 269         *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
 270
 271         /* Reset time-stamp counter */
 272         *IXP4XX_OSTS = 0;
 273
 274         /* Connect the interrupt handler and enable the interrupt */
 275         setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
 276
 277         ixp4xx_clocksource_init();
 278         ixp4xx_clockevent_init();
 279 }
 280
 281 struct sys_timer ixp4xx_timer = {
 282         .init           = ixp4xx_timer_init,
 283 };
 284
 285 static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
 286
 287 void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info)
 288 {
 289         memcpy(&ixp4xx_udc_info, info, sizeof *info);
 290 }
 291
 292 static struct resource ixp4xx_udc_resources[] = {
 293         [0] = {
 294                 .start  = 0xc800b000,
 295                 .end    = 0xc800bfff,
 296                 .flags  = IORESOURCE_MEM,
 297         },
 298         [1] = {
 299                 .start  = IRQ_IXP4XX_USB,
 300                 .end    = IRQ_IXP4XX_USB,
 301                 .flags  = IORESOURCE_IRQ,
 302         },
 303 };
 304
 305 /*
 306  * USB device controller. The IXP4xx uses the same controller as PXA2XX,
 307  * so we just use the same device.
 308  */
 309 static struct platform_device ixp4xx_udc_device = {
 310         .name           = "pxa2xx-udc",
 311         .id             = -1,
 312         .num_resources  = 2,
 313         .resource       = ixp4xx_udc_resources,
 314         .dev            = {
 315                 .platform_data = &ixp4xx_udc_info,
 316         },
 317 };
 318
 319 static struct platform_device *ixp4xx_devices[] __initdata = {
 320         &ixp4xx_udc_device,
 321 };
 322
 323 static struct resource ixp46x_i2c_resources[] = {
 324         [0] = {
 325                 .start  = 0xc8011000,
 326                 .end    = 0xc801101c,
 327                 .flags  = IORESOURCE_MEM,
 328         },
 329         [1] = {
 330                 .start  = IRQ_IXP4XX_I2C,
 331                 .end    = IRQ_IXP4XX_I2C,
 332                 .flags  = IORESOURCE_IRQ
 333         }
 334 };
 335
 336 /*
 337  * I2C controller. The IXP46x uses the same block as the IOP3xx, so
 338  * we just use the same device name.
 339  */
 340 static struct platform_device ixp46x_i2c_controller = {
 341         .name           = "IOP3xx-I2C",
 342         .id             = 0,
 343         .num_resources  = 2,
 344         .resource       = ixp46x_i2c_resources
 345 };
 346
 347 static struct platform_device *ixp46x_devices[] __initdata = {
 348         &ixp46x_i2c_controller
 349 };
 350
 351 unsigned long ixp4xx_exp_bus_size;
 352 EXPORT_SYMBOL(ixp4xx_exp_bus_size);
 353
 354 void __init ixp4xx_sys_init(void)
 355 {
 356         ixp4xx_exp_bus_size = SZ_16M;
 357
 358         platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
 359
 360         if (cpu_is_ixp46x()) {
 361                 int region;
 362
 363                 platform_add_devices(ixp46x_devices,
 364                                 ARRAY_SIZE(ixp46x_devices));
 365
 366                 for (region = 0; region < 7; region++) {
 367                         if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {
 368                                 ixp4xx_exp_bus_size = SZ_32M;
 369                                 break;
 370                         }
 371                 }
 372         }
 373
 374         printk("IXP4xx: Using %luMiB expansion bus window size\n",
 375                         ixp4xx_exp_bus_size >> 20);
 376 }
 377
 378 /*
 379  * clocksource
 380  */
 381 cycle_t ixp4xx_get_cycles(void)
 382 {
 383         return *IXP4XX_OSTS;
 384 }
 385
 386 static struct clocksource clocksource_ixp4xx = {
 387         .name           = "OSTS",
 388         .rating         = 200,
 389         .read           = ixp4xx_get_cycles,
 390         .mask           = CLOCKSOURCE_MASK(32),
 391         .shift          = 20,
 392         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 393 };
 394
 395 unsigned long ixp4xx_timer_freq = FREQ;
 396 static int __init ixp4xx_clocksource_init(void)
 397 {
 398         clocksource_ixp4xx.mult =
 399                 clocksource_hz2mult(ixp4xx_timer_freq,
 400                                     clocksource_ixp4xx.shift);
 401         clocksource_register(&clocksource_ixp4xx);
 402
 403         return 0;
 404 }
 405
 406 /*
 407  * clockevents
 408  */
 409 static int ixp4xx_set_next_event(unsigned long evt,
 410                                  struct clock_event_device *unused)
 411 {
 412         unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
 413
 414         *IXP4XX_OSRT1 = (evt & ~IXP4XX_OST_RELOAD_MASK) | opts;
 415
 416         return 0;
 417 }
 418
 419 static void ixp4xx_set_mode(enum clock_event_mode mode,
 420                             struct clock_event_device *evt)
 421 {
 422         unsigned long opts, osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK;
 423
 424         switch (mode) {
 425         case CLOCK_EVT_MODE_PERIODIC:
 426                 osrt = LATCH & ~IXP4XX_OST_RELOAD_MASK;
 427                 opts = IXP4XX_OST_ENABLE;
 428                 break;
 429         case CLOCK_EVT_MODE_ONESHOT:
 430                 /* period set by 'set next_event' */
 431                 osrt = 0;
 432                 opts = IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT;
 433                 break;
 434         case CLOCK_EVT_MODE_SHUTDOWN:
 435         case CLOCK_EVT_MODE_UNUSED:
 436         default:
 437                 osrt = opts = 0;
 438                 break;
 439         }
 440
 441         *IXP4XX_OSRT1 = osrt | opts;
 442 }
 443
 444 static struct clock_event_device clockevent_ixp4xx = {
 445         .name           = "ixp4xx timer1",
 446         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 447         .rating         = 200,
 448         .shift          = 24,
 449         .set_mode       = ixp4xx_set_mode,
 450         .set_next_event = ixp4xx_set_next_event,
 451 };
 452
 453 static int __init ixp4xx_clockevent_init(void)
 454 {
 455         clockevent_ixp4xx.mult = div_sc(FREQ, NSEC_PER_SEC,
 456                                         clockevent_ixp4xx.shift);
 457         clockevent_ixp4xx.max_delta_ns =
 458                 clockevent_delta2ns(0xfffffffe, &clockevent_ixp4xx);
 459         clockevent_ixp4xx.min_delta_ns =
 460                 clockevent_delta2ns(0xf, &clockevent_ixp4xx);
 461         clockevent_ixp4xx.cpumask = cpumask_of_cpu(0);
 462
 463         clockevents_register_device(&clockevent_ixp4xx);
 464         return 0;
 465 }