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atlx: timer cleanup
[linux-2.6/mini2440.git] / drivers / net / atlx / atl2.c
blob21ca6dd78b18f313b983df62a702caeac2ef49b6
1 /*
2 * Copyright(c) 2006 - 2007 Atheros Corporation. All rights reserved.
3 * Copyright(c) 2007 - 2008 Chris Snook <csnook@redhat.com>
4 *
5 * Derived from Intel e1000 driver
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22
23 #include <asm/atomic.h>
24 #include <linux/crc32.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/etherdevice.h>
27 #include <linux/ethtool.h>
28 #include <linux/hardirq.h>
29 #include <linux/if_vlan.h>
30 #include <linux/in.h>
31 #include <linux/interrupt.h>
32 #include <linux/ip.h>
33 #include <linux/irqflags.h>
34 #include <linux/irqreturn.h>
35 #include <linux/mii.h>
36 #include <linux/net.h>
37 #include <linux/netdevice.h>
38 #include <linux/pci.h>
39 #include <linux/pci_ids.h>
40 #include <linux/pm.h>
41 #include <linux/skbuff.h>
42 #include <linux/spinlock.h>
43 #include <linux/string.h>
44 #include <linux/tcp.h>
45 #include <linux/timer.h>
46 #include <linux/types.h>
47 #include <linux/workqueue.h>
48
49 #include "atl2.h"
50
51 #define ATL2_DRV_VERSION "2.2.3"
52
53 static char atl2_driver_name[] = "atl2";
54 static const char atl2_driver_string[] = "Atheros(R) L2 Ethernet Driver";
55 static char atl2_copyright[] = "Copyright (c) 2007 Atheros Corporation.";
56 static char atl2_driver_version[] = ATL2_DRV_VERSION;
57
58 MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>");
59 MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver");
60 MODULE_LICENSE("GPL");
61 MODULE_VERSION(ATL2_DRV_VERSION);
62
63 /*
64 * atl2_pci_tbl - PCI Device ID Table
65 */
66 static struct pci_device_id atl2_pci_tbl[] = {
67 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)},
68 /* required last entry */
69 {0,}
70 };
71 MODULE_DEVICE_TABLE(pci, atl2_pci_tbl);
72
73 static void atl2_set_ethtool_ops(struct net_device *netdev);
74
75 static void atl2_check_options(struct atl2_adapter *adapter);
76
77 /*
78 * atl2_sw_init - Initialize general software structures (struct atl2_adapter)
79 * @adapter: board private structure to initialize
80 *
81 * atl2_sw_init initializes the Adapter private data structure.
82 * Fields are initialized based on PCI device information and
83 * OS network device settings (MTU size).
84 */
85 static int __devinit atl2_sw_init(struct atl2_adapter *adapter)
86 {
87 struct atl2_hw *hw = &adapter->hw;
88 struct pci_dev *pdev = adapter->pdev;
89
90 /* PCI config space info */
91 hw->vendor_id = pdev->vendor;
92 hw->device_id = pdev->device;
93 hw->subsystem_vendor_id = pdev->subsystem_vendor;
94 hw->subsystem_id = pdev->subsystem_device;
95
96 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
97 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
98
99 adapter->wol = 0;
100 adapter->ict = 50000; /* ~100ms */
101 adapter->link_speed = SPEED_0; /* hardware init */
102 adapter->link_duplex = FULL_DUPLEX;
103
104 hw->phy_configured = false;
105 hw->preamble_len = 7;
106 hw->ipgt = 0x60;
107 hw->min_ifg = 0x50;
108 hw->ipgr1 = 0x40;
109 hw->ipgr2 = 0x60;
110 hw->retry_buf = 2;
111 hw->max_retry = 0xf;
112 hw->lcol = 0x37;
113 hw->jam_ipg = 7;
114 hw->fc_rxd_hi = 0;
115 hw->fc_rxd_lo = 0;
116 hw->max_frame_size = adapter->netdev->mtu;
117
118 spin_lock_init(&adapter->stats_lock);
119
120 set_bit(__ATL2_DOWN, &adapter->flags);
121
122 return 0;
123 }
124
125 /*
126 * atl2_set_multi - Multicast and Promiscuous mode set
127 * @netdev: network interface device structure
128 *
129 * The set_multi entry point is called whenever the multicast address
130 * list or the network interface flags are updated. This routine is
131 * responsible for configuring the hardware for proper multicast,
132 * promiscuous mode, and all-multi behavior.
133 */
134 static void atl2_set_multi(struct net_device *netdev)
135 {
136 struct atl2_adapter *adapter = netdev_priv(netdev);
137 struct atl2_hw *hw = &adapter->hw;
138 struct dev_mc_list *mc_ptr;
139 u32 rctl;
140 u32 hash_value;
141
142 /* Check for Promiscuous and All Multicast modes */
143 rctl = ATL2_READ_REG(hw, REG_MAC_CTRL);
144
145 if (netdev->flags & IFF_PROMISC) {
146 rctl |= MAC_CTRL_PROMIS_EN;
147 } else if (netdev->flags & IFF_ALLMULTI) {
148 rctl |= MAC_CTRL_MC_ALL_EN;
149 rctl &= ~MAC_CTRL_PROMIS_EN;
150 } else
151 rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
152
153 ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl);
154
155 /* clear the old settings from the multicast hash table */
156 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
157 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
158
159 /* comoute mc addresses' hash value ,and put it into hash table */
160 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
161 hash_value = atl2_hash_mc_addr(hw, mc_ptr->dmi_addr);
162 atl2_hash_set(hw, hash_value);
163 }
164 }
165
166 static void init_ring_ptrs(struct atl2_adapter *adapter)
167 {
168 /* Read / Write Ptr Initialize: */
169 adapter->txd_write_ptr = 0;
170 atomic_set(&adapter->txd_read_ptr, 0);
171
172 adapter->rxd_read_ptr = 0;
173 adapter->rxd_write_ptr = 0;
174
175 atomic_set(&adapter->txs_write_ptr, 0);
176 adapter->txs_next_clear = 0;
177 }
178
179 /*
180 * atl2_configure - Configure Transmit&Receive Unit after Reset
181 * @adapter: board private structure
182 *
183 * Configure the Tx /Rx unit of the MAC after a reset.
184 */
185 static int atl2_configure(struct atl2_adapter *adapter)
186 {
187 struct atl2_hw *hw = &adapter->hw;
188 u32 value;
189
190 /* clear interrupt status */
191 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff);
192
193 /* set MAC Address */
194 value = (((u32)hw->mac_addr[2]) << 24) |
195 (((u32)hw->mac_addr[3]) << 16) |
196 (((u32)hw->mac_addr[4]) << 8) |
197 (((u32)hw->mac_addr[5]));
198 ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value);
199 value = (((u32)hw->mac_addr[0]) << 8) |
200 (((u32)hw->mac_addr[1]));
201 ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value);
202
203 /* HI base address */
204 ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,
205 (u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32));
206
207 /* LO base address */
208 ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO,
209 (u32)(adapter->txd_dma & 0x00000000ffffffffULL));
210 ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO,
211 (u32)(adapter->txs_dma & 0x00000000ffffffffULL));
212 ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO,
213 (u32)(adapter->rxd_dma & 0x00000000ffffffffULL));
214
215 /* element count */
216 ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4));
217 ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size);
218 ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size);
219
220 /* config Internal SRAM */
221 /*
222 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end);
223 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end);
224 */
225
226 /* config IPG/IFG */
227 value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) <<
228 MAC_IPG_IFG_IPGT_SHIFT) |
229 (((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) <<
230 MAC_IPG_IFG_MIFG_SHIFT) |
231 (((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) <<
232 MAC_IPG_IFG_IPGR1_SHIFT)|
233 (((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) <<
234 MAC_IPG_IFG_IPGR2_SHIFT);
235 ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value);
236
237 /* config Half-Duplex Control */
238 value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
239 (((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) <<
240 MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
241 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
242 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
243 (((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) <<
244 MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
245 ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value);
246
247 /* set Interrupt Moderator Timer */
248 ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt);
249 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN);
250
251 /* set Interrupt Clear Timer */
252 ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict);
253
254 /* set MTU */
255 ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu +
256 ENET_HEADER_SIZE + VLAN_SIZE + ETHERNET_FCS_SIZE);
257
258 /* 1590 */
259 ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177);
260
261 /* flow control */
262 ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi);
263 ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo);
264
265 /* Init mailbox */
266 ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr);
267 ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr);
268
269 /* enable DMA read/write */
270 ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN);
271 ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN);
272
273 value = ATL2_READ_REG(&adapter->hw, REG_ISR);
274 if ((value & ISR_PHY_LINKDOWN) != 0)
275 value = 1; /* config failed */
276 else
277 value = 0;
278
279 /* clear all interrupt status */
280 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff);
281 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
282 return value;
283 }
284
285 /*
286 * atl2_setup_ring_resources - allocate Tx / RX descriptor resources
287 * @adapter: board private structure
288 *
289 * Return 0 on success, negative on failure
290 */
291 static s32 atl2_setup_ring_resources(struct atl2_adapter *adapter)
292 {
293 struct pci_dev *pdev = adapter->pdev;
294 int size;
295 u8 offset = 0;
296
297 /* real ring DMA buffer */
298 adapter->ring_size = size =
299 adapter->txd_ring_size * 1 + 7 + /* dword align */
300 adapter->txs_ring_size * 4 + 7 + /* dword align */
301 adapter->rxd_ring_size * 1536 + 127; /* 128bytes align */
302
303 adapter->ring_vir_addr = pci_alloc_consistent(pdev, size,
304 &adapter->ring_dma);
305 if (!adapter->ring_vir_addr)
306 return -ENOMEM;
307 memset(adapter->ring_vir_addr, 0, adapter->ring_size);
308
309 /* Init TXD Ring */
310 adapter->txd_dma = adapter->ring_dma ;
311 offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0;
312 adapter->txd_dma += offset;
313 adapter->txd_ring = (struct tx_pkt_header *) (adapter->ring_vir_addr +
314 offset);
315
316 /* Init TXS Ring */
317 adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size;
318 offset = (adapter->txs_dma & 0x7) ? (8 - (adapter->txs_dma & 0x7)) : 0;
319 adapter->txs_dma += offset;
320 adapter->txs_ring = (struct tx_pkt_status *)
321 (((u8 *)adapter->txd_ring) + (adapter->txd_ring_size + offset));
322
323 /* Init RXD Ring */
324 adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size * 4;
325 offset = (adapter->rxd_dma & 127) ?
326 (128 - (adapter->rxd_dma & 127)) : 0;
327 if (offset > 7)
328 offset -= 8;
329 else
330 offset += (128 - 8);
331
332 adapter->rxd_dma += offset;
333 adapter->rxd_ring = (struct rx_desc *) (((u8 *)adapter->txs_ring) +
334 (adapter->txs_ring_size * 4 + offset));
335
336 /*
337 * Read / Write Ptr Initialize:
338 * init_ring_ptrs(adapter);
339 */
340 return 0;
341 }
342
343 /*
344 * atl2_irq_enable - Enable default interrupt generation settings
345 * @adapter: board private structure
346 */
347 static inline void atl2_irq_enable(struct atl2_adapter *adapter)
348 {
349 ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
350 ATL2_WRITE_FLUSH(&adapter->hw);
351 }
352
353 /*
354 * atl2_irq_disable - Mask off interrupt generation on the NIC
355 * @adapter: board private structure
356 */
357 static inline void atl2_irq_disable(struct atl2_adapter *adapter)
358 {
359 ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0);
360 ATL2_WRITE_FLUSH(&adapter->hw);
361 synchronize_irq(adapter->pdev->irq);
362 }
363
364 #ifdef NETIF_F_HW_VLAN_TX
365 static void atl2_vlan_rx_register(struct net_device *netdev,
366 struct vlan_group *grp)
367 {
368 struct atl2_adapter *adapter = netdev_priv(netdev);
369 u32 ctrl;
370
371 atl2_irq_disable(adapter);
372 adapter->vlgrp = grp;
373
374 if (grp) {
375 /* enable VLAN tag insert/strip */
376 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
377 ctrl |= MAC_CTRL_RMV_VLAN;
378 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
379 } else {
380 /* disable VLAN tag insert/strip */
381 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
382 ctrl &= ~MAC_CTRL_RMV_VLAN;
383 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
384 }
385
386 atl2_irq_enable(adapter);
387 }
388
389 static void atl2_restore_vlan(struct atl2_adapter *adapter)
390 {
391 atl2_vlan_rx_register(adapter->netdev, adapter->vlgrp);
392 }
393 #endif
394
395 static void atl2_intr_rx(struct atl2_adapter *adapter)
396 {
397 struct net_device *netdev = adapter->netdev;
398 struct rx_desc *rxd;
399 struct sk_buff *skb;
400
401 do {
402 rxd = adapter->rxd_ring+adapter->rxd_write_ptr;
403 if (!rxd->status.update)
404 break; /* end of tx */
405
406 /* clear this flag at once */
407 rxd->status.update = 0;
408
409 if (rxd->status.ok && rxd->status.pkt_size >= 60) {
410 int rx_size = (int)(rxd->status.pkt_size - 4);
411 /* alloc new buffer */
412 skb = netdev_alloc_skb(netdev, rx_size + NET_IP_ALIGN);
413 if (NULL == skb) {
414 printk(KERN_WARNING
415 "%s: Mem squeeze, deferring packet.\n",
416 netdev->name);
417 /*
418 * Check that some rx space is free. If not,
419 * free one and mark stats->rx_dropped++.
420 */
421 netdev->stats.rx_dropped++;
422 break;
423 }
424 skb_reserve(skb, NET_IP_ALIGN);
425 skb->dev = netdev;
426 memcpy(skb->data, rxd->packet, rx_size);
427 skb_put(skb, rx_size);
428 skb->protocol = eth_type_trans(skb, netdev);
429 #ifdef NETIF_F_HW_VLAN_TX
430 if (adapter->vlgrp && (rxd->status.vlan)) {
431 u16 vlan_tag = (rxd->status.vtag>>4) |
432 ((rxd->status.vtag&7) << 13) |
433 ((rxd->status.vtag&8) << 9);
434 vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag);
435 } else
436 #endif
437 netif_rx(skb);
438 netdev->stats.rx_bytes += rx_size;
439 netdev->stats.rx_packets++;
440 netdev->last_rx = jiffies;
441 } else {
442 netdev->stats.rx_errors++;
443
444 if (rxd->status.ok && rxd->status.pkt_size <= 60)
445 netdev->stats.rx_length_errors++;
446 if (rxd->status.mcast)
447 netdev->stats.multicast++;
448 if (rxd->status.crc)
449 netdev->stats.rx_crc_errors++;
450 if (rxd->status.align)
451 netdev->stats.rx_frame_errors++;
452 }
453
454 /* advance write ptr */
455 if (++adapter->rxd_write_ptr == adapter->rxd_ring_size)
456 adapter->rxd_write_ptr = 0;
457 } while (1);
458
459 /* update mailbox? */
460 adapter->rxd_read_ptr = adapter->rxd_write_ptr;
461 ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr);
462 }
463
464 static void atl2_intr_tx(struct atl2_adapter *adapter)
465 {
466 struct net_device *netdev = adapter->netdev;
467 u32 txd_read_ptr;
468 u32 txs_write_ptr;
469 struct tx_pkt_status *txs;
470 struct tx_pkt_header *txph;
471 int free_hole = 0;
472
473 do {
474 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
475 txs = adapter->txs_ring + txs_write_ptr;
476 if (!txs->update)
477 break; /* tx stop here */
478
479 free_hole = 1;
480 txs->update = 0;
481
482 if (++txs_write_ptr == adapter->txs_ring_size)
483 txs_write_ptr = 0;
484 atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr);
485
486 txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr);
487 txph = (struct tx_pkt_header *)
488 (((u8 *)adapter->txd_ring) + txd_read_ptr);
489
490 if (txph->pkt_size != txs->pkt_size) {
491 struct tx_pkt_status *old_txs = txs;
492 printk(KERN_WARNING
493 "%s: txs packet size not consistent with txd"
494 " txd_:0x%08x, txs_:0x%08x!\n",
495 adapter->netdev->name,
496 *(u32 *)txph, *(u32 *)txs);
497 printk(KERN_WARNING
498 "txd read ptr: 0x%x\n",
499 txd_read_ptr);
500 txs = adapter->txs_ring + txs_write_ptr;
501 printk(KERN_WARNING
502 "txs-behind:0x%08x\n",
503 *(u32 *)txs);
504 if (txs_write_ptr < 2) {
505 txs = adapter->txs_ring +
506 (adapter->txs_ring_size +
507 txs_write_ptr - 2);
508 } else {
509 txs = adapter->txs_ring + (txs_write_ptr - 2);
510 }
511 printk(KERN_WARNING
512 "txs-before:0x%08x\n",
513 *(u32 *)txs);
514 txs = old_txs;
515 }
516
517 /* 4for TPH */
518 txd_read_ptr += (((u32)(txph->pkt_size) + 7) & ~3);
519 if (txd_read_ptr >= adapter->txd_ring_size)
520 txd_read_ptr -= adapter->txd_ring_size;
521
522 atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr);
523
524 /* tx statistics: */
525 if (txs->ok) {
526 netdev->stats.tx_bytes += txs->pkt_size;
527 netdev->stats.tx_packets++;
528 }
529 else
530 netdev->stats.tx_errors++;
531
532 if (txs->defer)
533 netdev->stats.collisions++;
534 if (txs->abort_col)
535 netdev->stats.tx_aborted_errors++;
536 if (txs->late_col)
537 netdev->stats.tx_window_errors++;
538 if (txs->underun)
539 netdev->stats.tx_fifo_errors++;
540 } while (1);
541
542 if (free_hole) {
543 if (netif_queue_stopped(adapter->netdev) &&
544 netif_carrier_ok(adapter->netdev))
545 netif_wake_queue(adapter->netdev);
546 }
547 }
548
549 static void atl2_check_for_link(struct atl2_adapter *adapter)
550 {
551 struct net_device *netdev = adapter->netdev;
552 u16 phy_data = 0;
553
554 spin_lock(&adapter->stats_lock);
555 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
556 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
557 spin_unlock(&adapter->stats_lock);
558
559 /* notify upper layer link down ASAP */
560 if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */
561 if (netif_carrier_ok(netdev)) { /* old link state: Up */
562 printk(KERN_INFO "%s: %s NIC Link is Down\n",
563 atl2_driver_name, netdev->name);
564 adapter->link_speed = SPEED_0;
565 netif_carrier_off(netdev);
566 netif_stop_queue(netdev);
567 }
568 }
569 schedule_work(&adapter->link_chg_task);
570 }
571
572 static inline void atl2_clear_phy_int(struct atl2_adapter *adapter)
573 {
574 u16 phy_data;
575 spin_lock(&adapter->stats_lock);
576 atl2_read_phy_reg(&adapter->hw, 19, &phy_data);
577 spin_unlock(&adapter->stats_lock);
578 }
579
580 /*
581 * atl2_intr - Interrupt Handler
582 * @irq: interrupt number
583 * @data: pointer to a network interface device structure
584 * @pt_regs: CPU registers structure
585 */
586 static irqreturn_t atl2_intr(int irq, void *data)
587 {
588 struct atl2_adapter *adapter = netdev_priv(data);
589 struct atl2_hw *hw = &adapter->hw;
590 u32 status;
591
592 status = ATL2_READ_REG(hw, REG_ISR);
593 if (0 == status)
594 return IRQ_NONE;
595
596 /* link event */
597 if (status & ISR_PHY)
598 atl2_clear_phy_int(adapter);
599
600 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
601 ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
602
603 /* check if PCIE PHY Link down */
604 if (status & ISR_PHY_LINKDOWN) {
605 if (netif_running(adapter->netdev)) { /* reset MAC */
606 ATL2_WRITE_REG(hw, REG_ISR, 0);
607 ATL2_WRITE_REG(hw, REG_IMR, 0);
608 ATL2_WRITE_FLUSH(hw);
609 schedule_work(&adapter->reset_task);
610 return IRQ_HANDLED;
611 }
612 }
613
614 /* check if DMA read/write error? */
615 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
616 ATL2_WRITE_REG(hw, REG_ISR, 0);
617 ATL2_WRITE_REG(hw, REG_IMR, 0);
618 ATL2_WRITE_FLUSH(hw);
619 schedule_work(&adapter->reset_task);
620 return IRQ_HANDLED;
621 }
622
623 /* link event */
624 if (status & (ISR_PHY | ISR_MANUAL)) {
625 adapter->netdev->stats.tx_carrier_errors++;
626 atl2_check_for_link(adapter);
627 }
628
629 /* transmit event */
630 if (status & ISR_TX_EVENT)
631 atl2_intr_tx(adapter);
632
633 /* rx exception */
634 if (status & ISR_RX_EVENT)
635 atl2_intr_rx(adapter);
636
637 /* re-enable Interrupt */
638 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
639 return IRQ_HANDLED;
640 }
641
642 static int atl2_request_irq(struct atl2_adapter *adapter)
643 {
644 struct net_device *netdev = adapter->netdev;
645 int flags, err = 0;
646
647 flags = IRQF_SHARED;
648 #ifdef CONFIG_PCI_MSI
649 adapter->have_msi = true;
650 err = pci_enable_msi(adapter->pdev);
651 if (err)
652 adapter->have_msi = false;
653
654 if (adapter->have_msi)
655 flags &= ~IRQF_SHARED;
656 #endif
657
658 return request_irq(adapter->pdev->irq, &atl2_intr, flags, netdev->name,
659 netdev);
660 }
661
662 /*
663 * atl2_free_ring_resources - Free Tx / RX descriptor Resources
664 * @adapter: board private structure
665 *
666 * Free all transmit software resources
667 */
668 static void atl2_free_ring_resources(struct atl2_adapter *adapter)
669 {
670 struct pci_dev *pdev = adapter->pdev;
671 pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr,
672 adapter->ring_dma);
673 }
674
675 /*
676 * atl2_open - Called when a network interface is made active
677 * @netdev: network interface device structure
678 *
679 * Returns 0 on success, negative value on failure
680 *
681 * The open entry point is called when a network interface is made
682 * active by the system (IFF_UP). At this point all resources needed
683 * for transmit and receive operations are allocated, the interrupt
684 * handler is registered with the OS, the watchdog timer is started,
685 * and the stack is notified that the interface is ready.
686 */
687 static int atl2_open(struct net_device *netdev)
688 {
689 struct atl2_adapter *adapter = netdev_priv(netdev);
690 int err;
691 u32 val;
692
693 /* disallow open during test */
694 if (test_bit(__ATL2_TESTING, &adapter->flags))
695 return -EBUSY;
696
697 /* allocate transmit descriptors */
698 err = atl2_setup_ring_resources(adapter);
699 if (err)
700 return err;
701
702 err = atl2_init_hw(&adapter->hw);
703 if (err) {
704 err = -EIO;
705 goto err_init_hw;
706 }
707
708 /* hardware has been reset, we need to reload some things */
709 atl2_set_multi(netdev);
710 init_ring_ptrs(adapter);
711
712 #ifdef NETIF_F_HW_VLAN_TX
713 atl2_restore_vlan(adapter);
714 #endif
715
716 if (atl2_configure(adapter)) {
717 err = -EIO;
718 goto err_config;
719 }
720
721 err = atl2_request_irq(adapter);
722 if (err)
723 goto err_req_irq;
724
725 clear_bit(__ATL2_DOWN, &adapter->flags);
726
727 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 4*HZ));
728
729 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
730 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
731 val | MASTER_CTRL_MANUAL_INT);
732
733 atl2_irq_enable(adapter);
734
735 return 0;
736
737 err_init_hw:
738 err_req_irq:
739 err_config:
740 atl2_free_ring_resources(adapter);
741 atl2_reset_hw(&adapter->hw);
742
743 return err;
744 }
745
746 static void atl2_down(struct atl2_adapter *adapter)
747 {
748 struct net_device *netdev = adapter->netdev;
749
750 /* signal that we're down so the interrupt handler does not
751 * reschedule our watchdog timer */
752 set_bit(__ATL2_DOWN, &adapter->flags);
753
754 netif_tx_disable(netdev);
755
756 /* reset MAC to disable all RX/TX */
757 atl2_reset_hw(&adapter->hw);
758 msleep(1);
759
760 atl2_irq_disable(adapter);
761
762 del_timer_sync(&adapter->watchdog_timer);
763 del_timer_sync(&adapter->phy_config_timer);
764 clear_bit(0, &adapter->cfg_phy);
765
766 netif_carrier_off(netdev);
767 adapter->link_speed = SPEED_0;
768 adapter->link_duplex = -1;
769 }
770
771 static void atl2_free_irq(struct atl2_adapter *adapter)
772 {
773 struct net_device *netdev = adapter->netdev;
774
775 free_irq(adapter->pdev->irq, netdev);
776
777 #ifdef CONFIG_PCI_MSI
778 if (adapter->have_msi)
779 pci_disable_msi(adapter->pdev);
780 #endif
781 }
782
783 /*
784 * atl2_close - Disables a network interface
785 * @netdev: network interface device structure
786 *
787 * Returns 0, this is not allowed to fail
788 *
789 * The close entry point is called when an interface is de-activated
790 * by the OS. The hardware is still under the drivers control, but
791 * needs to be disabled. A global MAC reset is issued to stop the
792 * hardware, and all transmit and receive resources are freed.
793 */
794 static int atl2_close(struct net_device *netdev)
795 {
796 struct atl2_adapter *adapter = netdev_priv(netdev);
797
798 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
799
800 atl2_down(adapter);
801 atl2_free_irq(adapter);
802 atl2_free_ring_resources(adapter);
803
804 return 0;
805 }
806
807 static inline int TxsFreeUnit(struct atl2_adapter *adapter)
808 {
809 u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
810
811 return (adapter->txs_next_clear >= txs_write_ptr) ?
812 (int) (adapter->txs_ring_size - adapter->txs_next_clear +
813 txs_write_ptr - 1) :
814 (int) (txs_write_ptr - adapter->txs_next_clear - 1);
815 }
816
817 static inline int TxdFreeBytes(struct atl2_adapter *adapter)
818 {
819 u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr);
820
821 return (adapter->txd_write_ptr >= txd_read_ptr) ?
822 (int) (adapter->txd_ring_size - adapter->txd_write_ptr +
823 txd_read_ptr - 1) :
824 (int) (txd_read_ptr - adapter->txd_write_ptr - 1);
825 }
826
827 static int atl2_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
828 {
829 struct atl2_adapter *adapter = netdev_priv(netdev);
830 struct tx_pkt_header *txph;
831 u32 offset, copy_len;
832 int txs_unused;
833 int txbuf_unused;
834
835 if (test_bit(__ATL2_DOWN, &adapter->flags)) {
836 dev_kfree_skb_any(skb);
837 return NETDEV_TX_OK;
838 }
839
840 if (unlikely(skb->len <= 0)) {
841 dev_kfree_skb_any(skb);
842 return NETDEV_TX_OK;
843 }
844
845 txs_unused = TxsFreeUnit(adapter);
846 txbuf_unused = TxdFreeBytes(adapter);
847
848 if (skb->len + sizeof(struct tx_pkt_header) + 4 > txbuf_unused ||
849 txs_unused < 1) {
850 /* not enough resources */
851 netif_stop_queue(netdev);
852 return NETDEV_TX_BUSY;
853 }
854
855 offset = adapter->txd_write_ptr;
856
857 txph = (struct tx_pkt_header *) (((u8 *)adapter->txd_ring) + offset);
858
859 *(u32 *)txph = 0;
860 txph->pkt_size = skb->len;
861
862 offset += 4;
863 if (offset >= adapter->txd_ring_size)
864 offset -= adapter->txd_ring_size;
865 copy_len = adapter->txd_ring_size - offset;
866 if (copy_len >= skb->len) {
867 memcpy(((u8 *)adapter->txd_ring) + offset, skb->data, skb->len);
868 offset += ((u32)(skb->len + 3) & ~3);
869 } else {
870 memcpy(((u8 *)adapter->txd_ring)+offset, skb->data, copy_len);
871 memcpy((u8 *)adapter->txd_ring, skb->data+copy_len,
872 skb->len-copy_len);
873 offset = ((u32)(skb->len-copy_len + 3) & ~3);
874 }
875 #ifdef NETIF_F_HW_VLAN_TX
876 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
877 u16 vlan_tag = vlan_tx_tag_get(skb);
878 vlan_tag = (vlan_tag << 4) |
879 (vlan_tag >> 13) |
880 ((vlan_tag >> 9) & 0x8);
881 txph->ins_vlan = 1;
882 txph->vlan = vlan_tag;
883 }
884 #endif
885 if (offset >= adapter->txd_ring_size)
886 offset -= adapter->txd_ring_size;
887 adapter->txd_write_ptr = offset;
888
889 /* clear txs before send */
890 adapter->txs_ring[adapter->txs_next_clear].update = 0;
891 if (++adapter->txs_next_clear == adapter->txs_ring_size)
892 adapter->txs_next_clear = 0;
893
894 ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX,
895 (adapter->txd_write_ptr >> 2));
896
897 mmiowb();
898 netdev->trans_start = jiffies;
899 dev_kfree_skb_any(skb);
900 return NETDEV_TX_OK;
901 }
902
903 /*
904 * atl2_change_mtu - Change the Maximum Transfer Unit
905 * @netdev: network interface device structure
906 * @new_mtu: new value for maximum frame size
907 *
908 * Returns 0 on success, negative on failure
909 */
910 static int atl2_change_mtu(struct net_device *netdev, int new_mtu)
911 {
912 struct atl2_adapter *adapter = netdev_priv(netdev);
913 struct atl2_hw *hw = &adapter->hw;
914
915 if ((new_mtu < 40) || (new_mtu > (ETH_DATA_LEN + VLAN_SIZE)))
916 return -EINVAL;
917
918 /* set MTU */
919 if (hw->max_frame_size != new_mtu) {
920 netdev->mtu = new_mtu;
921 ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ENET_HEADER_SIZE +
922 VLAN_SIZE + ETHERNET_FCS_SIZE);
923 }
924
925 return 0;
926 }
927
928 /*
929 * atl2_set_mac - Change the Ethernet Address of the NIC
930 * @netdev: network interface device structure
931 * @p: pointer to an address structure
932 *
933 * Returns 0 on success, negative on failure
934 */
935 static int atl2_set_mac(struct net_device *netdev, void *p)
936 {
937 struct atl2_adapter *adapter = netdev_priv(netdev);
938 struct sockaddr *addr = p;
939
940 if (!is_valid_ether_addr(addr->sa_data))
941 return -EADDRNOTAVAIL;
942
943 if (netif_running(netdev))
944 return -EBUSY;
945
946 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
947 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
948
949 atl2_set_mac_addr(&adapter->hw);
950
951 return 0;
952 }
953
954 /*
955 * atl2_mii_ioctl -
956 * @netdev:
957 * @ifreq:
958 * @cmd:
959 */
960 static int atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
961 {
962 struct atl2_adapter *adapter = netdev_priv(netdev);
963 struct mii_ioctl_data *data = if_mii(ifr);
964 unsigned long flags;
965
966 switch (cmd) {
967 case SIOCGMIIPHY:
968 data->phy_id = 0;
969 break;
970 case SIOCGMIIREG:
971 if (!capable(CAP_NET_ADMIN))
972 return -EPERM;
973 spin_lock_irqsave(&adapter->stats_lock, flags);
974 if (atl2_read_phy_reg(&adapter->hw,
975 data->reg_num & 0x1F, &data->val_out)) {
976 spin_unlock_irqrestore(&adapter->stats_lock, flags);
977 return -EIO;
978 }
979 spin_unlock_irqrestore(&adapter->stats_lock, flags);
980 break;
981 case SIOCSMIIREG:
982 if (!capable(CAP_NET_ADMIN))
983 return -EPERM;
984 if (data->reg_num & ~(0x1F))
985 return -EFAULT;
986 spin_lock_irqsave(&adapter->stats_lock, flags);
987 if (atl2_write_phy_reg(&adapter->hw, data->reg_num,
988 data->val_in)) {
989 spin_unlock_irqrestore(&adapter->stats_lock, flags);
990 return -EIO;
991 }
992 spin_unlock_irqrestore(&adapter->stats_lock, flags);
993 break;
994 default:
995 return -EOPNOTSUPP;
996 }
997 return 0;
998 }
999
1000 /*
1001 * atl2_ioctl -
1002 * @netdev:
1003 * @ifreq:
1004 * @cmd:
1005 */
1006 static int atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1007 {
1008 switch (cmd) {
1009 case SIOCGMIIPHY:
1010 case SIOCGMIIREG:
1011 case SIOCSMIIREG:
1012 return atl2_mii_ioctl(netdev, ifr, cmd);
1013 #ifdef ETHTOOL_OPS_COMPAT
1014 case SIOCETHTOOL:
1015 return ethtool_ioctl(ifr);
1016 #endif
1017 default:
1018 return -EOPNOTSUPP;
1019 }
1020 }
1021
1022 /*
1023 * atl2_tx_timeout - Respond to a Tx Hang
1024 * @netdev: network interface device structure
1025 */
1026 static void atl2_tx_timeout(struct net_device *netdev)
1027 {
1028 struct atl2_adapter *adapter = netdev_priv(netdev);
1029
1030 /* Do the reset outside of interrupt context */
1031 schedule_work(&adapter->reset_task);
1032 }
1033
1034 /*
1035 * atl2_watchdog - Timer Call-back
1036 * @data: pointer to netdev cast into an unsigned long
1037 */
1038 static void atl2_watchdog(unsigned long data)
1039 {
1040 struct atl2_adapter *adapter = (struct atl2_adapter *) data;
1041
1042 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
1043 u32 drop_rxd, drop_rxs;
1044 unsigned long flags;
1045
1046 spin_lock_irqsave(&adapter->stats_lock, flags);
1047 drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV);
1048 drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV);
1049 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1050
1051 adapter->netdev->stats.rx_over_errors += drop_rxd + drop_rxs;
1052
1053 /* Reset the timer */
1054 mod_timer(&adapter->watchdog_timer,
1055 round_jiffies(jiffies + 4 * HZ));
1056 }
1057 }
1058
1059 /*
1060 * atl2_phy_config - Timer Call-back
1061 * @data: pointer to netdev cast into an unsigned long
1062 */
1063 static void atl2_phy_config(unsigned long data)
1064 {
1065 struct atl2_adapter *adapter = (struct atl2_adapter *) data;
1066 struct atl2_hw *hw = &adapter->hw;
1067 unsigned long flags;
1068
1069 spin_lock_irqsave(&adapter->stats_lock, flags);
1070 atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
1071 atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN |
1072 MII_CR_RESTART_AUTO_NEG);
1073 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1074 clear_bit(0, &adapter->cfg_phy);
1075 }
1076
1077 static int atl2_up(struct atl2_adapter *adapter)
1078 {
1079 struct net_device *netdev = adapter->netdev;
1080 int err = 0;
1081 u32 val;
1082
1083 /* hardware has been reset, we need to reload some things */
1084
1085 err = atl2_init_hw(&adapter->hw);
1086 if (err) {
1087 err = -EIO;
1088 return err;
1089 }
1090
1091 atl2_set_multi(netdev);
1092 init_ring_ptrs(adapter);
1093
1094 #ifdef NETIF_F_HW_VLAN_TX
1095 atl2_restore_vlan(adapter);
1096 #endif
1097
1098 if (atl2_configure(adapter)) {
1099 err = -EIO;
1100 goto err_up;
1101 }
1102
1103 clear_bit(__ATL2_DOWN, &adapter->flags);
1104
1105 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
1106 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val |
1107 MASTER_CTRL_MANUAL_INT);
1108
1109 atl2_irq_enable(adapter);
1110
1111 err_up:
1112 return err;
1113 }
1114
1115 static void atl2_reinit_locked(struct atl2_adapter *adapter)
1116 {
1117 WARN_ON(in_interrupt());
1118 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1119 msleep(1);
1120 atl2_down(adapter);
1121 atl2_up(adapter);
1122 clear_bit(__ATL2_RESETTING, &adapter->flags);
1123 }
1124
1125 static void atl2_reset_task(struct work_struct *work)
1126 {
1127 struct atl2_adapter *adapter;
1128 adapter = container_of(work, struct atl2_adapter, reset_task);
1129
1130 atl2_reinit_locked(adapter);
1131 }
1132
1133 static void atl2_setup_mac_ctrl(struct atl2_adapter *adapter)
1134 {
1135 u32 value;
1136 struct atl2_hw *hw = &adapter->hw;
1137 struct net_device *netdev = adapter->netdev;
1138
1139 /* Config MAC CTRL Register */
1140 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1141
1142 /* duplex */
1143 if (FULL_DUPLEX == adapter->link_duplex)
1144 value |= MAC_CTRL_DUPLX;
1145
1146 /* flow control */
1147 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1148
1149 /* PAD & CRC */
1150 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1151
1152 /* preamble length */
1153 value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) <<
1154 MAC_CTRL_PRMLEN_SHIFT);
1155
1156 /* vlan */
1157 if (adapter->vlgrp)
1158 value |= MAC_CTRL_RMV_VLAN;
1159
1160 /* filter mode */
1161 value |= MAC_CTRL_BC_EN;
1162 if (netdev->flags & IFF_PROMISC)
1163 value |= MAC_CTRL_PROMIS_EN;
1164 else if (netdev->flags & IFF_ALLMULTI)
1165 value |= MAC_CTRL_MC_ALL_EN;
1166
1167 /* half retry buffer */
1168 value |= (((u32)(adapter->hw.retry_buf &
1169 MAC_CTRL_HALF_LEFT_BUF_MASK)) << MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1170
1171 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1172 }
1173
1174 static int atl2_check_link(struct atl2_adapter *adapter)
1175 {
1176 struct atl2_hw *hw = &adapter->hw;
1177 struct net_device *netdev = adapter->netdev;
1178 int ret_val;
1179 u16 speed, duplex, phy_data;
1180 int reconfig = 0;
1181
1182 /* MII_BMSR must read twise */
1183 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1184 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1185 if (!(phy_data&BMSR_LSTATUS)) { /* link down */
1186 if (netif_carrier_ok(netdev)) { /* old link state: Up */
1187 u32 value;
1188 /* disable rx */
1189 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1190 value &= ~MAC_CTRL_RX_EN;
1191 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1192 adapter->link_speed = SPEED_0;
1193 netif_carrier_off(netdev);
1194 netif_stop_queue(netdev);
1195 }
1196 return 0;
1197 }
1198
1199 /* Link Up */
1200 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1201 if (ret_val)
1202 return ret_val;
1203 switch (hw->MediaType) {
1204 case MEDIA_TYPE_100M_FULL:
1205 if (speed != SPEED_100 || duplex != FULL_DUPLEX)
1206 reconfig = 1;
1207 break;
1208 case MEDIA_TYPE_100M_HALF:
1209 if (speed != SPEED_100 || duplex != HALF_DUPLEX)
1210 reconfig = 1;
1211 break;
1212 case MEDIA_TYPE_10M_FULL:
1213 if (speed != SPEED_10 || duplex != FULL_DUPLEX)
1214 reconfig = 1;
1215 break;
1216 case MEDIA_TYPE_10M_HALF:
1217 if (speed != SPEED_10 || duplex != HALF_DUPLEX)
1218 reconfig = 1;
1219 break;
1220 }
1221 /* link result is our setting */
1222 if (reconfig == 0) {
1223 if (adapter->link_speed != speed ||
1224 adapter->link_duplex != duplex) {
1225 adapter->link_speed = speed;
1226 adapter->link_duplex = duplex;
1227 atl2_setup_mac_ctrl(adapter);
1228 printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n",
1229 atl2_driver_name, netdev->name,
1230 adapter->link_speed,
1231 adapter->link_duplex == FULL_DUPLEX ?
1232 "Full Duplex" : "Half Duplex");
1233 }
1234
1235 if (!netif_carrier_ok(netdev)) { /* Link down -> Up */
1236 netif_carrier_on(netdev);
1237 netif_wake_queue(netdev);
1238 }
1239 return 0;
1240 }
1241
1242 /* change original link status */
1243 if (netif_carrier_ok(netdev)) {
1244 u32 value;
1245 /* disable rx */
1246 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1247 value &= ~MAC_CTRL_RX_EN;
1248 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1249
1250 adapter->link_speed = SPEED_0;
1251 netif_carrier_off(netdev);
1252 netif_stop_queue(netdev);
1253 }
1254
1255 /* auto-neg, insert timer to re-config phy
1256 * (if interval smaller than 5 seconds, something strange) */
1257 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
1258 if (!test_and_set_bit(0, &adapter->cfg_phy))
1259 mod_timer(&adapter->phy_config_timer,
1260 round_jiffies(jiffies + 5 * HZ));
1261 }
1262
1263 return 0;
1264 }
1265
1266 /*
1267 * atl2_link_chg_task - deal with link change event Out of interrupt context
1268 * @netdev: network interface device structure
1269 */
1270 static void atl2_link_chg_task(struct work_struct *work)
1271 {
1272 struct atl2_adapter *adapter;
1273 unsigned long flags;
1274
1275 adapter = container_of(work, struct atl2_adapter, link_chg_task);
1276
1277 spin_lock_irqsave(&adapter->stats_lock, flags);
1278 atl2_check_link(adapter);
1279 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1280 }
1281
1282 static void atl2_setup_pcicmd(struct pci_dev *pdev)
1283 {
1284 u16 cmd;
1285
1286 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1287
1288 if (cmd & PCI_COMMAND_INTX_DISABLE)
1289 cmd &= ~PCI_COMMAND_INTX_DISABLE;
1290 if (cmd & PCI_COMMAND_IO)
1291 cmd &= ~PCI_COMMAND_IO;
1292 if (0 == (cmd & PCI_COMMAND_MEMORY))
1293 cmd |= PCI_COMMAND_MEMORY;
1294 if (0 == (cmd & PCI_COMMAND_MASTER))
1295 cmd |= PCI_COMMAND_MASTER;
1296 pci_write_config_word(pdev, PCI_COMMAND, cmd);
1297
1298 /*
1299 * some motherboards BIOS(PXE/EFI) driver may set PME
1300 * while they transfer control to OS (Windows/Linux)
1301 * so we should clear this bit before NIC work normally
1302 */
1303 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0);
1304 }
1305
1306 #ifdef CONFIG_NET_POLL_CONTROLLER
1307 static void atl2_poll_controller(struct net_device *netdev)
1308 {
1309 disable_irq(netdev->irq);
1310 atl2_intr(netdev->irq, netdev);
1311 enable_irq(netdev->irq);
1312 }
1313 #endif
1314
1315 /*
1316 * atl2_probe - Device Initialization Routine
1317 * @pdev: PCI device information struct
1318 * @ent: entry in atl2_pci_tbl
1319 *
1320 * Returns 0 on success, negative on failure
1321 *
1322 * atl2_probe initializes an adapter identified by a pci_dev structure.
1323 * The OS initialization, configuring of the adapter private structure,
1324 * and a hardware reset occur.
1325 */
1326 static int __devinit atl2_probe(struct pci_dev *pdev,
1327 const struct pci_device_id *ent)
1328 {
1329 struct net_device *netdev;
1330 struct atl2_adapter *adapter;
1331 static int cards_found;
1332 unsigned long mmio_start;
1333 int mmio_len;
1334 int err;
1335
1336 cards_found = 0;
1337
1338 err = pci_enable_device(pdev);
1339 if (err)
1340 return err;
1341
1342 /*
1343 * atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA
1344 * until the kernel has the proper infrastructure to support 64-bit DMA
1345 * on these devices.
1346 */
1347 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) &&
1348 pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
1349 printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n");
1350 goto err_dma;
1351 }
1352
1353 /* Mark all PCI regions associated with PCI device
1354 * pdev as being reserved by owner atl2_driver_name */
1355 err = pci_request_regions(pdev, atl2_driver_name);
1356 if (err)
1357 goto err_pci_reg;
1358
1359 /* Enables bus-mastering on the device and calls
1360 * pcibios_set_master to do the needed arch specific settings */
1361 pci_set_master(pdev);
1362
1363 err = -ENOMEM;
1364 netdev = alloc_etherdev(sizeof(struct atl2_adapter));
1365 if (!netdev)
1366 goto err_alloc_etherdev;
1367
1368 SET_NETDEV_DEV(netdev, &pdev->dev);
1369
1370 pci_set_drvdata(pdev, netdev);
1371 adapter = netdev_priv(netdev);
1372 adapter->netdev = netdev;
1373 adapter->pdev = pdev;
1374 adapter->hw.back = adapter;
1375
1376 mmio_start = pci_resource_start(pdev, 0x0);
1377 mmio_len = pci_resource_len(pdev, 0x0);
1378
1379 adapter->hw.mem_rang = (u32)mmio_len;
1380 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1381 if (!adapter->hw.hw_addr) {
1382 err = -EIO;
1383 goto err_ioremap;
1384 }
1385
1386 atl2_setup_pcicmd(pdev);
1387
1388 netdev->open = &atl2_open;
1389 netdev->stop = &atl2_close;
1390 netdev->hard_start_xmit = &atl2_xmit_frame;
1391 netdev->set_multicast_list = &atl2_set_multi;
1392 netdev->set_mac_address = &atl2_set_mac;
1393 netdev->change_mtu = &atl2_change_mtu;
1394 netdev->do_ioctl = &atl2_ioctl;
1395 atl2_set_ethtool_ops(netdev);
1396
1397 #ifdef CONFIG_NET_POLL_CONTROLLER
1398 netdev->poll_controller = atl2_poll_controller;
1399 #endif
1400 #ifdef HAVE_TX_TIMEOUT
1401 netdev->tx_timeout = &atl2_tx_timeout;
1402 netdev->watchdog_timeo = 5 * HZ;
1403 #endif
1404 #ifdef NETIF_F_HW_VLAN_TX
1405 netdev->vlan_rx_register = atl2_vlan_rx_register;
1406 #endif
1407 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1408
1409 netdev->mem_start = mmio_start;
1410 netdev->mem_end = mmio_start + mmio_len;
1411 adapter->bd_number = cards_found;
1412 adapter->pci_using_64 = false;
1413
1414 /* setup the private structure */
1415 err = atl2_sw_init(adapter);
1416 if (err)
1417 goto err_sw_init;
1418
1419 err = -EIO;
1420
1421 #ifdef NETIF_F_HW_VLAN_TX
1422 netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
1423 #endif
1424
1425 /* Init PHY as early as possible due to power saving issue */
1426 atl2_phy_init(&adapter->hw);
1427
1428 /* reset the controller to
1429 * put the device in a known good starting state */
1430
1431 if (atl2_reset_hw(&adapter->hw)) {
1432 err = -EIO;
1433 goto err_reset;
1434 }
1435
1436 /* copy the MAC address out of the EEPROM */
1437 atl2_read_mac_addr(&adapter->hw);
1438 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
1439 /* FIXME: do we still need this? */
1440 #ifdef ETHTOOL_GPERMADDR
1441 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1442
1443 if (!is_valid_ether_addr(netdev->perm_addr)) {
1444 #else
1445 if (!is_valid_ether_addr(netdev->dev_addr)) {
1446 #endif
1447 err = -EIO;
1448 goto err_eeprom;
1449 }
1450
1451 atl2_check_options(adapter);
1452
1453 init_timer(&adapter->watchdog_timer);
1454 adapter->watchdog_timer.function = &atl2_watchdog;
1455 adapter->watchdog_timer.data = (unsigned long) adapter;
1456
1457 init_timer(&adapter->phy_config_timer);
1458 adapter->phy_config_timer.function = &atl2_phy_config;
1459 adapter->phy_config_timer.data = (unsigned long) adapter;
1460
1461 INIT_WORK(&adapter->reset_task, atl2_reset_task);
1462 INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task);
1463
1464 strcpy(netdev->name, "eth%d"); /* ?? */
1465 err = register_netdev(netdev);
1466 if (err)
1467 goto err_register;
1468
1469 /* assume we have no link for now */
1470 netif_carrier_off(netdev);
1471 netif_stop_queue(netdev);
1472
1473 cards_found++;
1474
1475 return 0;
1476
1477 err_reset:
1478 err_register:
1479 err_sw_init:
1480 err_eeprom:
1481 iounmap(adapter->hw.hw_addr);
1482 err_ioremap:
1483 free_netdev(netdev);
1484 err_alloc_etherdev:
1485 pci_release_regions(pdev);
1486 err_pci_reg:
1487 err_dma:
1488 pci_disable_device(pdev);
1489 return err;
1490 }
1491
1492 /*
1493 * atl2_remove - Device Removal Routine
1494 * @pdev: PCI device information struct
1495 *
1496 * atl2_remove is called by the PCI subsystem to alert the driver
1497 * that it should release a PCI device. The could be caused by a
1498 * Hot-Plug event, or because the driver is going to be removed from
1499 * memory.
1500 */
1501 /* FIXME: write the original MAC address back in case it was changed from a
1502 * BIOS-set value, as in atl1 -- CHS */
1503 static void __devexit atl2_remove(struct pci_dev *pdev)
1504 {
1505 struct net_device *netdev = pci_get_drvdata(pdev);
1506 struct atl2_adapter *adapter = netdev_priv(netdev);
1507
1508 /* flush_scheduled work may reschedule our watchdog task, so
1509 * explicitly disable watchdog tasks from being rescheduled */
1510 set_bit(__ATL2_DOWN, &adapter->flags);
1511
1512 del_timer_sync(&adapter->watchdog_timer);
1513 del_timer_sync(&adapter->phy_config_timer);
1514
1515 flush_scheduled_work();
1516
1517 unregister_netdev(netdev);
1518
1519 atl2_force_ps(&adapter->hw);
1520
1521 iounmap(adapter->hw.hw_addr);
1522 pci_release_regions(pdev);
1523
1524 free_netdev(netdev);
1525
1526 pci_disable_device(pdev);
1527 }
1528
1529 static int atl2_suspend(struct pci_dev *pdev, pm_message_t state)
1530 {
1531 struct net_device *netdev = pci_get_drvdata(pdev);
1532 struct atl2_adapter *adapter = netdev_priv(netdev);
1533 struct atl2_hw *hw = &adapter->hw;
1534 u16 speed, duplex;
1535 u32 ctrl = 0;
1536 u32 wufc = adapter->wol;
1537
1538 #ifdef CONFIG_PM
1539 int retval = 0;
1540 #endif
1541
1542 netif_device_detach(netdev);
1543
1544 if (netif_running(netdev)) {
1545 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
1546 atl2_down(adapter);
1547 }
1548
1549 #ifdef CONFIG_PM
1550 retval = pci_save_state(pdev);
1551 if (retval)
1552 return retval;
1553 #endif
1554
1555 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1556 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1557 if (ctrl & BMSR_LSTATUS)
1558 wufc &= ~ATLX_WUFC_LNKC;
1559
1560 if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) {
1561 u32 ret_val;
1562 /* get current link speed & duplex */
1563 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1564 if (ret_val) {
1565 printk(KERN_DEBUG
1566 "%s: get speed&duplex error while suspend\n",
1567 atl2_driver_name);
1568 goto wol_dis;
1569 }
1570
1571 ctrl = 0;
1572
1573 /* turn on magic packet wol */
1574 if (wufc & ATLX_WUFC_MAG)
1575 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);
1576
1577 /* ignore Link Chg event when Link is up */
1578 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1579
1580 /* Config MAC CTRL Register */
1581 ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1582 if (FULL_DUPLEX == adapter->link_duplex)
1583 ctrl |= MAC_CTRL_DUPLX;
1584 ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1585 ctrl |= (((u32)adapter->hw.preamble_len &
1586 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1587 ctrl |= (((u32)(adapter->hw.retry_buf &
1588 MAC_CTRL_HALF_LEFT_BUF_MASK)) <<
1589 MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1590 if (wufc & ATLX_WUFC_MAG) {
1591 /* magic packet maybe Broadcast&multicast&Unicast */
1592 ctrl |= MAC_CTRL_BC_EN;
1593 }
1594
1595 ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl);
1596
1597 /* pcie patch */
1598 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1599 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1600 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1601 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1602 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1603 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1604
1605 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1606 goto suspend_exit;
1607 }
1608
1609 if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATLX_WUFC_LNKC)) {
1610 /* link is down, so only LINK CHG WOL event enable */
1611 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
1612 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1613 ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0);
1614
1615 /* pcie patch */
1616 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1617 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1618 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1619 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1620 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1621 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1622
1623 hw->phy_configured = false; /* re-init PHY when resume */
1624
1625 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1626
1627 goto suspend_exit;
1628 }
1629
1630 wol_dis:
1631 /* WOL disabled */
1632 ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0);
1633
1634 /* pcie patch */
1635 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1636 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1637 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1638 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1639 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1640 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1641
1642 atl2_force_ps(hw);
1643 hw->phy_configured = false; /* re-init PHY when resume */
1644
1645 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1646
1647 suspend_exit:
1648 if (netif_running(netdev))
1649 atl2_free_irq(adapter);
1650
1651 pci_disable_device(pdev);
1652
1653 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1654
1655 return 0;
1656 }
1657
1658 #ifdef CONFIG_PM
1659 static int atl2_resume(struct pci_dev *pdev)
1660 {
1661 struct net_device *netdev = pci_get_drvdata(pdev);
1662 struct atl2_adapter *adapter = netdev_priv(netdev);
1663 u32 err;
1664
1665 pci_set_power_state(pdev, PCI_D0);
1666 pci_restore_state(pdev);
1667
1668 err = pci_enable_device(pdev);
1669 if (err) {
1670 printk(KERN_ERR
1671 "atl2: Cannot enable PCI device from suspend\n");
1672 return err;
1673 }
1674
1675 pci_set_master(pdev);
1676
1677 ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */
1678
1679 pci_enable_wake(pdev, PCI_D3hot, 0);
1680 pci_enable_wake(pdev, PCI_D3cold, 0);
1681
1682 ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
1683
1684 err = atl2_request_irq(adapter);
1685 if (netif_running(netdev) && err)
1686 return err;
1687
1688 atl2_reset_hw(&adapter->hw);
1689
1690 if (netif_running(netdev))
1691 atl2_up(adapter);
1692
1693 netif_device_attach(netdev);
1694
1695 return 0;
1696 }
1697 #endif
1698
1699 static void atl2_shutdown(struct pci_dev *pdev)
1700 {
1701 atl2_suspend(pdev, PMSG_SUSPEND);
1702 }
1703
1704 static struct pci_driver atl2_driver = {
1705 .name = atl2_driver_name,
1706 .id_table = atl2_pci_tbl,
1707 .probe = atl2_probe,
1708 .remove = __devexit_p(atl2_remove),
1709 /* Power Managment Hooks */
1710 .suspend = atl2_suspend,
1711 #ifdef CONFIG_PM
1712 .resume = atl2_resume,
1713 #endif
1714 .shutdown = atl2_shutdown,
1715 };
1716
1717 /*
1718 * atl2_init_module - Driver Registration Routine
1719 *
1720 * atl2_init_module is the first routine called when the driver is
1721 * loaded. All it does is register with the PCI subsystem.
1722 */
1723 static int __init atl2_init_module(void)
1724 {
1725 printk(KERN_INFO "%s - version %s\n", atl2_driver_string,
1726 atl2_driver_version);
1727 printk(KERN_INFO "%s\n", atl2_copyright);
1728 return pci_register_driver(&atl2_driver);
1729 }
1730 module_init(atl2_init_module);
1731
1732 /*
1733 * atl2_exit_module - Driver Exit Cleanup Routine
1734 *
1735 * atl2_exit_module is called just before the driver is removed
1736 * from memory.
1737 */
1738 static void __exit atl2_exit_module(void)
1739 {
1740 pci_unregister_driver(&atl2_driver);
1741 }
1742 module_exit(atl2_exit_module);
1743
1744 static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1745 {
1746 struct atl2_adapter *adapter = hw->back;
1747 pci_read_config_word(adapter->pdev, reg, value);
1748 }
1749
1750 static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1751 {
1752 struct atl2_adapter *adapter = hw->back;
1753 pci_write_config_word(adapter->pdev, reg, *value);
1754 }
1755
1756 static int atl2_get_settings(struct net_device *netdev,
1757 struct ethtool_cmd *ecmd)
1758 {
1759 struct atl2_adapter *adapter = netdev_priv(netdev);
1760 struct atl2_hw *hw = &adapter->hw;
1761
1762 ecmd->supported = (SUPPORTED_10baseT_Half |
1763 SUPPORTED_10baseT_Full |
1764 SUPPORTED_100baseT_Half |
1765 SUPPORTED_100baseT_Full |
1766 SUPPORTED_Autoneg |
1767 SUPPORTED_TP);
1768 ecmd->advertising = ADVERTISED_TP;
1769
1770 ecmd->advertising |= ADVERTISED_Autoneg;
1771 ecmd->advertising |= hw->autoneg_advertised;
1772
1773 ecmd->port = PORT_TP;
1774 ecmd->phy_address = 0;
1775 ecmd->transceiver = XCVR_INTERNAL;
1776
1777 if (adapter->link_speed != SPEED_0) {
1778 ecmd->speed = adapter->link_speed;
1779 if (adapter->link_duplex == FULL_DUPLEX)
1780 ecmd->duplex = DUPLEX_FULL;
1781 else
1782 ecmd->duplex = DUPLEX_HALF;
1783 } else {
1784 ecmd->speed = -1;
1785 ecmd->duplex = -1;
1786 }
1787
1788 ecmd->autoneg = AUTONEG_ENABLE;
1789 return 0;
1790 }
1791
1792 static int atl2_set_settings(struct net_device *netdev,
1793 struct ethtool_cmd *ecmd)
1794 {
1795 struct atl2_adapter *adapter = netdev_priv(netdev);
1796 struct atl2_hw *hw = &adapter->hw;
1797
1798 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1799 msleep(1);
1800
1801 if (ecmd->autoneg == AUTONEG_ENABLE) {
1802 #define MY_ADV_MASK (ADVERTISE_10_HALF | \
1803 ADVERTISE_10_FULL | \
1804 ADVERTISE_100_HALF| \
1805 ADVERTISE_100_FULL)
1806
1807 if ((ecmd->advertising & MY_ADV_MASK) == MY_ADV_MASK) {
1808 hw->MediaType = MEDIA_TYPE_AUTO_SENSOR;
1809 hw->autoneg_advertised = MY_ADV_MASK;
1810 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1811 ADVERTISE_100_FULL) {
1812 hw->MediaType = MEDIA_TYPE_100M_FULL;
1813 hw->autoneg_advertised = ADVERTISE_100_FULL;
1814 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1815 ADVERTISE_100_HALF) {
1816 hw->MediaType = MEDIA_TYPE_100M_HALF;
1817 hw->autoneg_advertised = ADVERTISE_100_HALF;
1818 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1819 ADVERTISE_10_FULL) {
1820 hw->MediaType = MEDIA_TYPE_10M_FULL;
1821 hw->autoneg_advertised = ADVERTISE_10_FULL;
1822 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1823 ADVERTISE_10_HALF) {
1824 hw->MediaType = MEDIA_TYPE_10M_HALF;
1825 hw->autoneg_advertised = ADVERTISE_10_HALF;
1826 } else {
1827 clear_bit(__ATL2_RESETTING, &adapter->flags);
1828 return -EINVAL;
1829 }
1830 ecmd->advertising = hw->autoneg_advertised |
1831 ADVERTISED_TP | ADVERTISED_Autoneg;
1832 } else {
1833 clear_bit(__ATL2_RESETTING, &adapter->flags);
1834 return -EINVAL;
1835 }
1836
1837 /* reset the link */
1838 if (netif_running(adapter->netdev)) {
1839 atl2_down(adapter);
1840 atl2_up(adapter);
1841 } else
1842 atl2_reset_hw(&adapter->hw);
1843
1844 clear_bit(__ATL2_RESETTING, &adapter->flags);
1845 return 0;
1846 }
1847
1848 static u32 atl2_get_tx_csum(struct net_device *netdev)
1849 {
1850 return (netdev->features & NETIF_F_HW_CSUM) != 0;
1851 }
1852
1853 static u32 atl2_get_msglevel(struct net_device *netdev)
1854 {
1855 return 0;
1856 }
1857
1858 /*
1859 * It's sane for this to be empty, but we might want to take advantage of this.
1860 */
1861 static void atl2_set_msglevel(struct net_device *netdev, u32 data)
1862 {
1863 }
1864
1865 static int atl2_get_regs_len(struct net_device *netdev)
1866 {
1867 #define ATL2_REGS_LEN 42
1868 return sizeof(u32) * ATL2_REGS_LEN;
1869 }
1870
1871 static void atl2_get_regs(struct net_device *netdev,
1872 struct ethtool_regs *regs, void *p)
1873 {
1874 struct atl2_adapter *adapter = netdev_priv(netdev);
1875 struct atl2_hw *hw = &adapter->hw;
1876 u32 *regs_buff = p;
1877 u16 phy_data;
1878
1879 memset(p, 0, sizeof(u32) * ATL2_REGS_LEN);
1880
1881 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
1882
1883 regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP);
1884 regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
1885 regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG);
1886 regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL);
1887 regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL);
1888 regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL);
1889 regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT);
1890 regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT);
1891 regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE);
1892 regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER);
1893 regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS);
1894 regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL);
1895 regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK);
1896 regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL);
1897 regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG);
1898 regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
1899 regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4);
1900 regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE);
1901 regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4);
1902 regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL);
1903 regs_buff[20] = ATL2_READ_REG(hw, REG_MTU);
1904 regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL);
1905 regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END);
1906 regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI);
1907 regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO);
1908 regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE);
1909 regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO);
1910 regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE);
1911 regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO);
1912 regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM);
1913 regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR);
1914 regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH);
1915 regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW);
1916 regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH);
1917 regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH);
1918 regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX);
1919 regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX);
1920 regs_buff[38] = ATL2_READ_REG(hw, REG_ISR);
1921 regs_buff[39] = ATL2_READ_REG(hw, REG_IMR);
1922
1923 atl2_read_phy_reg(hw, MII_BMCR, &phy_data);
1924 regs_buff[40] = (u32)phy_data;
1925 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1926 regs_buff[41] = (u32)phy_data;
1927 }
1928
1929 static int atl2_get_eeprom_len(struct net_device *netdev)
1930 {
1931 struct atl2_adapter *adapter = netdev_priv(netdev);
1932
1933 if (!atl2_check_eeprom_exist(&adapter->hw))
1934 return 512;
1935 else
1936 return 0;
1937 }
1938
1939 static int atl2_get_eeprom(struct net_device *netdev,
1940 struct ethtool_eeprom *eeprom, u8 *bytes)
1941 {
1942 struct atl2_adapter *adapter = netdev_priv(netdev);
1943 struct atl2_hw *hw = &adapter->hw;
1944 u32 *eeprom_buff;
1945 int first_dword, last_dword;
1946 int ret_val = 0;
1947 int i;
1948
1949 if (eeprom->len == 0)
1950 return -EINVAL;
1951
1952 if (atl2_check_eeprom_exist(hw))
1953 return -EINVAL;
1954
1955 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
1956
1957 first_dword = eeprom->offset >> 2;
1958 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
1959
1960 eeprom_buff = kmalloc(sizeof(u32) * (last_dword - first_dword + 1),
1961 GFP_KERNEL);
1962 if (!eeprom_buff)
1963 return -ENOMEM;
1964
1965 for (i = first_dword; i < last_dword; i++) {
1966 if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword])))
1967 return -EIO;
1968 }
1969
1970 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3),
1971 eeprom->len);
1972 kfree(eeprom_buff);
1973
1974 return ret_val;
1975 }
1976
1977 static int atl2_set_eeprom(struct net_device *netdev,
1978 struct ethtool_eeprom *eeprom, u8 *bytes)
1979 {
1980 struct atl2_adapter *adapter = netdev_priv(netdev);
1981 struct atl2_hw *hw = &adapter->hw;
1982 u32 *eeprom_buff;
1983 u32 *ptr;
1984 int max_len, first_dword, last_dword, ret_val = 0;
1985 int i;
1986
1987 if (eeprom->len == 0)
1988 return -EOPNOTSUPP;
1989
1990 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
1991 return -EFAULT;
1992
1993 max_len = 512;
1994
1995 first_dword = eeprom->offset >> 2;
1996 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
1997 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
1998 if (!eeprom_buff)
1999 return -ENOMEM;
2000
2001 ptr = (u32 *)eeprom_buff;
2002
2003 if (eeprom->offset & 3) {
2004 /* need read/modify/write of first changed EEPROM word */
2005 /* only the second byte of the word is being modified */
2006 if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0])))
2007 return -EIO;
2008 ptr++;
2009 }
2010 if (((eeprom->offset + eeprom->len) & 3)) {
2011 /*
2012 * need read/modify/write of last changed EEPROM word
2013 * only the first byte of the word is being modified
2014 */
2015 if (!atl2_read_eeprom(hw, last_dword * 4,
2016 &(eeprom_buff[last_dword - first_dword])))
2017 return -EIO;
2018 }
2019
2020 /* Device's eeprom is always little-endian, word addressable */
2021 memcpy(ptr, bytes, eeprom->len);
2022
2023 for (i = 0; i < last_dword - first_dword + 1; i++) {
2024 if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i]))
2025 return -EIO;
2026 }
2027
2028 kfree(eeprom_buff);
2029 return ret_val;
2030 }
2031
2032 static void atl2_get_drvinfo(struct net_device *netdev,
2033 struct ethtool_drvinfo *drvinfo)
2034 {
2035 struct atl2_adapter *adapter = netdev_priv(netdev);
2036
2037 strncpy(drvinfo->driver, atl2_driver_name, 32);
2038 strncpy(drvinfo->version, atl2_driver_version, 32);
2039 strncpy(drvinfo->fw_version, "L2", 32);
2040 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
2041 drvinfo->n_stats = 0;
2042 drvinfo->testinfo_len = 0;
2043 drvinfo->regdump_len = atl2_get_regs_len(netdev);
2044 drvinfo->eedump_len = atl2_get_eeprom_len(netdev);
2045 }
2046
2047 static void atl2_get_wol(struct net_device *netdev,
2048 struct ethtool_wolinfo *wol)
2049 {
2050 struct atl2_adapter *adapter = netdev_priv(netdev);
2051
2052 wol->supported = WAKE_MAGIC;
2053 wol->wolopts = 0;
2054
2055 if (adapter->wol & ATLX_WUFC_EX)
2056 wol->wolopts |= WAKE_UCAST;
2057 if (adapter->wol & ATLX_WUFC_MC)
2058 wol->wolopts |= WAKE_MCAST;
2059 if (adapter->wol & ATLX_WUFC_BC)
2060 wol->wolopts |= WAKE_BCAST;
2061 if (adapter->wol & ATLX_WUFC_MAG)
2062 wol->wolopts |= WAKE_MAGIC;
2063 if (adapter->wol & ATLX_WUFC_LNKC)
2064 wol->wolopts |= WAKE_PHY;
2065 }
2066
2067 static int atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2068 {
2069 struct atl2_adapter *adapter = netdev_priv(netdev);
2070
2071 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
2072 return -EOPNOTSUPP;
2073
2074 if (wol->wolopts & (WAKE_MCAST|WAKE_BCAST|WAKE_MCAST))
2075 return -EOPNOTSUPP;
2076
2077 /* these settings will always override what we currently have */
2078 adapter->wol = 0;
2079
2080 if (wol->wolopts & WAKE_MAGIC)
2081 adapter->wol |= ATLX_WUFC_MAG;
2082 if (wol->wolopts & WAKE_PHY)
2083 adapter->wol |= ATLX_WUFC_LNKC;
2084
2085 return 0;
2086 }
2087
2088 static int atl2_nway_reset(struct net_device *netdev)
2089 {
2090 struct atl2_adapter *adapter = netdev_priv(netdev);
2091 if (netif_running(netdev))
2092 atl2_reinit_locked(adapter);
2093 return 0;
2094 }
2095
2096 static struct ethtool_ops atl2_ethtool_ops = {
2097 .get_settings = atl2_get_settings,
2098 .set_settings = atl2_set_settings,
2099 .get_drvinfo = atl2_get_drvinfo,
2100 .get_regs_len = atl2_get_regs_len,
2101 .get_regs = atl2_get_regs,
2102 .get_wol = atl2_get_wol,
2103 .set_wol = atl2_set_wol,
2104 .get_msglevel = atl2_get_msglevel,
2105 .set_msglevel = atl2_set_msglevel,
2106 .nway_reset = atl2_nway_reset,
2107 .get_link = ethtool_op_get_link,
2108 .get_eeprom_len = atl2_get_eeprom_len,
2109 .get_eeprom = atl2_get_eeprom,
2110 .set_eeprom = atl2_set_eeprom,
2111 .get_tx_csum = atl2_get_tx_csum,
2112 .get_sg = ethtool_op_get_sg,
2113 .set_sg = ethtool_op_set_sg,
2114 #ifdef NETIF_F_TSO
2115 .get_tso = ethtool_op_get_tso,
2116 #endif
2117 };
2118
2119 static void atl2_set_ethtool_ops(struct net_device *netdev)
2120 {
2121 SET_ETHTOOL_OPS(netdev, &atl2_ethtool_ops);
2122 }
2123
2124 #define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \
2125 (((a) & 0xff00ff00) >> 8))
2126 #define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16))
2127 #define SHORTSWAP(a) (((a) << 8) | ((a) >> 8))
2128
2129 /*
2130 * Reset the transmit and receive units; mask and clear all interrupts.
2131 *
2132 * hw - Struct containing variables accessed by shared code
2133 * return : 0 or idle status (if error)
2134 */
2135 static s32 atl2_reset_hw(struct atl2_hw *hw)
2136 {
2137 u32 icr;
2138 u16 pci_cfg_cmd_word;
2139 int i;
2140
2141 /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */
2142 atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2143 if ((pci_cfg_cmd_word &
2144 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) !=
2145 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) {
2146 pci_cfg_cmd_word |=
2147 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER);
2148 atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2149 }
2150
2151 /* Clear Interrupt mask to stop board from generating
2152 * interrupts & Clear any pending interrupt events
2153 */
2154 /* FIXME */
2155 /* ATL2_WRITE_REG(hw, REG_IMR, 0); */
2156 /* ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); */
2157
2158 /* Issue Soft Reset to the MAC. This will reset the chip's
2159 * transmit, receive, DMA. It will not effect
2160 * the current PCI configuration. The global reset bit is self-
2161 * clearing, and should clear within a microsecond.
2162 */
2163 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST);
2164 wmb();
2165 msleep(1); /* delay about 1ms */
2166
2167 /* Wait at least 10ms for All module to be Idle */
2168 for (i = 0; i < 10; i++) {
2169 icr = ATL2_READ_REG(hw, REG_IDLE_STATUS);
2170 if (!icr)
2171 break;
2172 msleep(1); /* delay 1 ms */
2173 cpu_relax();
2174 }
2175
2176 if (icr)
2177 return icr;
2178
2179 return 0;
2180 }
2181
2182 #define CUSTOM_SPI_CS_SETUP 2
2183 #define CUSTOM_SPI_CLK_HI 2
2184 #define CUSTOM_SPI_CLK_LO 2
2185 #define CUSTOM_SPI_CS_HOLD 2
2186 #define CUSTOM_SPI_CS_HI 3
2187
2188 static struct atl2_spi_flash_dev flash_table[] =
2189 {
2190 /* MFR WRSR READ PROGRAM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */
2191 {"Atmel", 0x0, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 },
2192 {"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 },
2193 {"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7 },
2194 };
2195
2196 static bool atl2_spi_read(struct atl2_hw *hw, u32 addr, u32 *buf)
2197 {
2198 int i;
2199 u32 value;
2200
2201 ATL2_WRITE_REG(hw, REG_SPI_DATA, 0);
2202 ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr);
2203
2204 value = SPI_FLASH_CTRL_WAIT_READY |
2205 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
2206 SPI_FLASH_CTRL_CS_SETUP_SHIFT |
2207 (CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) <<
2208 SPI_FLASH_CTRL_CLK_HI_SHIFT |
2209 (CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) <<
2210 SPI_FLASH_CTRL_CLK_LO_SHIFT |
2211 (CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) <<
2212 SPI_FLASH_CTRL_CS_HOLD_SHIFT |
2213 (CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) <<
2214 SPI_FLASH_CTRL_CS_HI_SHIFT |
2215 (0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT;
2216
2217 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2218
2219 value |= SPI_FLASH_CTRL_START;
2220
2221 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2222
2223 for (i = 0; i < 10; i++) {
2224 msleep(1);
2225 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2226 if (!(value & SPI_FLASH_CTRL_START))
2227 break;
2228 }
2229
2230 if (value & SPI_FLASH_CTRL_START)
2231 return false;
2232
2233 *buf = ATL2_READ_REG(hw, REG_SPI_DATA);
2234
2235 return true;
2236 }
2237
2238 /*
2239 * get_permanent_address
2240 * return 0 if get valid mac address,
2241 */
2242 static int get_permanent_address(struct atl2_hw *hw)
2243 {
2244 u32 Addr[2];
2245 u32 i, Control;
2246 u16 Register;
2247 u8 EthAddr[NODE_ADDRESS_SIZE];
2248 bool KeyValid;
2249
2250 if (is_valid_ether_addr(hw->perm_mac_addr))
2251 return 0;
2252
2253 Addr[0] = 0;
2254 Addr[1] = 0;
2255
2256 if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */
2257 Register = 0;
2258 KeyValid = false;
2259
2260 /* Read out all EEPROM content */
2261 i = 0;
2262 while (1) {
2263 if (atl2_read_eeprom(hw, i + 0x100, &Control)) {
2264 if (KeyValid) {
2265 if (Register == REG_MAC_STA_ADDR)
2266 Addr[0] = Control;
2267 else if (Register ==
2268 (REG_MAC_STA_ADDR + 4))
2269 Addr[1] = Control;
2270 KeyValid = false;
2271 } else if ((Control & 0xff) == 0x5A) {
2272 KeyValid = true;
2273 Register = (u16) (Control >> 16);
2274 } else {
2275 /* assume data end while encount an invalid KEYWORD */
2276 break;
2277 }
2278 } else {
2279 break; /* read error */
2280 }
2281 i += 4;
2282 }
2283
2284 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2285 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2286
2287 if (is_valid_ether_addr(EthAddr)) {
2288 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2289 return 0;
2290 }
2291 return 1;
2292 }
2293
2294 /* see if SPI flash exists? */
2295 Addr[0] = 0;
2296 Addr[1] = 0;
2297 Register = 0;
2298 KeyValid = false;
2299 i = 0;
2300 while (1) {
2301 if (atl2_spi_read(hw, i + 0x1f000, &Control)) {
2302 if (KeyValid) {
2303 if (Register == REG_MAC_STA_ADDR)
2304 Addr[0] = Control;
2305 else if (Register == (REG_MAC_STA_ADDR + 4))
2306 Addr[1] = Control;
2307 KeyValid = false;
2308 } else if ((Control & 0xff) == 0x5A) {
2309 KeyValid = true;
2310 Register = (u16) (Control >> 16);
2311 } else {
2312 break; /* data end */
2313 }
2314 } else {
2315 break; /* read error */
2316 }
2317 i += 4;
2318 }
2319
2320 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2321 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *)&Addr[1]);
2322 if (is_valid_ether_addr(EthAddr)) {
2323 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2324 return 0;
2325 }
2326 /* maybe MAC-address is from BIOS */
2327 Addr[0] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
2328 Addr[1] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR + 4);
2329 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2330 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2331
2332 if (is_valid_ether_addr(EthAddr)) {
2333 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2334 return 0;
2335 }
2336
2337 return 1;
2338 }
2339
2340 /*
2341 * Reads the adapter's MAC address from the EEPROM
2342 *
2343 * hw - Struct containing variables accessed by shared code
2344 */
2345 static s32 atl2_read_mac_addr(struct atl2_hw *hw)
2346 {
2347 u16 i;
2348
2349 if (get_permanent_address(hw)) {
2350 /* for test */
2351 /* FIXME: shouldn't we use random_ether_addr() here? */
2352 hw->perm_mac_addr[0] = 0x00;
2353 hw->perm_mac_addr[1] = 0x13;
2354 hw->perm_mac_addr[2] = 0x74;
2355 hw->perm_mac_addr[3] = 0x00;
2356 hw->perm_mac_addr[4] = 0x5c;
2357 hw->perm_mac_addr[5] = 0x38;
2358 }
2359
2360 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
2361 hw->mac_addr[i] = hw->perm_mac_addr[i];
2362
2363 return 0;
2364 }
2365
2366 /*
2367 * Hashes an address to determine its location in the multicast table
2368 *
2369 * hw - Struct containing variables accessed by shared code
2370 * mc_addr - the multicast address to hash
2371 *
2372 * atl2_hash_mc_addr
2373 * purpose
2374 * set hash value for a multicast address
2375 * hash calcu processing :
2376 * 1. calcu 32bit CRC for multicast address
2377 * 2. reverse crc with MSB to LSB
2378 */
2379 static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr)
2380 {
2381 u32 crc32, value;
2382 int i;
2383
2384 value = 0;
2385 crc32 = ether_crc_le(6, mc_addr);
2386
2387 for (i = 0; i < 32; i++)
2388 value |= (((crc32 >> i) & 1) << (31 - i));
2389
2390 return value;
2391 }
2392
2393 /*
2394 * Sets the bit in the multicast table corresponding to the hash value.
2395 *
2396 * hw - Struct containing variables accessed by shared code
2397 * hash_value - Multicast address hash value
2398 */
2399 static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value)
2400 {
2401 u32 hash_bit, hash_reg;
2402 u32 mta;
2403
2404 /* The HASH Table is a register array of 2 32-bit registers.
2405 * It is treated like an array of 64 bits. We want to set
2406 * bit BitArray[hash_value]. So we figure out what register
2407 * the bit is in, read it, OR in the new bit, then write
2408 * back the new value. The register is determined by the
2409 * upper 7 bits of the hash value and the bit within that
2410 * register are determined by the lower 5 bits of the value.
2411 */
2412 hash_reg = (hash_value >> 31) & 0x1;
2413 hash_bit = (hash_value >> 26) & 0x1F;
2414
2415 mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
2416
2417 mta |= (1 << hash_bit);
2418
2419 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
2420 }
2421
2422 /*
2423 * atl2_init_pcie - init PCIE module
2424 */
2425 static void atl2_init_pcie(struct atl2_hw *hw)
2426 {
2427 u32 value;
2428 value = LTSSM_TEST_MODE_DEF;
2429 ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value);
2430
2431 value = PCIE_DLL_TX_CTRL1_DEF;
2432 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value);
2433 }
2434
2435 static void atl2_init_flash_opcode(struct atl2_hw *hw)
2436 {
2437 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
2438 hw->flash_vendor = 0; /* ATMEL */
2439
2440 /* Init OP table */
2441 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM,
2442 flash_table[hw->flash_vendor].cmdPROGRAM);
2443 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE,
2444 flash_table[hw->flash_vendor].cmdSECTOR_ERASE);
2445 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE,
2446 flash_table[hw->flash_vendor].cmdCHIP_ERASE);
2447 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID,
2448 flash_table[hw->flash_vendor].cmdRDID);
2449 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN,
2450 flash_table[hw->flash_vendor].cmdWREN);
2451 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR,
2452 flash_table[hw->flash_vendor].cmdRDSR);
2453 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR,
2454 flash_table[hw->flash_vendor].cmdWRSR);
2455 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ,
2456 flash_table[hw->flash_vendor].cmdREAD);
2457 }
2458
2459 /********************************************************************
2460 * Performs basic configuration of the adapter.
2461 *
2462 * hw - Struct containing variables accessed by shared code
2463 * Assumes that the controller has previously been reset and is in a
2464 * post-reset uninitialized state. Initializes multicast table,
2465 * and Calls routines to setup link
2466 * Leaves the transmit and receive units disabled and uninitialized.
2467 ********************************************************************/
2468 static s32 atl2_init_hw(struct atl2_hw *hw)
2469 {
2470 u32 ret_val = 0;
2471
2472 atl2_init_pcie(hw);
2473
2474 /* Zero out the Multicast HASH table */
2475 /* clear the old settings from the multicast hash table */
2476 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
2477 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
2478
2479 atl2_init_flash_opcode(hw);
2480
2481 ret_val = atl2_phy_init(hw);
2482
2483 return ret_val;
2484 }
2485
2486 /*
2487 * Detects the current speed and duplex settings of the hardware.
2488 *
2489 * hw - Struct containing variables accessed by shared code
2490 * speed - Speed of the connection
2491 * duplex - Duplex setting of the connection
2492 */
2493 static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed,
2494 u16 *duplex)
2495 {
2496 s32 ret_val;
2497 u16 phy_data;
2498
2499 /* Read PHY Specific Status Register (17) */
2500 ret_val = atl2_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
2501 if (ret_val)
2502 return ret_val;
2503
2504 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
2505 return ATLX_ERR_PHY_RES;
2506
2507 switch (phy_data & MII_ATLX_PSSR_SPEED) {
2508 case MII_ATLX_PSSR_100MBS:
2509 *speed = SPEED_100;
2510 break;
2511 case MII_ATLX_PSSR_10MBS:
2512 *speed = SPEED_10;
2513 break;
2514 default:
2515 return ATLX_ERR_PHY_SPEED;
2516 break;
2517 }
2518
2519 if (phy_data & MII_ATLX_PSSR_DPLX)
2520 *duplex = FULL_DUPLEX;
2521 else
2522 *duplex = HALF_DUPLEX;
2523
2524 return 0;
2525 }
2526
2527 /*
2528 * Reads the value from a PHY register
2529 * hw - Struct containing variables accessed by shared code
2530 * reg_addr - address of the PHY register to read
2531 */
2532 static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data)
2533 {
2534 u32 val;
2535 int i;
2536
2537 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
2538 MDIO_START |
2539 MDIO_SUP_PREAMBLE |
2540 MDIO_RW |
2541 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2542 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2543
2544 wmb();
2545
2546 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2547 udelay(2);
2548 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2549 if (!(val & (MDIO_START | MDIO_BUSY)))
2550 break;
2551 wmb();
2552 }
2553 if (!(val & (MDIO_START | MDIO_BUSY))) {
2554 *phy_data = (u16)val;
2555 return 0;
2556 }
2557
2558 return ATLX_ERR_PHY;
2559 }
2560
2561 /*
2562 * Writes a value to a PHY register
2563 * hw - Struct containing variables accessed by shared code
2564 * reg_addr - address of the PHY register to write
2565 * data - data to write to the PHY
2566 */
2567 static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data)
2568 {
2569 int i;
2570 u32 val;
2571
2572 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
2573 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
2574 MDIO_SUP_PREAMBLE |
2575 MDIO_START |
2576 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2577 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2578
2579 wmb();
2580
2581 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2582 udelay(2);
2583 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2584 if (!(val & (MDIO_START | MDIO_BUSY)))
2585 break;
2586
2587 wmb();
2588 }
2589
2590 if (!(val & (MDIO_START | MDIO_BUSY)))
2591 return 0;
2592
2593 return ATLX_ERR_PHY;
2594 }
2595
2596 /*
2597 * Configures PHY autoneg and flow control advertisement settings
2598 *
2599 * hw - Struct containing variables accessed by shared code
2600 */
2601 static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw)
2602 {
2603 s32 ret_val;
2604 s16 mii_autoneg_adv_reg;
2605
2606 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2607 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
2608
2609 /* Need to parse autoneg_advertised and set up
2610 * the appropriate PHY registers. First we will parse for
2611 * autoneg_advertised software override. Since we can advertise
2612 * a plethora of combinations, we need to check each bit
2613 * individually.
2614 */
2615
2616 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2617 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2618 * the 1000Base-T Control Register (Address 9). */
2619 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
2620
2621 /* Need to parse MediaType and setup the
2622 * appropriate PHY registers. */
2623 switch (hw->MediaType) {
2624 case MEDIA_TYPE_AUTO_SENSOR:
2625 mii_autoneg_adv_reg |=
2626 (MII_AR_10T_HD_CAPS |
2627 MII_AR_10T_FD_CAPS |
2628 MII_AR_100TX_HD_CAPS|
2629 MII_AR_100TX_FD_CAPS);
2630 hw->autoneg_advertised =
2631 ADVERTISE_10_HALF |
2632 ADVERTISE_10_FULL |
2633 ADVERTISE_100_HALF|
2634 ADVERTISE_100_FULL;
2635 break;
2636 case MEDIA_TYPE_100M_FULL:
2637 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
2638 hw->autoneg_advertised = ADVERTISE_100_FULL;
2639 break;
2640 case MEDIA_TYPE_100M_HALF:
2641 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
2642 hw->autoneg_advertised = ADVERTISE_100_HALF;
2643 break;
2644 case MEDIA_TYPE_10M_FULL:
2645 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
2646 hw->autoneg_advertised = ADVERTISE_10_FULL;
2647 break;
2648 default:
2649 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
2650 hw->autoneg_advertised = ADVERTISE_10_HALF;
2651 break;
2652 }
2653
2654 /* flow control fixed to enable all */
2655 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
2656
2657 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
2658
2659 ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
2660
2661 if (ret_val)
2662 return ret_val;
2663
2664 return 0;
2665 }
2666
2667 /*
2668 * Resets the PHY and make all config validate
2669 *
2670 * hw - Struct containing variables accessed by shared code
2671 *
2672 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
2673 */
2674 static s32 atl2_phy_commit(struct atl2_hw *hw)
2675 {
2676 s32 ret_val;
2677 u16 phy_data;
2678
2679 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2680 ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data);
2681 if (ret_val) {
2682 u32 val;
2683 int i;
2684 /* pcie serdes link may be down ! */
2685 for (i = 0; i < 25; i++) {
2686 msleep(1);
2687 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2688 if (!(val & (MDIO_START | MDIO_BUSY)))
2689 break;
2690 }
2691
2692 if (0 != (val & (MDIO_START | MDIO_BUSY))) {
2693 printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n");
2694 return ret_val;
2695 }
2696 }
2697 return 0;
2698 }
2699
2700 static s32 atl2_phy_init(struct atl2_hw *hw)
2701 {
2702 s32 ret_val;
2703 u16 phy_val;
2704
2705 if (hw->phy_configured)
2706 return 0;
2707
2708 /* Enable PHY */
2709 ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1);
2710 ATL2_WRITE_FLUSH(hw);
2711 msleep(1);
2712
2713 /* check if the PHY is in powersaving mode */
2714 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2715 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2716
2717 /* 024E / 124E 0r 0274 / 1274 ? */
2718 if (phy_val & 0x1000) {
2719 phy_val &= ~0x1000;
2720 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val);
2721 }
2722
2723 msleep(1);
2724
2725 /*Enable PHY LinkChange Interrupt */
2726 ret_val = atl2_write_phy_reg(hw, 18, 0xC00);
2727 if (ret_val)
2728 return ret_val;
2729
2730 /* setup AutoNeg parameters */
2731 ret_val = atl2_phy_setup_autoneg_adv(hw);
2732 if (ret_val)
2733 return ret_val;
2734
2735 /* SW.Reset & En-Auto-Neg to restart Auto-Neg */
2736 ret_val = atl2_phy_commit(hw);
2737 if (ret_val)
2738 return ret_val;
2739
2740 hw->phy_configured = true;
2741
2742 return ret_val;
2743 }
2744
2745 static void atl2_set_mac_addr(struct atl2_hw *hw)
2746 {
2747 u32 value;
2748 /* 00-0B-6A-F6-00-DC
2749 * 0: 6AF600DC 1: 000B
2750 * low dword */
2751 value = (((u32)hw->mac_addr[2]) << 24) |
2752 (((u32)hw->mac_addr[3]) << 16) |
2753 (((u32)hw->mac_addr[4]) << 8) |
2754 (((u32)hw->mac_addr[5]));
2755 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
2756 /* hight dword */
2757 value = (((u32)hw->mac_addr[0]) << 8) |
2758 (((u32)hw->mac_addr[1]));
2759 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
2760 }
2761
2762 /*
2763 * check_eeprom_exist
2764 * return 0 if eeprom exist
2765 */
2766 static int atl2_check_eeprom_exist(struct atl2_hw *hw)
2767 {
2768 u32 value;
2769
2770 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2771 if (value & SPI_FLASH_CTRL_EN_VPD) {
2772 value &= ~SPI_FLASH_CTRL_EN_VPD;
2773 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2774 }
2775 value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST);
2776 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
2777 }
2778
2779 /* FIXME: This doesn't look right. -- CHS */
2780 static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value)
2781 {
2782 return true;
2783 }
2784
2785 static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue)
2786 {
2787 int i;
2788 u32 Control;
2789
2790 if (Offset & 0x3)
2791 return false; /* address do not align */
2792
2793 ATL2_WRITE_REG(hw, REG_VPD_DATA, 0);
2794 Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
2795 ATL2_WRITE_REG(hw, REG_VPD_CAP, Control);
2796
2797 for (i = 0; i < 10; i++) {
2798 msleep(2);
2799 Control = ATL2_READ_REG(hw, REG_VPD_CAP);
2800 if (Control & VPD_CAP_VPD_FLAG)
2801 break;
2802 }
2803
2804 if (Control & VPD_CAP_VPD_FLAG) {
2805 *pValue = ATL2_READ_REG(hw, REG_VPD_DATA);
2806 return true;
2807 }
2808 return false; /* timeout */
2809 }
2810
2811 static void atl2_force_ps(struct atl2_hw *hw)
2812 {
2813 u16 phy_val;
2814
2815 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2816 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2817 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000);
2818
2819 atl2_write_phy_reg(hw, MII_DBG_ADDR, 2);
2820 atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000);
2821 atl2_write_phy_reg(hw, MII_DBG_ADDR, 3);
2822 atl2_write_phy_reg(hw, MII_DBG_DATA, 0);
2823 }
2824
2825 /* This is the only thing that needs to be changed to adjust the
2826 * maximum number of ports that the driver can manage.
2827 */
2828 #define ATL2_MAX_NIC 4
2829
2830 #define OPTION_UNSET -1
2831 #define OPTION_DISABLED 0
2832 #define OPTION_ENABLED 1
2833
2834 /* All parameters are treated the same, as an integer array of values.
2835 * This macro just reduces the need to repeat the same declaration code
2836 * over and over (plus this helps to avoid typo bugs).
2837 */
2838 #define ATL2_PARAM_INIT {[0 ... ATL2_MAX_NIC] = OPTION_UNSET}
2839 #ifndef module_param_array
2840 /* Module Parameters are always initialized to -1, so that the driver
2841 * can tell the difference between no user specified value or the
2842 * user asking for the default value.
2843 * The true default values are loaded in when atl2_check_options is called.
2844 *
2845 * This is a GCC extension to ANSI C.
2846 * See the item "Labeled Elements in Initializers" in the section
2847 * "Extensions to the C Language Family" of the GCC documentation.
2848 */
2849
2850 #define ATL2_PARAM(X, desc) \
2851 static const int __devinitdata X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \
2852 MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \
2853 MODULE_PARM_DESC(X, desc);
2854 #else
2855 #define ATL2_PARAM(X, desc) \
2856 static int __devinitdata X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \
2857 static int num_##X = 0; \
2858 module_param_array_named(X, X, int, &num_##X, 0); \
2859 MODULE_PARM_DESC(X, desc);
2860 #endif
2861
2862 /*
2863 * Transmit Memory Size
2864 * Valid Range: 64-2048
2865 * Default Value: 128
2866 */
2867 #define ATL2_MIN_TX_MEMSIZE 4 /* 4KB */
2868 #define ATL2_MAX_TX_MEMSIZE 64 /* 64KB */
2869 #define ATL2_DEFAULT_TX_MEMSIZE 8 /* 8KB */
2870 ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory");
2871
2872 /*
2873 * Receive Memory Block Count
2874 * Valid Range: 16-512
2875 * Default Value: 128
2876 */
2877 #define ATL2_MIN_RXD_COUNT 16
2878 #define ATL2_MAX_RXD_COUNT 512
2879 #define ATL2_DEFAULT_RXD_COUNT 64
2880 ATL2_PARAM(RxMemBlock, "Number of receive memory block");
2881
2882 /*
2883 * User Specified MediaType Override
2884 *
2885 * Valid Range: 0-5
2886 * - 0 - auto-negotiate at all supported speeds
2887 * - 1 - only link at 1000Mbps Full Duplex
2888 * - 2 - only link at 100Mbps Full Duplex
2889 * - 3 - only link at 100Mbps Half Duplex
2890 * - 4 - only link at 10Mbps Full Duplex
2891 * - 5 - only link at 10Mbps Half Duplex
2892 * Default Value: 0
2893 */
2894 ATL2_PARAM(MediaType, "MediaType Select");
2895
2896 /*
2897 * Interrupt Moderate Timer in units of 2048 ns (~2 us)
2898 * Valid Range: 10-65535
2899 * Default Value: 45000(90ms)
2900 */
2901 #define INT_MOD_DEFAULT_CNT 100 /* 200us */
2902 #define INT_MOD_MAX_CNT 65000
2903 #define INT_MOD_MIN_CNT 50
2904 ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer");
2905
2906 /*
2907 * FlashVendor
2908 * Valid Range: 0-2
2909 * 0 - Atmel
2910 * 1 - SST
2911 * 2 - ST
2912 */
2913 ATL2_PARAM(FlashVendor, "SPI Flash Vendor");
2914
2915 #define AUTONEG_ADV_DEFAULT 0x2F
2916 #define AUTONEG_ADV_MASK 0x2F
2917 #define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL
2918
2919 #define FLASH_VENDOR_DEFAULT 0
2920 #define FLASH_VENDOR_MIN 0
2921 #define FLASH_VENDOR_MAX 2
2922
2923 struct atl2_option {
2924 enum { enable_option, range_option, list_option } type;
2925 char *name;
2926 char *err;
2927 int def;
2928 union {
2929 struct { /* range_option info */
2930 int min;
2931 int max;
2932 } r;
2933 struct { /* list_option info */
2934 int nr;
2935 struct atl2_opt_list { int i; char *str; } *p;
2936 } l;
2937 } arg;
2938 };
2939
2940 static int __devinit atl2_validate_option(int *value, struct atl2_option *opt)
2941 {
2942 int i;
2943 struct atl2_opt_list *ent;
2944
2945 if (*value == OPTION_UNSET) {
2946 *value = opt->def;
2947 return 0;
2948 }
2949
2950 switch (opt->type) {
2951 case enable_option:
2952 switch (*value) {
2953 case OPTION_ENABLED:
2954 printk(KERN_INFO "%s Enabled\n", opt->name);
2955 return 0;
2956 break;
2957 case OPTION_DISABLED:
2958 printk(KERN_INFO "%s Disabled\n", opt->name);
2959 return 0;
2960 break;
2961 }
2962 break;
2963 case range_option:
2964 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
2965 printk(KERN_INFO "%s set to %i\n", opt->name, *value);
2966 return 0;
2967 }
2968 break;
2969 case list_option:
2970 for (i = 0; i < opt->arg.l.nr; i++) {
2971 ent = &opt->arg.l.p[i];
2972 if (*value == ent->i) {
2973 if (ent->str[0] != '\0')
2974 printk(KERN_INFO "%s\n", ent->str);
2975 return 0;
2976 }
2977 }
2978 break;
2979 default:
2980 BUG();
2981 }
2982
2983 printk(KERN_INFO "Invalid %s specified (%i) %s\n",
2984 opt->name, *value, opt->err);
2985 *value = opt->def;
2986 return -1;
2987 }
2988
2989 /*
2990 * atl2_check_options - Range Checking for Command Line Parameters
2991 * @adapter: board private structure
2992 *
2993 * This routine checks all command line parameters for valid user
2994 * input. If an invalid value is given, or if no user specified
2995 * value exists, a default value is used. The final value is stored
2996 * in a variable in the adapter structure.
2997 */
2998 static void __devinit atl2_check_options(struct atl2_adapter *adapter)
2999 {
3000 int val;
3001 struct atl2_option opt;
3002 int bd = adapter->bd_number;
3003 if (bd >= ATL2_MAX_NIC) {
3004 printk(KERN_NOTICE "Warning: no configuration for board #%i\n",
3005 bd);
3006 printk(KERN_NOTICE "Using defaults for all values\n");
3007 #ifndef module_param_array
3008 bd = ATL2_MAX_NIC;
3009 #endif
3010 }
3011
3012 /* Bytes of Transmit Memory */
3013 opt.type = range_option;
3014 opt.name = "Bytes of Transmit Memory";
3015 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE);
3016 opt.def = ATL2_DEFAULT_TX_MEMSIZE;
3017 opt.arg.r.min = ATL2_MIN_TX_MEMSIZE;
3018 opt.arg.r.max = ATL2_MAX_TX_MEMSIZE;
3019 #ifdef module_param_array
3020 if (num_TxMemSize > bd) {
3021 #endif
3022 val = TxMemSize[bd];
3023 atl2_validate_option(&val, &opt);
3024 adapter->txd_ring_size = ((u32) val) * 1024;
3025 #ifdef module_param_array
3026 } else
3027 adapter->txd_ring_size = ((u32)opt.def) * 1024;
3028 #endif
3029 /* txs ring size: */
3030 adapter->txs_ring_size = adapter->txd_ring_size / 128;
3031 if (adapter->txs_ring_size > 160)
3032 adapter->txs_ring_size = 160;
3033
3034 /* Receive Memory Block Count */
3035 opt.type = range_option;
3036 opt.name = "Number of receive memory block";
3037 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT);
3038 opt.def = ATL2_DEFAULT_RXD_COUNT;
3039 opt.arg.r.min = ATL2_MIN_RXD_COUNT;
3040 opt.arg.r.max = ATL2_MAX_RXD_COUNT;
3041 #ifdef module_param_array
3042 if (num_RxMemBlock > bd) {
3043 #endif
3044 val = RxMemBlock[bd];
3045 atl2_validate_option(&val, &opt);
3046 adapter->rxd_ring_size = (u32)val;
3047 /* FIXME */
3048 /* ((u16)val)&~1; */ /* even number */
3049 #ifdef module_param_array
3050 } else
3051 adapter->rxd_ring_size = (u32)opt.def;
3052 #endif
3053 /* init RXD Flow control value */
3054 adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size / 8) * 7;
3055 adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT / 8) >
3056 (adapter->rxd_ring_size / 12) ? (ATL2_MIN_RXD_COUNT / 8) :
3057 (adapter->rxd_ring_size / 12);
3058
3059 /* Interrupt Moderate Timer */
3060 opt.type = range_option;
3061 opt.name = "Interrupt Moderate Timer";
3062 opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT);
3063 opt.def = INT_MOD_DEFAULT_CNT;
3064 opt.arg.r.min = INT_MOD_MIN_CNT;
3065 opt.arg.r.max = INT_MOD_MAX_CNT;
3066 #ifdef module_param_array
3067 if (num_IntModTimer > bd) {
3068 #endif
3069 val = IntModTimer[bd];
3070 atl2_validate_option(&val, &opt);
3071 adapter->imt = (u16) val;
3072 #ifdef module_param_array
3073 } else
3074 adapter->imt = (u16)(opt.def);
3075 #endif
3076 /* Flash Vendor */
3077 opt.type = range_option;
3078 opt.name = "SPI Flash Vendor";
3079 opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT);
3080 opt.def = FLASH_VENDOR_DEFAULT;
3081 opt.arg.r.min = FLASH_VENDOR_MIN;
3082 opt.arg.r.max = FLASH_VENDOR_MAX;
3083 #ifdef module_param_array
3084 if (num_FlashVendor > bd) {
3085 #endif
3086 val = FlashVendor[bd];
3087 atl2_validate_option(&val, &opt);
3088 adapter->hw.flash_vendor = (u8) val;
3089 #ifdef module_param_array
3090 } else
3091 adapter->hw.flash_vendor = (u8)(opt.def);
3092 #endif
3093 /* MediaType */
3094 opt.type = range_option;
3095 opt.name = "Speed/Duplex Selection";
3096 opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR);
3097 opt.def = MEDIA_TYPE_AUTO_SENSOR;
3098 opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR;
3099 opt.arg.r.max = MEDIA_TYPE_10M_HALF;
3100 #ifdef module_param_array
3101 if (num_MediaType > bd) {
3102 #endif
3103 val = MediaType[bd];
3104 atl2_validate_option(&val, &opt);
3105 adapter->hw.MediaType = (u16) val;
3106 #ifdef module_param_array
3107 } else
3108 adapter->hw.MediaType = (u16)(opt.def);
3109 #endif
3110 }
Support for the Chinese Samsung S3C2440 based development boards