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x86: PAT avoid aliasing in /dev/mem read/write
[linux-2.6/mini2440.git] / drivers / char / synclinkmp.c
blobc96062ea72b4acffd82ea352006e7af53adb4329
1 /*
2 * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
3 *
4 * Device driver for Microgate SyncLink Multiport
5 * high speed multiprotocol serial adapter.
6 *
7 * written by Paul Fulghum for Microgate Corporation
8 * paulkf@microgate.com
9 *
10 * Microgate and SyncLink are trademarks of Microgate Corporation
11 *
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13 * This code is released under the GNU General Public License (GPL)
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
25 * OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
29 #if defined(__i386__)
30 # define BREAKPOINT() asm(" int $3");
31 #else
32 # define BREAKPOINT() { }
33 #endif
34
35 #define MAX_DEVICES 12
36
37 #include <linux/module.h>
38 #include <linux/errno.h>
39 #include <linux/signal.h>
40 #include <linux/sched.h>
41 #include <linux/timer.h>
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/tty.h>
45 #include <linux/tty_flip.h>
46 #include <linux/serial.h>
47 #include <linux/major.h>
48 #include <linux/string.h>
49 #include <linux/fcntl.h>
50 #include <linux/ptrace.h>
51 #include <linux/ioport.h>
52 #include <linux/mm.h>
53 #include <linux/slab.h>
54 #include <linux/netdevice.h>
55 #include <linux/vmalloc.h>
56 #include <linux/init.h>
57 #include <linux/delay.h>
58 #include <linux/ioctl.h>
59
60 #include <asm/system.h>
61 #include <asm/io.h>
62 #include <asm/irq.h>
63 #include <asm/dma.h>
64 #include <linux/bitops.h>
65 #include <asm/types.h>
66 #include <linux/termios.h>
67 #include <linux/workqueue.h>
68 #include <linux/hdlc.h>
69 #include <linux/synclink.h>
70
71 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
72 #define SYNCLINK_GENERIC_HDLC 1
73 #else
74 #define SYNCLINK_GENERIC_HDLC 0
75 #endif
76
77 #define GET_USER(error,value,addr) error = get_user(value,addr)
78 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
79 #define PUT_USER(error,value,addr) error = put_user(value,addr)
80 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
81
82 #include <asm/uaccess.h>
83
84 static MGSL_PARAMS default_params = {
85 MGSL_MODE_HDLC, /* unsigned long mode */
86 0, /* unsigned char loopback; */
87 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
88 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
89 0, /* unsigned long clock_speed; */
90 0xff, /* unsigned char addr_filter; */
91 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
92 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
93 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
94 9600, /* unsigned long data_rate; */
95 8, /* unsigned char data_bits; */
96 1, /* unsigned char stop_bits; */
97 ASYNC_PARITY_NONE /* unsigned char parity; */
98 };
99
100 /* size in bytes of DMA data buffers */
101 #define SCABUFSIZE 1024
102 #define SCA_MEM_SIZE 0x40000
103 #define SCA_BASE_SIZE 512
104 #define SCA_REG_SIZE 16
105 #define SCA_MAX_PORTS 4
106 #define SCAMAXDESC 128
107
108 #define BUFFERLISTSIZE 4096
109
110 /* SCA-I style DMA buffer descriptor */
111 typedef struct _SCADESC
112 {
113 u16 next; /* lower l6 bits of next descriptor addr */
114 u16 buf_ptr; /* lower 16 bits of buffer addr */
115 u8 buf_base; /* upper 8 bits of buffer addr */
116 u8 pad1;
117 u16 length; /* length of buffer */
118 u8 status; /* status of buffer */
119 u8 pad2;
120 } SCADESC, *PSCADESC;
121
122 typedef struct _SCADESC_EX
123 {
124 /* device driver bookkeeping section */
125 char *virt_addr; /* virtual address of data buffer */
126 u16 phys_entry; /* lower 16-bits of physical address of this descriptor */
127 } SCADESC_EX, *PSCADESC_EX;
128
129 /* The queue of BH actions to be performed */
130
131 #define BH_RECEIVE 1
132 #define BH_TRANSMIT 2
133 #define BH_STATUS 4
134
135 #define IO_PIN_SHUTDOWN_LIMIT 100
136
137 struct _input_signal_events {
138 int ri_up;
139 int ri_down;
140 int dsr_up;
141 int dsr_down;
142 int dcd_up;
143 int dcd_down;
144 int cts_up;
145 int cts_down;
146 };
147
148 /*
149 * Device instance data structure
150 */
151 typedef struct _synclinkmp_info {
152 void *if_ptr; /* General purpose pointer (used by SPPP) */
153 int magic;
154 int flags;
155 int count; /* count of opens */
156 int line;
157 unsigned short close_delay;
158 unsigned short closing_wait; /* time to wait before closing */
159
160 struct mgsl_icount icount;
161
162 struct tty_struct *tty;
163 int timeout;
164 int x_char; /* xon/xoff character */
165 int blocked_open; /* # of blocked opens */
166 u16 read_status_mask1; /* break detection (SR1 indications) */
167 u16 read_status_mask2; /* parity/framing/overun (SR2 indications) */
168 unsigned char ignore_status_mask1; /* break detection (SR1 indications) */
169 unsigned char ignore_status_mask2; /* parity/framing/overun (SR2 indications) */
170 unsigned char *tx_buf;
171 int tx_put;
172 int tx_get;
173 int tx_count;
174
175 wait_queue_head_t open_wait;
176 wait_queue_head_t close_wait;
177
178 wait_queue_head_t status_event_wait_q;
179 wait_queue_head_t event_wait_q;
180 struct timer_list tx_timer; /* HDLC transmit timeout timer */
181 struct _synclinkmp_info *next_device; /* device list link */
182 struct timer_list status_timer; /* input signal status check timer */
183
184 spinlock_t lock; /* spinlock for synchronizing with ISR */
185 struct work_struct task; /* task structure for scheduling bh */
186
187 u32 max_frame_size; /* as set by device config */
188
189 u32 pending_bh;
190
191 int bh_running; /* Protection from multiple */
192 int isr_overflow;
193 int bh_requested;
194
195 int dcd_chkcount; /* check counts to prevent */
196 int cts_chkcount; /* too many IRQs if a signal */
197 int dsr_chkcount; /* is floating */
198 int ri_chkcount;
199
200 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
201 unsigned long buffer_list_phys;
202
203 unsigned int rx_buf_count; /* count of total allocated Rx buffers */
204 SCADESC *rx_buf_list; /* list of receive buffer entries */
205 SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
206 unsigned int current_rx_buf;
207
208 unsigned int tx_buf_count; /* count of total allocated Tx buffers */
209 SCADESC *tx_buf_list; /* list of transmit buffer entries */
210 SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
211 unsigned int last_tx_buf;
212
213 unsigned char *tmp_rx_buf;
214 unsigned int tmp_rx_buf_count;
215
216 int rx_enabled;
217 int rx_overflow;
218
219 int tx_enabled;
220 int tx_active;
221 u32 idle_mode;
222
223 unsigned char ie0_value;
224 unsigned char ie1_value;
225 unsigned char ie2_value;
226 unsigned char ctrlreg_value;
227 unsigned char old_signals;
228
229 char device_name[25]; /* device instance name */
230
231 int port_count;
232 int adapter_num;
233 int port_num;
234
235 struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
236
237 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
238
239 unsigned int irq_level; /* interrupt level */
240 unsigned long irq_flags;
241 int irq_requested; /* nonzero if IRQ requested */
242
243 MGSL_PARAMS params; /* communications parameters */
244
245 unsigned char serial_signals; /* current serial signal states */
246
247 int irq_occurred; /* for diagnostics use */
248 unsigned int init_error; /* Initialization startup error */
249
250 u32 last_mem_alloc;
251 unsigned char* memory_base; /* shared memory address (PCI only) */
252 u32 phys_memory_base;
253 int shared_mem_requested;
254
255 unsigned char* sca_base; /* HD64570 SCA Memory address */
256 u32 phys_sca_base;
257 u32 sca_offset;
258 int sca_base_requested;
259
260 unsigned char* lcr_base; /* local config registers (PCI only) */
261 u32 phys_lcr_base;
262 u32 lcr_offset;
263 int lcr_mem_requested;
264
265 unsigned char* statctrl_base; /* status/control register memory */
266 u32 phys_statctrl_base;
267 u32 statctrl_offset;
268 int sca_statctrl_requested;
269
270 u32 misc_ctrl_value;
271 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
272 char char_buf[MAX_ASYNC_BUFFER_SIZE];
273 BOOLEAN drop_rts_on_tx_done;
274
275 struct _input_signal_events input_signal_events;
276
277 /* SPPP/Cisco HDLC device parts */
278 int netcount;
279 int dosyncppp;
280 spinlock_t netlock;
281
282 #if SYNCLINK_GENERIC_HDLC
283 struct net_device *netdev;
284 #endif
285
286 } SLMP_INFO;
287
288 #define MGSL_MAGIC 0x5401
289
290 /*
291 * define serial signal status change macros
292 */
293 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */
294 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */
295 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */
296 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
297
298 /* Common Register macros */
299 #define LPR 0x00
300 #define PABR0 0x02
301 #define PABR1 0x03
302 #define WCRL 0x04
303 #define WCRM 0x05
304 #define WCRH 0x06
305 #define DPCR 0x08
306 #define DMER 0x09
307 #define ISR0 0x10
308 #define ISR1 0x11
309 #define ISR2 0x12
310 #define IER0 0x14
311 #define IER1 0x15
312 #define IER2 0x16
313 #define ITCR 0x18
314 #define INTVR 0x1a
315 #define IMVR 0x1c
316
317 /* MSCI Register macros */
318 #define TRB 0x20
319 #define TRBL 0x20
320 #define TRBH 0x21
321 #define SR0 0x22
322 #define SR1 0x23
323 #define SR2 0x24
324 #define SR3 0x25
325 #define FST 0x26
326 #define IE0 0x28
327 #define IE1 0x29
328 #define IE2 0x2a
329 #define FIE 0x2b
330 #define CMD 0x2c
331 #define MD0 0x2e
332 #define MD1 0x2f
333 #define MD2 0x30
334 #define CTL 0x31
335 #define SA0 0x32
336 #define SA1 0x33
337 #define IDL 0x34
338 #define TMC 0x35
339 #define RXS 0x36
340 #define TXS 0x37
341 #define TRC0 0x38
342 #define TRC1 0x39
343 #define RRC 0x3a
344 #define CST0 0x3c
345 #define CST1 0x3d
346
347 /* Timer Register Macros */
348 #define TCNT 0x60
349 #define TCNTL 0x60
350 #define TCNTH 0x61
351 #define TCONR 0x62
352 #define TCONRL 0x62
353 #define TCONRH 0x63
354 #define TMCS 0x64
355 #define TEPR 0x65
356
357 /* DMA Controller Register macros */
358 #define DARL 0x80
359 #define DARH 0x81
360 #define DARB 0x82
361 #define BAR 0x80
362 #define BARL 0x80
363 #define BARH 0x81
364 #define BARB 0x82
365 #define SAR 0x84
366 #define SARL 0x84
367 #define SARH 0x85
368 #define SARB 0x86
369 #define CPB 0x86
370 #define CDA 0x88
371 #define CDAL 0x88
372 #define CDAH 0x89
373 #define EDA 0x8a
374 #define EDAL 0x8a
375 #define EDAH 0x8b
376 #define BFL 0x8c
377 #define BFLL 0x8c
378 #define BFLH 0x8d
379 #define BCR 0x8e
380 #define BCRL 0x8e
381 #define BCRH 0x8f
382 #define DSR 0x90
383 #define DMR 0x91
384 #define FCT 0x93
385 #define DIR 0x94
386 #define DCMD 0x95
387
388 /* combine with timer or DMA register address */
389 #define TIMER0 0x00
390 #define TIMER1 0x08
391 #define TIMER2 0x10
392 #define TIMER3 0x18
393 #define RXDMA 0x00
394 #define TXDMA 0x20
395
396 /* SCA Command Codes */
397 #define NOOP 0x00
398 #define TXRESET 0x01
399 #define TXENABLE 0x02
400 #define TXDISABLE 0x03
401 #define TXCRCINIT 0x04
402 #define TXCRCEXCL 0x05
403 #define TXEOM 0x06
404 #define TXABORT 0x07
405 #define MPON 0x08
406 #define TXBUFCLR 0x09
407 #define RXRESET 0x11
408 #define RXENABLE 0x12
409 #define RXDISABLE 0x13
410 #define RXCRCINIT 0x14
411 #define RXREJECT 0x15
412 #define SEARCHMP 0x16
413 #define RXCRCEXCL 0x17
414 #define RXCRCCALC 0x18
415 #define CHRESET 0x21
416 #define HUNT 0x31
417
418 /* DMA command codes */
419 #define SWABORT 0x01
420 #define FEICLEAR 0x02
421
422 /* IE0 */
423 #define TXINTE BIT7
424 #define RXINTE BIT6
425 #define TXRDYE BIT1
426 #define RXRDYE BIT0
427
428 /* IE1 & SR1 */
429 #define UDRN BIT7
430 #define IDLE BIT6
431 #define SYNCD BIT4
432 #define FLGD BIT4
433 #define CCTS BIT3
434 #define CDCD BIT2
435 #define BRKD BIT1
436 #define ABTD BIT1
437 #define GAPD BIT1
438 #define BRKE BIT0
439 #define IDLD BIT0
440
441 /* IE2 & SR2 */
442 #define EOM BIT7
443 #define PMP BIT6
444 #define SHRT BIT6
445 #define PE BIT5
446 #define ABT BIT5
447 #define FRME BIT4
448 #define RBIT BIT4
449 #define OVRN BIT3
450 #define CRCE BIT2
451
452
453 /*
454 * Global linked list of SyncLink devices
455 */
456 static SLMP_INFO *synclinkmp_device_list = NULL;
457 static int synclinkmp_adapter_count = -1;
458 static int synclinkmp_device_count = 0;
459
460 /*
461 * Set this param to non-zero to load eax with the
462 * .text section address and breakpoint on module load.
463 * This is useful for use with gdb and add-symbol-file command.
464 */
465 static int break_on_load=0;
466
467 /*
468 * Driver major number, defaults to zero to get auto
469 * assigned major number. May be forced as module parameter.
470 */
471 static int ttymajor=0;
472
473 /*
474 * Array of user specified options for ISA adapters.
475 */
476 static int debug_level = 0;
477 static int maxframe[MAX_DEVICES] = {0,};
478 static int dosyncppp[MAX_DEVICES] = {0,};
479
480 module_param(break_on_load, bool, 0);
481 module_param(ttymajor, int, 0);
482 module_param(debug_level, int, 0);
483 module_param_array(maxframe, int, NULL, 0);
484 module_param_array(dosyncppp, int, NULL, 0);
485
486 static char *driver_name = "SyncLink MultiPort driver";
487 static char *driver_version = "$Revision: 4.38 $";
488
489 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
490 static void synclinkmp_remove_one(struct pci_dev *dev);
491
492 static struct pci_device_id synclinkmp_pci_tbl[] = {
493 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
494 { 0, }, /* terminate list */
495 };
496 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
497
498 MODULE_LICENSE("GPL");
499
500 static struct pci_driver synclinkmp_pci_driver = {
501 .name = "synclinkmp",
502 .id_table = synclinkmp_pci_tbl,
503 .probe = synclinkmp_init_one,
504 .remove = __devexit_p(synclinkmp_remove_one),
505 };
506
507
508 static struct tty_driver *serial_driver;
509
510 /* number of characters left in xmit buffer before we ask for more */
511 #define WAKEUP_CHARS 256
512
513
514 /* tty callbacks */
515
516 static int open(struct tty_struct *tty, struct file * filp);
517 static void close(struct tty_struct *tty, struct file * filp);
518 static void hangup(struct tty_struct *tty);
519 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
520
521 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
522 static void put_char(struct tty_struct *tty, unsigned char ch);
523 static void send_xchar(struct tty_struct *tty, char ch);
524 static void wait_until_sent(struct tty_struct *tty, int timeout);
525 static int write_room(struct tty_struct *tty);
526 static void flush_chars(struct tty_struct *tty);
527 static void flush_buffer(struct tty_struct *tty);
528 static void tx_hold(struct tty_struct *tty);
529 static void tx_release(struct tty_struct *tty);
530
531 static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
532 static int read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
533 static int chars_in_buffer(struct tty_struct *tty);
534 static void throttle(struct tty_struct * tty);
535 static void unthrottle(struct tty_struct * tty);
536 static void set_break(struct tty_struct *tty, int break_state);
537
538 #if SYNCLINK_GENERIC_HDLC
539 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
540 static void hdlcdev_tx_done(SLMP_INFO *info);
541 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
542 static int hdlcdev_init(SLMP_INFO *info);
543 static void hdlcdev_exit(SLMP_INFO *info);
544 #endif
545
546 /* ioctl handlers */
547
548 static int get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
549 static int get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
550 static int set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
551 static int get_txidle(SLMP_INFO *info, int __user *idle_mode);
552 static int set_txidle(SLMP_INFO *info, int idle_mode);
553 static int tx_enable(SLMP_INFO *info, int enable);
554 static int tx_abort(SLMP_INFO *info);
555 static int rx_enable(SLMP_INFO *info, int enable);
556 static int modem_input_wait(SLMP_INFO *info,int arg);
557 static int wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
558 static int tiocmget(struct tty_struct *tty, struct file *file);
559 static int tiocmset(struct tty_struct *tty, struct file *file,
560 unsigned int set, unsigned int clear);
561 static void set_break(struct tty_struct *tty, int break_state);
562
563 static void add_device(SLMP_INFO *info);
564 static void device_init(int adapter_num, struct pci_dev *pdev);
565 static int claim_resources(SLMP_INFO *info);
566 static void release_resources(SLMP_INFO *info);
567
568 static int startup(SLMP_INFO *info);
569 static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
570 static void shutdown(SLMP_INFO *info);
571 static void program_hw(SLMP_INFO *info);
572 static void change_params(SLMP_INFO *info);
573
574 static int init_adapter(SLMP_INFO *info);
575 static int register_test(SLMP_INFO *info);
576 static int irq_test(SLMP_INFO *info);
577 static int loopback_test(SLMP_INFO *info);
578 static int adapter_test(SLMP_INFO *info);
579 static int memory_test(SLMP_INFO *info);
580
581 static void reset_adapter(SLMP_INFO *info);
582 static void reset_port(SLMP_INFO *info);
583 static void async_mode(SLMP_INFO *info);
584 static void hdlc_mode(SLMP_INFO *info);
585
586 static void rx_stop(SLMP_INFO *info);
587 static void rx_start(SLMP_INFO *info);
588 static void rx_reset_buffers(SLMP_INFO *info);
589 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
590 static int rx_get_frame(SLMP_INFO *info);
591
592 static void tx_start(SLMP_INFO *info);
593 static void tx_stop(SLMP_INFO *info);
594 static void tx_load_fifo(SLMP_INFO *info);
595 static void tx_set_idle(SLMP_INFO *info);
596 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
597
598 static void get_signals(SLMP_INFO *info);
599 static void set_signals(SLMP_INFO *info);
600 static void enable_loopback(SLMP_INFO *info, int enable);
601 static void set_rate(SLMP_INFO *info, u32 data_rate);
602
603 static int bh_action(SLMP_INFO *info);
604 static void bh_handler(struct work_struct *work);
605 static void bh_receive(SLMP_INFO *info);
606 static void bh_transmit(SLMP_INFO *info);
607 static void bh_status(SLMP_INFO *info);
608 static void isr_timer(SLMP_INFO *info);
609 static void isr_rxint(SLMP_INFO *info);
610 static void isr_rxrdy(SLMP_INFO *info);
611 static void isr_txint(SLMP_INFO *info);
612 static void isr_txrdy(SLMP_INFO *info);
613 static void isr_rxdmaok(SLMP_INFO *info);
614 static void isr_rxdmaerror(SLMP_INFO *info);
615 static void isr_txdmaok(SLMP_INFO *info);
616 static void isr_txdmaerror(SLMP_INFO *info);
617 static void isr_io_pin(SLMP_INFO *info, u16 status);
618
619 static int alloc_dma_bufs(SLMP_INFO *info);
620 static void free_dma_bufs(SLMP_INFO *info);
621 static int alloc_buf_list(SLMP_INFO *info);
622 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
623 static int alloc_tmp_rx_buf(SLMP_INFO *info);
624 static void free_tmp_rx_buf(SLMP_INFO *info);
625
626 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
627 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
628 static void tx_timeout(unsigned long context);
629 static void status_timeout(unsigned long context);
630
631 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
632 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
633 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
634 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
635 static unsigned char read_status_reg(SLMP_INFO * info);
636 static void write_control_reg(SLMP_INFO * info);
637
638
639 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
640 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
641 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
642
643 static u32 misc_ctrl_value = 0x007e4040;
644 static u32 lcr1_brdr_value = 0x00800028;
645
646 static u32 read_ahead_count = 8;
647
648 /* DPCR, DMA Priority Control
649 *
650 * 07..05 Not used, must be 0
651 * 04 BRC, bus release condition: 0=all transfers complete
652 * 1=release after 1 xfer on all channels
653 * 03 CCC, channel change condition: 0=every cycle
654 * 1=after each channel completes all xfers
655 * 02..00 PR<2..0>, priority 100=round robin
656 *
657 * 00000100 = 0x00
658 */
659 static unsigned char dma_priority = 0x04;
660
661 // Number of bytes that can be written to shared RAM
662 // in a single write operation
663 static u32 sca_pci_load_interval = 64;
664
665 /*
666 * 1st function defined in .text section. Calling this function in
667 * init_module() followed by a breakpoint allows a remote debugger
668 * (gdb) to get the .text address for the add-symbol-file command.
669 * This allows remote debugging of dynamically loadable modules.
670 */
671 static void* synclinkmp_get_text_ptr(void);
672 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
673
674 static inline int sanity_check(SLMP_INFO *info,
675 char *name, const char *routine)
676 {
677 #ifdef SANITY_CHECK
678 static const char *badmagic =
679 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
680 static const char *badinfo =
681 "Warning: null synclinkmp_struct for (%s) in %s\n";
682
683 if (!info) {
684 printk(badinfo, name, routine);
685 return 1;
686 }
687 if (info->magic != MGSL_MAGIC) {
688 printk(badmagic, name, routine);
689 return 1;
690 }
691 #else
692 if (!info)
693 return 1;
694 #endif
695 return 0;
696 }
697
698 /**
699 * line discipline callback wrappers
700 *
701 * The wrappers maintain line discipline references
702 * while calling into the line discipline.
703 *
704 * ldisc_receive_buf - pass receive data to line discipline
705 */
706
707 static void ldisc_receive_buf(struct tty_struct *tty,
708 const __u8 *data, char *flags, int count)
709 {
710 struct tty_ldisc *ld;
711 if (!tty)
712 return;
713 ld = tty_ldisc_ref(tty);
714 if (ld) {
715 if (ld->receive_buf)
716 ld->receive_buf(tty, data, flags, count);
717 tty_ldisc_deref(ld);
718 }
719 }
720
721 /* tty callbacks */
722
723 /* Called when a port is opened. Init and enable port.
724 */
725 static int open(struct tty_struct *tty, struct file *filp)
726 {
727 SLMP_INFO *info;
728 int retval, line;
729 unsigned long flags;
730
731 line = tty->index;
732 if ((line < 0) || (line >= synclinkmp_device_count)) {
733 printk("%s(%d): open with invalid line #%d.\n",
734 __FILE__,__LINE__,line);
735 return -ENODEV;
736 }
737
738 info = synclinkmp_device_list;
739 while(info && info->line != line)
740 info = info->next_device;
741 if (sanity_check(info, tty->name, "open"))
742 return -ENODEV;
743 if ( info->init_error ) {
744 printk("%s(%d):%s device is not allocated, init error=%d\n",
745 __FILE__,__LINE__,info->device_name,info->init_error);
746 return -ENODEV;
747 }
748
749 tty->driver_data = info;
750 info->tty = tty;
751
752 if (debug_level >= DEBUG_LEVEL_INFO)
753 printk("%s(%d):%s open(), old ref count = %d\n",
754 __FILE__,__LINE__,tty->driver->name, info->count);
755
756 /* If port is closing, signal caller to try again */
757 if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
758 if (info->flags & ASYNC_CLOSING)
759 interruptible_sleep_on(&info->close_wait);
760 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
761 -EAGAIN : -ERESTARTSYS);
762 goto cleanup;
763 }
764
765 info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
766
767 spin_lock_irqsave(&info->netlock, flags);
768 if (info->netcount) {
769 retval = -EBUSY;
770 spin_unlock_irqrestore(&info->netlock, flags);
771 goto cleanup;
772 }
773 info->count++;
774 spin_unlock_irqrestore(&info->netlock, flags);
775
776 if (info->count == 1) {
777 /* 1st open on this device, init hardware */
778 retval = startup(info);
779 if (retval < 0)
780 goto cleanup;
781 }
782
783 retval = block_til_ready(tty, filp, info);
784 if (retval) {
785 if (debug_level >= DEBUG_LEVEL_INFO)
786 printk("%s(%d):%s block_til_ready() returned %d\n",
787 __FILE__,__LINE__, info->device_name, retval);
788 goto cleanup;
789 }
790
791 if (debug_level >= DEBUG_LEVEL_INFO)
792 printk("%s(%d):%s open() success\n",
793 __FILE__,__LINE__, info->device_name);
794 retval = 0;
795
796 cleanup:
797 if (retval) {
798 if (tty->count == 1)
799 info->tty = NULL; /* tty layer will release tty struct */
800 if(info->count)
801 info->count--;
802 }
803
804 return retval;
805 }
806
807 /* Called when port is closed. Wait for remaining data to be
808 * sent. Disable port and free resources.
809 */
810 static void close(struct tty_struct *tty, struct file *filp)
811 {
812 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
813
814 if (sanity_check(info, tty->name, "close"))
815 return;
816
817 if (debug_level >= DEBUG_LEVEL_INFO)
818 printk("%s(%d):%s close() entry, count=%d\n",
819 __FILE__,__LINE__, info->device_name, info->count);
820
821 if (!info->count)
822 return;
823
824 if (tty_hung_up_p(filp))
825 goto cleanup;
826
827 if ((tty->count == 1) && (info->count != 1)) {
828 /*
829 * tty->count is 1 and the tty structure will be freed.
830 * info->count should be one in this case.
831 * if it's not, correct it so that the port is shutdown.
832 */
833 printk("%s(%d):%s close: bad refcount; tty->count is 1, "
834 "info->count is %d\n",
835 __FILE__,__LINE__, info->device_name, info->count);
836 info->count = 1;
837 }
838
839 info->count--;
840
841 /* if at least one open remaining, leave hardware active */
842 if (info->count)
843 goto cleanup;
844
845 info->flags |= ASYNC_CLOSING;
846
847 /* set tty->closing to notify line discipline to
848 * only process XON/XOFF characters. Only the N_TTY
849 * discipline appears to use this (ppp does not).
850 */
851 tty->closing = 1;
852
853 /* wait for transmit data to clear all layers */
854
855 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
856 if (debug_level >= DEBUG_LEVEL_INFO)
857 printk("%s(%d):%s close() calling tty_wait_until_sent\n",
858 __FILE__,__LINE__, info->device_name );
859 tty_wait_until_sent(tty, info->closing_wait);
860 }
861
862 if (info->flags & ASYNC_INITIALIZED)
863 wait_until_sent(tty, info->timeout);
864
865 if (tty->driver->flush_buffer)
866 tty->driver->flush_buffer(tty);
867
868 tty_ldisc_flush(tty);
869
870 shutdown(info);
871
872 tty->closing = 0;
873 info->tty = NULL;
874
875 if (info->blocked_open) {
876 if (info->close_delay) {
877 msleep_interruptible(jiffies_to_msecs(info->close_delay));
878 }
879 wake_up_interruptible(&info->open_wait);
880 }
881
882 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
883
884 wake_up_interruptible(&info->close_wait);
885
886 cleanup:
887 if (debug_level >= DEBUG_LEVEL_INFO)
888 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
889 tty->driver->name, info->count);
890 }
891
892 /* Called by tty_hangup() when a hangup is signaled.
893 * This is the same as closing all open descriptors for the port.
894 */
895 static void hangup(struct tty_struct *tty)
896 {
897 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
898
899 if (debug_level >= DEBUG_LEVEL_INFO)
900 printk("%s(%d):%s hangup()\n",
901 __FILE__,__LINE__, info->device_name );
902
903 if (sanity_check(info, tty->name, "hangup"))
904 return;
905
906 flush_buffer(tty);
907 shutdown(info);
908
909 info->count = 0;
910 info->flags &= ~ASYNC_NORMAL_ACTIVE;
911 info->tty = NULL;
912
913 wake_up_interruptible(&info->open_wait);
914 }
915
916 /* Set new termios settings
917 */
918 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
919 {
920 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
921 unsigned long flags;
922
923 if (debug_level >= DEBUG_LEVEL_INFO)
924 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
925 tty->driver->name );
926
927 change_params(info);
928
929 /* Handle transition to B0 status */
930 if (old_termios->c_cflag & CBAUD &&
931 !(tty->termios->c_cflag & CBAUD)) {
932 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
933 spin_lock_irqsave(&info->lock,flags);
934 set_signals(info);
935 spin_unlock_irqrestore(&info->lock,flags);
936 }
937
938 /* Handle transition away from B0 status */
939 if (!(old_termios->c_cflag & CBAUD) &&
940 tty->termios->c_cflag & CBAUD) {
941 info->serial_signals |= SerialSignal_DTR;
942 if (!(tty->termios->c_cflag & CRTSCTS) ||
943 !test_bit(TTY_THROTTLED, &tty->flags)) {
944 info->serial_signals |= SerialSignal_RTS;
945 }
946 spin_lock_irqsave(&info->lock,flags);
947 set_signals(info);
948 spin_unlock_irqrestore(&info->lock,flags);
949 }
950
951 /* Handle turning off CRTSCTS */
952 if (old_termios->c_cflag & CRTSCTS &&
953 !(tty->termios->c_cflag & CRTSCTS)) {
954 tty->hw_stopped = 0;
955 tx_release(tty);
956 }
957 }
958
959 /* Send a block of data
960 *
961 * Arguments:
962 *
963 * tty pointer to tty information structure
964 * buf pointer to buffer containing send data
965 * count size of send data in bytes
966 *
967 * Return Value: number of characters written
968 */
969 static int write(struct tty_struct *tty,
970 const unsigned char *buf, int count)
971 {
972 int c, ret = 0;
973 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
974 unsigned long flags;
975
976 if (debug_level >= DEBUG_LEVEL_INFO)
977 printk("%s(%d):%s write() count=%d\n",
978 __FILE__,__LINE__,info->device_name,count);
979
980 if (sanity_check(info, tty->name, "write"))
981 goto cleanup;
982
983 if (!info->tx_buf)
984 goto cleanup;
985
986 if (info->params.mode == MGSL_MODE_HDLC) {
987 if (count > info->max_frame_size) {
988 ret = -EIO;
989 goto cleanup;
990 }
991 if (info->tx_active)
992 goto cleanup;
993 if (info->tx_count) {
994 /* send accumulated data from send_char() calls */
995 /* as frame and wait before accepting more data. */
996 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
997 goto start;
998 }
999 ret = info->tx_count = count;
1000 tx_load_dma_buffer(info, buf, count);
1001 goto start;
1002 }
1003
1004 for (;;) {
1005 c = min_t(int, count,
1006 min(info->max_frame_size - info->tx_count - 1,
1007 info->max_frame_size - info->tx_put));
1008 if (c <= 0)
1009 break;
1010
1011 memcpy(info->tx_buf + info->tx_put, buf, c);
1012
1013 spin_lock_irqsave(&info->lock,flags);
1014 info->tx_put += c;
1015 if (info->tx_put >= info->max_frame_size)
1016 info->tx_put -= info->max_frame_size;
1017 info->tx_count += c;
1018 spin_unlock_irqrestore(&info->lock,flags);
1019
1020 buf += c;
1021 count -= c;
1022 ret += c;
1023 }
1024
1025 if (info->params.mode == MGSL_MODE_HDLC) {
1026 if (count) {
1027 ret = info->tx_count = 0;
1028 goto cleanup;
1029 }
1030 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1031 }
1032 start:
1033 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1034 spin_lock_irqsave(&info->lock,flags);
1035 if (!info->tx_active)
1036 tx_start(info);
1037 spin_unlock_irqrestore(&info->lock,flags);
1038 }
1039
1040 cleanup:
1041 if (debug_level >= DEBUG_LEVEL_INFO)
1042 printk( "%s(%d):%s write() returning=%d\n",
1043 __FILE__,__LINE__,info->device_name,ret);
1044 return ret;
1045 }
1046
1047 /* Add a character to the transmit buffer.
1048 */
1049 static void put_char(struct tty_struct *tty, unsigned char ch)
1050 {
1051 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1052 unsigned long flags;
1053
1054 if ( debug_level >= DEBUG_LEVEL_INFO ) {
1055 printk( "%s(%d):%s put_char(%d)\n",
1056 __FILE__,__LINE__,info->device_name,ch);
1057 }
1058
1059 if (sanity_check(info, tty->name, "put_char"))
1060 return;
1061
1062 if (!info->tx_buf)
1063 return;
1064
1065 spin_lock_irqsave(&info->lock,flags);
1066
1067 if ( (info->params.mode != MGSL_MODE_HDLC) ||
1068 !info->tx_active ) {
1069
1070 if (info->tx_count < info->max_frame_size - 1) {
1071 info->tx_buf[info->tx_put++] = ch;
1072 if (info->tx_put >= info->max_frame_size)
1073 info->tx_put -= info->max_frame_size;
1074 info->tx_count++;
1075 }
1076 }
1077
1078 spin_unlock_irqrestore(&info->lock,flags);
1079 }
1080
1081 /* Send a high-priority XON/XOFF character
1082 */
1083 static void send_xchar(struct tty_struct *tty, char ch)
1084 {
1085 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1086 unsigned long flags;
1087
1088 if (debug_level >= DEBUG_LEVEL_INFO)
1089 printk("%s(%d):%s send_xchar(%d)\n",
1090 __FILE__,__LINE__, info->device_name, ch );
1091
1092 if (sanity_check(info, tty->name, "send_xchar"))
1093 return;
1094
1095 info->x_char = ch;
1096 if (ch) {
1097 /* Make sure transmit interrupts are on */
1098 spin_lock_irqsave(&info->lock,flags);
1099 if (!info->tx_enabled)
1100 tx_start(info);
1101 spin_unlock_irqrestore(&info->lock,flags);
1102 }
1103 }
1104
1105 /* Wait until the transmitter is empty.
1106 */
1107 static void wait_until_sent(struct tty_struct *tty, int timeout)
1108 {
1109 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1110 unsigned long orig_jiffies, char_time;
1111
1112 if (!info )
1113 return;
1114
1115 if (debug_level >= DEBUG_LEVEL_INFO)
1116 printk("%s(%d):%s wait_until_sent() entry\n",
1117 __FILE__,__LINE__, info->device_name );
1118
1119 if (sanity_check(info, tty->name, "wait_until_sent"))
1120 return;
1121
1122 if (!(info->flags & ASYNC_INITIALIZED))
1123 goto exit;
1124
1125 orig_jiffies = jiffies;
1126
1127 /* Set check interval to 1/5 of estimated time to
1128 * send a character, and make it at least 1. The check
1129 * interval should also be less than the timeout.
1130 * Note: use tight timings here to satisfy the NIST-PCTS.
1131 */
1132
1133 if ( info->params.data_rate ) {
1134 char_time = info->timeout/(32 * 5);
1135 if (!char_time)
1136 char_time++;
1137 } else
1138 char_time = 1;
1139
1140 if (timeout)
1141 char_time = min_t(unsigned long, char_time, timeout);
1142
1143 if ( info->params.mode == MGSL_MODE_HDLC ) {
1144 while (info->tx_active) {
1145 msleep_interruptible(jiffies_to_msecs(char_time));
1146 if (signal_pending(current))
1147 break;
1148 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1149 break;
1150 }
1151 } else {
1152 //TODO: determine if there is something similar to USC16C32
1153 // TXSTATUS_ALL_SENT status
1154 while ( info->tx_active && info->tx_enabled) {
1155 msleep_interruptible(jiffies_to_msecs(char_time));
1156 if (signal_pending(current))
1157 break;
1158 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1159 break;
1160 }
1161 }
1162
1163 exit:
1164 if (debug_level >= DEBUG_LEVEL_INFO)
1165 printk("%s(%d):%s wait_until_sent() exit\n",
1166 __FILE__,__LINE__, info->device_name );
1167 }
1168
1169 /* Return the count of free bytes in transmit buffer
1170 */
1171 static int write_room(struct tty_struct *tty)
1172 {
1173 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1174 int ret;
1175
1176 if (sanity_check(info, tty->name, "write_room"))
1177 return 0;
1178
1179 if (info->params.mode == MGSL_MODE_HDLC) {
1180 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1181 } else {
1182 ret = info->max_frame_size - info->tx_count - 1;
1183 if (ret < 0)
1184 ret = 0;
1185 }
1186
1187 if (debug_level >= DEBUG_LEVEL_INFO)
1188 printk("%s(%d):%s write_room()=%d\n",
1189 __FILE__, __LINE__, info->device_name, ret);
1190
1191 return ret;
1192 }
1193
1194 /* enable transmitter and send remaining buffered characters
1195 */
1196 static void flush_chars(struct tty_struct *tty)
1197 {
1198 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1199 unsigned long flags;
1200
1201 if ( debug_level >= DEBUG_LEVEL_INFO )
1202 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1203 __FILE__,__LINE__,info->device_name,info->tx_count);
1204
1205 if (sanity_check(info, tty->name, "flush_chars"))
1206 return;
1207
1208 if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1209 !info->tx_buf)
1210 return;
1211
1212 if ( debug_level >= DEBUG_LEVEL_INFO )
1213 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1214 __FILE__,__LINE__,info->device_name );
1215
1216 spin_lock_irqsave(&info->lock,flags);
1217
1218 if (!info->tx_active) {
1219 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1220 info->tx_count ) {
1221 /* operating in synchronous (frame oriented) mode */
1222 /* copy data from circular tx_buf to */
1223 /* transmit DMA buffer. */
1224 tx_load_dma_buffer(info,
1225 info->tx_buf,info->tx_count);
1226 }
1227 tx_start(info);
1228 }
1229
1230 spin_unlock_irqrestore(&info->lock,flags);
1231 }
1232
1233 /* Discard all data in the send buffer
1234 */
1235 static void flush_buffer(struct tty_struct *tty)
1236 {
1237 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1238 unsigned long flags;
1239
1240 if (debug_level >= DEBUG_LEVEL_INFO)
1241 printk("%s(%d):%s flush_buffer() entry\n",
1242 __FILE__,__LINE__, info->device_name );
1243
1244 if (sanity_check(info, tty->name, "flush_buffer"))
1245 return;
1246
1247 spin_lock_irqsave(&info->lock,flags);
1248 info->tx_count = info->tx_put = info->tx_get = 0;
1249 del_timer(&info->tx_timer);
1250 spin_unlock_irqrestore(&info->lock,flags);
1251
1252 tty_wakeup(tty);
1253 }
1254
1255 /* throttle (stop) transmitter
1256 */
1257 static void tx_hold(struct tty_struct *tty)
1258 {
1259 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1260 unsigned long flags;
1261
1262 if (sanity_check(info, tty->name, "tx_hold"))
1263 return;
1264
1265 if ( debug_level >= DEBUG_LEVEL_INFO )
1266 printk("%s(%d):%s tx_hold()\n",
1267 __FILE__,__LINE__,info->device_name);
1268
1269 spin_lock_irqsave(&info->lock,flags);
1270 if (info->tx_enabled)
1271 tx_stop(info);
1272 spin_unlock_irqrestore(&info->lock,flags);
1273 }
1274
1275 /* release (start) transmitter
1276 */
1277 static void tx_release(struct tty_struct *tty)
1278 {
1279 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1280 unsigned long flags;
1281
1282 if (sanity_check(info, tty->name, "tx_release"))
1283 return;
1284
1285 if ( debug_level >= DEBUG_LEVEL_INFO )
1286 printk("%s(%d):%s tx_release()\n",
1287 __FILE__,__LINE__,info->device_name);
1288
1289 spin_lock_irqsave(&info->lock,flags);
1290 if (!info->tx_enabled)
1291 tx_start(info);
1292 spin_unlock_irqrestore(&info->lock,flags);
1293 }
1294
1295 /* Service an IOCTL request
1296 *
1297 * Arguments:
1298 *
1299 * tty pointer to tty instance data
1300 * file pointer to associated file object for device
1301 * cmd IOCTL command code
1302 * arg command argument/context
1303 *
1304 * Return Value: 0 if success, otherwise error code
1305 */
1306 static int ioctl(struct tty_struct *tty, struct file *file,
1307 unsigned int cmd, unsigned long arg)
1308 {
1309 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1310 int error;
1311 struct mgsl_icount cnow; /* kernel counter temps */
1312 struct serial_icounter_struct __user *p_cuser; /* user space */
1313 unsigned long flags;
1314 void __user *argp = (void __user *)arg;
1315
1316 if (debug_level >= DEBUG_LEVEL_INFO)
1317 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1318 info->device_name, cmd );
1319
1320 if (sanity_check(info, tty->name, "ioctl"))
1321 return -ENODEV;
1322
1323 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1324 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1325 if (tty->flags & (1 << TTY_IO_ERROR))
1326 return -EIO;
1327 }
1328
1329 switch (cmd) {
1330 case MGSL_IOCGPARAMS:
1331 return get_params(info, argp);
1332 case MGSL_IOCSPARAMS:
1333 return set_params(info, argp);
1334 case MGSL_IOCGTXIDLE:
1335 return get_txidle(info, argp);
1336 case MGSL_IOCSTXIDLE:
1337 return set_txidle(info, (int)arg);
1338 case MGSL_IOCTXENABLE:
1339 return tx_enable(info, (int)arg);
1340 case MGSL_IOCRXENABLE:
1341 return rx_enable(info, (int)arg);
1342 case MGSL_IOCTXABORT:
1343 return tx_abort(info);
1344 case MGSL_IOCGSTATS:
1345 return get_stats(info, argp);
1346 case MGSL_IOCWAITEVENT:
1347 return wait_mgsl_event(info, argp);
1348 case MGSL_IOCLOOPTXDONE:
1349 return 0; // TODO: Not supported, need to document
1350 /* Wait for modem input (DCD,RI,DSR,CTS) change
1351 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1352 */
1353 case TIOCMIWAIT:
1354 return modem_input_wait(info,(int)arg);
1355
1356 /*
1357 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1358 * Return: write counters to the user passed counter struct
1359 * NB: both 1->0 and 0->1 transitions are counted except for
1360 * RI where only 0->1 is counted.
1361 */
1362 case TIOCGICOUNT:
1363 spin_lock_irqsave(&info->lock,flags);
1364 cnow = info->icount;
1365 spin_unlock_irqrestore(&info->lock,flags);
1366 p_cuser = argp;
1367 PUT_USER(error,cnow.cts, &p_cuser->cts);
1368 if (error) return error;
1369 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1370 if (error) return error;
1371 PUT_USER(error,cnow.rng, &p_cuser->rng);
1372 if (error) return error;
1373 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1374 if (error) return error;
1375 PUT_USER(error,cnow.rx, &p_cuser->rx);
1376 if (error) return error;
1377 PUT_USER(error,cnow.tx, &p_cuser->tx);
1378 if (error) return error;
1379 PUT_USER(error,cnow.frame, &p_cuser->frame);
1380 if (error) return error;
1381 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1382 if (error) return error;
1383 PUT_USER(error,cnow.parity, &p_cuser->parity);
1384 if (error) return error;
1385 PUT_USER(error,cnow.brk, &p_cuser->brk);
1386 if (error) return error;
1387 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1388 if (error) return error;
1389 return 0;
1390 default:
1391 return -ENOIOCTLCMD;
1392 }
1393 return 0;
1394 }
1395
1396 /*
1397 * /proc fs routines....
1398 */
1399
1400 static inline int line_info(char *buf, SLMP_INFO *info)
1401 {
1402 char stat_buf[30];
1403 int ret;
1404 unsigned long flags;
1405
1406 ret = sprintf(buf, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1407 "\tIRQ=%d MaxFrameSize=%u\n",
1408 info->device_name,
1409 info->phys_sca_base,
1410 info->phys_memory_base,
1411 info->phys_statctrl_base,
1412 info->phys_lcr_base,
1413 info->irq_level,
1414 info->max_frame_size );
1415
1416 /* output current serial signal states */
1417 spin_lock_irqsave(&info->lock,flags);
1418 get_signals(info);
1419 spin_unlock_irqrestore(&info->lock,flags);
1420
1421 stat_buf[0] = 0;
1422 stat_buf[1] = 0;
1423 if (info->serial_signals & SerialSignal_RTS)
1424 strcat(stat_buf, "|RTS");
1425 if (info->serial_signals & SerialSignal_CTS)
1426 strcat(stat_buf, "|CTS");
1427 if (info->serial_signals & SerialSignal_DTR)
1428 strcat(stat_buf, "|DTR");
1429 if (info->serial_signals & SerialSignal_DSR)
1430 strcat(stat_buf, "|DSR");
1431 if (info->serial_signals & SerialSignal_DCD)
1432 strcat(stat_buf, "|CD");
1433 if (info->serial_signals & SerialSignal_RI)
1434 strcat(stat_buf, "|RI");
1435
1436 if (info->params.mode == MGSL_MODE_HDLC) {
1437 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1438 info->icount.txok, info->icount.rxok);
1439 if (info->icount.txunder)
1440 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1441 if (info->icount.txabort)
1442 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1443 if (info->icount.rxshort)
1444 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1445 if (info->icount.rxlong)
1446 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1447 if (info->icount.rxover)
1448 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1449 if (info->icount.rxcrc)
1450 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
1451 } else {
1452 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1453 info->icount.tx, info->icount.rx);
1454 if (info->icount.frame)
1455 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1456 if (info->icount.parity)
1457 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1458 if (info->icount.brk)
1459 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1460 if (info->icount.overrun)
1461 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1462 }
1463
1464 /* Append serial signal status to end */
1465 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1466
1467 ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1468 info->tx_active,info->bh_requested,info->bh_running,
1469 info->pending_bh);
1470
1471 return ret;
1472 }
1473
1474 /* Called to print information about devices
1475 */
1476 int read_proc(char *page, char **start, off_t off, int count,
1477 int *eof, void *data)
1478 {
1479 int len = 0, l;
1480 off_t begin = 0;
1481 SLMP_INFO *info;
1482
1483 len += sprintf(page, "synclinkmp driver:%s\n", driver_version);
1484
1485 info = synclinkmp_device_list;
1486 while( info ) {
1487 l = line_info(page + len, info);
1488 len += l;
1489 if (len+begin > off+count)
1490 goto done;
1491 if (len+begin < off) {
1492 begin += len;
1493 len = 0;
1494 }
1495 info = info->next_device;
1496 }
1497
1498 *eof = 1;
1499 done:
1500 if (off >= len+begin)
1501 return 0;
1502 *start = page + (off-begin);
1503 return ((count < begin+len-off) ? count : begin+len-off);
1504 }
1505
1506 /* Return the count of bytes in transmit buffer
1507 */
1508 static int chars_in_buffer(struct tty_struct *tty)
1509 {
1510 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1511
1512 if (sanity_check(info, tty->name, "chars_in_buffer"))
1513 return 0;
1514
1515 if (debug_level >= DEBUG_LEVEL_INFO)
1516 printk("%s(%d):%s chars_in_buffer()=%d\n",
1517 __FILE__, __LINE__, info->device_name, info->tx_count);
1518
1519 return info->tx_count;
1520 }
1521
1522 /* Signal remote device to throttle send data (our receive data)
1523 */
1524 static void throttle(struct tty_struct * tty)
1525 {
1526 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1527 unsigned long flags;
1528
1529 if (debug_level >= DEBUG_LEVEL_INFO)
1530 printk("%s(%d):%s throttle() entry\n",
1531 __FILE__,__LINE__, info->device_name );
1532
1533 if (sanity_check(info, tty->name, "throttle"))
1534 return;
1535
1536 if (I_IXOFF(tty))
1537 send_xchar(tty, STOP_CHAR(tty));
1538
1539 if (tty->termios->c_cflag & CRTSCTS) {
1540 spin_lock_irqsave(&info->lock,flags);
1541 info->serial_signals &= ~SerialSignal_RTS;
1542 set_signals(info);
1543 spin_unlock_irqrestore(&info->lock,flags);
1544 }
1545 }
1546
1547 /* Signal remote device to stop throttling send data (our receive data)
1548 */
1549 static void unthrottle(struct tty_struct * tty)
1550 {
1551 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1552 unsigned long flags;
1553
1554 if (debug_level >= DEBUG_LEVEL_INFO)
1555 printk("%s(%d):%s unthrottle() entry\n",
1556 __FILE__,__LINE__, info->device_name );
1557
1558 if (sanity_check(info, tty->name, "unthrottle"))
1559 return;
1560
1561 if (I_IXOFF(tty)) {
1562 if (info->x_char)
1563 info->x_char = 0;
1564 else
1565 send_xchar(tty, START_CHAR(tty));
1566 }
1567
1568 if (tty->termios->c_cflag & CRTSCTS) {
1569 spin_lock_irqsave(&info->lock,flags);
1570 info->serial_signals |= SerialSignal_RTS;
1571 set_signals(info);
1572 spin_unlock_irqrestore(&info->lock,flags);
1573 }
1574 }
1575
1576 /* set or clear transmit break condition
1577 * break_state -1=set break condition, 0=clear
1578 */
1579 static void set_break(struct tty_struct *tty, int break_state)
1580 {
1581 unsigned char RegValue;
1582 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1583 unsigned long flags;
1584
1585 if (debug_level >= DEBUG_LEVEL_INFO)
1586 printk("%s(%d):%s set_break(%d)\n",
1587 __FILE__,__LINE__, info->device_name, break_state);
1588
1589 if (sanity_check(info, tty->name, "set_break"))
1590 return;
1591
1592 spin_lock_irqsave(&info->lock,flags);
1593 RegValue = read_reg(info, CTL);
1594 if (break_state == -1)
1595 RegValue |= BIT3;
1596 else
1597 RegValue &= ~BIT3;
1598 write_reg(info, CTL, RegValue);
1599 spin_unlock_irqrestore(&info->lock,flags);
1600 }
1601
1602 #if SYNCLINK_GENERIC_HDLC
1603
1604 /**
1605 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1606 * set encoding and frame check sequence (FCS) options
1607 *
1608 * dev pointer to network device structure
1609 * encoding serial encoding setting
1610 * parity FCS setting
1611 *
1612 * returns 0 if success, otherwise error code
1613 */
1614 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1615 unsigned short parity)
1616 {
1617 SLMP_INFO *info = dev_to_port(dev);
1618 unsigned char new_encoding;
1619 unsigned short new_crctype;
1620
1621 /* return error if TTY interface open */
1622 if (info->count)
1623 return -EBUSY;
1624
1625 switch (encoding)
1626 {
1627 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1628 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1629 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1630 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1631 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1632 default: return -EINVAL;
1633 }
1634
1635 switch (parity)
1636 {
1637 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1638 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1639 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1640 default: return -EINVAL;
1641 }
1642
1643 info->params.encoding = new_encoding;
1644 info->params.crc_type = new_crctype;
1645
1646 /* if network interface up, reprogram hardware */
1647 if (info->netcount)
1648 program_hw(info);
1649
1650 return 0;
1651 }
1652
1653 /**
1654 * called by generic HDLC layer to send frame
1655 *
1656 * skb socket buffer containing HDLC frame
1657 * dev pointer to network device structure
1658 *
1659 * returns 0 if success, otherwise error code
1660 */
1661 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1662 {
1663 SLMP_INFO *info = dev_to_port(dev);
1664 struct net_device_stats *stats = hdlc_stats(dev);
1665 unsigned long flags;
1666
1667 if (debug_level >= DEBUG_LEVEL_INFO)
1668 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1669
1670 /* stop sending until this frame completes */
1671 netif_stop_queue(dev);
1672
1673 /* copy data to device buffers */
1674 info->tx_count = skb->len;
1675 tx_load_dma_buffer(info, skb->data, skb->len);
1676
1677 /* update network statistics */
1678 stats->tx_packets++;
1679 stats->tx_bytes += skb->len;
1680
1681 /* done with socket buffer, so free it */
1682 dev_kfree_skb(skb);
1683
1684 /* save start time for transmit timeout detection */
1685 dev->trans_start = jiffies;
1686
1687 /* start hardware transmitter if necessary */
1688 spin_lock_irqsave(&info->lock,flags);
1689 if (!info->tx_active)
1690 tx_start(info);
1691 spin_unlock_irqrestore(&info->lock,flags);
1692
1693 return 0;
1694 }
1695
1696 /**
1697 * called by network layer when interface enabled
1698 * claim resources and initialize hardware
1699 *
1700 * dev pointer to network device structure
1701 *
1702 * returns 0 if success, otherwise error code
1703 */
1704 static int hdlcdev_open(struct net_device *dev)
1705 {
1706 SLMP_INFO *info = dev_to_port(dev);
1707 int rc;
1708 unsigned long flags;
1709
1710 if (debug_level >= DEBUG_LEVEL_INFO)
1711 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1712
1713 /* generic HDLC layer open processing */
1714 if ((rc = hdlc_open(dev)))
1715 return rc;
1716
1717 /* arbitrate between network and tty opens */
1718 spin_lock_irqsave(&info->netlock, flags);
1719 if (info->count != 0 || info->netcount != 0) {
1720 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1721 spin_unlock_irqrestore(&info->netlock, flags);
1722 return -EBUSY;
1723 }
1724 info->netcount=1;
1725 spin_unlock_irqrestore(&info->netlock, flags);
1726
1727 /* claim resources and init adapter */
1728 if ((rc = startup(info)) != 0) {
1729 spin_lock_irqsave(&info->netlock, flags);
1730 info->netcount=0;
1731 spin_unlock_irqrestore(&info->netlock, flags);
1732 return rc;
1733 }
1734
1735 /* assert DTR and RTS, apply hardware settings */
1736 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1737 program_hw(info);
1738
1739 /* enable network layer transmit */
1740 dev->trans_start = jiffies;
1741 netif_start_queue(dev);
1742
1743 /* inform generic HDLC layer of current DCD status */
1744 spin_lock_irqsave(&info->lock, flags);
1745 get_signals(info);
1746 spin_unlock_irqrestore(&info->lock, flags);
1747 if (info->serial_signals & SerialSignal_DCD)
1748 netif_carrier_on(dev);
1749 else
1750 netif_carrier_off(dev);
1751 return 0;
1752 }
1753
1754 /**
1755 * called by network layer when interface is disabled
1756 * shutdown hardware and release resources
1757 *
1758 * dev pointer to network device structure
1759 *
1760 * returns 0 if success, otherwise error code
1761 */
1762 static int hdlcdev_close(struct net_device *dev)
1763 {
1764 SLMP_INFO *info = dev_to_port(dev);
1765 unsigned long flags;
1766
1767 if (debug_level >= DEBUG_LEVEL_INFO)
1768 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1769
1770 netif_stop_queue(dev);
1771
1772 /* shutdown adapter and release resources */
1773 shutdown(info);
1774
1775 hdlc_close(dev);
1776
1777 spin_lock_irqsave(&info->netlock, flags);
1778 info->netcount=0;
1779 spin_unlock_irqrestore(&info->netlock, flags);
1780
1781 return 0;
1782 }
1783
1784 /**
1785 * called by network layer to process IOCTL call to network device
1786 *
1787 * dev pointer to network device structure
1788 * ifr pointer to network interface request structure
1789 * cmd IOCTL command code
1790 *
1791 * returns 0 if success, otherwise error code
1792 */
1793 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1794 {
1795 const size_t size = sizeof(sync_serial_settings);
1796 sync_serial_settings new_line;
1797 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1798 SLMP_INFO *info = dev_to_port(dev);
1799 unsigned int flags;
1800
1801 if (debug_level >= DEBUG_LEVEL_INFO)
1802 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1803
1804 /* return error if TTY interface open */
1805 if (info->count)
1806 return -EBUSY;
1807
1808 if (cmd != SIOCWANDEV)
1809 return hdlc_ioctl(dev, ifr, cmd);
1810
1811 switch(ifr->ifr_settings.type) {
1812 case IF_GET_IFACE: /* return current sync_serial_settings */
1813
1814 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1815 if (ifr->ifr_settings.size < size) {
1816 ifr->ifr_settings.size = size; /* data size wanted */
1817 return -ENOBUFS;
1818 }
1819
1820 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1821 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1822 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1823 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1824
1825 switch (flags){
1826 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1827 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1828 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1829 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1830 default: new_line.clock_type = CLOCK_DEFAULT;
1831 }
1832
1833 new_line.clock_rate = info->params.clock_speed;
1834 new_line.loopback = info->params.loopback ? 1:0;
1835
1836 if (copy_to_user(line, &new_line, size))
1837 return -EFAULT;
1838 return 0;
1839
1840 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1841
1842 if(!capable(CAP_NET_ADMIN))
1843 return -EPERM;
1844 if (copy_from_user(&new_line, line, size))
1845 return -EFAULT;
1846
1847 switch (new_line.clock_type)
1848 {
1849 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1850 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1851 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1852 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1853 case CLOCK_DEFAULT: flags = info->params.flags &
1854 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1855 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1856 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1857 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1858 default: return -EINVAL;
1859 }
1860
1861 if (new_line.loopback != 0 && new_line.loopback != 1)
1862 return -EINVAL;
1863
1864 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1865 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1866 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1867 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1868 info->params.flags |= flags;
1869
1870 info->params.loopback = new_line.loopback;
1871
1872 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1873 info->params.clock_speed = new_line.clock_rate;
1874 else
1875 info->params.clock_speed = 0;
1876
1877 /* if network interface up, reprogram hardware */
1878 if (info->netcount)
1879 program_hw(info);
1880 return 0;
1881
1882 default:
1883 return hdlc_ioctl(dev, ifr, cmd);
1884 }
1885 }
1886
1887 /**
1888 * called by network layer when transmit timeout is detected
1889 *
1890 * dev pointer to network device structure
1891 */
1892 static void hdlcdev_tx_timeout(struct net_device *dev)
1893 {
1894 SLMP_INFO *info = dev_to_port(dev);
1895 struct net_device_stats *stats = hdlc_stats(dev);
1896 unsigned long flags;
1897
1898 if (debug_level >= DEBUG_LEVEL_INFO)
1899 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1900
1901 stats->tx_errors++;
1902 stats->tx_aborted_errors++;
1903
1904 spin_lock_irqsave(&info->lock,flags);
1905 tx_stop(info);
1906 spin_unlock_irqrestore(&info->lock,flags);
1907
1908 netif_wake_queue(dev);
1909 }
1910
1911 /**
1912 * called by device driver when transmit completes
1913 * reenable network layer transmit if stopped
1914 *
1915 * info pointer to device instance information
1916 */
1917 static void hdlcdev_tx_done(SLMP_INFO *info)
1918 {
1919 if (netif_queue_stopped(info->netdev))
1920 netif_wake_queue(info->netdev);
1921 }
1922
1923 /**
1924 * called by device driver when frame received
1925 * pass frame to network layer
1926 *
1927 * info pointer to device instance information
1928 * buf pointer to buffer contianing frame data
1929 * size count of data bytes in buf
1930 */
1931 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1932 {
1933 struct sk_buff *skb = dev_alloc_skb(size);
1934 struct net_device *dev = info->netdev;
1935 struct net_device_stats *stats = hdlc_stats(dev);
1936
1937 if (debug_level >= DEBUG_LEVEL_INFO)
1938 printk("hdlcdev_rx(%s)\n",dev->name);
1939
1940 if (skb == NULL) {
1941 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
1942 stats->rx_dropped++;
1943 return;
1944 }
1945
1946 memcpy(skb_put(skb, size),buf,size);
1947
1948 skb->protocol = hdlc_type_trans(skb, info->netdev);
1949
1950 stats->rx_packets++;
1951 stats->rx_bytes += size;
1952
1953 netif_rx(skb);
1954
1955 info->netdev->last_rx = jiffies;
1956 }
1957
1958 /**
1959 * called by device driver when adding device instance
1960 * do generic HDLC initialization
1961 *
1962 * info pointer to device instance information
1963 *
1964 * returns 0 if success, otherwise error code
1965 */
1966 static int hdlcdev_init(SLMP_INFO *info)
1967 {
1968 int rc;
1969 struct net_device *dev;
1970 hdlc_device *hdlc;
1971
1972 /* allocate and initialize network and HDLC layer objects */
1973
1974 if (!(dev = alloc_hdlcdev(info))) {
1975 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1976 return -ENOMEM;
1977 }
1978
1979 /* for network layer reporting purposes only */
1980 dev->mem_start = info->phys_sca_base;
1981 dev->mem_end = info->phys_sca_base + SCA_BASE_SIZE - 1;
1982 dev->irq = info->irq_level;
1983
1984 /* network layer callbacks and settings */
1985 dev->do_ioctl = hdlcdev_ioctl;
1986 dev->open = hdlcdev_open;
1987 dev->stop = hdlcdev_close;
1988 dev->tx_timeout = hdlcdev_tx_timeout;
1989 dev->watchdog_timeo = 10*HZ;
1990 dev->tx_queue_len = 50;
1991
1992 /* generic HDLC layer callbacks and settings */
1993 hdlc = dev_to_hdlc(dev);
1994 hdlc->attach = hdlcdev_attach;
1995 hdlc->xmit = hdlcdev_xmit;
1996
1997 /* register objects with HDLC layer */
1998 if ((rc = register_hdlc_device(dev))) {
1999 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
2000 free_netdev(dev);
2001 return rc;
2002 }
2003
2004 info->netdev = dev;
2005 return 0;
2006 }
2007
2008 /**
2009 * called by device driver when removing device instance
2010 * do generic HDLC cleanup
2011 *
2012 * info pointer to device instance information
2013 */
2014 static void hdlcdev_exit(SLMP_INFO *info)
2015 {
2016 unregister_hdlc_device(info->netdev);
2017 free_netdev(info->netdev);
2018 info->netdev = NULL;
2019 }
2020
2021 #endif /* CONFIG_HDLC */
2022
2023
2024 /* Return next bottom half action to perform.
2025 * Return Value: BH action code or 0 if nothing to do.
2026 */
2027 int bh_action(SLMP_INFO *info)
2028 {
2029 unsigned long flags;
2030 int rc = 0;
2031
2032 spin_lock_irqsave(&info->lock,flags);
2033
2034 if (info->pending_bh & BH_RECEIVE) {
2035 info->pending_bh &= ~BH_RECEIVE;
2036 rc = BH_RECEIVE;
2037 } else if (info->pending_bh & BH_TRANSMIT) {
2038 info->pending_bh &= ~BH_TRANSMIT;
2039 rc = BH_TRANSMIT;
2040 } else if (info->pending_bh & BH_STATUS) {
2041 info->pending_bh &= ~BH_STATUS;
2042 rc = BH_STATUS;
2043 }
2044
2045 if (!rc) {
2046 /* Mark BH routine as complete */
2047 info->bh_running = 0;
2048 info->bh_requested = 0;
2049 }
2050
2051 spin_unlock_irqrestore(&info->lock,flags);
2052
2053 return rc;
2054 }
2055
2056 /* Perform bottom half processing of work items queued by ISR.
2057 */
2058 void bh_handler(struct work_struct *work)
2059 {
2060 SLMP_INFO *info = container_of(work, SLMP_INFO, task);
2061 int action;
2062
2063 if (!info)
2064 return;
2065
2066 if ( debug_level >= DEBUG_LEVEL_BH )
2067 printk( "%s(%d):%s bh_handler() entry\n",
2068 __FILE__,__LINE__,info->device_name);
2069
2070 info->bh_running = 1;
2071
2072 while((action = bh_action(info)) != 0) {
2073
2074 /* Process work item */
2075 if ( debug_level >= DEBUG_LEVEL_BH )
2076 printk( "%s(%d):%s bh_handler() work item action=%d\n",
2077 __FILE__,__LINE__,info->device_name, action);
2078
2079 switch (action) {
2080
2081 case BH_RECEIVE:
2082 bh_receive(info);
2083 break;
2084 case BH_TRANSMIT:
2085 bh_transmit(info);
2086 break;
2087 case BH_STATUS:
2088 bh_status(info);
2089 break;
2090 default:
2091 /* unknown work item ID */
2092 printk("%s(%d):%s Unknown work item ID=%08X!\n",
2093 __FILE__,__LINE__,info->device_name,action);
2094 break;
2095 }
2096 }
2097
2098 if ( debug_level >= DEBUG_LEVEL_BH )
2099 printk( "%s(%d):%s bh_handler() exit\n",
2100 __FILE__,__LINE__,info->device_name);
2101 }
2102
2103 void bh_receive(SLMP_INFO *info)
2104 {
2105 if ( debug_level >= DEBUG_LEVEL_BH )
2106 printk( "%s(%d):%s bh_receive()\n",
2107 __FILE__,__LINE__,info->device_name);
2108
2109 while( rx_get_frame(info) );
2110 }
2111
2112 void bh_transmit(SLMP_INFO *info)
2113 {
2114 struct tty_struct *tty = info->tty;
2115
2116 if ( debug_level >= DEBUG_LEVEL_BH )
2117 printk( "%s(%d):%s bh_transmit() entry\n",
2118 __FILE__,__LINE__,info->device_name);
2119
2120 if (tty)
2121 tty_wakeup(tty);
2122 }
2123
2124 void bh_status(SLMP_INFO *info)
2125 {
2126 if ( debug_level >= DEBUG_LEVEL_BH )
2127 printk( "%s(%d):%s bh_status() entry\n",
2128 __FILE__,__LINE__,info->device_name);
2129
2130 info->ri_chkcount = 0;
2131 info->dsr_chkcount = 0;
2132 info->dcd_chkcount = 0;
2133 info->cts_chkcount = 0;
2134 }
2135
2136 void isr_timer(SLMP_INFO * info)
2137 {
2138 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2139
2140 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2141 write_reg(info, IER2, 0);
2142
2143 /* TMCS, Timer Control/Status Register
2144 *
2145 * 07 CMF, Compare match flag (read only) 1=match
2146 * 06 ECMI, CMF Interrupt Enable: 0=disabled
2147 * 05 Reserved, must be 0
2148 * 04 TME, Timer Enable
2149 * 03..00 Reserved, must be 0
2150 *
2151 * 0000 0000
2152 */
2153 write_reg(info, (unsigned char)(timer + TMCS), 0);
2154
2155 info->irq_occurred = TRUE;
2156
2157 if ( debug_level >= DEBUG_LEVEL_ISR )
2158 printk("%s(%d):%s isr_timer()\n",
2159 __FILE__,__LINE__,info->device_name);
2160 }
2161
2162 void isr_rxint(SLMP_INFO * info)
2163 {
2164 struct tty_struct *tty = info->tty;
2165 struct mgsl_icount *icount = &info->icount;
2166 unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2167 unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2168
2169 /* clear status bits */
2170 if (status)
2171 write_reg(info, SR1, status);
2172
2173 if (status2)
2174 write_reg(info, SR2, status2);
2175
2176 if ( debug_level >= DEBUG_LEVEL_ISR )
2177 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2178 __FILE__,__LINE__,info->device_name,status,status2);
2179
2180 if (info->params.mode == MGSL_MODE_ASYNC) {
2181 if (status & BRKD) {
2182 icount->brk++;
2183
2184 /* process break detection if tty control
2185 * is not set to ignore it
2186 */
2187 if ( tty ) {
2188 if (!(status & info->ignore_status_mask1)) {
2189 if (info->read_status_mask1 & BRKD) {
2190 tty_insert_flip_char(tty, 0, TTY_BREAK);
2191 if (info->flags & ASYNC_SAK)
2192 do_SAK(tty);
2193 }
2194 }
2195 }
2196 }
2197 }
2198 else {
2199 if (status & (FLGD|IDLD)) {
2200 if (status & FLGD)
2201 info->icount.exithunt++;
2202 else if (status & IDLD)
2203 info->icount.rxidle++;
2204 wake_up_interruptible(&info->event_wait_q);
2205 }
2206 }
2207
2208 if (status & CDCD) {
2209 /* simulate a common modem status change interrupt
2210 * for our handler
2211 */
2212 get_signals( info );
2213 isr_io_pin(info,
2214 MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2215 }
2216 }
2217
2218 /*
2219 * handle async rx data interrupts
2220 */
2221 void isr_rxrdy(SLMP_INFO * info)
2222 {
2223 u16 status;
2224 unsigned char DataByte;
2225 struct tty_struct *tty = info->tty;
2226 struct mgsl_icount *icount = &info->icount;
2227
2228 if ( debug_level >= DEBUG_LEVEL_ISR )
2229 printk("%s(%d):%s isr_rxrdy\n",
2230 __FILE__,__LINE__,info->device_name);
2231
2232 while((status = read_reg(info,CST0)) & BIT0)
2233 {
2234 int flag = 0;
2235 int over = 0;
2236 DataByte = read_reg(info,TRB);
2237
2238 icount->rx++;
2239
2240 if ( status & (PE + FRME + OVRN) ) {
2241 printk("%s(%d):%s rxerr=%04X\n",
2242 __FILE__,__LINE__,info->device_name,status);
2243
2244 /* update error statistics */
2245 if (status & PE)
2246 icount->parity++;
2247 else if (status & FRME)
2248 icount->frame++;
2249 else if (status & OVRN)
2250 icount->overrun++;
2251
2252 /* discard char if tty control flags say so */
2253 if (status & info->ignore_status_mask2)
2254 continue;
2255
2256 status &= info->read_status_mask2;
2257
2258 if ( tty ) {
2259 if (status & PE)
2260 flag = TTY_PARITY;
2261 else if (status & FRME)
2262 flag = TTY_FRAME;
2263 if (status & OVRN) {
2264 /* Overrun is special, since it's
2265 * reported immediately, and doesn't
2266 * affect the current character
2267 */
2268 over = 1;
2269 }
2270 }
2271 } /* end of if (error) */
2272
2273 if ( tty ) {
2274 tty_insert_flip_char(tty, DataByte, flag);
2275 if (over)
2276 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
2277 }
2278 }
2279
2280 if ( debug_level >= DEBUG_LEVEL_ISR ) {
2281 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2282 __FILE__,__LINE__,info->device_name,
2283 icount->rx,icount->brk,icount->parity,
2284 icount->frame,icount->overrun);
2285 }
2286
2287 if ( tty )
2288 tty_flip_buffer_push(tty);
2289 }
2290
2291 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2292 {
2293 if ( debug_level >= DEBUG_LEVEL_ISR )
2294 printk("%s(%d):%s isr_txeom status=%02x\n",
2295 __FILE__,__LINE__,info->device_name,status);
2296
2297 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2298 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2299 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2300
2301 if (status & UDRN) {
2302 write_reg(info, CMD, TXRESET);
2303 write_reg(info, CMD, TXENABLE);
2304 } else
2305 write_reg(info, CMD, TXBUFCLR);
2306
2307 /* disable and clear tx interrupts */
2308 info->ie0_value &= ~TXRDYE;
2309 info->ie1_value &= ~(IDLE + UDRN);
2310 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2311 write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2312
2313 if ( info->tx_active ) {
2314 if (info->params.mode != MGSL_MODE_ASYNC) {
2315 if (status & UDRN)
2316 info->icount.txunder++;
2317 else if (status & IDLE)
2318 info->icount.txok++;
2319 }
2320
2321 info->tx_active = 0;
2322 info->tx_count = info->tx_put = info->tx_get = 0;
2323
2324 del_timer(&info->tx_timer);
2325
2326 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2327 info->serial_signals &= ~SerialSignal_RTS;
2328 info->drop_rts_on_tx_done = 0;
2329 set_signals(info);
2330 }
2331
2332 #if SYNCLINK_GENERIC_HDLC
2333 if (info->netcount)
2334 hdlcdev_tx_done(info);
2335 else
2336 #endif
2337 {
2338 if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2339 tx_stop(info);
2340 return;
2341 }
2342 info->pending_bh |= BH_TRANSMIT;
2343 }
2344 }
2345 }
2346
2347
2348 /*
2349 * handle tx status interrupts
2350 */
2351 void isr_txint(SLMP_INFO * info)
2352 {
2353 unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2354
2355 /* clear status bits */
2356 write_reg(info, SR1, status);
2357
2358 if ( debug_level >= DEBUG_LEVEL_ISR )
2359 printk("%s(%d):%s isr_txint status=%02x\n",
2360 __FILE__,__LINE__,info->device_name,status);
2361
2362 if (status & (UDRN + IDLE))
2363 isr_txeom(info, status);
2364
2365 if (status & CCTS) {
2366 /* simulate a common modem status change interrupt
2367 * for our handler
2368 */
2369 get_signals( info );
2370 isr_io_pin(info,
2371 MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2372
2373 }
2374 }
2375
2376 /*
2377 * handle async tx data interrupts
2378 */
2379 void isr_txrdy(SLMP_INFO * info)
2380 {
2381 if ( debug_level >= DEBUG_LEVEL_ISR )
2382 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2383 __FILE__,__LINE__,info->device_name,info->tx_count);
2384
2385 if (info->params.mode != MGSL_MODE_ASYNC) {
2386 /* disable TXRDY IRQ, enable IDLE IRQ */
2387 info->ie0_value &= ~TXRDYE;
2388 info->ie1_value |= IDLE;
2389 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2390 return;
2391 }
2392
2393 if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2394 tx_stop(info);
2395 return;
2396 }
2397
2398 if ( info->tx_count )
2399 tx_load_fifo( info );
2400 else {
2401 info->tx_active = 0;
2402 info->ie0_value &= ~TXRDYE;
2403 write_reg(info, IE0, info->ie0_value);
2404 }
2405
2406 if (info->tx_count < WAKEUP_CHARS)
2407 info->pending_bh |= BH_TRANSMIT;
2408 }
2409
2410 void isr_rxdmaok(SLMP_INFO * info)
2411 {
2412 /* BIT7 = EOT (end of transfer)
2413 * BIT6 = EOM (end of message/frame)
2414 */
2415 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2416
2417 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2418 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2419
2420 if ( debug_level >= DEBUG_LEVEL_ISR )
2421 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2422 __FILE__,__LINE__,info->device_name,status);
2423
2424 info->pending_bh |= BH_RECEIVE;
2425 }
2426
2427 void isr_rxdmaerror(SLMP_INFO * info)
2428 {
2429 /* BIT5 = BOF (buffer overflow)
2430 * BIT4 = COF (counter overflow)
2431 */
2432 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2433
2434 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2435 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2436
2437 if ( debug_level >= DEBUG_LEVEL_ISR )
2438 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2439 __FILE__,__LINE__,info->device_name,status);
2440
2441 info->rx_overflow = TRUE;
2442 info->pending_bh |= BH_RECEIVE;
2443 }
2444
2445 void isr_txdmaok(SLMP_INFO * info)
2446 {
2447 unsigned char status_reg1 = read_reg(info, SR1);
2448
2449 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2450 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2451 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2452
2453 if ( debug_level >= DEBUG_LEVEL_ISR )
2454 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2455 __FILE__,__LINE__,info->device_name,status_reg1);
2456
2457 /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2458 write_reg16(info, TRC0, 0);
2459 info->ie0_value |= TXRDYE;
2460 write_reg(info, IE0, info->ie0_value);
2461 }
2462
2463 void isr_txdmaerror(SLMP_INFO * info)
2464 {
2465 /* BIT5 = BOF (buffer overflow)
2466 * BIT4 = COF (counter overflow)
2467 */
2468 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2469
2470 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2471 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2472
2473 if ( debug_level >= DEBUG_LEVEL_ISR )
2474 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2475 __FILE__,__LINE__,info->device_name,status);
2476 }
2477
2478 /* handle input serial signal changes
2479 */
2480 void isr_io_pin( SLMP_INFO *info, u16 status )
2481 {
2482 struct mgsl_icount *icount;
2483
2484 if ( debug_level >= DEBUG_LEVEL_ISR )
2485 printk("%s(%d):isr_io_pin status=%04X\n",
2486 __FILE__,__LINE__,status);
2487
2488 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2489 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2490 icount = &info->icount;
2491 /* update input line counters */
2492 if (status & MISCSTATUS_RI_LATCHED) {
2493 icount->rng++;
2494 if ( status & SerialSignal_RI )
2495 info->input_signal_events.ri_up++;
2496 else
2497 info->input_signal_events.ri_down++;
2498 }
2499 if (status & MISCSTATUS_DSR_LATCHED) {
2500 icount->dsr++;
2501 if ( status & SerialSignal_DSR )
2502 info->input_signal_events.dsr_up++;
2503 else
2504 info->input_signal_events.dsr_down++;
2505 }
2506 if (status & MISCSTATUS_DCD_LATCHED) {
2507 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2508 info->ie1_value &= ~CDCD;
2509 write_reg(info, IE1, info->ie1_value);
2510 }
2511 icount->dcd++;
2512 if (status & SerialSignal_DCD) {
2513 info->input_signal_events.dcd_up++;
2514 } else
2515 info->input_signal_events.dcd_down++;
2516 #if SYNCLINK_GENERIC_HDLC
2517 if (info->netcount) {
2518 if (status & SerialSignal_DCD)
2519 netif_carrier_on(info->netdev);
2520 else
2521 netif_carrier_off(info->netdev);
2522 }
2523 #endif
2524 }
2525 if (status & MISCSTATUS_CTS_LATCHED)
2526 {
2527 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2528 info->ie1_value &= ~CCTS;
2529 write_reg(info, IE1, info->ie1_value);
2530 }
2531 icount->cts++;
2532 if ( status & SerialSignal_CTS )
2533 info->input_signal_events.cts_up++;
2534 else
2535 info->input_signal_events.cts_down++;
2536 }
2537 wake_up_interruptible(&info->status_event_wait_q);
2538 wake_up_interruptible(&info->event_wait_q);
2539
2540 if ( (info->flags & ASYNC_CHECK_CD) &&
2541 (status & MISCSTATUS_DCD_LATCHED) ) {
2542 if ( debug_level >= DEBUG_LEVEL_ISR )
2543 printk("%s CD now %s...", info->device_name,
2544 (status & SerialSignal_DCD) ? "on" : "off");
2545 if (status & SerialSignal_DCD)
2546 wake_up_interruptible(&info->open_wait);
2547 else {
2548 if ( debug_level >= DEBUG_LEVEL_ISR )
2549 printk("doing serial hangup...");
2550 if (info->tty)
2551 tty_hangup(info->tty);
2552 }
2553 }
2554
2555 if ( (info->flags & ASYNC_CTS_FLOW) &&
2556 (status & MISCSTATUS_CTS_LATCHED) ) {
2557 if ( info->tty ) {
2558 if (info->tty->hw_stopped) {
2559 if (status & SerialSignal_CTS) {
2560 if ( debug_level >= DEBUG_LEVEL_ISR )
2561 printk("CTS tx start...");
2562 info->tty->hw_stopped = 0;
2563 tx_start(info);
2564 info->pending_bh |= BH_TRANSMIT;
2565 return;
2566 }
2567 } else {
2568 if (!(status & SerialSignal_CTS)) {
2569 if ( debug_level >= DEBUG_LEVEL_ISR )
2570 printk("CTS tx stop...");
2571 info->tty->hw_stopped = 1;
2572 tx_stop(info);
2573 }
2574 }
2575 }
2576 }
2577 }
2578
2579 info->pending_bh |= BH_STATUS;
2580 }
2581
2582 /* Interrupt service routine entry point.
2583 *
2584 * Arguments:
2585 * irq interrupt number that caused interrupt
2586 * dev_id device ID supplied during interrupt registration
2587 * regs interrupted processor context
2588 */
2589 static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
2590 {
2591 SLMP_INFO *info = dev_id;
2592 unsigned char status, status0, status1=0;
2593 unsigned char dmastatus, dmastatus0, dmastatus1=0;
2594 unsigned char timerstatus0, timerstatus1=0;
2595 unsigned char shift;
2596 unsigned int i;
2597 unsigned short tmp;
2598
2599 if ( debug_level >= DEBUG_LEVEL_ISR )
2600 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2601 __FILE__, __LINE__, info->irq_level);
2602
2603 spin_lock(&info->lock);
2604
2605 for(;;) {
2606
2607 /* get status for SCA0 (ports 0-1) */
2608 tmp = read_reg16(info, ISR0); /* get ISR0 and ISR1 in one read */
2609 status0 = (unsigned char)tmp;
2610 dmastatus0 = (unsigned char)(tmp>>8);
2611 timerstatus0 = read_reg(info, ISR2);
2612
2613 if ( debug_level >= DEBUG_LEVEL_ISR )
2614 printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2615 __FILE__, __LINE__, info->device_name,
2616 status0, dmastatus0, timerstatus0);
2617
2618 if (info->port_count == 4) {
2619 /* get status for SCA1 (ports 2-3) */
2620 tmp = read_reg16(info->port_array[2], ISR0);
2621 status1 = (unsigned char)tmp;
2622 dmastatus1 = (unsigned char)(tmp>>8);
2623 timerstatus1 = read_reg(info->port_array[2], ISR2);
2624
2625 if ( debug_level >= DEBUG_LEVEL_ISR )
2626 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2627 __FILE__,__LINE__,info->device_name,
2628 status1,dmastatus1,timerstatus1);
2629 }
2630
2631 if (!status0 && !dmastatus0 && !timerstatus0 &&
2632 !status1 && !dmastatus1 && !timerstatus1)
2633 break;
2634
2635 for(i=0; i < info->port_count ; i++) {
2636 if (info->port_array[i] == NULL)
2637 continue;
2638 if (i < 2) {
2639 status = status0;
2640 dmastatus = dmastatus0;
2641 } else {
2642 status = status1;
2643 dmastatus = dmastatus1;
2644 }
2645
2646 shift = i & 1 ? 4 :0;
2647
2648 if (status & BIT0 << shift)
2649 isr_rxrdy(info->port_array[i]);
2650 if (status & BIT1 << shift)
2651 isr_txrdy(info->port_array[i]);
2652 if (status & BIT2 << shift)
2653 isr_rxint(info->port_array[i]);
2654 if (status & BIT3 << shift)
2655 isr_txint(info->port_array[i]);
2656
2657 if (dmastatus & BIT0 << shift)
2658 isr_rxdmaerror(info->port_array[i]);
2659 if (dmastatus & BIT1 << shift)
2660 isr_rxdmaok(info->port_array[i]);
2661 if (dmastatus & BIT2 << shift)
2662 isr_txdmaerror(info->port_array[i]);
2663 if (dmastatus & BIT3 << shift)
2664 isr_txdmaok(info->port_array[i]);
2665 }
2666
2667 if (timerstatus0 & (BIT5 | BIT4))
2668 isr_timer(info->port_array[0]);
2669 if (timerstatus0 & (BIT7 | BIT6))
2670 isr_timer(info->port_array[1]);
2671 if (timerstatus1 & (BIT5 | BIT4))
2672 isr_timer(info->port_array[2]);
2673 if (timerstatus1 & (BIT7 | BIT6))
2674 isr_timer(info->port_array[3]);
2675 }
2676
2677 for(i=0; i < info->port_count ; i++) {
2678 SLMP_INFO * port = info->port_array[i];
2679
2680 /* Request bottom half processing if there's something
2681 * for it to do and the bh is not already running.
2682 *
2683 * Note: startup adapter diags require interrupts.
2684 * do not request bottom half processing if the
2685 * device is not open in a normal mode.
2686 */
2687 if ( port && (port->count || port->netcount) &&
2688 port->pending_bh && !port->bh_running &&
2689 !port->bh_requested ) {
2690 if ( debug_level >= DEBUG_LEVEL_ISR )
2691 printk("%s(%d):%s queueing bh task.\n",
2692 __FILE__,__LINE__,port->device_name);
2693 schedule_work(&port->task);
2694 port->bh_requested = 1;
2695 }
2696 }
2697
2698 spin_unlock(&info->lock);
2699
2700 if ( debug_level >= DEBUG_LEVEL_ISR )
2701 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2702 __FILE__, __LINE__, info->irq_level);
2703 return IRQ_HANDLED;
2704 }
2705
2706 /* Initialize and start device.
2707 */
2708 static int startup(SLMP_INFO * info)
2709 {
2710 if ( debug_level >= DEBUG_LEVEL_INFO )
2711 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2712
2713 if (info->flags & ASYNC_INITIALIZED)
2714 return 0;
2715
2716 if (!info->tx_buf) {
2717 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2718 if (!info->tx_buf) {
2719 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2720 __FILE__,__LINE__,info->device_name);
2721 return -ENOMEM;
2722 }
2723 }
2724
2725 info->pending_bh = 0;
2726
2727 memset(&info->icount, 0, sizeof(info->icount));
2728
2729 /* program hardware for current parameters */
2730 reset_port(info);
2731
2732 change_params(info);
2733
2734 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2735
2736 if (info->tty)
2737 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2738
2739 info->flags |= ASYNC_INITIALIZED;
2740
2741 return 0;
2742 }
2743
2744 /* Called by close() and hangup() to shutdown hardware
2745 */
2746 static void shutdown(SLMP_INFO * info)
2747 {
2748 unsigned long flags;
2749
2750 if (!(info->flags & ASYNC_INITIALIZED))
2751 return;
2752
2753 if (debug_level >= DEBUG_LEVEL_INFO)
2754 printk("%s(%d):%s synclinkmp_shutdown()\n",
2755 __FILE__,__LINE__, info->device_name );
2756
2757 /* clear status wait queue because status changes */
2758 /* can't happen after shutting down the hardware */
2759 wake_up_interruptible(&info->status_event_wait_q);
2760 wake_up_interruptible(&info->event_wait_q);
2761
2762 del_timer(&info->tx_timer);
2763 del_timer(&info->status_timer);
2764
2765 kfree(info->tx_buf);
2766 info->tx_buf = NULL;
2767
2768 spin_lock_irqsave(&info->lock,flags);
2769
2770 reset_port(info);
2771
2772 if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2773 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2774 set_signals(info);
2775 }
2776
2777 spin_unlock_irqrestore(&info->lock,flags);
2778
2779 if (info->tty)
2780 set_bit(TTY_IO_ERROR, &info->tty->flags);
2781
2782 info->flags &= ~ASYNC_INITIALIZED;
2783 }
2784
2785 static void program_hw(SLMP_INFO *info)
2786 {
2787 unsigned long flags;
2788
2789 spin_lock_irqsave(&info->lock,flags);
2790
2791 rx_stop(info);
2792 tx_stop(info);
2793
2794 info->tx_count = info->tx_put = info->tx_get = 0;
2795
2796 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2797 hdlc_mode(info);
2798 else
2799 async_mode(info);
2800
2801 set_signals(info);
2802
2803 info->dcd_chkcount = 0;
2804 info->cts_chkcount = 0;
2805 info->ri_chkcount = 0;
2806 info->dsr_chkcount = 0;
2807
2808 info->ie1_value |= (CDCD|CCTS);
2809 write_reg(info, IE1, info->ie1_value);
2810
2811 get_signals(info);
2812
2813 if (info->netcount || (info->tty && info->tty->termios->c_cflag & CREAD) )
2814 rx_start(info);
2815
2816 spin_unlock_irqrestore(&info->lock,flags);
2817 }
2818
2819 /* Reconfigure adapter based on new parameters
2820 */
2821 static void change_params(SLMP_INFO *info)
2822 {
2823 unsigned cflag;
2824 int bits_per_char;
2825
2826 if (!info->tty || !info->tty->termios)
2827 return;
2828
2829 if (debug_level >= DEBUG_LEVEL_INFO)
2830 printk("%s(%d):%s change_params()\n",
2831 __FILE__,__LINE__, info->device_name );
2832
2833 cflag = info->tty->termios->c_cflag;
2834
2835 /* if B0 rate (hangup) specified then negate DTR and RTS */
2836 /* otherwise assert DTR and RTS */
2837 if (cflag & CBAUD)
2838 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2839 else
2840 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2841
2842 /* byte size and parity */
2843
2844 switch (cflag & CSIZE) {
2845 case CS5: info->params.data_bits = 5; break;
2846 case CS6: info->params.data_bits = 6; break;
2847 case CS7: info->params.data_bits = 7; break;
2848 case CS8: info->params.data_bits = 8; break;
2849 /* Never happens, but GCC is too dumb to figure it out */
2850 default: info->params.data_bits = 7; break;
2851 }
2852
2853 if (cflag & CSTOPB)
2854 info->params.stop_bits = 2;
2855 else
2856 info->params.stop_bits = 1;
2857
2858 info->params.parity = ASYNC_PARITY_NONE;
2859 if (cflag & PARENB) {
2860 if (cflag & PARODD)
2861 info->params.parity = ASYNC_PARITY_ODD;
2862 else
2863 info->params.parity = ASYNC_PARITY_EVEN;
2864 #ifdef CMSPAR
2865 if (cflag & CMSPAR)
2866 info->params.parity = ASYNC_PARITY_SPACE;
2867 #endif
2868 }
2869
2870 /* calculate number of jiffies to transmit a full
2871 * FIFO (32 bytes) at specified data rate
2872 */
2873 bits_per_char = info->params.data_bits +
2874 info->params.stop_bits + 1;
2875
2876 /* if port data rate is set to 460800 or less then
2877 * allow tty settings to override, otherwise keep the
2878 * current data rate.
2879 */
2880 if (info->params.data_rate <= 460800) {
2881 info->params.data_rate = tty_get_baud_rate(info->tty);
2882 }
2883
2884 if ( info->params.data_rate ) {
2885 info->timeout = (32*HZ*bits_per_char) /
2886 info->params.data_rate;
2887 }
2888 info->timeout += HZ/50; /* Add .02 seconds of slop */
2889
2890 if (cflag & CRTSCTS)
2891 info->flags |= ASYNC_CTS_FLOW;
2892 else
2893 info->flags &= ~ASYNC_CTS_FLOW;
2894
2895 if (cflag & CLOCAL)
2896 info->flags &= ~ASYNC_CHECK_CD;
2897 else
2898 info->flags |= ASYNC_CHECK_CD;
2899
2900 /* process tty input control flags */
2901
2902 info->read_status_mask2 = OVRN;
2903 if (I_INPCK(info->tty))
2904 info->read_status_mask2 |= PE | FRME;
2905 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2906 info->read_status_mask1 |= BRKD;
2907 if (I_IGNPAR(info->tty))
2908 info->ignore_status_mask2 |= PE | FRME;
2909 if (I_IGNBRK(info->tty)) {
2910 info->ignore_status_mask1 |= BRKD;
2911 /* If ignoring parity and break indicators, ignore
2912 * overruns too. (For real raw support).
2913 */
2914 if (I_IGNPAR(info->tty))
2915 info->ignore_status_mask2 |= OVRN;
2916 }
2917
2918 program_hw(info);
2919 }
2920
2921 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2922 {
2923 int err;
2924
2925 if (debug_level >= DEBUG_LEVEL_INFO)
2926 printk("%s(%d):%s get_params()\n",
2927 __FILE__,__LINE__, info->device_name);
2928
2929 if (!user_icount) {
2930 memset(&info->icount, 0, sizeof(info->icount));
2931 } else {
2932 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2933 if (err)
2934 return -EFAULT;
2935 }
2936
2937 return 0;
2938 }
2939
2940 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2941 {
2942 int err;
2943 if (debug_level >= DEBUG_LEVEL_INFO)
2944 printk("%s(%d):%s get_params()\n",
2945 __FILE__,__LINE__, info->device_name);
2946
2947 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2948 if (err) {
2949 if ( debug_level >= DEBUG_LEVEL_INFO )
2950 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2951 __FILE__,__LINE__,info->device_name);
2952 return -EFAULT;
2953 }
2954
2955 return 0;
2956 }
2957
2958 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2959 {
2960 unsigned long flags;
2961 MGSL_PARAMS tmp_params;
2962 int err;
2963
2964 if (debug_level >= DEBUG_LEVEL_INFO)
2965 printk("%s(%d):%s set_params\n",
2966 __FILE__,__LINE__,info->device_name );
2967 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2968 if (err) {
2969 if ( debug_level >= DEBUG_LEVEL_INFO )
2970 printk( "%s(%d):%s set_params() user buffer copy failed\n",
2971 __FILE__,__LINE__,info->device_name);
2972 return -EFAULT;
2973 }
2974
2975 spin_lock_irqsave(&info->lock,flags);
2976 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2977 spin_unlock_irqrestore(&info->lock,flags);
2978
2979 change_params(info);
2980
2981 return 0;
2982 }
2983
2984 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2985 {
2986 int err;
2987
2988 if (debug_level >= DEBUG_LEVEL_INFO)
2989 printk("%s(%d):%s get_txidle()=%d\n",
2990 __FILE__,__LINE__, info->device_name, info->idle_mode);
2991
2992 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2993 if (err) {
2994 if ( debug_level >= DEBUG_LEVEL_INFO )
2995 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
2996 __FILE__,__LINE__,info->device_name);
2997 return -EFAULT;
2998 }
2999
3000 return 0;
3001 }
3002
3003 static int set_txidle(SLMP_INFO * info, int idle_mode)
3004 {
3005 unsigned long flags;
3006
3007 if (debug_level >= DEBUG_LEVEL_INFO)
3008 printk("%s(%d):%s set_txidle(%d)\n",
3009 __FILE__,__LINE__,info->device_name, idle_mode );
3010
3011 spin_lock_irqsave(&info->lock,flags);
3012 info->idle_mode = idle_mode;
3013 tx_set_idle( info );
3014 spin_unlock_irqrestore(&info->lock,flags);
3015 return 0;
3016 }
3017
3018 static int tx_enable(SLMP_INFO * info, int enable)
3019 {
3020 unsigned long flags;
3021
3022 if (debug_level >= DEBUG_LEVEL_INFO)
3023 printk("%s(%d):%s tx_enable(%d)\n",
3024 __FILE__,__LINE__,info->device_name, enable);
3025
3026 spin_lock_irqsave(&info->lock,flags);
3027 if ( enable ) {
3028 if ( !info->tx_enabled ) {
3029 tx_start(info);
3030 }
3031 } else {
3032 if ( info->tx_enabled )
3033 tx_stop(info);
3034 }
3035 spin_unlock_irqrestore(&info->lock,flags);
3036 return 0;
3037 }
3038
3039 /* abort send HDLC frame
3040 */
3041 static int tx_abort(SLMP_INFO * info)
3042 {
3043 unsigned long flags;
3044
3045 if (debug_level >= DEBUG_LEVEL_INFO)
3046 printk("%s(%d):%s tx_abort()\n",
3047 __FILE__,__LINE__,info->device_name);
3048
3049 spin_lock_irqsave(&info->lock,flags);
3050 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
3051 info->ie1_value &= ~UDRN;
3052 info->ie1_value |= IDLE;
3053 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
3054 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
3055
3056 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
3057 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3058
3059 write_reg(info, CMD, TXABORT);
3060 }
3061 spin_unlock_irqrestore(&info->lock,flags);
3062 return 0;
3063 }
3064
3065 static int rx_enable(SLMP_INFO * info, int enable)
3066 {
3067 unsigned long flags;
3068
3069 if (debug_level >= DEBUG_LEVEL_INFO)
3070 printk("%s(%d):%s rx_enable(%d)\n",
3071 __FILE__,__LINE__,info->device_name,enable);
3072
3073 spin_lock_irqsave(&info->lock,flags);
3074 if ( enable ) {
3075 if ( !info->rx_enabled )
3076 rx_start(info);
3077 } else {
3078 if ( info->rx_enabled )
3079 rx_stop(info);
3080 }
3081 spin_unlock_irqrestore(&info->lock,flags);
3082 return 0;
3083 }
3084
3085 /* wait for specified event to occur
3086 */
3087 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3088 {
3089 unsigned long flags;
3090 int s;
3091 int rc=0;
3092 struct mgsl_icount cprev, cnow;
3093 int events;
3094 int mask;
3095 struct _input_signal_events oldsigs, newsigs;
3096 DECLARE_WAITQUEUE(wait, current);
3097
3098 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3099 if (rc) {
3100 return -EFAULT;
3101 }
3102
3103 if (debug_level >= DEBUG_LEVEL_INFO)
3104 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3105 __FILE__,__LINE__,info->device_name,mask);
3106
3107 spin_lock_irqsave(&info->lock,flags);
3108
3109 /* return immediately if state matches requested events */
3110 get_signals(info);
3111 s = info->serial_signals;
3112
3113 events = mask &
3114 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3115 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3116 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3117 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3118 if (events) {
3119 spin_unlock_irqrestore(&info->lock,flags);
3120 goto exit;
3121 }
3122
3123 /* save current irq counts */
3124 cprev = info->icount;
3125 oldsigs = info->input_signal_events;
3126
3127 /* enable hunt and idle irqs if needed */
3128 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3129 unsigned char oldval = info->ie1_value;
3130 unsigned char newval = oldval +
3131 (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3132 (mask & MgslEvent_IdleReceived ? IDLD:0);
3133 if ( oldval != newval ) {
3134 info->ie1_value = newval;
3135 write_reg(info, IE1, info->ie1_value);
3136 }
3137 }
3138
3139 set_current_state(TASK_INTERRUPTIBLE);
3140 add_wait_queue(&info->event_wait_q, &wait);
3141
3142 spin_unlock_irqrestore(&info->lock,flags);
3143
3144 for(;;) {
3145 schedule();
3146 if (signal_pending(current)) {
3147 rc = -ERESTARTSYS;
3148 break;
3149 }
3150
3151 /* get current irq counts */
3152 spin_lock_irqsave(&info->lock,flags);
3153 cnow = info->icount;
3154 newsigs = info->input_signal_events;
3155 set_current_state(TASK_INTERRUPTIBLE);
3156 spin_unlock_irqrestore(&info->lock,flags);
3157
3158 /* if no change, wait aborted for some reason */
3159 if (newsigs.dsr_up == oldsigs.dsr_up &&
3160 newsigs.dsr_down == oldsigs.dsr_down &&
3161 newsigs.dcd_up == oldsigs.dcd_up &&
3162 newsigs.dcd_down == oldsigs.dcd_down &&
3163 newsigs.cts_up == oldsigs.cts_up &&
3164 newsigs.cts_down == oldsigs.cts_down &&
3165 newsigs.ri_up == oldsigs.ri_up &&
3166 newsigs.ri_down == oldsigs.ri_down &&
3167 cnow.exithunt == cprev.exithunt &&
3168 cnow.rxidle == cprev.rxidle) {
3169 rc = -EIO;
3170 break;
3171 }
3172
3173 events = mask &
3174 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
3175 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3176 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
3177 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3178 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
3179 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3180 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
3181 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
3182 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
3183 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
3184 if (events)
3185 break;
3186
3187 cprev = cnow;
3188 oldsigs = newsigs;
3189 }
3190
3191 remove_wait_queue(&info->event_wait_q, &wait);
3192 set_current_state(TASK_RUNNING);
3193
3194
3195 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3196 spin_lock_irqsave(&info->lock,flags);
3197 if (!waitqueue_active(&info->event_wait_q)) {
3198 /* disable enable exit hunt mode/idle rcvd IRQs */
3199 info->ie1_value &= ~(FLGD|IDLD);
3200 write_reg(info, IE1, info->ie1_value);
3201 }
3202 spin_unlock_irqrestore(&info->lock,flags);
3203 }
3204 exit:
3205 if ( rc == 0 )
3206 PUT_USER(rc, events, mask_ptr);
3207
3208 return rc;
3209 }
3210
3211 static int modem_input_wait(SLMP_INFO *info,int arg)
3212 {
3213 unsigned long flags;
3214 int rc;
3215 struct mgsl_icount cprev, cnow;
3216 DECLARE_WAITQUEUE(wait, current);
3217
3218 /* save current irq counts */
3219 spin_lock_irqsave(&info->lock,flags);
3220 cprev = info->icount;
3221 add_wait_queue(&info->status_event_wait_q, &wait);
3222 set_current_state(TASK_INTERRUPTIBLE);
3223 spin_unlock_irqrestore(&info->lock,flags);
3224
3225 for(;;) {
3226 schedule();
3227 if (signal_pending(current)) {
3228 rc = -ERESTARTSYS;
3229 break;
3230 }
3231
3232 /* get new irq counts */
3233 spin_lock_irqsave(&info->lock,flags);
3234 cnow = info->icount;
3235 set_current_state(TASK_INTERRUPTIBLE);
3236 spin_unlock_irqrestore(&info->lock,flags);
3237
3238 /* if no change, wait aborted for some reason */
3239 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3240 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3241 rc = -EIO;
3242 break;
3243 }
3244
3245 /* check for change in caller specified modem input */
3246 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3247 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3248 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3249 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3250 rc = 0;
3251 break;
3252 }
3253
3254 cprev = cnow;
3255 }
3256 remove_wait_queue(&info->status_event_wait_q, &wait);
3257 set_current_state(TASK_RUNNING);
3258 return rc;
3259 }
3260
3261 /* return the state of the serial control and status signals
3262 */
3263 static int tiocmget(struct tty_struct *tty, struct file *file)
3264 {
3265 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3266 unsigned int result;
3267 unsigned long flags;
3268
3269 spin_lock_irqsave(&info->lock,flags);
3270 get_signals(info);
3271 spin_unlock_irqrestore(&info->lock,flags);
3272
3273 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3274 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3275 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3276 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3277 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3278 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3279
3280 if (debug_level >= DEBUG_LEVEL_INFO)
3281 printk("%s(%d):%s tiocmget() value=%08X\n",
3282 __FILE__,__LINE__, info->device_name, result );
3283 return result;
3284 }
3285
3286 /* set modem control signals (DTR/RTS)
3287 */
3288 static int tiocmset(struct tty_struct *tty, struct file *file,
3289 unsigned int set, unsigned int clear)
3290 {
3291 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3292 unsigned long flags;
3293
3294 if (debug_level >= DEBUG_LEVEL_INFO)
3295 printk("%s(%d):%s tiocmset(%x,%x)\n",
3296 __FILE__,__LINE__,info->device_name, set, clear);
3297
3298 if (set & TIOCM_RTS)
3299 info->serial_signals |= SerialSignal_RTS;
3300 if (set & TIOCM_DTR)
3301 info->serial_signals |= SerialSignal_DTR;
3302 if (clear & TIOCM_RTS)
3303 info->serial_signals &= ~SerialSignal_RTS;
3304 if (clear & TIOCM_DTR)
3305 info->serial_signals &= ~SerialSignal_DTR;
3306
3307 spin_lock_irqsave(&info->lock,flags);
3308 set_signals(info);
3309 spin_unlock_irqrestore(&info->lock,flags);
3310
3311 return 0;
3312 }
3313
3314
3315
3316 /* Block the current process until the specified port is ready to open.
3317 */
3318 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3319 SLMP_INFO *info)
3320 {
3321 DECLARE_WAITQUEUE(wait, current);
3322 int retval;
3323 int do_clocal = 0, extra_count = 0;
3324 unsigned long flags;
3325
3326 if (debug_level >= DEBUG_LEVEL_INFO)
3327 printk("%s(%d):%s block_til_ready()\n",
3328 __FILE__,__LINE__, tty->driver->name );
3329
3330 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3331 /* nonblock mode is set or port is not enabled */
3332 /* just verify that callout device is not active */
3333 info->flags |= ASYNC_NORMAL_ACTIVE;
3334 return 0;
3335 }
3336
3337 if (tty->termios->c_cflag & CLOCAL)
3338 do_clocal = 1;
3339
3340 /* Wait for carrier detect and the line to become
3341 * free (i.e., not in use by the callout). While we are in
3342 * this loop, info->count is dropped by one, so that
3343 * close() knows when to free things. We restore it upon
3344 * exit, either normal or abnormal.
3345 */
3346
3347 retval = 0;
3348 add_wait_queue(&info->open_wait, &wait);
3349
3350 if (debug_level >= DEBUG_LEVEL_INFO)
3351 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3352 __FILE__,__LINE__, tty->driver->name, info->count );
3353
3354 spin_lock_irqsave(&info->lock, flags);
3355 if (!tty_hung_up_p(filp)) {
3356 extra_count = 1;
3357 info->count--;
3358 }
3359 spin_unlock_irqrestore(&info->lock, flags);
3360 info->blocked_open++;
3361
3362 while (1) {
3363 if ((tty->termios->c_cflag & CBAUD)) {
3364 spin_lock_irqsave(&info->lock,flags);
3365 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3366 set_signals(info);
3367 spin_unlock_irqrestore(&info->lock,flags);
3368 }
3369
3370 set_current_state(TASK_INTERRUPTIBLE);
3371
3372 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3373 retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3374 -EAGAIN : -ERESTARTSYS;
3375 break;
3376 }
3377
3378 spin_lock_irqsave(&info->lock,flags);
3379 get_signals(info);
3380 spin_unlock_irqrestore(&info->lock,flags);
3381
3382 if (!(info->flags & ASYNC_CLOSING) &&
3383 (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3384 break;
3385 }
3386
3387 if (signal_pending(current)) {
3388 retval = -ERESTARTSYS;
3389 break;
3390 }
3391
3392 if (debug_level >= DEBUG_LEVEL_INFO)
3393 printk("%s(%d):%s block_til_ready() count=%d\n",
3394 __FILE__,__LINE__, tty->driver->name, info->count );
3395
3396 schedule();
3397 }
3398
3399 set_current_state(TASK_RUNNING);
3400 remove_wait_queue(&info->open_wait, &wait);
3401
3402 if (extra_count)
3403 info->count++;
3404 info->blocked_open--;
3405
3406 if (debug_level >= DEBUG_LEVEL_INFO)
3407 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3408 __FILE__,__LINE__, tty->driver->name, info->count );
3409
3410 if (!retval)
3411 info->flags |= ASYNC_NORMAL_ACTIVE;
3412
3413 return retval;
3414 }
3415
3416 int alloc_dma_bufs(SLMP_INFO *info)
3417 {
3418 unsigned short BuffersPerFrame;
3419 unsigned short BufferCount;
3420
3421 // Force allocation to start at 64K boundary for each port.
3422 // This is necessary because *all* buffer descriptors for a port
3423 // *must* be in the same 64K block. All descriptors on a port
3424 // share a common 'base' address (upper 8 bits of 24 bits) programmed
3425 // into the CBP register.
3426 info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3427
3428 /* Calculate the number of DMA buffers necessary to hold the */
3429 /* largest allowable frame size. Note: If the max frame size is */
3430 /* not an even multiple of the DMA buffer size then we need to */
3431 /* round the buffer count per frame up one. */
3432
3433 BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3434 if ( info->max_frame_size % SCABUFSIZE )
3435 BuffersPerFrame++;
3436
3437 /* calculate total number of data buffers (SCABUFSIZE) possible
3438 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3439 * for the descriptor list (BUFFERLISTSIZE).
3440 */
3441 BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3442
3443 /* limit number of buffers to maximum amount of descriptors */
3444 if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3445 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3446
3447 /* use enough buffers to transmit one max size frame */
3448 info->tx_buf_count = BuffersPerFrame + 1;
3449
3450 /* never use more than half the available buffers for transmit */
3451 if (info->tx_buf_count > (BufferCount/2))
3452 info->tx_buf_count = BufferCount/2;
3453
3454 if (info->tx_buf_count > SCAMAXDESC)
3455 info->tx_buf_count = SCAMAXDESC;
3456
3457 /* use remaining buffers for receive */
3458 info->rx_buf_count = BufferCount - info->tx_buf_count;
3459
3460 if (info->rx_buf_count > SCAMAXDESC)
3461 info->rx_buf_count = SCAMAXDESC;
3462
3463 if ( debug_level >= DEBUG_LEVEL_INFO )
3464 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3465 __FILE__,__LINE__, info->device_name,
3466 info->tx_buf_count,info->rx_buf_count);
3467
3468 if ( alloc_buf_list( info ) < 0 ||
3469 alloc_frame_bufs(info,
3470 info->rx_buf_list,
3471 info->rx_buf_list_ex,
3472 info->rx_buf_count) < 0 ||
3473 alloc_frame_bufs(info,
3474 info->tx_buf_list,
3475 info->tx_buf_list_ex,
3476 info->tx_buf_count) < 0 ||
3477 alloc_tmp_rx_buf(info) < 0 ) {
3478 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3479 __FILE__,__LINE__, info->device_name);
3480 return -ENOMEM;
3481 }
3482
3483 rx_reset_buffers( info );
3484
3485 return 0;
3486 }
3487
3488 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3489 */
3490 int alloc_buf_list(SLMP_INFO *info)
3491 {
3492 unsigned int i;
3493
3494 /* build list in adapter shared memory */
3495 info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3496 info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3497 info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3498
3499 memset(info->buffer_list, 0, BUFFERLISTSIZE);
3500
3501 /* Save virtual address pointers to the receive and */
3502 /* transmit buffer lists. (Receive 1st). These pointers will */
3503 /* be used by the processor to access the lists. */
3504 info->rx_buf_list = (SCADESC *)info->buffer_list;
3505
3506 info->tx_buf_list = (SCADESC *)info->buffer_list;
3507 info->tx_buf_list += info->rx_buf_count;
3508
3509 /* Build links for circular buffer entry lists (tx and rx)
3510 *
3511 * Note: links are physical addresses read by the SCA device
3512 * to determine the next buffer entry to use.
3513 */
3514
3515 for ( i = 0; i < info->rx_buf_count; i++ ) {
3516 /* calculate and store physical address of this buffer entry */
3517 info->rx_buf_list_ex[i].phys_entry =
3518 info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3519
3520 /* calculate and store physical address of */
3521 /* next entry in cirular list of entries */
3522 info->rx_buf_list[i].next = info->buffer_list_phys;
3523 if ( i < info->rx_buf_count - 1 )
3524 info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3525
3526 info->rx_buf_list[i].length = SCABUFSIZE;
3527 }
3528
3529 for ( i = 0; i < info->tx_buf_count; i++ ) {
3530 /* calculate and store physical address of this buffer entry */
3531 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3532 ((info->rx_buf_count + i) * sizeof(SCADESC));
3533
3534 /* calculate and store physical address of */
3535 /* next entry in cirular list of entries */
3536
3537 info->tx_buf_list[i].next = info->buffer_list_phys +
3538 info->rx_buf_count * sizeof(SCADESC);
3539
3540 if ( i < info->tx_buf_count - 1 )
3541 info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3542 }
3543
3544 return 0;
3545 }
3546
3547 /* Allocate the frame DMA buffers used by the specified buffer list.
3548 */
3549 int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3550 {
3551 int i;
3552 unsigned long phys_addr;
3553
3554 for ( i = 0; i < count; i++ ) {
3555 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3556 phys_addr = info->port_array[0]->last_mem_alloc;
3557 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3558
3559 buf_list[i].buf_ptr = (unsigned short)phys_addr;
3560 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3561 }
3562
3563 return 0;
3564 }
3565
3566 void free_dma_bufs(SLMP_INFO *info)
3567 {
3568 info->buffer_list = NULL;
3569 info->rx_buf_list = NULL;
3570 info->tx_buf_list = NULL;
3571 }
3572
3573 /* allocate buffer large enough to hold max_frame_size.
3574 * This buffer is used to pass an assembled frame to the line discipline.
3575 */
3576 int alloc_tmp_rx_buf(SLMP_INFO *info)
3577 {
3578 info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3579 if (info->tmp_rx_buf == NULL)
3580 return -ENOMEM;
3581 return 0;
3582 }
3583
3584 void free_tmp_rx_buf(SLMP_INFO *info)
3585 {
3586 kfree(info->tmp_rx_buf);
3587 info->tmp_rx_buf = NULL;
3588 }
3589
3590 int claim_resources(SLMP_INFO *info)
3591 {
3592 if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3593 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3594 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3595 info->init_error = DiagStatus_AddressConflict;
3596 goto errout;
3597 }
3598 else
3599 info->shared_mem_requested = 1;
3600
3601 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3602 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3603 __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3604 info->init_error = DiagStatus_AddressConflict;
3605 goto errout;
3606 }
3607 else
3608 info->lcr_mem_requested = 1;
3609
3610 if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3611 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3612 __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3613 info->init_error = DiagStatus_AddressConflict;
3614 goto errout;
3615 }
3616 else
3617 info->sca_base_requested = 1;
3618
3619 if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3620 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3621 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3622 info->init_error = DiagStatus_AddressConflict;
3623 goto errout;
3624 }
3625 else
3626 info->sca_statctrl_requested = 1;
3627
3628 info->memory_base = ioremap(info->phys_memory_base,SCA_MEM_SIZE);
3629 if (!info->memory_base) {
3630 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3631 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3632 info->init_error = DiagStatus_CantAssignPciResources;
3633 goto errout;
3634 }
3635
3636 info->lcr_base = ioremap(info->phys_lcr_base,PAGE_SIZE);
3637 if (!info->lcr_base) {
3638 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3639 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3640 info->init_error = DiagStatus_CantAssignPciResources;
3641 goto errout;
3642 }
3643 info->lcr_base += info->lcr_offset;
3644
3645 info->sca_base = ioremap(info->phys_sca_base,PAGE_SIZE);
3646 if (!info->sca_base) {
3647 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3648 __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3649 info->init_error = DiagStatus_CantAssignPciResources;
3650 goto errout;
3651 }
3652 info->sca_base += info->sca_offset;
3653
3654 info->statctrl_base = ioremap(info->phys_statctrl_base,PAGE_SIZE);
3655 if (!info->statctrl_base) {
3656 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3657 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3658 info->init_error = DiagStatus_CantAssignPciResources;
3659 goto errout;
3660 }
3661 info->statctrl_base += info->statctrl_offset;
3662
3663 if ( !memory_test(info) ) {
3664 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3665 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3666 info->init_error = DiagStatus_MemoryError;
3667 goto errout;
3668 }
3669
3670 return 0;
3671
3672 errout:
3673 release_resources( info );
3674 return -ENODEV;
3675 }
3676
3677 void release_resources(SLMP_INFO *info)
3678 {
3679 if ( debug_level >= DEBUG_LEVEL_INFO )
3680 printk( "%s(%d):%s release_resources() entry\n",
3681 __FILE__,__LINE__,info->device_name );
3682
3683 if ( info->irq_requested ) {
3684 free_irq(info->irq_level, info);
3685 info->irq_requested = 0;
3686 }
3687
3688 if ( info->shared_mem_requested ) {
3689 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3690 info->shared_mem_requested = 0;
3691 }
3692 if ( info->lcr_mem_requested ) {
3693 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3694 info->lcr_mem_requested = 0;
3695 }
3696 if ( info->sca_base_requested ) {
3697 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3698 info->sca_base_requested = 0;
3699 }
3700 if ( info->sca_statctrl_requested ) {
3701 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3702 info->sca_statctrl_requested = 0;
3703 }
3704
3705 if (info->memory_base){
3706 iounmap(info->memory_base);
3707 info->memory_base = NULL;
3708 }
3709
3710 if (info->sca_base) {
3711 iounmap(info->sca_base - info->sca_offset);
3712 info->sca_base=NULL;
3713 }
3714
3715 if (info->statctrl_base) {
3716 iounmap(info->statctrl_base - info->statctrl_offset);
3717 info->statctrl_base=NULL;
3718 }
3719
3720 if (info->lcr_base){
3721 iounmap(info->lcr_base - info->lcr_offset);
3722 info->lcr_base = NULL;
3723 }
3724
3725 if ( debug_level >= DEBUG_LEVEL_INFO )
3726 printk( "%s(%d):%s release_resources() exit\n",
3727 __FILE__,__LINE__,info->device_name );
3728 }
3729
3730 /* Add the specified device instance data structure to the
3731 * global linked list of devices and increment the device count.
3732 */
3733 void add_device(SLMP_INFO *info)
3734 {
3735 info->next_device = NULL;
3736 info->line = synclinkmp_device_count;
3737 sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3738
3739 if (info->line < MAX_DEVICES) {
3740 if (maxframe[info->line])
3741 info->max_frame_size = maxframe[info->line];
3742 info->dosyncppp = dosyncppp[info->line];
3743 }
3744
3745 synclinkmp_device_count++;
3746
3747 if ( !synclinkmp_device_list )
3748 synclinkmp_device_list = info;
3749 else {
3750 SLMP_INFO *current_dev = synclinkmp_device_list;
3751 while( current_dev->next_device )
3752 current_dev = current_dev->next_device;
3753 current_dev->next_device = info;
3754 }
3755
3756 if ( info->max_frame_size < 4096 )
3757 info->max_frame_size = 4096;
3758 else if ( info->max_frame_size > 65535 )
3759 info->max_frame_size = 65535;
3760
3761 printk( "SyncLink MultiPort %s: "
3762 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3763 info->device_name,
3764 info->phys_sca_base,
3765 info->phys_memory_base,
3766 info->phys_statctrl_base,
3767 info->phys_lcr_base,
3768 info->irq_level,
3769 info->max_frame_size );
3770
3771 #if SYNCLINK_GENERIC_HDLC
3772 hdlcdev_init(info);
3773 #endif
3774 }
3775
3776 /* Allocate and initialize a device instance structure
3777 *
3778 * Return Value: pointer to SLMP_INFO if success, otherwise NULL
3779 */
3780 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3781 {
3782 SLMP_INFO *info;
3783
3784 info = kzalloc(sizeof(SLMP_INFO),
3785 GFP_KERNEL);
3786
3787 if (!info) {
3788 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3789 __FILE__,__LINE__, adapter_num, port_num);
3790 } else {
3791 info->magic = MGSL_MAGIC;
3792 INIT_WORK(&info->task, bh_handler);
3793 info->max_frame_size = 4096;
3794 info->close_delay = 5*HZ/10;
3795 info->closing_wait = 30*HZ;
3796 init_waitqueue_head(&info->open_wait);
3797 init_waitqueue_head(&info->close_wait);
3798 init_waitqueue_head(&info->status_event_wait_q);
3799 init_waitqueue_head(&info->event_wait_q);
3800 spin_lock_init(&info->netlock);
3801 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3802 info->idle_mode = HDLC_TXIDLE_FLAGS;
3803 info->adapter_num = adapter_num;
3804 info->port_num = port_num;
3805
3806 /* Copy configuration info to device instance data */
3807 info->irq_level = pdev->irq;
3808 info->phys_lcr_base = pci_resource_start(pdev,0);
3809 info->phys_sca_base = pci_resource_start(pdev,2);
3810 info->phys_memory_base = pci_resource_start(pdev,3);
3811 info->phys_statctrl_base = pci_resource_start(pdev,4);
3812
3813 /* Because veremap only works on page boundaries we must map
3814 * a larger area than is actually implemented for the LCR
3815 * memory range. We map a full page starting at the page boundary.
3816 */
3817 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
3818 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3819
3820 info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1);
3821 info->phys_sca_base &= ~(PAGE_SIZE-1);
3822
3823 info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1);
3824 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3825
3826 info->bus_type = MGSL_BUS_TYPE_PCI;
3827 info->irq_flags = IRQF_SHARED;
3828
3829 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3830 setup_timer(&info->status_timer, status_timeout,
3831 (unsigned long)info);
3832
3833 /* Store the PCI9050 misc control register value because a flaw
3834 * in the PCI9050 prevents LCR registers from being read if
3835 * BIOS assigns an LCR base address with bit 7 set.
3836 *
3837 * Only the misc control register is accessed for which only
3838 * write access is needed, so set an initial value and change
3839 * bits to the device instance data as we write the value
3840 * to the actual misc control register.
3841 */
3842 info->misc_ctrl_value = 0x087e4546;
3843
3844 /* initial port state is unknown - if startup errors
3845 * occur, init_error will be set to indicate the
3846 * problem. Once the port is fully initialized,
3847 * this value will be set to 0 to indicate the
3848 * port is available.
3849 */
3850 info->init_error = -1;
3851 }
3852
3853 return info;
3854 }
3855
3856 void device_init(int adapter_num, struct pci_dev *pdev)
3857 {
3858 SLMP_INFO *port_array[SCA_MAX_PORTS];
3859 int port;
3860
3861 /* allocate device instances for up to SCA_MAX_PORTS devices */
3862 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3863 port_array[port] = alloc_dev(adapter_num,port,pdev);
3864 if( port_array[port] == NULL ) {
3865 for ( --port; port >= 0; --port )
3866 kfree(port_array[port]);
3867 return;
3868 }
3869 }
3870
3871 /* give copy of port_array to all ports and add to device list */
3872 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3873 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3874 add_device( port_array[port] );
3875 spin_lock_init(&port_array[port]->lock);
3876 }
3877
3878 /* Allocate and claim adapter resources */
3879 if ( !claim_resources(port_array[0]) ) {
3880
3881 alloc_dma_bufs(port_array[0]);
3882
3883 /* copy resource information from first port to others */
3884 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3885 port_array[port]->lock = port_array[0]->lock;
3886 port_array[port]->irq_level = port_array[0]->irq_level;
3887 port_array[port]->memory_base = port_array[0]->memory_base;
3888 port_array[port]->sca_base = port_array[0]->sca_base;
3889 port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3890 port_array[port]->lcr_base = port_array[0]->lcr_base;
3891 alloc_dma_bufs(port_array[port]);
3892 }
3893
3894 if ( request_irq(port_array[0]->irq_level,
3895 synclinkmp_interrupt,
3896 port_array[0]->irq_flags,
3897 port_array[0]->device_name,
3898 port_array[0]) < 0 ) {
3899 printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3900 __FILE__,__LINE__,
3901 port_array[0]->device_name,
3902 port_array[0]->irq_level );
3903 }
3904 else {
3905 port_array[0]->irq_requested = 1;
3906 adapter_test(port_array[0]);
3907 }
3908 }
3909 }
3910
3911 static const struct tty_operations ops = {
3912 .open = open,
3913 .close = close,
3914 .write = write,
3915 .put_char = put_char,
3916 .flush_chars = flush_chars,
3917 .write_room = write_room,
3918 .chars_in_buffer = chars_in_buffer,
3919 .flush_buffer = flush_buffer,
3920 .ioctl = ioctl,
3921 .throttle = throttle,
3922 .unthrottle = unthrottle,
3923 .send_xchar = send_xchar,
3924 .break_ctl = set_break,
3925 .wait_until_sent = wait_until_sent,
3926 .read_proc = read_proc,
3927 .set_termios = set_termios,
3928 .stop = tx_hold,
3929 .start = tx_release,
3930 .hangup = hangup,
3931 .tiocmget = tiocmget,
3932 .tiocmset = tiocmset,
3933 };
3934
3935 static void synclinkmp_cleanup(void)
3936 {
3937 int rc;
3938 SLMP_INFO *info;
3939 SLMP_INFO *tmp;
3940
3941 printk("Unloading %s %s\n", driver_name, driver_version);
3942
3943 if (serial_driver) {
3944 if ((rc = tty_unregister_driver(serial_driver)))
3945 printk("%s(%d) failed to unregister tty driver err=%d\n",
3946 __FILE__,__LINE__,rc);
3947 put_tty_driver(serial_driver);
3948 }
3949
3950 /* reset devices */
3951 info = synclinkmp_device_list;
3952 while(info) {
3953 reset_port(info);
3954 info = info->next_device;
3955 }
3956
3957 /* release devices */
3958 info = synclinkmp_device_list;
3959 while(info) {
3960 #if SYNCLINK_GENERIC_HDLC
3961 hdlcdev_exit(info);
3962 #endif
3963 free_dma_bufs(info);
3964 free_tmp_rx_buf(info);
3965 if ( info->port_num == 0 ) {
3966 if (info->sca_base)
3967 write_reg(info, LPR, 1); /* set low power mode */
3968 release_resources(info);
3969 }
3970 tmp = info;
3971 info = info->next_device;
3972 kfree(tmp);
3973 }
3974
3975 pci_unregister_driver(&synclinkmp_pci_driver);
3976 }
3977
3978 /* Driver initialization entry point.
3979 */
3980
3981 static int __init synclinkmp_init(void)
3982 {
3983 int rc;
3984
3985 if (break_on_load) {
3986 synclinkmp_get_text_ptr();
3987 BREAKPOINT();
3988 }
3989
3990 printk("%s %s\n", driver_name, driver_version);
3991
3992 if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
3993 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
3994 return rc;
3995 }
3996
3997 serial_driver = alloc_tty_driver(128);
3998 if (!serial_driver) {
3999 rc = -ENOMEM;
4000 goto error;
4001 }
4002
4003 /* Initialize the tty_driver structure */
4004
4005 serial_driver->owner = THIS_MODULE;
4006 serial_driver->driver_name = "synclinkmp";
4007 serial_driver->name = "ttySLM";
4008 serial_driver->major = ttymajor;
4009 serial_driver->minor_start = 64;
4010 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4011 serial_driver->subtype = SERIAL_TYPE_NORMAL;
4012 serial_driver->init_termios = tty_std_termios;
4013 serial_driver->init_termios.c_cflag =
4014 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4015 serial_driver->init_termios.c_ispeed = 9600;
4016 serial_driver->init_termios.c_ospeed = 9600;
4017 serial_driver->flags = TTY_DRIVER_REAL_RAW;
4018 tty_set_operations(serial_driver, &ops);
4019 if ((rc = tty_register_driver(serial_driver)) < 0) {
4020 printk("%s(%d):Couldn't register serial driver\n",
4021 __FILE__,__LINE__);
4022 put_tty_driver(serial_driver);
4023 serial_driver = NULL;
4024 goto error;
4025 }
4026
4027 printk("%s %s, tty major#%d\n",
4028 driver_name, driver_version,
4029 serial_driver->major);
4030
4031 return 0;
4032
4033 error:
4034 synclinkmp_cleanup();
4035 return rc;
4036 }
4037
4038 static void __exit synclinkmp_exit(void)
4039 {
4040 synclinkmp_cleanup();
4041 }
4042
4043 module_init(synclinkmp_init);
4044 module_exit(synclinkmp_exit);
4045
4046 /* Set the port for internal loopback mode.
4047 * The TxCLK and RxCLK signals are generated from the BRG and
4048 * the TxD is looped back to the RxD internally.
4049 */
4050 void enable_loopback(SLMP_INFO *info, int enable)
4051 {
4052 if (enable) {
4053 /* MD2 (Mode Register 2)
4054 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback
4055 */
4056 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4057
4058 /* degate external TxC clock source */
4059 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4060 write_control_reg(info);
4061
4062 /* RXS/TXS (Rx/Tx clock source)
4063 * 07 Reserved, must be 0
4064 * 06..04 Clock Source, 100=BRG
4065 * 03..00 Clock Divisor, 0000=1
4066 */
4067 write_reg(info, RXS, 0x40);
4068 write_reg(info, TXS, 0x40);
4069
4070 } else {
4071 /* MD2 (Mode Register 2)
4072 * 01..00 CNCT<1..0> Channel connection, 0=normal
4073 */
4074 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4075
4076 /* RXS/TXS (Rx/Tx clock source)
4077 * 07 Reserved, must be 0
4078 * 06..04 Clock Source, 000=RxC/TxC Pin
4079 * 03..00 Clock Divisor, 0000=1
4080 */
4081 write_reg(info, RXS, 0x00);
4082 write_reg(info, TXS, 0x00);
4083 }
4084
4085 /* set LinkSpeed if available, otherwise default to 2Mbps */
4086 if (info->params.clock_speed)
4087 set_rate(info, info->params.clock_speed);
4088 else
4089 set_rate(info, 3686400);
4090 }
4091
4092 /* Set the baud rate register to the desired speed
4093 *
4094 * data_rate data rate of clock in bits per second
4095 * A data rate of 0 disables the AUX clock.
4096 */
4097 void set_rate( SLMP_INFO *info, u32 data_rate )
4098 {
4099 u32 TMCValue;
4100 unsigned char BRValue;
4101 u32 Divisor=0;
4102
4103 /* fBRG = fCLK/(TMC * 2^BR)
4104 */
4105 if (data_rate != 0) {
4106 Divisor = 14745600/data_rate;
4107 if (!Divisor)
4108 Divisor = 1;
4109
4110 TMCValue = Divisor;
4111
4112 BRValue = 0;
4113 if (TMCValue != 1 && TMCValue != 2) {
4114 /* BRValue of 0 provides 50/50 duty cycle *only* when
4115 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4116 * 50/50 duty cycle.
4117 */
4118 BRValue = 1;
4119 TMCValue >>= 1;
4120 }
4121
4122 /* while TMCValue is too big for TMC register, divide
4123 * by 2 and increment BR exponent.
4124 */
4125 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4126 TMCValue >>= 1;
4127
4128 write_reg(info, TXS,
4129 (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4130 write_reg(info, RXS,
4131 (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4132 write_reg(info, TMC, (unsigned char)TMCValue);
4133 }
4134 else {
4135 write_reg(info, TXS,0);
4136 write_reg(info, RXS,0);
4137 write_reg(info, TMC, 0);
4138 }
4139 }
4140
4141 /* Disable receiver
4142 */
4143 void rx_stop(SLMP_INFO *info)
4144 {
4145 if (debug_level >= DEBUG_LEVEL_ISR)
4146 printk("%s(%d):%s rx_stop()\n",
4147 __FILE__,__LINE__, info->device_name );
4148
4149 write_reg(info, CMD, RXRESET);
4150
4151 info->ie0_value &= ~RXRDYE;
4152 write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */
4153
4154 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4155 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4156 write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */
4157
4158 info->rx_enabled = 0;
4159 info->rx_overflow = 0;
4160 }
4161
4162 /* enable the receiver
4163 */
4164 void rx_start(SLMP_INFO *info)
4165 {
4166 int i;
4167
4168 if (debug_level >= DEBUG_LEVEL_ISR)
4169 printk("%s(%d):%s rx_start()\n",
4170 __FILE__,__LINE__, info->device_name );
4171
4172 write_reg(info, CMD, RXRESET);
4173
4174 if ( info->params.mode == MGSL_MODE_HDLC ) {
4175 /* HDLC, disabe IRQ on rxdata */
4176 info->ie0_value &= ~RXRDYE;
4177 write_reg(info, IE0, info->ie0_value);
4178
4179 /* Reset all Rx DMA buffers and program rx dma */
4180 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4181 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4182
4183 for (i = 0; i < info->rx_buf_count; i++) {
4184 info->rx_buf_list[i].status = 0xff;
4185
4186 // throttle to 4 shared memory writes at a time to prevent
4187 // hogging local bus (keep latency time for DMA requests low).
4188 if (!(i % 4))
4189 read_status_reg(info);
4190 }
4191 info->current_rx_buf = 0;
4192
4193 /* set current/1st descriptor address */
4194 write_reg16(info, RXDMA + CDA,
4195 info->rx_buf_list_ex[0].phys_entry);
4196
4197 /* set new last rx descriptor address */
4198 write_reg16(info, RXDMA + EDA,
4199 info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4200
4201 /* set buffer length (shared by all rx dma data buffers) */
4202 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4203
4204 write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
4205 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4206 } else {
4207 /* async, enable IRQ on rxdata */
4208 info->ie0_value |= RXRDYE;
4209 write_reg(info, IE0, info->ie0_value);
4210 }
4211
4212 write_reg(info, CMD, RXENABLE);
4213
4214 info->rx_overflow = FALSE;
4215 info->rx_enabled = 1;
4216 }
4217
4218 /* Enable the transmitter and send a transmit frame if
4219 * one is loaded in the DMA buffers.
4220 */
4221 void tx_start(SLMP_INFO *info)
4222 {
4223 if (debug_level >= DEBUG_LEVEL_ISR)
4224 printk("%s(%d):%s tx_start() tx_count=%d\n",
4225 __FILE__,__LINE__, info->device_name,info->tx_count );
4226
4227 if (!info->tx_enabled ) {
4228 write_reg(info, CMD, TXRESET);
4229 write_reg(info, CMD, TXENABLE);
4230 info->tx_enabled = TRUE;
4231 }
4232
4233 if ( info->tx_count ) {
4234
4235 /* If auto RTS enabled and RTS is inactive, then assert */
4236 /* RTS and set a flag indicating that the driver should */
4237 /* negate RTS when the transmission completes. */
4238
4239 info->drop_rts_on_tx_done = 0;
4240
4241 if (info->params.mode != MGSL_MODE_ASYNC) {
4242
4243 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4244 get_signals( info );
4245 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4246 info->serial_signals |= SerialSignal_RTS;
4247 set_signals( info );
4248 info->drop_rts_on_tx_done = 1;
4249 }
4250 }
4251
4252 write_reg16(info, TRC0,
4253 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4254
4255 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4256 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4257
4258 /* set TX CDA (current descriptor address) */
4259 write_reg16(info, TXDMA + CDA,
4260 info->tx_buf_list_ex[0].phys_entry);
4261
4262 /* set TX EDA (last descriptor address) */
4263 write_reg16(info, TXDMA + EDA,
4264 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4265
4266 /* enable underrun IRQ */
4267 info->ie1_value &= ~IDLE;
4268 info->ie1_value |= UDRN;
4269 write_reg(info, IE1, info->ie1_value);
4270 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4271
4272 write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
4273 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4274
4275 mod_timer(&info->tx_timer, jiffies +
4276 msecs_to_jiffies(5000));
4277 }
4278 else {
4279 tx_load_fifo(info);
4280 /* async, enable IRQ on txdata */
4281 info->ie0_value |= TXRDYE;
4282 write_reg(info, IE0, info->ie0_value);
4283 }
4284
4285 info->tx_active = 1;
4286 }
4287 }
4288
4289 /* stop the transmitter and DMA
4290 */
4291 void tx_stop( SLMP_INFO *info )
4292 {
4293 if (debug_level >= DEBUG_LEVEL_ISR)
4294 printk("%s(%d):%s tx_stop()\n",
4295 __FILE__,__LINE__, info->device_name );
4296
4297 del_timer(&info->tx_timer);
4298
4299 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4300 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4301
4302 write_reg(info, CMD, TXRESET);
4303
4304 info->ie1_value &= ~(UDRN + IDLE);
4305 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
4306 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
4307
4308 info->ie0_value &= ~TXRDYE;
4309 write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */
4310
4311 info->tx_enabled = 0;
4312 info->tx_active = 0;
4313 }
4314
4315 /* Fill the transmit FIFO until the FIFO is full or
4316 * there is no more data to load.
4317 */
4318 void tx_load_fifo(SLMP_INFO *info)
4319 {
4320 u8 TwoBytes[2];
4321
4322 /* do nothing is now tx data available and no XON/XOFF pending */
4323
4324 if ( !info->tx_count && !info->x_char )
4325 return;
4326
4327 /* load the Transmit FIFO until FIFOs full or all data sent */
4328
4329 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4330
4331 /* there is more space in the transmit FIFO and */
4332 /* there is more data in transmit buffer */
4333
4334 if ( (info->tx_count > 1) && !info->x_char ) {
4335 /* write 16-bits */
4336 TwoBytes[0] = info->tx_buf[info->tx_get++];
4337 if (info->tx_get >= info->max_frame_size)
4338 info->tx_get -= info->max_frame_size;
4339 TwoBytes[1] = info->tx_buf[info->tx_get++];
4340 if (info->tx_get >= info->max_frame_size)
4341 info->tx_get -= info->max_frame_size;
4342
4343 write_reg16(info, TRB, *((u16 *)TwoBytes));
4344
4345 info->tx_count -= 2;
4346 info->icount.tx += 2;
4347 } else {
4348 /* only 1 byte left to transmit or 1 FIFO slot left */
4349
4350 if (info->x_char) {
4351 /* transmit pending high priority char */
4352 write_reg(info, TRB, info->x_char);
4353 info->x_char = 0;
4354 } else {
4355 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4356 if (info->tx_get >= info->max_frame_size)
4357 info->tx_get -= info->max_frame_size;
4358 info->tx_count--;
4359 }
4360 info->icount.tx++;
4361 }
4362 }
4363 }
4364
4365 /* Reset a port to a known state
4366 */
4367 void reset_port(SLMP_INFO *info)
4368 {
4369 if (info->sca_base) {
4370
4371 tx_stop(info);
4372 rx_stop(info);
4373
4374 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4375 set_signals(info);
4376
4377 /* disable all port interrupts */
4378 info->ie0_value = 0;
4379 info->ie1_value = 0;
4380 info->ie2_value = 0;
4381 write_reg(info, IE0, info->ie0_value);
4382 write_reg(info, IE1, info->ie1_value);
4383 write_reg(info, IE2, info->ie2_value);
4384
4385 write_reg(info, CMD, CHRESET);
4386 }
4387 }
4388
4389 /* Reset all the ports to a known state.
4390 */
4391 void reset_adapter(SLMP_INFO *info)
4392 {
4393 int i;
4394
4395 for ( i=0; i < SCA_MAX_PORTS; ++i) {
4396 if (info->port_array[i])
4397 reset_port(info->port_array[i]);
4398 }
4399 }
4400
4401 /* Program port for asynchronous communications.
4402 */
4403 void async_mode(SLMP_INFO *info)
4404 {
4405
4406 unsigned char RegValue;
4407
4408 tx_stop(info);
4409 rx_stop(info);
4410
4411 /* MD0, Mode Register 0
4412 *
4413 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async
4414 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4415 * 03 Reserved, must be 0
4416 * 02 CRCCC, CRC Calculation, 0=disabled
4417 * 01..00 STOP<1..0> Stop bits (00=1,10=2)
4418 *
4419 * 0000 0000
4420 */
4421 RegValue = 0x00;
4422 if (info->params.stop_bits != 1)
4423 RegValue |= BIT1;
4424 write_reg(info, MD0, RegValue);
4425
4426 /* MD1, Mode Register 1
4427 *
4428 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4429 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4430 * 03..02 RXCHR<1..0>, rx char size
4431 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4432 *
4433 * 0100 0000
4434 */
4435 RegValue = 0x40;
4436 switch (info->params.data_bits) {
4437 case 7: RegValue |= BIT4 + BIT2; break;
4438 case 6: RegValue |= BIT5 + BIT3; break;
4439 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4440 }
4441 if (info->params.parity != ASYNC_PARITY_NONE) {
4442 RegValue |= BIT1;
4443 if (info->params.parity == ASYNC_PARITY_ODD)
4444 RegValue |= BIT0;
4445 }
4446 write_reg(info, MD1, RegValue);
4447
4448 /* MD2, Mode Register 2
4449 *
4450 * 07..02 Reserved, must be 0
4451 * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback
4452 *
4453 * 0000 0000
4454 */
4455 RegValue = 0x00;
4456 if (info->params.loopback)
4457 RegValue |= (BIT1 + BIT0);
4458 write_reg(info, MD2, RegValue);
4459
4460 /* RXS, Receive clock source
4461 *
4462 * 07 Reserved, must be 0
4463 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4464 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4465 */
4466 RegValue=BIT6;
4467 write_reg(info, RXS, RegValue);
4468
4469 /* TXS, Transmit clock source
4470 *
4471 * 07 Reserved, must be 0
4472 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4473 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4474 */
4475 RegValue=BIT6;
4476 write_reg(info, TXS, RegValue);
4477
4478 /* Control Register
4479 *
4480 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4481 */
4482 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4483 write_control_reg(info);
4484
4485 tx_set_idle(info);
4486
4487 /* RRC Receive Ready Control 0
4488 *
4489 * 07..05 Reserved, must be 0
4490 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4491 */
4492 write_reg(info, RRC, 0x00);
4493
4494 /* TRC0 Transmit Ready Control 0
4495 *
4496 * 07..05 Reserved, must be 0
4497 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4498 */
4499 write_reg(info, TRC0, 0x10);
4500
4501 /* TRC1 Transmit Ready Control 1
4502 *
4503 * 07..05 Reserved, must be 0
4504 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4505 */
4506 write_reg(info, TRC1, 0x1e);
4507
4508 /* CTL, MSCI control register
4509 *
4510 * 07..06 Reserved, set to 0
4511 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4512 * 04 IDLC, idle control, 0=mark 1=idle register
4513 * 03 BRK, break, 0=off 1 =on (async)
4514 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4515 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4516 * 00 RTS, RTS output control, 0=active 1=inactive
4517 *
4518 * 0001 0001
4519 */
4520 RegValue = 0x10;
4521 if (!(info->serial_signals & SerialSignal_RTS))
4522 RegValue |= 0x01;
4523 write_reg(info, CTL, RegValue);
4524
4525 /* enable status interrupts */
4526 info->ie0_value |= TXINTE + RXINTE;
4527 write_reg(info, IE0, info->ie0_value);
4528
4529 /* enable break detect interrupt */
4530 info->ie1_value = BRKD;
4531 write_reg(info, IE1, info->ie1_value);
4532
4533 /* enable rx overrun interrupt */
4534 info->ie2_value = OVRN;
4535 write_reg(info, IE2, info->ie2_value);
4536
4537 set_rate( info, info->params.data_rate * 16 );
4538 }
4539
4540 /* Program the SCA for HDLC communications.
4541 */
4542 void hdlc_mode(SLMP_INFO *info)
4543 {
4544 unsigned char RegValue;
4545 u32 DpllDivisor;
4546
4547 // Can't use DPLL because SCA outputs recovered clock on RxC when
4548 // DPLL mode selected. This causes output contention with RxC receiver.
4549 // Use of DPLL would require external hardware to disable RxC receiver
4550 // when DPLL mode selected.
4551 info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4552
4553 /* disable DMA interrupts */
4554 write_reg(info, TXDMA + DIR, 0);
4555 write_reg(info, RXDMA + DIR, 0);
4556
4557 /* MD0, Mode Register 0
4558 *
4559 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC
4560 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4561 * 03 Reserved, must be 0
4562 * 02 CRCCC, CRC Calculation, 1=enabled
4563 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4564 * 00 CRC0, CRC initial value, 1 = all 1s
4565 *
4566 * 1000 0001
4567 */
4568 RegValue = 0x81;
4569 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4570 RegValue |= BIT4;
4571 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4572 RegValue |= BIT4;
4573 if (info->params.crc_type == HDLC_CRC_16_CCITT)
4574 RegValue |= BIT2 + BIT1;
4575 write_reg(info, MD0, RegValue);
4576
4577 /* MD1, Mode Register 1
4578 *
4579 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check
4580 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits
4581 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits
4582 * 01..00 PMPM<1..0>, Parity mode, 00=no parity
4583 *
4584 * 0000 0000
4585 */
4586 RegValue = 0x00;
4587 write_reg(info, MD1, RegValue);
4588
4589 /* MD2, Mode Register 2
4590 *
4591 * 07 NRZFM, 0=NRZ, 1=FM
4592 * 06..05 CODE<1..0> Encoding, 00=NRZ
4593 * 04..03 DRATE<1..0> DPLL Divisor, 00=8
4594 * 02 Reserved, must be 0
4595 * 01..00 CNCT<1..0> Channel connection, 0=normal
4596 *
4597 * 0000 0000
4598 */
4599 RegValue = 0x00;
4600 switch(info->params.encoding) {
4601 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break;
4602 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4603 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4604 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */
4605 #if 0
4606 case HDLC_ENCODING_NRZB: /* not supported */
4607 case HDLC_ENCODING_NRZI_MARK: /* not supported */
4608 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */
4609 #endif
4610 }
4611 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4612 DpllDivisor = 16;
4613 RegValue |= BIT3;
4614 } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4615 DpllDivisor = 8;
4616 } else {
4617 DpllDivisor = 32;
4618 RegValue |= BIT4;
4619 }
4620 write_reg(info, MD2, RegValue);
4621
4622
4623 /* RXS, Receive clock source
4624 *
4625 * 07 Reserved, must be 0
4626 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4627 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4628 */
4629 RegValue=0;
4630 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4631 RegValue |= BIT6;
4632 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4633 RegValue |= BIT6 + BIT5;
4634 write_reg(info, RXS, RegValue);
4635
4636 /* TXS, Transmit clock source
4637 *
4638 * 07 Reserved, must be 0
4639 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4640 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4641 */
4642 RegValue=0;
4643 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4644 RegValue |= BIT6;
4645 if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4646 RegValue |= BIT6 + BIT5;
4647 write_reg(info, TXS, RegValue);
4648
4649 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4650 set_rate(info, info->params.clock_speed * DpllDivisor);
4651 else
4652 set_rate(info, info->params.clock_speed);
4653
4654 /* GPDATA (General Purpose I/O Data Register)
4655 *
4656 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4657 */
4658 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4659 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4660 else
4661 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4662 write_control_reg(info);
4663
4664 /* RRC Receive Ready Control 0
4665 *
4666 * 07..05 Reserved, must be 0
4667 * 04..00 RRC<4..0> Rx FIFO trigger active
4668 */
4669 write_reg(info, RRC, rx_active_fifo_level);
4670
4671 /* TRC0 Transmit Ready Control 0
4672 *
4673 * 07..05 Reserved, must be 0
4674 * 04..00 TRC<4..0> Tx FIFO trigger active
4675 */
4676 write_reg(info, TRC0, tx_active_fifo_level);
4677
4678 /* TRC1 Transmit Ready Control 1
4679 *
4680 * 07..05 Reserved, must be 0
4681 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4682 */
4683 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4684
4685 /* DMR, DMA Mode Register
4686 *
4687 * 07..05 Reserved, must be 0
4688 * 04 TMOD, Transfer Mode: 1=chained-block
4689 * 03 Reserved, must be 0
4690 * 02 NF, Number of Frames: 1=multi-frame
4691 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled
4692 * 00 Reserved, must be 0
4693 *
4694 * 0001 0100
4695 */
4696 write_reg(info, TXDMA + DMR, 0x14);
4697 write_reg(info, RXDMA + DMR, 0x14);
4698
4699 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4700 write_reg(info, RXDMA + CPB,
4701 (unsigned char)(info->buffer_list_phys >> 16));
4702
4703 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4704 write_reg(info, TXDMA + CPB,
4705 (unsigned char)(info->buffer_list_phys >> 16));
4706
4707 /* enable status interrupts. other code enables/disables
4708 * the individual sources for these two interrupt classes.
4709 */
4710 info->ie0_value |= TXINTE + RXINTE;
4711 write_reg(info, IE0, info->ie0_value);
4712
4713 /* CTL, MSCI control register
4714 *
4715 * 07..06 Reserved, set to 0
4716 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4717 * 04 IDLC, idle control, 0=mark 1=idle register
4718 * 03 BRK, break, 0=off 1 =on (async)
4719 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4720 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4721 * 00 RTS, RTS output control, 0=active 1=inactive
4722 *
4723 * 0001 0001
4724 */
4725 RegValue = 0x10;
4726 if (!(info->serial_signals & SerialSignal_RTS))
4727 RegValue |= 0x01;
4728 write_reg(info, CTL, RegValue);
4729
4730 /* preamble not supported ! */
4731
4732 tx_set_idle(info);
4733 tx_stop(info);
4734 rx_stop(info);
4735
4736 set_rate(info, info->params.clock_speed);
4737
4738 if (info->params.loopback)
4739 enable_loopback(info,1);
4740 }
4741
4742 /* Set the transmit HDLC idle mode
4743 */
4744 void tx_set_idle(SLMP_INFO *info)
4745 {
4746 unsigned char RegValue = 0xff;
4747
4748 /* Map API idle mode to SCA register bits */
4749 switch(info->idle_mode) {
4750 case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break;
4751 case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break;
4752 case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break;
4753 case HDLC_TXIDLE_ONES: RegValue = 0xff; break;
4754 case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break;
4755 case HDLC_TXIDLE_SPACE: RegValue = 0x00; break;
4756 case HDLC_TXIDLE_MARK: RegValue = 0xff; break;
4757 }
4758
4759 write_reg(info, IDL, RegValue);
4760 }
4761
4762 /* Query the adapter for the state of the V24 status (input) signals.
4763 */
4764 void get_signals(SLMP_INFO *info)
4765 {
4766 u16 status = read_reg(info, SR3);
4767 u16 gpstatus = read_status_reg(info);
4768 u16 testbit;
4769
4770 /* clear all serial signals except DTR and RTS */
4771 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4772
4773 /* set serial signal bits to reflect MISR */
4774
4775 if (!(status & BIT3))
4776 info->serial_signals |= SerialSignal_CTS;
4777
4778 if ( !(status & BIT2))
4779 info->serial_signals |= SerialSignal_DCD;
4780
4781 testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4782 if (!(gpstatus & testbit))
4783 info->serial_signals |= SerialSignal_RI;
4784
4785 testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4786 if (!(gpstatus & testbit))
4787 info->serial_signals |= SerialSignal_DSR;
4788 }
4789
4790 /* Set the state of DTR and RTS based on contents of
4791 * serial_signals member of device context.
4792 */
4793 void set_signals(SLMP_INFO *info)
4794 {
4795 unsigned char RegValue;
4796 u16 EnableBit;
4797
4798 RegValue = read_reg(info, CTL);
4799 if (info->serial_signals & SerialSignal_RTS)
4800 RegValue &= ~BIT0;
4801 else
4802 RegValue |= BIT0;
4803 write_reg(info, CTL, RegValue);
4804
4805 // Port 0..3 DTR is ctrl reg <1,3,5,7>
4806 EnableBit = BIT1 << (info->port_num*2);
4807 if (info->serial_signals & SerialSignal_DTR)
4808 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4809 else
4810 info->port_array[0]->ctrlreg_value |= EnableBit;
4811 write_control_reg(info);
4812 }
4813
4814 /*******************/
4815 /* DMA Buffer Code */
4816 /*******************/
4817
4818 /* Set the count for all receive buffers to SCABUFSIZE
4819 * and set the current buffer to the first buffer. This effectively
4820 * makes all buffers free and discards any data in buffers.
4821 */
4822 void rx_reset_buffers(SLMP_INFO *info)
4823 {
4824 rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4825 }
4826
4827 /* Free the buffers used by a received frame
4828 *
4829 * info pointer to device instance data
4830 * first index of 1st receive buffer of frame
4831 * last index of last receive buffer of frame
4832 */
4833 void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4834 {
4835 int done = 0;
4836
4837 while(!done) {
4838 /* reset current buffer for reuse */
4839 info->rx_buf_list[first].status = 0xff;
4840
4841 if (first == last) {
4842 done = 1;
4843 /* set new last rx descriptor address */
4844 write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4845 }
4846
4847 first++;
4848 if (first == info->rx_buf_count)
4849 first = 0;
4850 }
4851
4852 /* set current buffer to next buffer after last buffer of frame */
4853 info->current_rx_buf = first;
4854 }
4855
4856 /* Return a received frame from the receive DMA buffers.
4857 * Only frames received without errors are returned.
4858 *
4859 * Return Value: 1 if frame returned, otherwise 0
4860 */
4861 int rx_get_frame(SLMP_INFO *info)
4862 {
4863 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
4864 unsigned short status;
4865 unsigned int framesize = 0;
4866 int ReturnCode = 0;
4867 unsigned long flags;
4868 struct tty_struct *tty = info->tty;
4869 unsigned char addr_field = 0xff;
4870 SCADESC *desc;
4871 SCADESC_EX *desc_ex;
4872
4873 CheckAgain:
4874 /* assume no frame returned, set zero length */
4875 framesize = 0;
4876 addr_field = 0xff;
4877
4878 /*
4879 * current_rx_buf points to the 1st buffer of the next available
4880 * receive frame. To find the last buffer of the frame look for
4881 * a non-zero status field in the buffer entries. (The status
4882 * field is set by the 16C32 after completing a receive frame.
4883 */
4884 StartIndex = EndIndex = info->current_rx_buf;
4885
4886 for ( ;; ) {
4887 desc = &info->rx_buf_list[EndIndex];
4888 desc_ex = &info->rx_buf_list_ex[EndIndex];
4889
4890 if (desc->status == 0xff)
4891 goto Cleanup; /* current desc still in use, no frames available */
4892
4893 if (framesize == 0 && info->params.addr_filter != 0xff)
4894 addr_field = desc_ex->virt_addr[0];
4895
4896 framesize += desc->length;
4897
4898 /* Status != 0 means last buffer of frame */
4899 if (desc->status)
4900 break;
4901
4902 EndIndex++;
4903 if (EndIndex == info->rx_buf_count)
4904 EndIndex = 0;
4905
4906 if (EndIndex == info->current_rx_buf) {
4907 /* all buffers have been 'used' but none mark */
4908 /* the end of a frame. Reset buffers and receiver. */
4909 if ( info->rx_enabled ){
4910 spin_lock_irqsave(&info->lock,flags);
4911 rx_start(info);
4912 spin_unlock_irqrestore(&info->lock,flags);
4913 }
4914 goto Cleanup;
4915 }
4916
4917 }
4918
4919 /* check status of receive frame */
4920
4921 /* frame status is byte stored after frame data
4922 *
4923 * 7 EOM (end of msg), 1 = last buffer of frame
4924 * 6 Short Frame, 1 = short frame
4925 * 5 Abort, 1 = frame aborted
4926 * 4 Residue, 1 = last byte is partial
4927 * 3 Overrun, 1 = overrun occurred during frame reception
4928 * 2 CRC, 1 = CRC error detected
4929 *
4930 */
4931 status = desc->status;
4932
4933 /* ignore CRC bit if not using CRC (bit is undefined) */
4934 /* Note:CRC is not save to data buffer */
4935 if (info->params.crc_type == HDLC_CRC_NONE)
4936 status &= ~BIT2;
4937
4938 if (framesize == 0 ||
4939 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4940 /* discard 0 byte frames, this seems to occur sometime
4941 * when remote is idling flags.
4942 */
4943 rx_free_frame_buffers(info, StartIndex, EndIndex);
4944 goto CheckAgain;
4945 }
4946
4947 if (framesize < 2)
4948 status |= BIT6;
4949
4950 if (status & (BIT6+BIT5+BIT3+BIT2)) {
4951 /* received frame has errors,
4952 * update counts and mark frame size as 0
4953 */
4954 if (status & BIT6)
4955 info->icount.rxshort++;
4956 else if (status & BIT5)
4957 info->icount.rxabort++;
4958 else if (status & BIT3)
4959 info->icount.rxover++;
4960 else
4961 info->icount.rxcrc++;
4962
4963 framesize = 0;
4964 #if SYNCLINK_GENERIC_HDLC
4965 {
4966 struct net_device_stats *stats = hdlc_stats(info->netdev);
4967 stats->rx_errors++;
4968 stats->rx_frame_errors++;
4969 }
4970 #endif
4971 }
4972
4973 if ( debug_level >= DEBUG_LEVEL_BH )
4974 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4975 __FILE__,__LINE__,info->device_name,status,framesize);
4976
4977 if ( debug_level >= DEBUG_LEVEL_DATA )
4978 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4979 min_t(int, framesize,SCABUFSIZE),0);
4980
4981 if (framesize) {
4982 if (framesize > info->max_frame_size)
4983 info->icount.rxlong++;
4984 else {
4985 /* copy dma buffer(s) to contiguous intermediate buffer */
4986 int copy_count = framesize;
4987 int index = StartIndex;
4988 unsigned char *ptmp = info->tmp_rx_buf;
4989 info->tmp_rx_buf_count = framesize;
4990
4991 info->icount.rxok++;
4992
4993 while(copy_count) {
4994 int partial_count = min(copy_count,SCABUFSIZE);
4995 memcpy( ptmp,
4996 info->rx_buf_list_ex[index].virt_addr,
4997 partial_count );
4998 ptmp += partial_count;
4999 copy_count -= partial_count;
5000
5001 if ( ++index == info->rx_buf_count )
5002 index = 0;
5003 }
5004
5005 #if SYNCLINK_GENERIC_HDLC
5006 if (info->netcount)
5007 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
5008 else
5009 #endif
5010 ldisc_receive_buf(tty,info->tmp_rx_buf,
5011 info->flag_buf, framesize);
5012 }
5013 }
5014 /* Free the buffers used by this frame. */
5015 rx_free_frame_buffers( info, StartIndex, EndIndex );
5016
5017 ReturnCode = 1;
5018
5019 Cleanup:
5020 if ( info->rx_enabled && info->rx_overflow ) {
5021 /* Receiver is enabled, but needs to restarted due to
5022 * rx buffer overflow. If buffers are empty, restart receiver.
5023 */
5024 if (info->rx_buf_list[EndIndex].status == 0xff) {
5025 spin_lock_irqsave(&info->lock,flags);
5026 rx_start(info);
5027 spin_unlock_irqrestore(&info->lock,flags);
5028 }
5029 }
5030
5031 return ReturnCode;
5032 }
5033
5034 /* load the transmit DMA buffer with data
5035 */
5036 void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5037 {
5038 unsigned short copy_count;
5039 unsigned int i = 0;
5040 SCADESC *desc;
5041 SCADESC_EX *desc_ex;
5042
5043 if ( debug_level >= DEBUG_LEVEL_DATA )
5044 trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1);
5045
5046 /* Copy source buffer to one or more DMA buffers, starting with
5047 * the first transmit dma buffer.
5048 */
5049 for(i=0;;)
5050 {
5051 copy_count = min_t(unsigned short,count,SCABUFSIZE);
5052
5053 desc = &info->tx_buf_list[i];
5054 desc_ex = &info->tx_buf_list_ex[i];
5055
5056 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5057
5058 desc->length = copy_count;
5059 desc->status = 0;
5060
5061 buf += copy_count;
5062 count -= copy_count;
5063
5064 if (!count)
5065 break;
5066
5067 i++;
5068 if (i >= info->tx_buf_count)
5069 i = 0;
5070 }
5071
5072 info->tx_buf_list[i].status = 0x81; /* set EOM and EOT status */
5073 info->last_tx_buf = ++i;
5074 }
5075
5076 int register_test(SLMP_INFO *info)
5077 {
5078 static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5079 static unsigned int count = ARRAY_SIZE(testval);
5080 unsigned int i;
5081 int rc = TRUE;
5082 unsigned long flags;
5083
5084 spin_lock_irqsave(&info->lock,flags);
5085 reset_port(info);
5086
5087 /* assume failure */
5088 info->init_error = DiagStatus_AddressFailure;
5089
5090 /* Write bit patterns to various registers but do it out of */
5091 /* sync, then read back and verify values. */
5092
5093 for (i = 0 ; i < count ; i++) {
5094 write_reg(info, TMC, testval[i]);
5095 write_reg(info, IDL, testval[(i+1)%count]);
5096 write_reg(info, SA0, testval[(i+2)%count]);
5097 write_reg(info, SA1, testval[(i+3)%count]);
5098
5099 if ( (read_reg(info, TMC) != testval[i]) ||
5100 (read_reg(info, IDL) != testval[(i+1)%count]) ||
5101 (read_reg(info, SA0) != testval[(i+2)%count]) ||
5102 (read_reg(info, SA1) != testval[(i+3)%count]) )
5103 {
5104 rc = FALSE;
5105 break;
5106 }
5107 }
5108
5109 reset_port(info);
5110 spin_unlock_irqrestore(&info->lock,flags);
5111
5112 return rc;
5113 }
5114
5115 int irq_test(SLMP_INFO *info)
5116 {
5117 unsigned long timeout;
5118 unsigned long flags;
5119
5120 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5121
5122 spin_lock_irqsave(&info->lock,flags);
5123 reset_port(info);
5124
5125 /* assume failure */
5126 info->init_error = DiagStatus_IrqFailure;
5127 info->irq_occurred = FALSE;
5128
5129 /* setup timer0 on SCA0 to interrupt */
5130
5131 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5132 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5133
5134 write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */
5135 write_reg16(info, (unsigned char)(timer + TCONR), 1); /* timer constant */
5136
5137
5138 /* TMCS, Timer Control/Status Register
5139 *
5140 * 07 CMF, Compare match flag (read only) 1=match
5141 * 06 ECMI, CMF Interrupt Enable: 1=enabled
5142 * 05 Reserved, must be 0
5143 * 04 TME, Timer Enable
5144 * 03..00 Reserved, must be 0
5145 *
5146 * 0101 0000
5147 */
5148 write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5149
5150 spin_unlock_irqrestore(&info->lock,flags);
5151
5152 timeout=100;
5153 while( timeout-- && !info->irq_occurred ) {
5154 msleep_interruptible(10);
5155 }
5156
5157 spin_lock_irqsave(&info->lock,flags);
5158 reset_port(info);
5159 spin_unlock_irqrestore(&info->lock,flags);
5160
5161 return info->irq_occurred;
5162 }
5163
5164 /* initialize individual SCA device (2 ports)
5165 */
5166 static int sca_init(SLMP_INFO *info)
5167 {
5168 /* set wait controller to single mem partition (low), no wait states */
5169 write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */
5170 write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */
5171 write_reg(info, WCRL, 0); /* wait controller low range */
5172 write_reg(info, WCRM, 0); /* wait controller mid range */
5173 write_reg(info, WCRH, 0); /* wait controller high range */
5174
5175 /* DPCR, DMA Priority Control
5176 *
5177 * 07..05 Not used, must be 0
5178 * 04 BRC, bus release condition: 0=all transfers complete
5179 * 03 CCC, channel change condition: 0=every cycle
5180 * 02..00 PR<2..0>, priority 100=round robin
5181 *
5182 * 00000100 = 0x04
5183 */
5184 write_reg(info, DPCR, dma_priority);
5185
5186 /* DMA Master Enable, BIT7: 1=enable all channels */
5187 write_reg(info, DMER, 0x80);
5188
5189 /* enable all interrupt classes */
5190 write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5191 write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */
5192 write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */
5193
5194 /* ITCR, interrupt control register
5195 * 07 IPC, interrupt priority, 0=MSCI->DMA
5196 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5197 * 04 VOS, Vector Output, 0=unmodified vector
5198 * 03..00 Reserved, must be 0
5199 */
5200 write_reg(info, ITCR, 0);
5201
5202 return TRUE;
5203 }
5204
5205 /* initialize adapter hardware
5206 */
5207 int init_adapter(SLMP_INFO *info)
5208 {
5209 int i;
5210
5211 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5212 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5213 u32 readval;
5214
5215 info->misc_ctrl_value |= BIT30;
5216 *MiscCtrl = info->misc_ctrl_value;
5217
5218 /*
5219 * Force at least 170ns delay before clearing
5220 * reset bit. Each read from LCR takes at least
5221 * 30ns so 10 times for 300ns to be safe.
5222 */
5223 for(i=0;i<10;i++)
5224 readval = *MiscCtrl;
5225
5226 info->misc_ctrl_value &= ~BIT30;
5227 *MiscCtrl = info->misc_ctrl_value;
5228
5229 /* init control reg (all DTRs off, all clksel=input) */
5230 info->ctrlreg_value = 0xaa;
5231 write_control_reg(info);
5232
5233 {
5234 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5235 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5236
5237 switch(read_ahead_count)
5238 {
5239 case 16:
5240 lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5241 break;
5242 case 8:
5243 lcr1_brdr_value |= BIT5 + BIT4;
5244 break;
5245 case 4:
5246 lcr1_brdr_value |= BIT5 + BIT3;
5247 break;
5248 case 0:
5249 lcr1_brdr_value |= BIT5;
5250 break;
5251 }
5252
5253 *LCR1BRDR = lcr1_brdr_value;
5254 *MiscCtrl = misc_ctrl_value;
5255 }
5256
5257 sca_init(info->port_array[0]);
5258 sca_init(info->port_array[2]);
5259
5260 return TRUE;
5261 }
5262
5263 /* Loopback an HDLC frame to test the hardware
5264 * interrupt and DMA functions.
5265 */
5266 int loopback_test(SLMP_INFO *info)
5267 {
5268 #define TESTFRAMESIZE 20
5269
5270 unsigned long timeout;
5271 u16 count = TESTFRAMESIZE;
5272 unsigned char buf[TESTFRAMESIZE];
5273 int rc = FALSE;
5274 unsigned long flags;
5275
5276 struct tty_struct *oldtty = info->tty;
5277 u32 speed = info->params.clock_speed;
5278
5279 info->params.clock_speed = 3686400;
5280 info->tty = NULL;
5281
5282 /* assume failure */
5283 info->init_error = DiagStatus_DmaFailure;
5284
5285 /* build and send transmit frame */
5286 for (count = 0; count < TESTFRAMESIZE;++count)
5287 buf[count] = (unsigned char)count;
5288
5289 memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5290
5291 /* program hardware for HDLC and enabled receiver */
5292 spin_lock_irqsave(&info->lock,flags);
5293 hdlc_mode(info);
5294 enable_loopback(info,1);
5295 rx_start(info);
5296 info->tx_count = count;
5297 tx_load_dma_buffer(info,buf,count);
5298 tx_start(info);
5299 spin_unlock_irqrestore(&info->lock,flags);
5300
5301 /* wait for receive complete */
5302 /* Set a timeout for waiting for interrupt. */
5303 for ( timeout = 100; timeout; --timeout ) {
5304 msleep_interruptible(10);
5305
5306 if (rx_get_frame(info)) {
5307 rc = TRUE;
5308 break;
5309 }
5310 }
5311
5312 /* verify received frame length and contents */
5313 if (rc == TRUE &&
5314 ( info->tmp_rx_buf_count != count ||
5315 memcmp(buf, info->tmp_rx_buf,count))) {
5316 rc = FALSE;
5317 }
5318
5319 spin_lock_irqsave(&info->lock,flags);
5320 reset_adapter(info);
5321 spin_unlock_irqrestore(&info->lock,flags);
5322
5323 info->params.clock_speed = speed;
5324 info->tty = oldtty;
5325
5326 return rc;
5327 }
5328
5329 /* Perform diagnostics on hardware
5330 */
5331 int adapter_test( SLMP_INFO *info )
5332 {
5333 unsigned long flags;
5334 if ( debug_level >= DEBUG_LEVEL_INFO )
5335 printk( "%s(%d):Testing device %s\n",
5336 __FILE__,__LINE__,info->device_name );
5337
5338 spin_lock_irqsave(&info->lock,flags);
5339 init_adapter(info);
5340 spin_unlock_irqrestore(&info->lock,flags);
5341
5342 info->port_array[0]->port_count = 0;
5343
5344 if ( register_test(info->port_array[0]) &&
5345 register_test(info->port_array[1])) {
5346
5347 info->port_array[0]->port_count = 2;
5348
5349 if ( register_test(info->port_array[2]) &&
5350 register_test(info->port_array[3]) )
5351 info->port_array[0]->port_count += 2;
5352 }
5353 else {
5354 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5355 __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5356 return -ENODEV;
5357 }
5358
5359 if ( !irq_test(info->port_array[0]) ||
5360 !irq_test(info->port_array[1]) ||
5361 (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5362 (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5363 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5364 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5365 return -ENODEV;
5366 }
5367
5368 if (!loopback_test(info->port_array[0]) ||
5369 !loopback_test(info->port_array[1]) ||
5370 (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5371 (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5372 printk( "%s(%d):DMA test failure for device %s\n",
5373 __FILE__,__LINE__,info->device_name);
5374 return -ENODEV;
5375 }
5376
5377 if ( debug_level >= DEBUG_LEVEL_INFO )
5378 printk( "%s(%d):device %s passed diagnostics\n",
5379 __FILE__,__LINE__,info->device_name );
5380
5381 info->port_array[0]->init_error = 0;
5382 info->port_array[1]->init_error = 0;
5383 if ( info->port_count > 2 ) {
5384 info->port_array[2]->init_error = 0;
5385 info->port_array[3]->init_error = 0;
5386 }
5387
5388 return 0;
5389 }
5390
5391 /* Test the shared memory on a PCI adapter.
5392 */
5393 int memory_test(SLMP_INFO *info)
5394 {
5395 static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5396 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5397 unsigned long count = ARRAY_SIZE(testval);
5398 unsigned long i;
5399 unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5400 unsigned long * addr = (unsigned long *)info->memory_base;
5401
5402 /* Test data lines with test pattern at one location. */
5403
5404 for ( i = 0 ; i < count ; i++ ) {
5405 *addr = testval[i];
5406 if ( *addr != testval[i] )
5407 return FALSE;
5408 }
5409
5410 /* Test address lines with incrementing pattern over */
5411 /* entire address range. */
5412
5413 for ( i = 0 ; i < limit ; i++ ) {
5414 *addr = i * 4;
5415 addr++;
5416 }
5417
5418 addr = (unsigned long *)info->memory_base;
5419
5420 for ( i = 0 ; i < limit ; i++ ) {
5421 if ( *addr != i * 4 )
5422 return FALSE;
5423 addr++;
5424 }
5425
5426 memset( info->memory_base, 0, SCA_MEM_SIZE );
5427 return TRUE;
5428 }
5429
5430 /* Load data into PCI adapter shared memory.
5431 *
5432 * The PCI9050 releases control of the local bus
5433 * after completing the current read or write operation.
5434 *
5435 * While the PCI9050 write FIFO not empty, the
5436 * PCI9050 treats all of the writes as a single transaction
5437 * and does not release the bus. This causes DMA latency problems
5438 * at high speeds when copying large data blocks to the shared memory.
5439 *
5440 * This function breaks a write into multiple transations by
5441 * interleaving a read which flushes the write FIFO and 'completes'
5442 * the write transation. This allows any pending DMA request to gain control
5443 * of the local bus in a timely fasion.
5444 */
5445 void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5446 {
5447 /* A load interval of 16 allows for 4 32-bit writes at */
5448 /* 136ns each for a maximum latency of 542ns on the local bus.*/
5449
5450 unsigned short interval = count / sca_pci_load_interval;
5451 unsigned short i;
5452
5453 for ( i = 0 ; i < interval ; i++ )
5454 {
5455 memcpy(dest, src, sca_pci_load_interval);
5456 read_status_reg(info);
5457 dest += sca_pci_load_interval;
5458 src += sca_pci_load_interval;
5459 }
5460
5461 memcpy(dest, src, count % sca_pci_load_interval);
5462 }
5463
5464 void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5465 {
5466 int i;
5467 int linecount;
5468 if (xmit)
5469 printk("%s tx data:\n",info->device_name);
5470 else
5471 printk("%s rx data:\n",info->device_name);
5472
5473 while(count) {
5474 if (count > 16)
5475 linecount = 16;
5476 else
5477 linecount = count;
5478
5479 for(i=0;i<linecount;i++)
5480 printk("%02X ",(unsigned char)data[i]);
5481 for(;i<17;i++)
5482 printk(" ");
5483 for(i=0;i<linecount;i++) {
5484 if (data[i]>=040 && data[i]<=0176)
5485 printk("%c",data[i]);
5486 else
5487 printk(".");
5488 }
5489 printk("\n");
5490
5491 data += linecount;
5492 count -= linecount;
5493 }
5494 } /* end of trace_block() */
5495
5496 /* called when HDLC frame times out
5497 * update stats and do tx completion processing
5498 */
5499 void tx_timeout(unsigned long context)
5500 {
5501 SLMP_INFO *info = (SLMP_INFO*)context;
5502 unsigned long flags;
5503
5504 if ( debug_level >= DEBUG_LEVEL_INFO )
5505 printk( "%s(%d):%s tx_timeout()\n",
5506 __FILE__,__LINE__,info->device_name);
5507 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5508 info->icount.txtimeout++;
5509 }
5510 spin_lock_irqsave(&info->lock,flags);
5511 info->tx_active = 0;
5512 info->tx_count = info->tx_put = info->tx_get = 0;
5513
5514 spin_unlock_irqrestore(&info->lock,flags);
5515
5516 #if SYNCLINK_GENERIC_HDLC
5517 if (info->netcount)
5518 hdlcdev_tx_done(info);
5519 else
5520 #endif
5521 bh_transmit(info);
5522 }
5523
5524 /* called to periodically check the DSR/RI modem signal input status
5525 */
5526 void status_timeout(unsigned long context)
5527 {
5528 u16 status = 0;
5529 SLMP_INFO *info = (SLMP_INFO*)context;
5530 unsigned long flags;
5531 unsigned char delta;
5532
5533
5534 spin_lock_irqsave(&info->lock,flags);
5535 get_signals(info);
5536 spin_unlock_irqrestore(&info->lock,flags);
5537
5538 /* check for DSR/RI state change */
5539
5540 delta = info->old_signals ^ info->serial_signals;
5541 info->old_signals = info->serial_signals;
5542
5543 if (delta & SerialSignal_DSR)
5544 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5545
5546 if (delta & SerialSignal_RI)
5547 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5548
5549 if (delta & SerialSignal_DCD)
5550 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5551
5552 if (delta & SerialSignal_CTS)
5553 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5554
5555 if (status)
5556 isr_io_pin(info,status);
5557
5558 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
5559 }
5560
5561
5562 /* Register Access Routines -
5563 * All registers are memory mapped
5564 */
5565 #define CALC_REGADDR() \
5566 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5567 if (info->port_num > 1) \
5568 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5569 if ( info->port_num & 1) { \
5570 if (Addr > 0x7f) \
5571 RegAddr += 0x40; /* DMA access */ \
5572 else if (Addr > 0x1f && Addr < 0x60) \
5573 RegAddr += 0x20; /* MSCI access */ \
5574 }
5575
5576
5577 unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5578 {
5579 CALC_REGADDR();
5580 return *RegAddr;
5581 }
5582 void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5583 {
5584 CALC_REGADDR();
5585 *RegAddr = Value;
5586 }
5587
5588 u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5589 {
5590 CALC_REGADDR();
5591 return *((u16 *)RegAddr);
5592 }
5593
5594 void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5595 {
5596 CALC_REGADDR();
5597 *((u16 *)RegAddr) = Value;
5598 }
5599
5600 unsigned char read_status_reg(SLMP_INFO * info)
5601 {
5602 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5603 return *RegAddr;
5604 }
5605
5606 void write_control_reg(SLMP_INFO * info)
5607 {
5608 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5609 *RegAddr = info->port_array[0]->ctrlreg_value;
5610 }
5611
5612
5613 static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5614 const struct pci_device_id *ent)
5615 {
5616 if (pci_enable_device(dev)) {
5617 printk("error enabling pci device %p\n", dev);
5618 return -EIO;
5619 }
5620 device_init( ++synclinkmp_adapter_count, dev );
5621 return 0;
5622 }
5623
5624 static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5625 {
5626 }
Support for the Chinese Samsung S3C2440 based development boards