2 * linux/drivers/char/synclink.c
4 * $Id: synclink.c,v 4.38 2005/11/07 16:30:34 paulkf Exp $
6 * Device driver for Microgate SyncLink ISA and PCI
7 * high speed multiprotocol serial adapters.
9 * written by Paul Fulghum for Microgate Corporation
10 * paulkf@microgate.com
12 * Microgate and SyncLink are trademarks of Microgate Corporation
14 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
16 * Original release 01/11/99
18 * This code is released under the GNU General Public License (GPL)
20 * This driver is primarily intended for use in synchronous
21 * HDLC mode. Asynchronous mode is also provided.
23 * When operating in synchronous mode, each call to mgsl_write()
24 * contains exactly one complete HDLC frame. Calling mgsl_put_char
25 * will start assembling an HDLC frame that will not be sent until
26 * mgsl_flush_chars or mgsl_write is called.
28 * Synchronous receive data is reported as complete frames. To accomplish
29 * this, the TTY flip buffer is bypassed (too small to hold largest
30 * frame and may fragment frames) and the line discipline
31 * receive entry point is called directly.
33 * This driver has been tested with a slightly modified ppp.c driver
34 * for synchronous PPP.
37 * Added interface for syncppp.c driver (an alternate synchronous PPP
38 * implementation that also supports Cisco HDLC). Each device instance
39 * registers as a tty device AND a network device (if dosyncppp option
40 * is set for the device). The functionality is determined by which
41 * device interface is opened.
43 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
44 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
45 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
46 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
47 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
48 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
49 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
51 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
53 * OF THE POSSIBILITY OF SUCH DAMAGE.
57 # define BREAKPOINT() asm(" int $3");
59 # define BREAKPOINT() { }
62 #define MAX_ISA_DEVICES 10
63 #define MAX_PCI_DEVICES 10
64 #define MAX_TOTAL_DEVICES 20
66 #include <linux/module.h>
67 #include <linux/errno.h>
68 #include <linux/signal.h>
69 #include <linux/sched.h>
70 #include <linux/timer.h>
71 #include <linux/interrupt.h>
72 #include <linux/pci.h>
73 #include <linux/tty.h>
74 #include <linux/tty_flip.h>
75 #include <linux/serial.h>
76 #include <linux/major.h>
77 #include <linux/string.h>
78 #include <linux/fcntl.h>
79 #include <linux/ptrace.h>
80 #include <linux/ioport.h>
82 #include <linux/slab.h>
83 #include <linux/delay.h>
84 #include <linux/netdevice.h>
85 #include <linux/vmalloc.h>
86 #include <linux/init.h>
87 #include <linux/ioctl.h>
88 #include <linux/synclink.h>
90 #include <asm/system.h>
94 #include <linux/bitops.h>
95 #include <asm/types.h>
96 #include <linux/termios.h>
97 #include <linux/workqueue.h>
98 #include <linux/hdlc.h>
99 #include <linux/dma-mapping.h>
101 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_MODULE))
102 #define SYNCLINK_GENERIC_HDLC 1
104 #define SYNCLINK_GENERIC_HDLC 0
107 #define GET_USER(error,value,addr) error = get_user(value,addr)
108 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
109 #define PUT_USER(error,value,addr) error = put_user(value,addr)
110 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
112 #include <asm/uaccess.h>
114 #define RCLRVALUE 0xffff
116 static MGSL_PARAMS default_params
= {
117 MGSL_MODE_HDLC
, /* unsigned long mode */
118 0, /* unsigned char loopback; */
119 HDLC_FLAG_UNDERRUN_ABORT15
, /* unsigned short flags; */
120 HDLC_ENCODING_NRZI_SPACE
, /* unsigned char encoding; */
121 0, /* unsigned long clock_speed; */
122 0xff, /* unsigned char addr_filter; */
123 HDLC_CRC_16_CCITT
, /* unsigned short crc_type; */
124 HDLC_PREAMBLE_LENGTH_8BITS
, /* unsigned char preamble_length; */
125 HDLC_PREAMBLE_PATTERN_NONE
, /* unsigned char preamble; */
126 9600, /* unsigned long data_rate; */
127 8, /* unsigned char data_bits; */
128 1, /* unsigned char stop_bits; */
129 ASYNC_PARITY_NONE
/* unsigned char parity; */
132 #define SHARED_MEM_ADDRESS_SIZE 0x40000
133 #define BUFFERLISTSIZE 4096
134 #define DMABUFFERSIZE 4096
135 #define MAXRXFRAMES 7
137 typedef struct _DMABUFFERENTRY
139 u32 phys_addr
; /* 32-bit flat physical address of data buffer */
140 volatile u16 count
; /* buffer size/data count */
141 volatile u16 status
; /* Control/status field */
142 volatile u16 rcc
; /* character count field */
143 u16 reserved
; /* padding required by 16C32 */
144 u32 link
; /* 32-bit flat link to next buffer entry */
145 char *virt_addr
; /* virtual address of data buffer */
146 u32 phys_entry
; /* physical address of this buffer entry */
148 } DMABUFFERENTRY
, *DMAPBUFFERENTRY
;
150 /* The queue of BH actions to be performed */
153 #define BH_TRANSMIT 2
156 #define IO_PIN_SHUTDOWN_LIMIT 100
158 struct _input_signal_events
{
169 /* transmit holding buffer definitions*/
170 #define MAX_TX_HOLDING_BUFFERS 5
171 struct tx_holding_buffer
{
173 unsigned char * buffer
;
178 * Device instance data structure
184 int count
; /* count of opens */
187 unsigned short close_delay
;
188 unsigned short closing_wait
; /* time to wait before closing */
190 struct mgsl_icount icount
;
192 struct tty_struct
*tty
;
194 int x_char
; /* xon/xoff character */
195 int blocked_open
; /* # of blocked opens */
196 u16 read_status_mask
;
197 u16 ignore_status_mask
;
198 unsigned char *xmit_buf
;
203 wait_queue_head_t open_wait
;
204 wait_queue_head_t close_wait
;
206 wait_queue_head_t status_event_wait_q
;
207 wait_queue_head_t event_wait_q
;
208 struct timer_list tx_timer
; /* HDLC transmit timeout timer */
209 struct mgsl_struct
*next_device
; /* device list link */
211 spinlock_t irq_spinlock
; /* spinlock for synchronizing with ISR */
212 struct work_struct task
; /* task structure for scheduling bh */
214 u32 EventMask
; /* event trigger mask */
215 u32 RecordedEvents
; /* pending events */
217 u32 max_frame_size
; /* as set by device config */
221 int bh_running
; /* Protection from multiple */
225 int dcd_chkcount
; /* check counts to prevent */
226 int cts_chkcount
; /* too many IRQs if a signal */
227 int dsr_chkcount
; /* is floating */
230 char *buffer_list
; /* virtual address of Rx & Tx buffer lists */
231 u32 buffer_list_phys
;
232 dma_addr_t buffer_list_dma_addr
;
234 unsigned int rx_buffer_count
; /* count of total allocated Rx buffers */
235 DMABUFFERENTRY
*rx_buffer_list
; /* list of receive buffer entries */
236 unsigned int current_rx_buffer
;
238 int num_tx_dma_buffers
; /* number of tx dma frames required */
239 int tx_dma_buffers_used
;
240 unsigned int tx_buffer_count
; /* count of total allocated Tx buffers */
241 DMABUFFERENTRY
*tx_buffer_list
; /* list of transmit buffer entries */
242 int start_tx_dma_buffer
; /* tx dma buffer to start tx dma operation */
243 int current_tx_buffer
; /* next tx dma buffer to be loaded */
245 unsigned char *intermediate_rxbuffer
;
247 int num_tx_holding_buffers
; /* number of tx holding buffer allocated */
248 int get_tx_holding_index
; /* next tx holding buffer for adapter to load */
249 int put_tx_holding_index
; /* next tx holding buffer to store user request */
250 int tx_holding_count
; /* number of tx holding buffers waiting */
251 struct tx_holding_buffer tx_holding_buffers
[MAX_TX_HOLDING_BUFFERS
];
264 char device_name
[25]; /* device instance name */
266 unsigned int bus_type
; /* expansion bus type (ISA,EISA,PCI) */
267 unsigned char bus
; /* expansion bus number (zero based) */
268 unsigned char function
; /* PCI device number */
270 unsigned int io_base
; /* base I/O address of adapter */
271 unsigned int io_addr_size
; /* size of the I/O address range */
272 int io_addr_requested
; /* nonzero if I/O address requested */
274 unsigned int irq_level
; /* interrupt level */
275 unsigned long irq_flags
;
276 int irq_requested
; /* nonzero if IRQ requested */
278 unsigned int dma_level
; /* DMA channel */
279 int dma_requested
; /* nonzero if dma channel requested */
285 MGSL_PARAMS params
; /* communications parameters */
287 unsigned char serial_signals
; /* current serial signal states */
289 int irq_occurred
; /* for diagnostics use */
290 unsigned int init_error
; /* Initialization startup error (DIAGS) */
291 int fDiagnosticsmode
; /* Driver in Diagnostic mode? (DIAGS) */
294 unsigned char* memory_base
; /* shared memory address (PCI only) */
295 u32 phys_memory_base
;
296 int shared_mem_requested
;
298 unsigned char* lcr_base
; /* local config registers (PCI only) */
301 int lcr_mem_requested
;
304 char flag_buf
[MAX_ASYNC_BUFFER_SIZE
];
305 char char_buf
[MAX_ASYNC_BUFFER_SIZE
];
306 BOOLEAN drop_rts_on_tx_done
;
308 BOOLEAN loopmode_insert_requested
;
309 BOOLEAN loopmode_send_done_requested
;
311 struct _input_signal_events input_signal_events
;
313 /* generic HDLC device parts */
318 #if SYNCLINK_GENERIC_HDLC
319 struct net_device
*netdev
;
323 #define MGSL_MAGIC 0x5401
326 * The size of the serial xmit buffer is 1 page, or 4096 bytes
328 #ifndef SERIAL_XMIT_SIZE
329 #define SERIAL_XMIT_SIZE 4096
333 * These macros define the offsets used in calculating the
334 * I/O address of the specified USC registers.
338 #define DCPIN 2 /* Bit 1 of I/O address */
339 #define SDPIN 4 /* Bit 2 of I/O address */
341 #define DCAR 0 /* DMA command/address register */
342 #define CCAR SDPIN /* channel command/address register */
343 #define DATAREG DCPIN + SDPIN /* serial data register */
348 * These macros define the register address (ordinal number)
349 * used for writing address/value pairs to the USC.
352 #define CMR 0x02 /* Channel mode Register */
353 #define CCSR 0x04 /* Channel Command/status Register */
354 #define CCR 0x06 /* Channel Control Register */
355 #define PSR 0x08 /* Port status Register */
356 #define PCR 0x0a /* Port Control Register */
357 #define TMDR 0x0c /* Test mode Data Register */
358 #define TMCR 0x0e /* Test mode Control Register */
359 #define CMCR 0x10 /* Clock mode Control Register */
360 #define HCR 0x12 /* Hardware Configuration Register */
361 #define IVR 0x14 /* Interrupt Vector Register */
362 #define IOCR 0x16 /* Input/Output Control Register */
363 #define ICR 0x18 /* Interrupt Control Register */
364 #define DCCR 0x1a /* Daisy Chain Control Register */
365 #define MISR 0x1c /* Misc Interrupt status Register */
366 #define SICR 0x1e /* status Interrupt Control Register */
367 #define RDR 0x20 /* Receive Data Register */
368 #define RMR 0x22 /* Receive mode Register */
369 #define RCSR 0x24 /* Receive Command/status Register */
370 #define RICR 0x26 /* Receive Interrupt Control Register */
371 #define RSR 0x28 /* Receive Sync Register */
372 #define RCLR 0x2a /* Receive count Limit Register */
373 #define RCCR 0x2c /* Receive Character count Register */
374 #define TC0R 0x2e /* Time Constant 0 Register */
375 #define TDR 0x30 /* Transmit Data Register */
376 #define TMR 0x32 /* Transmit mode Register */
377 #define TCSR 0x34 /* Transmit Command/status Register */
378 #define TICR 0x36 /* Transmit Interrupt Control Register */
379 #define TSR 0x38 /* Transmit Sync Register */
380 #define TCLR 0x3a /* Transmit count Limit Register */
381 #define TCCR 0x3c /* Transmit Character count Register */
382 #define TC1R 0x3e /* Time Constant 1 Register */
386 * MACRO DEFINITIONS FOR DMA REGISTERS
389 #define DCR 0x06 /* DMA Control Register (shared) */
390 #define DACR 0x08 /* DMA Array count Register (shared) */
391 #define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
392 #define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
393 #define DICR 0x18 /* DMA Interrupt Control Register (shared) */
394 #define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
395 #define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
397 #define TDMR 0x02 /* Transmit DMA mode Register */
398 #define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
399 #define TBCR 0x2a /* Transmit Byte count Register */
400 #define TARL 0x2c /* Transmit Address Register (low) */
401 #define TARU 0x2e /* Transmit Address Register (high) */
402 #define NTBCR 0x3a /* Next Transmit Byte count Register */
403 #define NTARL 0x3c /* Next Transmit Address Register (low) */
404 #define NTARU 0x3e /* Next Transmit Address Register (high) */
406 #define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
407 #define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
408 #define RBCR 0xaa /* Receive Byte count Register */
409 #define RARL 0xac /* Receive Address Register (low) */
410 #define RARU 0xae /* Receive Address Register (high) */
411 #define NRBCR 0xba /* Next Receive Byte count Register */
412 #define NRARL 0xbc /* Next Receive Address Register (low) */
413 #define NRARU 0xbe /* Next Receive Address Register (high) */
417 * MACRO DEFINITIONS FOR MODEM STATUS BITS
420 #define MODEMSTATUS_DTR 0x80
421 #define MODEMSTATUS_DSR 0x40
422 #define MODEMSTATUS_RTS 0x20
423 #define MODEMSTATUS_CTS 0x10
424 #define MODEMSTATUS_RI 0x04
425 #define MODEMSTATUS_DCD 0x01
429 * Channel Command/Address Register (CCAR) Command Codes
432 #define RTCmd_Null 0x0000
433 #define RTCmd_ResetHighestIus 0x1000
434 #define RTCmd_TriggerChannelLoadDma 0x2000
435 #define RTCmd_TriggerRxDma 0x2800
436 #define RTCmd_TriggerTxDma 0x3000
437 #define RTCmd_TriggerRxAndTxDma 0x3800
438 #define RTCmd_PurgeRxFifo 0x4800
439 #define RTCmd_PurgeTxFifo 0x5000
440 #define RTCmd_PurgeRxAndTxFifo 0x5800
441 #define RTCmd_LoadRcc 0x6800
442 #define RTCmd_LoadTcc 0x7000
443 #define RTCmd_LoadRccAndTcc 0x7800
444 #define RTCmd_LoadTC0 0x8800
445 #define RTCmd_LoadTC1 0x9000
446 #define RTCmd_LoadTC0AndTC1 0x9800
447 #define RTCmd_SerialDataLSBFirst 0xa000
448 #define RTCmd_SerialDataMSBFirst 0xa800
449 #define RTCmd_SelectBigEndian 0xb000
450 #define RTCmd_SelectLittleEndian 0xb800
454 * DMA Command/Address Register (DCAR) Command Codes
457 #define DmaCmd_Null 0x0000
458 #define DmaCmd_ResetTxChannel 0x1000
459 #define DmaCmd_ResetRxChannel 0x1200
460 #define DmaCmd_StartTxChannel 0x2000
461 #define DmaCmd_StartRxChannel 0x2200
462 #define DmaCmd_ContinueTxChannel 0x3000
463 #define DmaCmd_ContinueRxChannel 0x3200
464 #define DmaCmd_PauseTxChannel 0x4000
465 #define DmaCmd_PauseRxChannel 0x4200
466 #define DmaCmd_AbortTxChannel 0x5000
467 #define DmaCmd_AbortRxChannel 0x5200
468 #define DmaCmd_InitTxChannel 0x7000
469 #define DmaCmd_InitRxChannel 0x7200
470 #define DmaCmd_ResetHighestDmaIus 0x8000
471 #define DmaCmd_ResetAllChannels 0x9000
472 #define DmaCmd_StartAllChannels 0xa000
473 #define DmaCmd_ContinueAllChannels 0xb000
474 #define DmaCmd_PauseAllChannels 0xc000
475 #define DmaCmd_AbortAllChannels 0xd000
476 #define DmaCmd_InitAllChannels 0xf000
478 #define TCmd_Null 0x0000
479 #define TCmd_ClearTxCRC 0x2000
480 #define TCmd_SelectTicrTtsaData 0x4000
481 #define TCmd_SelectTicrTxFifostatus 0x5000
482 #define TCmd_SelectTicrIntLevel 0x6000
483 #define TCmd_SelectTicrdma_level 0x7000
484 #define TCmd_SendFrame 0x8000
485 #define TCmd_SendAbort 0x9000
486 #define TCmd_EnableDleInsertion 0xc000
487 #define TCmd_DisableDleInsertion 0xd000
488 #define TCmd_ClearEofEom 0xe000
489 #define TCmd_SetEofEom 0xf000
491 #define RCmd_Null 0x0000
492 #define RCmd_ClearRxCRC 0x2000
493 #define RCmd_EnterHuntmode 0x3000
494 #define RCmd_SelectRicrRtsaData 0x4000
495 #define RCmd_SelectRicrRxFifostatus 0x5000
496 #define RCmd_SelectRicrIntLevel 0x6000
497 #define RCmd_SelectRicrdma_level 0x7000
500 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
503 #define RECEIVE_STATUS BIT5
504 #define RECEIVE_DATA BIT4
505 #define TRANSMIT_STATUS BIT3
506 #define TRANSMIT_DATA BIT2
512 * Receive status Bits in Receive Command/status Register RCSR
515 #define RXSTATUS_SHORT_FRAME BIT8
516 #define RXSTATUS_CODE_VIOLATION BIT8
517 #define RXSTATUS_EXITED_HUNT BIT7
518 #define RXSTATUS_IDLE_RECEIVED BIT6
519 #define RXSTATUS_BREAK_RECEIVED BIT5
520 #define RXSTATUS_ABORT_RECEIVED BIT5
521 #define RXSTATUS_RXBOUND BIT4
522 #define RXSTATUS_CRC_ERROR BIT3
523 #define RXSTATUS_FRAMING_ERROR BIT3
524 #define RXSTATUS_ABORT BIT2
525 #define RXSTATUS_PARITY_ERROR BIT2
526 #define RXSTATUS_OVERRUN BIT1
527 #define RXSTATUS_DATA_AVAILABLE BIT0
528 #define RXSTATUS_ALL 0x01f6
529 #define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
532 * Values for setting transmit idle mode in
533 * Transmit Control/status Register (TCSR)
535 #define IDLEMODE_FLAGS 0x0000
536 #define IDLEMODE_ALT_ONE_ZERO 0x0100
537 #define IDLEMODE_ZERO 0x0200
538 #define IDLEMODE_ONE 0x0300
539 #define IDLEMODE_ALT_MARK_SPACE 0x0500
540 #define IDLEMODE_SPACE 0x0600
541 #define IDLEMODE_MARK 0x0700
542 #define IDLEMODE_MASK 0x0700
545 * IUSC revision identifiers
547 #define IUSC_SL1660 0x4d44
548 #define IUSC_PRE_SL1660 0x4553
551 * Transmit status Bits in Transmit Command/status Register (TCSR)
554 #define TCSR_PRESERVE 0x0F00
556 #define TCSR_UNDERWAIT BIT11
557 #define TXSTATUS_PREAMBLE_SENT BIT7
558 #define TXSTATUS_IDLE_SENT BIT6
559 #define TXSTATUS_ABORT_SENT BIT5
560 #define TXSTATUS_EOF_SENT BIT4
561 #define TXSTATUS_EOM_SENT BIT4
562 #define TXSTATUS_CRC_SENT BIT3
563 #define TXSTATUS_ALL_SENT BIT2
564 #define TXSTATUS_UNDERRUN BIT1
565 #define TXSTATUS_FIFO_EMPTY BIT0
566 #define TXSTATUS_ALL 0x00fa
567 #define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
570 #define MISCSTATUS_RXC_LATCHED BIT15
571 #define MISCSTATUS_RXC BIT14
572 #define MISCSTATUS_TXC_LATCHED BIT13
573 #define MISCSTATUS_TXC BIT12
574 #define MISCSTATUS_RI_LATCHED BIT11
575 #define MISCSTATUS_RI BIT10
576 #define MISCSTATUS_DSR_LATCHED BIT9
577 #define MISCSTATUS_DSR BIT8
578 #define MISCSTATUS_DCD_LATCHED BIT7
579 #define MISCSTATUS_DCD BIT6
580 #define MISCSTATUS_CTS_LATCHED BIT5
581 #define MISCSTATUS_CTS BIT4
582 #define MISCSTATUS_RCC_UNDERRUN BIT3
583 #define MISCSTATUS_DPLL_NO_SYNC BIT2
584 #define MISCSTATUS_BRG1_ZERO BIT1
585 #define MISCSTATUS_BRG0_ZERO BIT0
587 #define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
588 #define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
590 #define SICR_RXC_ACTIVE BIT15
591 #define SICR_RXC_INACTIVE BIT14
592 #define SICR_RXC (BIT15+BIT14)
593 #define SICR_TXC_ACTIVE BIT13
594 #define SICR_TXC_INACTIVE BIT12
595 #define SICR_TXC (BIT13+BIT12)
596 #define SICR_RI_ACTIVE BIT11
597 #define SICR_RI_INACTIVE BIT10
598 #define SICR_RI (BIT11+BIT10)
599 #define SICR_DSR_ACTIVE BIT9
600 #define SICR_DSR_INACTIVE BIT8
601 #define SICR_DSR (BIT9+BIT8)
602 #define SICR_DCD_ACTIVE BIT7
603 #define SICR_DCD_INACTIVE BIT6
604 #define SICR_DCD (BIT7+BIT6)
605 #define SICR_CTS_ACTIVE BIT5
606 #define SICR_CTS_INACTIVE BIT4
607 #define SICR_CTS (BIT5+BIT4)
608 #define SICR_RCC_UNDERFLOW BIT3
609 #define SICR_DPLL_NO_SYNC BIT2
610 #define SICR_BRG1_ZERO BIT1
611 #define SICR_BRG0_ZERO BIT0
613 void usc_DisableMasterIrqBit( struct mgsl_struct
*info
);
614 void usc_EnableMasterIrqBit( struct mgsl_struct
*info
);
615 void usc_EnableInterrupts( struct mgsl_struct
*info
, u16 IrqMask
);
616 void usc_DisableInterrupts( struct mgsl_struct
*info
, u16 IrqMask
);
617 void usc_ClearIrqPendingBits( struct mgsl_struct
*info
, u16 IrqMask
);
619 #define usc_EnableInterrupts( a, b ) \
620 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
622 #define usc_DisableInterrupts( a, b ) \
623 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
625 #define usc_EnableMasterIrqBit(a) \
626 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
628 #define usc_DisableMasterIrqBit(a) \
629 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
631 #define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
634 * Transmit status Bits in Transmit Control status Register (TCSR)
635 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
638 #define TXSTATUS_PREAMBLE_SENT BIT7
639 #define TXSTATUS_IDLE_SENT BIT6
640 #define TXSTATUS_ABORT_SENT BIT5
641 #define TXSTATUS_EOF BIT4
642 #define TXSTATUS_CRC_SENT BIT3
643 #define TXSTATUS_ALL_SENT BIT2
644 #define TXSTATUS_UNDERRUN BIT1
645 #define TXSTATUS_FIFO_EMPTY BIT0
647 #define DICR_MASTER BIT15
648 #define DICR_TRANSMIT BIT0
649 #define DICR_RECEIVE BIT1
651 #define usc_EnableDmaInterrupts(a,b) \
652 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
654 #define usc_DisableDmaInterrupts(a,b) \
655 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
657 #define usc_EnableStatusIrqs(a,b) \
658 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
660 #define usc_DisablestatusIrqs(a,b) \
661 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
663 /* Transmit status Bits in Transmit Control status Register (TCSR) */
664 /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
667 #define DISABLE_UNCONDITIONAL 0
668 #define DISABLE_END_OF_FRAME 1
669 #define ENABLE_UNCONDITIONAL 2
670 #define ENABLE_AUTO_CTS 3
671 #define ENABLE_AUTO_DCD 3
672 #define usc_EnableTransmitter(a,b) \
673 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
674 #define usc_EnableReceiver(a,b) \
675 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
677 static u16
usc_InDmaReg( struct mgsl_struct
*info
, u16 Port
);
678 static void usc_OutDmaReg( struct mgsl_struct
*info
, u16 Port
, u16 Value
);
679 static void usc_DmaCmd( struct mgsl_struct
*info
, u16 Cmd
);
681 static u16
usc_InReg( struct mgsl_struct
*info
, u16 Port
);
682 static void usc_OutReg( struct mgsl_struct
*info
, u16 Port
, u16 Value
);
683 static void usc_RTCmd( struct mgsl_struct
*info
, u16 Cmd
);
684 void usc_RCmd( struct mgsl_struct
*info
, u16 Cmd
);
685 void usc_TCmd( struct mgsl_struct
*info
, u16 Cmd
);
687 #define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
688 #define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
690 #define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
692 static void usc_process_rxoverrun_sync( struct mgsl_struct
*info
);
693 static void usc_start_receiver( struct mgsl_struct
*info
);
694 static void usc_stop_receiver( struct mgsl_struct
*info
);
696 static void usc_start_transmitter( struct mgsl_struct
*info
);
697 static void usc_stop_transmitter( struct mgsl_struct
*info
);
698 static void usc_set_txidle( struct mgsl_struct
*info
);
699 static void usc_load_txfifo( struct mgsl_struct
*info
);
701 static void usc_enable_aux_clock( struct mgsl_struct
*info
, u32 DataRate
);
702 static void usc_enable_loopback( struct mgsl_struct
*info
, int enable
);
704 static void usc_get_serial_signals( struct mgsl_struct
*info
);
705 static void usc_set_serial_signals( struct mgsl_struct
*info
);
707 static void usc_reset( struct mgsl_struct
*info
);
709 static void usc_set_sync_mode( struct mgsl_struct
*info
);
710 static void usc_set_sdlc_mode( struct mgsl_struct
*info
);
711 static void usc_set_async_mode( struct mgsl_struct
*info
);
712 static void usc_enable_async_clock( struct mgsl_struct
*info
, u32 DataRate
);
714 static void usc_loopback_frame( struct mgsl_struct
*info
);
716 static void mgsl_tx_timeout(unsigned long context
);
719 static void usc_loopmode_cancel_transmit( struct mgsl_struct
* info
);
720 static void usc_loopmode_insert_request( struct mgsl_struct
* info
);
721 static int usc_loopmode_active( struct mgsl_struct
* info
);
722 static void usc_loopmode_send_done( struct mgsl_struct
* info
);
724 static int mgsl_ioctl_common(struct mgsl_struct
*info
, unsigned int cmd
, unsigned long arg
);
726 #if SYNCLINK_GENERIC_HDLC
727 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
728 static void hdlcdev_tx_done(struct mgsl_struct
*info
);
729 static void hdlcdev_rx(struct mgsl_struct
*info
, char *buf
, int size
);
730 static int hdlcdev_init(struct mgsl_struct
*info
);
731 static void hdlcdev_exit(struct mgsl_struct
*info
);
735 * Defines a BUS descriptor value for the PCI adapter
736 * local bus address ranges.
739 #define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
750 static void mgsl_trace_block(struct mgsl_struct
*info
,const char* data
, int count
, int xmit
);
753 * Adapter diagnostic routines
755 static BOOLEAN
mgsl_register_test( struct mgsl_struct
*info
);
756 static BOOLEAN
mgsl_irq_test( struct mgsl_struct
*info
);
757 static BOOLEAN
mgsl_dma_test( struct mgsl_struct
*info
);
758 static BOOLEAN
mgsl_memory_test( struct mgsl_struct
*info
);
759 static int mgsl_adapter_test( struct mgsl_struct
*info
);
762 * device and resource management routines
764 static int mgsl_claim_resources(struct mgsl_struct
*info
);
765 static void mgsl_release_resources(struct mgsl_struct
*info
);
766 static void mgsl_add_device(struct mgsl_struct
*info
);
767 static struct mgsl_struct
* mgsl_allocate_device(void);
770 * DMA buffer manupulation functions.
772 static void mgsl_free_rx_frame_buffers( struct mgsl_struct
*info
, unsigned int StartIndex
, unsigned int EndIndex
);
773 static int mgsl_get_rx_frame( struct mgsl_struct
*info
);
774 static int mgsl_get_raw_rx_frame( struct mgsl_struct
*info
);
775 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct
*info
);
776 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct
*info
);
777 static int num_free_tx_dma_buffers(struct mgsl_struct
*info
);
778 static void mgsl_load_tx_dma_buffer( struct mgsl_struct
*info
, const char *Buffer
, unsigned int BufferSize
);
779 static void mgsl_load_pci_memory(char* TargetPtr
, const char* SourcePtr
, unsigned short count
);
782 * DMA and Shared Memory buffer allocation and formatting
784 static int mgsl_allocate_dma_buffers(struct mgsl_struct
*info
);
785 static void mgsl_free_dma_buffers(struct mgsl_struct
*info
);
786 static int mgsl_alloc_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
,int Buffercount
);
787 static void mgsl_free_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
,int Buffercount
);
788 static int mgsl_alloc_buffer_list_memory(struct mgsl_struct
*info
);
789 static void mgsl_free_buffer_list_memory(struct mgsl_struct
*info
);
790 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct
*info
);
791 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct
*info
);
792 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct
*info
);
793 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct
*info
);
794 static int load_next_tx_holding_buffer(struct mgsl_struct
*info
);
795 static int save_tx_buffer_request(struct mgsl_struct
*info
,const char *Buffer
, unsigned int BufferSize
);
798 * Bottom half interrupt handlers
800 static void mgsl_bh_handler(struct work_struct
*work
);
801 static void mgsl_bh_receive(struct mgsl_struct
*info
);
802 static void mgsl_bh_transmit(struct mgsl_struct
*info
);
803 static void mgsl_bh_status(struct mgsl_struct
*info
);
806 * Interrupt handler routines and dispatch table.
808 static void mgsl_isr_null( struct mgsl_struct
*info
);
809 static void mgsl_isr_transmit_data( struct mgsl_struct
*info
);
810 static void mgsl_isr_receive_data( struct mgsl_struct
*info
);
811 static void mgsl_isr_receive_status( struct mgsl_struct
*info
);
812 static void mgsl_isr_transmit_status( struct mgsl_struct
*info
);
813 static void mgsl_isr_io_pin( struct mgsl_struct
*info
);
814 static void mgsl_isr_misc( struct mgsl_struct
*info
);
815 static void mgsl_isr_receive_dma( struct mgsl_struct
*info
);
816 static void mgsl_isr_transmit_dma( struct mgsl_struct
*info
);
818 typedef void (*isr_dispatch_func
)(struct mgsl_struct
*);
820 static isr_dispatch_func UscIsrTable
[7] =
825 mgsl_isr_transmit_data
,
826 mgsl_isr_transmit_status
,
827 mgsl_isr_receive_data
,
828 mgsl_isr_receive_status
832 * ioctl call handlers
834 static int tiocmget(struct tty_struct
*tty
, struct file
*file
);
835 static int tiocmset(struct tty_struct
*tty
, struct file
*file
,
836 unsigned int set
, unsigned int clear
);
837 static int mgsl_get_stats(struct mgsl_struct
* info
, struct mgsl_icount
838 __user
*user_icount
);
839 static int mgsl_get_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*user_params
);
840 static int mgsl_set_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*new_params
);
841 static int mgsl_get_txidle(struct mgsl_struct
* info
, int __user
*idle_mode
);
842 static int mgsl_set_txidle(struct mgsl_struct
* info
, int idle_mode
);
843 static int mgsl_txenable(struct mgsl_struct
* info
, int enable
);
844 static int mgsl_txabort(struct mgsl_struct
* info
);
845 static int mgsl_rxenable(struct mgsl_struct
* info
, int enable
);
846 static int mgsl_wait_event(struct mgsl_struct
* info
, int __user
*mask
);
847 static int mgsl_loopmode_send_done( struct mgsl_struct
* info
);
849 /* set non-zero on successful registration with PCI subsystem */
850 static int pci_registered
;
853 * Global linked list of SyncLink devices
855 static struct mgsl_struct
*mgsl_device_list
;
856 static int mgsl_device_count
;
859 * Set this param to non-zero to load eax with the
860 * .text section address and breakpoint on module load.
861 * This is useful for use with gdb and add-symbol-file command.
863 static int break_on_load
;
866 * Driver major number, defaults to zero to get auto
867 * assigned major number. May be forced as module parameter.
872 * Array of user specified options for ISA adapters.
874 static int io
[MAX_ISA_DEVICES
];
875 static int irq
[MAX_ISA_DEVICES
];
876 static int dma
[MAX_ISA_DEVICES
];
877 static int debug_level
;
878 static int maxframe
[MAX_TOTAL_DEVICES
];
879 static int dosyncppp
[MAX_TOTAL_DEVICES
];
880 static int txdmabufs
[MAX_TOTAL_DEVICES
];
881 static int txholdbufs
[MAX_TOTAL_DEVICES
];
883 module_param(break_on_load
, bool, 0);
884 module_param(ttymajor
, int, 0);
885 module_param_array(io
, int, NULL
, 0);
886 module_param_array(irq
, int, NULL
, 0);
887 module_param_array(dma
, int, NULL
, 0);
888 module_param(debug_level
, int, 0);
889 module_param_array(maxframe
, int, NULL
, 0);
890 module_param_array(dosyncppp
, int, NULL
, 0);
891 module_param_array(txdmabufs
, int, NULL
, 0);
892 module_param_array(txholdbufs
, int, NULL
, 0);
894 static char *driver_name
= "SyncLink serial driver";
895 static char *driver_version
= "$Revision: 4.38 $";
897 static int synclink_init_one (struct pci_dev
*dev
,
898 const struct pci_device_id
*ent
);
899 static void synclink_remove_one (struct pci_dev
*dev
);
901 static struct pci_device_id synclink_pci_tbl
[] = {
902 { PCI_VENDOR_ID_MICROGATE
, PCI_DEVICE_ID_MICROGATE_USC
, PCI_ANY_ID
, PCI_ANY_ID
, },
903 { PCI_VENDOR_ID_MICROGATE
, 0x0210, PCI_ANY_ID
, PCI_ANY_ID
, },
904 { 0, }, /* terminate list */
906 MODULE_DEVICE_TABLE(pci
, synclink_pci_tbl
);
908 MODULE_LICENSE("GPL");
910 static struct pci_driver synclink_pci_driver
= {
912 .id_table
= synclink_pci_tbl
,
913 .probe
= synclink_init_one
,
914 .remove
= __devexit_p(synclink_remove_one
),
917 static struct tty_driver
*serial_driver
;
919 /* number of characters left in xmit buffer before we ask for more */
920 #define WAKEUP_CHARS 256
923 static void mgsl_change_params(struct mgsl_struct
*info
);
924 static void mgsl_wait_until_sent(struct tty_struct
*tty
, int timeout
);
927 * 1st function defined in .text section. Calling this function in
928 * init_module() followed by a breakpoint allows a remote debugger
929 * (gdb) to get the .text address for the add-symbol-file command.
930 * This allows remote debugging of dynamically loadable modules.
932 static void* mgsl_get_text_ptr(void)
934 return mgsl_get_text_ptr
;
937 static inline int mgsl_paranoia_check(struct mgsl_struct
*info
,
938 char *name
, const char *routine
)
940 #ifdef MGSL_PARANOIA_CHECK
941 static const char *badmagic
=
942 "Warning: bad magic number for mgsl struct (%s) in %s\n";
943 static const char *badinfo
=
944 "Warning: null mgsl_struct for (%s) in %s\n";
947 printk(badinfo
, name
, routine
);
950 if (info
->magic
!= MGSL_MAGIC
) {
951 printk(badmagic
, name
, routine
);
962 * line discipline callback wrappers
964 * The wrappers maintain line discipline references
965 * while calling into the line discipline.
967 * ldisc_receive_buf - pass receive data to line discipline
970 static void ldisc_receive_buf(struct tty_struct
*tty
,
971 const __u8
*data
, char *flags
, int count
)
973 struct tty_ldisc
*ld
;
976 ld
= tty_ldisc_ref(tty
);
979 ld
->receive_buf(tty
, data
, flags
, count
);
984 /* mgsl_stop() throttle (stop) transmitter
986 * Arguments: tty pointer to tty info structure
989 static void mgsl_stop(struct tty_struct
*tty
)
991 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
994 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_stop"))
997 if ( debug_level
>= DEBUG_LEVEL_INFO
)
998 printk("mgsl_stop(%s)\n",info
->device_name
);
1000 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1001 if (info
->tx_enabled
)
1002 usc_stop_transmitter(info
);
1003 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1005 } /* end of mgsl_stop() */
1007 /* mgsl_start() release (start) transmitter
1009 * Arguments: tty pointer to tty info structure
1010 * Return Value: None
1012 static void mgsl_start(struct tty_struct
*tty
)
1014 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
1015 unsigned long flags
;
1017 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_start"))
1020 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1021 printk("mgsl_start(%s)\n",info
->device_name
);
1023 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1024 if (!info
->tx_enabled
)
1025 usc_start_transmitter(info
);
1026 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1028 } /* end of mgsl_start() */
1031 * Bottom half work queue access functions
1034 /* mgsl_bh_action() Return next bottom half action to perform.
1035 * Return Value: BH action code or 0 if nothing to do.
1037 static int mgsl_bh_action(struct mgsl_struct
*info
)
1039 unsigned long flags
;
1042 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1044 if (info
->pending_bh
& BH_RECEIVE
) {
1045 info
->pending_bh
&= ~BH_RECEIVE
;
1047 } else if (info
->pending_bh
& BH_TRANSMIT
) {
1048 info
->pending_bh
&= ~BH_TRANSMIT
;
1050 } else if (info
->pending_bh
& BH_STATUS
) {
1051 info
->pending_bh
&= ~BH_STATUS
;
1056 /* Mark BH routine as complete */
1057 info
->bh_running
= 0;
1058 info
->bh_requested
= 0;
1061 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1067 * Perform bottom half processing of work items queued by ISR.
1069 static void mgsl_bh_handler(struct work_struct
*work
)
1071 struct mgsl_struct
*info
=
1072 container_of(work
, struct mgsl_struct
, task
);
1078 if ( debug_level
>= DEBUG_LEVEL_BH
)
1079 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1080 __FILE__
,__LINE__
,info
->device_name
);
1082 info
->bh_running
= 1;
1084 while((action
= mgsl_bh_action(info
)) != 0) {
1086 /* Process work item */
1087 if ( debug_level
>= DEBUG_LEVEL_BH
)
1088 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1089 __FILE__
,__LINE__
,action
);
1094 mgsl_bh_receive(info
);
1097 mgsl_bh_transmit(info
);
1100 mgsl_bh_status(info
);
1103 /* unknown work item ID */
1104 printk("Unknown work item ID=%08X!\n", action
);
1109 if ( debug_level
>= DEBUG_LEVEL_BH
)
1110 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1111 __FILE__
,__LINE__
,info
->device_name
);
1114 static void mgsl_bh_receive(struct mgsl_struct
*info
)
1116 int (*get_rx_frame
)(struct mgsl_struct
*info
) =
1117 (info
->params
.mode
== MGSL_MODE_HDLC
? mgsl_get_rx_frame
: mgsl_get_raw_rx_frame
);
1119 if ( debug_level
>= DEBUG_LEVEL_BH
)
1120 printk( "%s(%d):mgsl_bh_receive(%s)\n",
1121 __FILE__
,__LINE__
,info
->device_name
);
1125 if (info
->rx_rcc_underrun
) {
1126 unsigned long flags
;
1127 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1128 usc_start_receiver(info
);
1129 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1132 } while(get_rx_frame(info
));
1135 static void mgsl_bh_transmit(struct mgsl_struct
*info
)
1137 struct tty_struct
*tty
= info
->tty
;
1138 unsigned long flags
;
1140 if ( debug_level
>= DEBUG_LEVEL_BH
)
1141 printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1142 __FILE__
,__LINE__
,info
->device_name
);
1147 /* if transmitter idle and loopmode_send_done_requested
1148 * then start echoing RxD to TxD
1150 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1151 if ( !info
->tx_active
&& info
->loopmode_send_done_requested
)
1152 usc_loopmode_send_done( info
);
1153 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1156 static void mgsl_bh_status(struct mgsl_struct
*info
)
1158 if ( debug_level
>= DEBUG_LEVEL_BH
)
1159 printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1160 __FILE__
,__LINE__
,info
->device_name
);
1162 info
->ri_chkcount
= 0;
1163 info
->dsr_chkcount
= 0;
1164 info
->dcd_chkcount
= 0;
1165 info
->cts_chkcount
= 0;
1168 /* mgsl_isr_receive_status()
1170 * Service a receive status interrupt. The type of status
1171 * interrupt is indicated by the state of the RCSR.
1172 * This is only used for HDLC mode.
1174 * Arguments: info pointer to device instance data
1175 * Return Value: None
1177 static void mgsl_isr_receive_status( struct mgsl_struct
*info
)
1179 u16 status
= usc_InReg( info
, RCSR
);
1181 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1182 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1183 __FILE__
,__LINE__
,status
);
1185 if ( (status
& RXSTATUS_ABORT_RECEIVED
) &&
1186 info
->loopmode_insert_requested
&&
1187 usc_loopmode_active(info
) )
1189 ++info
->icount
.rxabort
;
1190 info
->loopmode_insert_requested
= FALSE
;
1192 /* clear CMR:13 to start echoing RxD to TxD */
1193 info
->cmr_value
&= ~BIT13
;
1194 usc_OutReg(info
, CMR
, info
->cmr_value
);
1196 /* disable received abort irq (no longer required) */
1197 usc_OutReg(info
, RICR
,
1198 (usc_InReg(info
, RICR
) & ~RXSTATUS_ABORT_RECEIVED
));
1201 if (status
& (RXSTATUS_EXITED_HUNT
+ RXSTATUS_IDLE_RECEIVED
)) {
1202 if (status
& RXSTATUS_EXITED_HUNT
)
1203 info
->icount
.exithunt
++;
1204 if (status
& RXSTATUS_IDLE_RECEIVED
)
1205 info
->icount
.rxidle
++;
1206 wake_up_interruptible(&info
->event_wait_q
);
1209 if (status
& RXSTATUS_OVERRUN
){
1210 info
->icount
.rxover
++;
1211 usc_process_rxoverrun_sync( info
);
1214 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
1215 usc_UnlatchRxstatusBits( info
, status
);
1217 } /* end of mgsl_isr_receive_status() */
1219 /* mgsl_isr_transmit_status()
1221 * Service a transmit status interrupt
1222 * HDLC mode :end of transmit frame
1223 * Async mode:all data is sent
1224 * transmit status is indicated by bits in the TCSR.
1226 * Arguments: info pointer to device instance data
1227 * Return Value: None
1229 static void mgsl_isr_transmit_status( struct mgsl_struct
*info
)
1231 u16 status
= usc_InReg( info
, TCSR
);
1233 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1234 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1235 __FILE__
,__LINE__
,status
);
1237 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
1238 usc_UnlatchTxstatusBits( info
, status
);
1240 if ( status
& (TXSTATUS_UNDERRUN
| TXSTATUS_ABORT_SENT
) )
1242 /* finished sending HDLC abort. This may leave */
1243 /* the TxFifo with data from the aborted frame */
1244 /* so purge the TxFifo. Also shutdown the DMA */
1245 /* channel in case there is data remaining in */
1246 /* the DMA buffer */
1247 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
1248 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
1251 if ( status
& TXSTATUS_EOF_SENT
)
1252 info
->icount
.txok
++;
1253 else if ( status
& TXSTATUS_UNDERRUN
)
1254 info
->icount
.txunder
++;
1255 else if ( status
& TXSTATUS_ABORT_SENT
)
1256 info
->icount
.txabort
++;
1258 info
->icount
.txunder
++;
1260 info
->tx_active
= 0;
1261 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
1262 del_timer(&info
->tx_timer
);
1264 if ( info
->drop_rts_on_tx_done
) {
1265 usc_get_serial_signals( info
);
1266 if ( info
->serial_signals
& SerialSignal_RTS
) {
1267 info
->serial_signals
&= ~SerialSignal_RTS
;
1268 usc_set_serial_signals( info
);
1270 info
->drop_rts_on_tx_done
= 0;
1273 #if SYNCLINK_GENERIC_HDLC
1275 hdlcdev_tx_done(info
);
1279 if (info
->tty
->stopped
|| info
->tty
->hw_stopped
) {
1280 usc_stop_transmitter(info
);
1283 info
->pending_bh
|= BH_TRANSMIT
;
1286 } /* end of mgsl_isr_transmit_status() */
1288 /* mgsl_isr_io_pin()
1290 * Service an Input/Output pin interrupt. The type of
1291 * interrupt is indicated by bits in the MISR
1293 * Arguments: info pointer to device instance data
1294 * Return Value: None
1296 static void mgsl_isr_io_pin( struct mgsl_struct
*info
)
1298 struct mgsl_icount
*icount
;
1299 u16 status
= usc_InReg( info
, MISR
);
1301 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1302 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1303 __FILE__
,__LINE__
,status
);
1305 usc_ClearIrqPendingBits( info
, IO_PIN
);
1306 usc_UnlatchIostatusBits( info
, status
);
1308 if (status
& (MISCSTATUS_CTS_LATCHED
| MISCSTATUS_DCD_LATCHED
|
1309 MISCSTATUS_DSR_LATCHED
| MISCSTATUS_RI_LATCHED
) ) {
1310 icount
= &info
->icount
;
1311 /* update input line counters */
1312 if (status
& MISCSTATUS_RI_LATCHED
) {
1313 if ((info
->ri_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1314 usc_DisablestatusIrqs(info
,SICR_RI
);
1316 if ( status
& MISCSTATUS_RI
)
1317 info
->input_signal_events
.ri_up
++;
1319 info
->input_signal_events
.ri_down
++;
1321 if (status
& MISCSTATUS_DSR_LATCHED
) {
1322 if ((info
->dsr_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1323 usc_DisablestatusIrqs(info
,SICR_DSR
);
1325 if ( status
& MISCSTATUS_DSR
)
1326 info
->input_signal_events
.dsr_up
++;
1328 info
->input_signal_events
.dsr_down
++;
1330 if (status
& MISCSTATUS_DCD_LATCHED
) {
1331 if ((info
->dcd_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1332 usc_DisablestatusIrqs(info
,SICR_DCD
);
1334 if (status
& MISCSTATUS_DCD
) {
1335 info
->input_signal_events
.dcd_up
++;
1337 info
->input_signal_events
.dcd_down
++;
1338 #if SYNCLINK_GENERIC_HDLC
1339 if (info
->netcount
) {
1340 if (status
& MISCSTATUS_DCD
)
1341 netif_carrier_on(info
->netdev
);
1343 netif_carrier_off(info
->netdev
);
1347 if (status
& MISCSTATUS_CTS_LATCHED
)
1349 if ((info
->cts_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1350 usc_DisablestatusIrqs(info
,SICR_CTS
);
1352 if ( status
& MISCSTATUS_CTS
)
1353 info
->input_signal_events
.cts_up
++;
1355 info
->input_signal_events
.cts_down
++;
1357 wake_up_interruptible(&info
->status_event_wait_q
);
1358 wake_up_interruptible(&info
->event_wait_q
);
1360 if ( (info
->flags
& ASYNC_CHECK_CD
) &&
1361 (status
& MISCSTATUS_DCD_LATCHED
) ) {
1362 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1363 printk("%s CD now %s...", info
->device_name
,
1364 (status
& MISCSTATUS_DCD
) ? "on" : "off");
1365 if (status
& MISCSTATUS_DCD
)
1366 wake_up_interruptible(&info
->open_wait
);
1368 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1369 printk("doing serial hangup...");
1371 tty_hangup(info
->tty
);
1375 if ( (info
->flags
& ASYNC_CTS_FLOW
) &&
1376 (status
& MISCSTATUS_CTS_LATCHED
) ) {
1377 if (info
->tty
->hw_stopped
) {
1378 if (status
& MISCSTATUS_CTS
) {
1379 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1380 printk("CTS tx start...");
1382 info
->tty
->hw_stopped
= 0;
1383 usc_start_transmitter(info
);
1384 info
->pending_bh
|= BH_TRANSMIT
;
1388 if (!(status
& MISCSTATUS_CTS
)) {
1389 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1390 printk("CTS tx stop...");
1392 info
->tty
->hw_stopped
= 1;
1393 usc_stop_transmitter(info
);
1399 info
->pending_bh
|= BH_STATUS
;
1401 /* for diagnostics set IRQ flag */
1402 if ( status
& MISCSTATUS_TXC_LATCHED
){
1403 usc_OutReg( info
, SICR
,
1404 (unsigned short)(usc_InReg(info
,SICR
) & ~(SICR_TXC_ACTIVE
+SICR_TXC_INACTIVE
)) );
1405 usc_UnlatchIostatusBits( info
, MISCSTATUS_TXC_LATCHED
);
1406 info
->irq_occurred
= 1;
1409 } /* end of mgsl_isr_io_pin() */
1411 /* mgsl_isr_transmit_data()
1413 * Service a transmit data interrupt (async mode only).
1415 * Arguments: info pointer to device instance data
1416 * Return Value: None
1418 static void mgsl_isr_transmit_data( struct mgsl_struct
*info
)
1420 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1421 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1422 __FILE__
,__LINE__
,info
->xmit_cnt
);
1424 usc_ClearIrqPendingBits( info
, TRANSMIT_DATA
);
1426 if (info
->tty
->stopped
|| info
->tty
->hw_stopped
) {
1427 usc_stop_transmitter(info
);
1431 if ( info
->xmit_cnt
)
1432 usc_load_txfifo( info
);
1434 info
->tx_active
= 0;
1436 if (info
->xmit_cnt
< WAKEUP_CHARS
)
1437 info
->pending_bh
|= BH_TRANSMIT
;
1439 } /* end of mgsl_isr_transmit_data() */
1441 /* mgsl_isr_receive_data()
1443 * Service a receive data interrupt. This occurs
1444 * when operating in asynchronous interrupt transfer mode.
1445 * The receive data FIFO is flushed to the receive data buffers.
1447 * Arguments: info pointer to device instance data
1448 * Return Value: None
1450 static void mgsl_isr_receive_data( struct mgsl_struct
*info
)
1455 unsigned char DataByte
;
1456 struct tty_struct
*tty
= info
->tty
;
1457 struct mgsl_icount
*icount
= &info
->icount
;
1459 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1460 printk("%s(%d):mgsl_isr_receive_data\n",
1463 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
);
1465 /* select FIFO status for RICR readback */
1466 usc_RCmd( info
, RCmd_SelectRicrRxFifostatus
);
1468 /* clear the Wordstatus bit so that status readback */
1469 /* only reflects the status of this byte */
1470 usc_OutReg( info
, RICR
+LSBONLY
, (u16
)(usc_InReg(info
, RICR
+LSBONLY
) & ~BIT3
));
1472 /* flush the receive FIFO */
1474 while( (Fifocount
= (usc_InReg(info
,RICR
) >> 8)) ) {
1477 /* read one byte from RxFIFO */
1478 outw( (inw(info
->io_base
+ CCAR
) & 0x0780) | (RDR
+LSBONLY
),
1479 info
->io_base
+ CCAR
);
1480 DataByte
= inb( info
->io_base
+ CCAR
);
1482 /* get the status of the received byte */
1483 status
= usc_InReg(info
, RCSR
);
1484 if ( status
& (RXSTATUS_FRAMING_ERROR
+ RXSTATUS_PARITY_ERROR
+
1485 RXSTATUS_OVERRUN
+ RXSTATUS_BREAK_RECEIVED
) )
1486 usc_UnlatchRxstatusBits(info
,RXSTATUS_ALL
);
1491 if ( status
& (RXSTATUS_FRAMING_ERROR
+ RXSTATUS_PARITY_ERROR
+
1492 RXSTATUS_OVERRUN
+ RXSTATUS_BREAK_RECEIVED
) ) {
1493 printk("rxerr=%04X\n",status
);
1494 /* update error statistics */
1495 if ( status
& RXSTATUS_BREAK_RECEIVED
) {
1496 status
&= ~(RXSTATUS_FRAMING_ERROR
+ RXSTATUS_PARITY_ERROR
);
1498 } else if (status
& RXSTATUS_PARITY_ERROR
)
1500 else if (status
& RXSTATUS_FRAMING_ERROR
)
1502 else if (status
& RXSTATUS_OVERRUN
) {
1503 /* must issue purge fifo cmd before */
1504 /* 16C32 accepts more receive chars */
1505 usc_RTCmd(info
,RTCmd_PurgeRxFifo
);
1509 /* discard char if tty control flags say so */
1510 if (status
& info
->ignore_status_mask
)
1513 status
&= info
->read_status_mask
;
1515 if (status
& RXSTATUS_BREAK_RECEIVED
) {
1517 if (info
->flags
& ASYNC_SAK
)
1519 } else if (status
& RXSTATUS_PARITY_ERROR
)
1521 else if (status
& RXSTATUS_FRAMING_ERROR
)
1523 } /* end of if (error) */
1524 tty_insert_flip_char(tty
, DataByte
, flag
);
1525 if (status
& RXSTATUS_OVERRUN
) {
1526 /* Overrun is special, since it's
1527 * reported immediately, and doesn't
1528 * affect the current character
1530 work
+= tty_insert_flip_char(tty
, 0, TTY_OVERRUN
);
1534 if ( debug_level
>= DEBUG_LEVEL_ISR
) {
1535 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1536 __FILE__
,__LINE__
,icount
->rx
,icount
->brk
,
1537 icount
->parity
,icount
->frame
,icount
->overrun
);
1541 tty_flip_buffer_push(tty
);
1546 * Service a miscellaneous interrupt source.
1548 * Arguments: info pointer to device extension (instance data)
1549 * Return Value: None
1551 static void mgsl_isr_misc( struct mgsl_struct
*info
)
1553 u16 status
= usc_InReg( info
, MISR
);
1555 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1556 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1557 __FILE__
,__LINE__
,status
);
1559 if ((status
& MISCSTATUS_RCC_UNDERRUN
) &&
1560 (info
->params
.mode
== MGSL_MODE_HDLC
)) {
1562 /* turn off receiver and rx DMA */
1563 usc_EnableReceiver(info
,DISABLE_UNCONDITIONAL
);
1564 usc_DmaCmd(info
, DmaCmd_ResetRxChannel
);
1565 usc_UnlatchRxstatusBits(info
, RXSTATUS_ALL
);
1566 usc_ClearIrqPendingBits(info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
1567 usc_DisableInterrupts(info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
1569 /* schedule BH handler to restart receiver */
1570 info
->pending_bh
|= BH_RECEIVE
;
1571 info
->rx_rcc_underrun
= 1;
1574 usc_ClearIrqPendingBits( info
, MISC
);
1575 usc_UnlatchMiscstatusBits( info
, status
);
1577 } /* end of mgsl_isr_misc() */
1581 * Services undefined interrupt vectors from the
1582 * USC. (hence this function SHOULD never be called)
1584 * Arguments: info pointer to device extension (instance data)
1585 * Return Value: None
1587 static void mgsl_isr_null( struct mgsl_struct
*info
)
1590 } /* end of mgsl_isr_null() */
1592 /* mgsl_isr_receive_dma()
1594 * Service a receive DMA channel interrupt.
1595 * For this driver there are two sources of receive DMA interrupts
1596 * as identified in the Receive DMA mode Register (RDMR):
1598 * BIT3 EOA/EOL End of List, all receive buffers in receive
1599 * buffer list have been filled (no more free buffers
1600 * available). The DMA controller has shut down.
1602 * BIT2 EOB End of Buffer. This interrupt occurs when a receive
1603 * DMA buffer is terminated in response to completion
1604 * of a good frame or a frame with errors. The status
1605 * of the frame is stored in the buffer entry in the
1606 * list of receive buffer entries.
1608 * Arguments: info pointer to device instance data
1609 * Return Value: None
1611 static void mgsl_isr_receive_dma( struct mgsl_struct
*info
)
1615 /* clear interrupt pending and IUS bit for Rx DMA IRQ */
1616 usc_OutDmaReg( info
, CDIR
, BIT9
+BIT1
);
1618 /* Read the receive DMA status to identify interrupt type. */
1619 /* This also clears the status bits. */
1620 status
= usc_InDmaReg( info
, RDMR
);
1622 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1623 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1624 __FILE__
,__LINE__
,info
->device_name
,status
);
1626 info
->pending_bh
|= BH_RECEIVE
;
1628 if ( status
& BIT3
) {
1629 info
->rx_overflow
= 1;
1630 info
->icount
.buf_overrun
++;
1633 } /* end of mgsl_isr_receive_dma() */
1635 /* mgsl_isr_transmit_dma()
1637 * This function services a transmit DMA channel interrupt.
1639 * For this driver there is one source of transmit DMA interrupts
1640 * as identified in the Transmit DMA Mode Register (TDMR):
1642 * BIT2 EOB End of Buffer. This interrupt occurs when a
1643 * transmit DMA buffer has been emptied.
1645 * The driver maintains enough transmit DMA buffers to hold at least
1646 * one max frame size transmit frame. When operating in a buffered
1647 * transmit mode, there may be enough transmit DMA buffers to hold at
1648 * least two or more max frame size frames. On an EOB condition,
1649 * determine if there are any queued transmit buffers and copy into
1650 * transmit DMA buffers if we have room.
1652 * Arguments: info pointer to device instance data
1653 * Return Value: None
1655 static void mgsl_isr_transmit_dma( struct mgsl_struct
*info
)
1659 /* clear interrupt pending and IUS bit for Tx DMA IRQ */
1660 usc_OutDmaReg(info
, CDIR
, BIT8
+BIT0
);
1662 /* Read the transmit DMA status to identify interrupt type. */
1663 /* This also clears the status bits. */
1665 status
= usc_InDmaReg( info
, TDMR
);
1667 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1668 printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1669 __FILE__
,__LINE__
,info
->device_name
,status
);
1671 if ( status
& BIT2
) {
1672 --info
->tx_dma_buffers_used
;
1674 /* if there are transmit frames queued,
1675 * try to load the next one
1677 if ( load_next_tx_holding_buffer(info
) ) {
1678 /* if call returns non-zero value, we have
1679 * at least one free tx holding buffer
1681 info
->pending_bh
|= BH_TRANSMIT
;
1685 } /* end of mgsl_isr_transmit_dma() */
1689 * Interrupt service routine entry point.
1693 * irq interrupt number that caused interrupt
1694 * dev_id device ID supplied during interrupt registration
1696 * Return Value: None
1698 static irqreturn_t
mgsl_interrupt(int dummy
, void *dev_id
)
1700 struct mgsl_struct
*info
= dev_id
;
1704 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1705 printk(KERN_DEBUG
"%s(%d):mgsl_interrupt(%d)entry.\n",
1706 __FILE__
, __LINE__
, info
->irq_level
);
1708 spin_lock(&info
->irq_spinlock
);
1711 /* Read the interrupt vectors from hardware. */
1712 UscVector
= usc_InReg(info
, IVR
) >> 9;
1713 DmaVector
= usc_InDmaReg(info
, DIVR
);
1715 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1716 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1717 __FILE__
,__LINE__
,info
->device_name
,UscVector
,DmaVector
);
1719 if ( !UscVector
&& !DmaVector
)
1722 /* Dispatch interrupt vector */
1724 (*UscIsrTable
[UscVector
])(info
);
1725 else if ( (DmaVector
&(BIT10
|BIT9
)) == BIT10
)
1726 mgsl_isr_transmit_dma(info
);
1728 mgsl_isr_receive_dma(info
);
1730 if ( info
->isr_overflow
) {
1731 printk(KERN_ERR
"%s(%d):%s isr overflow irq=%d\n",
1732 __FILE__
, __LINE__
, info
->device_name
, info
->irq_level
);
1733 usc_DisableMasterIrqBit(info
);
1734 usc_DisableDmaInterrupts(info
,DICR_MASTER
);
1739 /* Request bottom half processing if there's something
1740 * for it to do and the bh is not already running
1743 if ( info
->pending_bh
&& !info
->bh_running
&& !info
->bh_requested
) {
1744 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1745 printk("%s(%d):%s queueing bh task.\n",
1746 __FILE__
,__LINE__
,info
->device_name
);
1747 schedule_work(&info
->task
);
1748 info
->bh_requested
= 1;
1751 spin_unlock(&info
->irq_spinlock
);
1753 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1754 printk(KERN_DEBUG
"%s(%d):mgsl_interrupt(%d)exit.\n",
1755 __FILE__
, __LINE__
, info
->irq_level
);
1758 } /* end of mgsl_interrupt() */
1762 * Initialize and start device.
1764 * Arguments: info pointer to device instance data
1765 * Return Value: 0 if success, otherwise error code
1767 static int startup(struct mgsl_struct
* info
)
1771 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1772 printk("%s(%d):mgsl_startup(%s)\n",__FILE__
,__LINE__
,info
->device_name
);
1774 if (info
->flags
& ASYNC_INITIALIZED
)
1777 if (!info
->xmit_buf
) {
1778 /* allocate a page of memory for a transmit buffer */
1779 info
->xmit_buf
= (unsigned char *)get_zeroed_page(GFP_KERNEL
);
1780 if (!info
->xmit_buf
) {
1781 printk(KERN_ERR
"%s(%d):%s can't allocate transmit buffer\n",
1782 __FILE__
,__LINE__
,info
->device_name
);
1787 info
->pending_bh
= 0;
1789 memset(&info
->icount
, 0, sizeof(info
->icount
));
1791 setup_timer(&info
->tx_timer
, mgsl_tx_timeout
, (unsigned long)info
);
1793 /* Allocate and claim adapter resources */
1794 retval
= mgsl_claim_resources(info
);
1796 /* perform existence check and diagnostics */
1798 retval
= mgsl_adapter_test(info
);
1801 if (capable(CAP_SYS_ADMIN
) && info
->tty
)
1802 set_bit(TTY_IO_ERROR
, &info
->tty
->flags
);
1803 mgsl_release_resources(info
);
1807 /* program hardware for current parameters */
1808 mgsl_change_params(info
);
1811 clear_bit(TTY_IO_ERROR
, &info
->tty
->flags
);
1813 info
->flags
|= ASYNC_INITIALIZED
;
1817 } /* end of startup() */
1821 * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
1823 * Arguments: info pointer to device instance data
1824 * Return Value: None
1826 static void shutdown(struct mgsl_struct
* info
)
1828 unsigned long flags
;
1830 if (!(info
->flags
& ASYNC_INITIALIZED
))
1833 if (debug_level
>= DEBUG_LEVEL_INFO
)
1834 printk("%s(%d):mgsl_shutdown(%s)\n",
1835 __FILE__
,__LINE__
, info
->device_name
);
1837 /* clear status wait queue because status changes */
1838 /* can't happen after shutting down the hardware */
1839 wake_up_interruptible(&info
->status_event_wait_q
);
1840 wake_up_interruptible(&info
->event_wait_q
);
1842 del_timer_sync(&info
->tx_timer
);
1844 if (info
->xmit_buf
) {
1845 free_page((unsigned long) info
->xmit_buf
);
1846 info
->xmit_buf
= NULL
;
1849 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1850 usc_DisableMasterIrqBit(info
);
1851 usc_stop_receiver(info
);
1852 usc_stop_transmitter(info
);
1853 usc_DisableInterrupts(info
,RECEIVE_DATA
+ RECEIVE_STATUS
+
1854 TRANSMIT_DATA
+ TRANSMIT_STATUS
+ IO_PIN
+ MISC
);
1855 usc_DisableDmaInterrupts(info
,DICR_MASTER
+ DICR_TRANSMIT
+ DICR_RECEIVE
);
1857 /* Disable DMAEN (Port 7, Bit 14) */
1858 /* This disconnects the DMA request signal from the ISA bus */
1859 /* on the ISA adapter. This has no effect for the PCI adapter */
1860 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT15
) | BIT14
));
1862 /* Disable INTEN (Port 6, Bit12) */
1863 /* This disconnects the IRQ request signal to the ISA bus */
1864 /* on the ISA adapter. This has no effect for the PCI adapter */
1865 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) | BIT12
));
1867 if (!info
->tty
|| info
->tty
->termios
->c_cflag
& HUPCL
) {
1868 info
->serial_signals
&= ~(SerialSignal_DTR
+ SerialSignal_RTS
);
1869 usc_set_serial_signals(info
);
1872 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1874 mgsl_release_resources(info
);
1877 set_bit(TTY_IO_ERROR
, &info
->tty
->flags
);
1879 info
->flags
&= ~ASYNC_INITIALIZED
;
1881 } /* end of shutdown() */
1883 static void mgsl_program_hw(struct mgsl_struct
*info
)
1885 unsigned long flags
;
1887 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1889 usc_stop_receiver(info
);
1890 usc_stop_transmitter(info
);
1891 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
1893 if (info
->params
.mode
== MGSL_MODE_HDLC
||
1894 info
->params
.mode
== MGSL_MODE_RAW
||
1896 usc_set_sync_mode(info
);
1898 usc_set_async_mode(info
);
1900 usc_set_serial_signals(info
);
1902 info
->dcd_chkcount
= 0;
1903 info
->cts_chkcount
= 0;
1904 info
->ri_chkcount
= 0;
1905 info
->dsr_chkcount
= 0;
1907 usc_EnableStatusIrqs(info
,SICR_CTS
+SICR_DSR
+SICR_DCD
+SICR_RI
);
1908 usc_EnableInterrupts(info
, IO_PIN
);
1909 usc_get_serial_signals(info
);
1911 if (info
->netcount
|| info
->tty
->termios
->c_cflag
& CREAD
)
1912 usc_start_receiver(info
);
1914 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1917 /* Reconfigure adapter based on new parameters
1919 static void mgsl_change_params(struct mgsl_struct
*info
)
1924 if (!info
->tty
|| !info
->tty
->termios
)
1927 if (debug_level
>= DEBUG_LEVEL_INFO
)
1928 printk("%s(%d):mgsl_change_params(%s)\n",
1929 __FILE__
,__LINE__
, info
->device_name
);
1931 cflag
= info
->tty
->termios
->c_cflag
;
1933 /* if B0 rate (hangup) specified then negate DTR and RTS */
1934 /* otherwise assert DTR and RTS */
1936 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
1938 info
->serial_signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
1940 /* byte size and parity */
1942 switch (cflag
& CSIZE
) {
1943 case CS5
: info
->params
.data_bits
= 5; break;
1944 case CS6
: info
->params
.data_bits
= 6; break;
1945 case CS7
: info
->params
.data_bits
= 7; break;
1946 case CS8
: info
->params
.data_bits
= 8; break;
1947 /* Never happens, but GCC is too dumb to figure it out */
1948 default: info
->params
.data_bits
= 7; break;
1952 info
->params
.stop_bits
= 2;
1954 info
->params
.stop_bits
= 1;
1956 info
->params
.parity
= ASYNC_PARITY_NONE
;
1957 if (cflag
& PARENB
) {
1959 info
->params
.parity
= ASYNC_PARITY_ODD
;
1961 info
->params
.parity
= ASYNC_PARITY_EVEN
;
1964 info
->params
.parity
= ASYNC_PARITY_SPACE
;
1968 /* calculate number of jiffies to transmit a full
1969 * FIFO (32 bytes) at specified data rate
1971 bits_per_char
= info
->params
.data_bits
+
1972 info
->params
.stop_bits
+ 1;
1974 /* if port data rate is set to 460800 or less then
1975 * allow tty settings to override, otherwise keep the
1976 * current data rate.
1978 if (info
->params
.data_rate
<= 460800)
1979 info
->params
.data_rate
= tty_get_baud_rate(info
->tty
);
1981 if ( info
->params
.data_rate
) {
1982 info
->timeout
= (32*HZ
*bits_per_char
) /
1983 info
->params
.data_rate
;
1985 info
->timeout
+= HZ
/50; /* Add .02 seconds of slop */
1987 if (cflag
& CRTSCTS
)
1988 info
->flags
|= ASYNC_CTS_FLOW
;
1990 info
->flags
&= ~ASYNC_CTS_FLOW
;
1993 info
->flags
&= ~ASYNC_CHECK_CD
;
1995 info
->flags
|= ASYNC_CHECK_CD
;
1997 /* process tty input control flags */
1999 info
->read_status_mask
= RXSTATUS_OVERRUN
;
2000 if (I_INPCK(info
->tty
))
2001 info
->read_status_mask
|= RXSTATUS_PARITY_ERROR
| RXSTATUS_FRAMING_ERROR
;
2002 if (I_BRKINT(info
->tty
) || I_PARMRK(info
->tty
))
2003 info
->read_status_mask
|= RXSTATUS_BREAK_RECEIVED
;
2005 if (I_IGNPAR(info
->tty
))
2006 info
->ignore_status_mask
|= RXSTATUS_PARITY_ERROR
| RXSTATUS_FRAMING_ERROR
;
2007 if (I_IGNBRK(info
->tty
)) {
2008 info
->ignore_status_mask
|= RXSTATUS_BREAK_RECEIVED
;
2009 /* If ignoring parity and break indicators, ignore
2010 * overruns too. (For real raw support).
2012 if (I_IGNPAR(info
->tty
))
2013 info
->ignore_status_mask
|= RXSTATUS_OVERRUN
;
2016 mgsl_program_hw(info
);
2018 } /* end of mgsl_change_params() */
2022 * Add a character to the transmit buffer.
2024 * Arguments: tty pointer to tty information structure
2025 * ch character to add to transmit buffer
2027 * Return Value: None
2029 static void mgsl_put_char(struct tty_struct
*tty
, unsigned char ch
)
2031 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2032 unsigned long flags
;
2034 if ( debug_level
>= DEBUG_LEVEL_INFO
) {
2035 printk( "%s(%d):mgsl_put_char(%d) on %s\n",
2036 __FILE__
,__LINE__
,ch
,info
->device_name
);
2039 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_put_char"))
2042 if (!tty
|| !info
->xmit_buf
)
2045 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2047 if ( (info
->params
.mode
== MGSL_MODE_ASYNC
) || !info
->tx_active
) {
2049 if (info
->xmit_cnt
< SERIAL_XMIT_SIZE
- 1) {
2050 info
->xmit_buf
[info
->xmit_head
++] = ch
;
2051 info
->xmit_head
&= SERIAL_XMIT_SIZE
-1;
2056 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2058 } /* end of mgsl_put_char() */
2060 /* mgsl_flush_chars()
2062 * Enable transmitter so remaining characters in the
2063 * transmit buffer are sent.
2065 * Arguments: tty pointer to tty information structure
2066 * Return Value: None
2068 static void mgsl_flush_chars(struct tty_struct
*tty
)
2070 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2071 unsigned long flags
;
2073 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2074 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2075 __FILE__
,__LINE__
,info
->device_name
,info
->xmit_cnt
);
2077 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_flush_chars"))
2080 if (info
->xmit_cnt
<= 0 || tty
->stopped
|| tty
->hw_stopped
||
2084 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2085 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2086 __FILE__
,__LINE__
,info
->device_name
);
2088 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2090 if (!info
->tx_active
) {
2091 if ( (info
->params
.mode
== MGSL_MODE_HDLC
||
2092 info
->params
.mode
== MGSL_MODE_RAW
) && info
->xmit_cnt
) {
2093 /* operating in synchronous (frame oriented) mode */
2094 /* copy data from circular xmit_buf to */
2095 /* transmit DMA buffer. */
2096 mgsl_load_tx_dma_buffer(info
,
2097 info
->xmit_buf
,info
->xmit_cnt
);
2099 usc_start_transmitter(info
);
2102 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2104 } /* end of mgsl_flush_chars() */
2108 * Send a block of data
2112 * tty pointer to tty information structure
2113 * buf pointer to buffer containing send data
2114 * count size of send data in bytes
2116 * Return Value: number of characters written
2118 static int mgsl_write(struct tty_struct
* tty
,
2119 const unsigned char *buf
, int count
)
2122 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2123 unsigned long flags
;
2125 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2126 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2127 __FILE__
,__LINE__
,info
->device_name
,count
);
2129 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_write"))
2132 if (!tty
|| !info
->xmit_buf
)
2135 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
2136 info
->params
.mode
== MGSL_MODE_RAW
) {
2137 /* operating in synchronous (frame oriented) mode */
2138 /* operating in synchronous (frame oriented) mode */
2139 if (info
->tx_active
) {
2141 if ( info
->params
.mode
== MGSL_MODE_HDLC
) {
2145 /* transmitter is actively sending data -
2146 * if we have multiple transmit dma and
2147 * holding buffers, attempt to queue this
2148 * frame for transmission at a later time.
2150 if (info
->tx_holding_count
>= info
->num_tx_holding_buffers
) {
2151 /* no tx holding buffers available */
2156 /* queue transmit frame request */
2158 save_tx_buffer_request(info
,buf
,count
);
2160 /* if we have sufficient tx dma buffers,
2161 * load the next buffered tx request
2163 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2164 load_next_tx_holding_buffer(info
);
2165 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2169 /* if operating in HDLC LoopMode and the adapter */
2170 /* has yet to be inserted into the loop, we can't */
2173 if ( (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) &&
2174 !usc_loopmode_active(info
) )
2180 if ( info
->xmit_cnt
) {
2181 /* Send accumulated from send_char() calls */
2182 /* as frame and wait before accepting more data. */
2185 /* copy data from circular xmit_buf to */
2186 /* transmit DMA buffer. */
2187 mgsl_load_tx_dma_buffer(info
,
2188 info
->xmit_buf
,info
->xmit_cnt
);
2189 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2190 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2191 __FILE__
,__LINE__
,info
->device_name
);
2193 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2194 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2195 __FILE__
,__LINE__
,info
->device_name
);
2197 info
->xmit_cnt
= count
;
2198 mgsl_load_tx_dma_buffer(info
,buf
,count
);
2202 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2203 c
= min_t(int, count
,
2204 min(SERIAL_XMIT_SIZE
- info
->xmit_cnt
- 1,
2205 SERIAL_XMIT_SIZE
- info
->xmit_head
));
2207 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2210 memcpy(info
->xmit_buf
+ info
->xmit_head
, buf
, c
);
2211 info
->xmit_head
= ((info
->xmit_head
+ c
) &
2212 (SERIAL_XMIT_SIZE
-1));
2213 info
->xmit_cnt
+= c
;
2214 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2221 if (info
->xmit_cnt
&& !tty
->stopped
&& !tty
->hw_stopped
) {
2222 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2223 if (!info
->tx_active
)
2224 usc_start_transmitter(info
);
2225 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2228 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2229 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2230 __FILE__
,__LINE__
,info
->device_name
,ret
);
2234 } /* end of mgsl_write() */
2236 /* mgsl_write_room()
2238 * Return the count of free bytes in transmit buffer
2240 * Arguments: tty pointer to tty info structure
2241 * Return Value: None
2243 static int mgsl_write_room(struct tty_struct
*tty
)
2245 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2248 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_write_room"))
2250 ret
= SERIAL_XMIT_SIZE
- info
->xmit_cnt
- 1;
2254 if (debug_level
>= DEBUG_LEVEL_INFO
)
2255 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2256 __FILE__
,__LINE__
, info
->device_name
,ret
);
2258 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
2259 info
->params
.mode
== MGSL_MODE_RAW
) {
2260 /* operating in synchronous (frame oriented) mode */
2261 if ( info
->tx_active
)
2264 return HDLC_MAX_FRAME_SIZE
;
2269 } /* end of mgsl_write_room() */
2271 /* mgsl_chars_in_buffer()
2273 * Return the count of bytes in transmit buffer
2275 * Arguments: tty pointer to tty info structure
2276 * Return Value: None
2278 static int mgsl_chars_in_buffer(struct tty_struct
*tty
)
2280 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2282 if (debug_level
>= DEBUG_LEVEL_INFO
)
2283 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2284 __FILE__
,__LINE__
, info
->device_name
);
2286 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_chars_in_buffer"))
2289 if (debug_level
>= DEBUG_LEVEL_INFO
)
2290 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2291 __FILE__
,__LINE__
, info
->device_name
,info
->xmit_cnt
);
2293 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
2294 info
->params
.mode
== MGSL_MODE_RAW
) {
2295 /* operating in synchronous (frame oriented) mode */
2296 if ( info
->tx_active
)
2297 return info
->max_frame_size
;
2302 return info
->xmit_cnt
;
2303 } /* end of mgsl_chars_in_buffer() */
2305 /* mgsl_flush_buffer()
2307 * Discard all data in the send buffer
2309 * Arguments: tty pointer to tty info structure
2310 * Return Value: None
2312 static void mgsl_flush_buffer(struct tty_struct
*tty
)
2314 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2315 unsigned long flags
;
2317 if (debug_level
>= DEBUG_LEVEL_INFO
)
2318 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2319 __FILE__
,__LINE__
, info
->device_name
);
2321 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_flush_buffer"))
2324 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2325 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
2326 del_timer(&info
->tx_timer
);
2327 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2332 /* mgsl_send_xchar()
2334 * Send a high-priority XON/XOFF character
2336 * Arguments: tty pointer to tty info structure
2337 * ch character to send
2338 * Return Value: None
2340 static void mgsl_send_xchar(struct tty_struct
*tty
, char ch
)
2342 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2343 unsigned long flags
;
2345 if (debug_level
>= DEBUG_LEVEL_INFO
)
2346 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2347 __FILE__
,__LINE__
, info
->device_name
, ch
);
2349 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_send_xchar"))
2354 /* Make sure transmit interrupts are on */
2355 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2356 if (!info
->tx_enabled
)
2357 usc_start_transmitter(info
);
2358 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2360 } /* end of mgsl_send_xchar() */
2364 * Signal remote device to throttle send data (our receive data)
2366 * Arguments: tty pointer to tty info structure
2367 * Return Value: None
2369 static void mgsl_throttle(struct tty_struct
* tty
)
2371 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2372 unsigned long flags
;
2374 if (debug_level
>= DEBUG_LEVEL_INFO
)
2375 printk("%s(%d):mgsl_throttle(%s) entry\n",
2376 __FILE__
,__LINE__
, info
->device_name
);
2378 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_throttle"))
2382 mgsl_send_xchar(tty
, STOP_CHAR(tty
));
2384 if (tty
->termios
->c_cflag
& CRTSCTS
) {
2385 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2386 info
->serial_signals
&= ~SerialSignal_RTS
;
2387 usc_set_serial_signals(info
);
2388 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2390 } /* end of mgsl_throttle() */
2392 /* mgsl_unthrottle()
2394 * Signal remote device to stop throttling send data (our receive data)
2396 * Arguments: tty pointer to tty info structure
2397 * Return Value: None
2399 static void mgsl_unthrottle(struct tty_struct
* tty
)
2401 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2402 unsigned long flags
;
2404 if (debug_level
>= DEBUG_LEVEL_INFO
)
2405 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2406 __FILE__
,__LINE__
, info
->device_name
);
2408 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_unthrottle"))
2415 mgsl_send_xchar(tty
, START_CHAR(tty
));
2418 if (tty
->termios
->c_cflag
& CRTSCTS
) {
2419 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2420 info
->serial_signals
|= SerialSignal_RTS
;
2421 usc_set_serial_signals(info
);
2422 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2425 } /* end of mgsl_unthrottle() */
2429 * get the current serial parameters information
2431 * Arguments: info pointer to device instance data
2432 * user_icount pointer to buffer to hold returned stats
2434 * Return Value: 0 if success, otherwise error code
2436 static int mgsl_get_stats(struct mgsl_struct
* info
, struct mgsl_icount __user
*user_icount
)
2440 if (debug_level
>= DEBUG_LEVEL_INFO
)
2441 printk("%s(%d):mgsl_get_params(%s)\n",
2442 __FILE__
,__LINE__
, info
->device_name
);
2445 memset(&info
->icount
, 0, sizeof(info
->icount
));
2447 COPY_TO_USER(err
, user_icount
, &info
->icount
, sizeof(struct mgsl_icount
));
2454 } /* end of mgsl_get_stats() */
2456 /* mgsl_get_params()
2458 * get the current serial parameters information
2460 * Arguments: info pointer to device instance data
2461 * user_params pointer to buffer to hold returned params
2463 * Return Value: 0 if success, otherwise error code
2465 static int mgsl_get_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*user_params
)
2468 if (debug_level
>= DEBUG_LEVEL_INFO
)
2469 printk("%s(%d):mgsl_get_params(%s)\n",
2470 __FILE__
,__LINE__
, info
->device_name
);
2472 COPY_TO_USER(err
,user_params
, &info
->params
, sizeof(MGSL_PARAMS
));
2474 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2475 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2476 __FILE__
,__LINE__
,info
->device_name
);
2482 } /* end of mgsl_get_params() */
2484 /* mgsl_set_params()
2486 * set the serial parameters
2490 * info pointer to device instance data
2491 * new_params user buffer containing new serial params
2493 * Return Value: 0 if success, otherwise error code
2495 static int mgsl_set_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*new_params
)
2497 unsigned long flags
;
2498 MGSL_PARAMS tmp_params
;
2501 if (debug_level
>= DEBUG_LEVEL_INFO
)
2502 printk("%s(%d):mgsl_set_params %s\n", __FILE__
,__LINE__
,
2503 info
->device_name
);
2504 COPY_FROM_USER(err
,&tmp_params
, new_params
, sizeof(MGSL_PARAMS
));
2506 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2507 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2508 __FILE__
,__LINE__
,info
->device_name
);
2512 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2513 memcpy(&info
->params
,&tmp_params
,sizeof(MGSL_PARAMS
));
2514 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2516 mgsl_change_params(info
);
2520 } /* end of mgsl_set_params() */
2522 /* mgsl_get_txidle()
2524 * get the current transmit idle mode
2526 * Arguments: info pointer to device instance data
2527 * idle_mode pointer to buffer to hold returned idle mode
2529 * Return Value: 0 if success, otherwise error code
2531 static int mgsl_get_txidle(struct mgsl_struct
* info
, int __user
*idle_mode
)
2535 if (debug_level
>= DEBUG_LEVEL_INFO
)
2536 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2537 __FILE__
,__LINE__
, info
->device_name
, info
->idle_mode
);
2539 COPY_TO_USER(err
,idle_mode
, &info
->idle_mode
, sizeof(int));
2541 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2542 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2543 __FILE__
,__LINE__
,info
->device_name
);
2549 } /* end of mgsl_get_txidle() */
2551 /* mgsl_set_txidle() service ioctl to set transmit idle mode
2553 * Arguments: info pointer to device instance data
2554 * idle_mode new idle mode
2556 * Return Value: 0 if success, otherwise error code
2558 static int mgsl_set_txidle(struct mgsl_struct
* info
, int idle_mode
)
2560 unsigned long flags
;
2562 if (debug_level
>= DEBUG_LEVEL_INFO
)
2563 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__
,__LINE__
,
2564 info
->device_name
, idle_mode
);
2566 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2567 info
->idle_mode
= idle_mode
;
2568 usc_set_txidle( info
);
2569 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2572 } /* end of mgsl_set_txidle() */
2576 * enable or disable the transmitter
2580 * info pointer to device instance data
2581 * enable 1 = enable, 0 = disable
2583 * Return Value: 0 if success, otherwise error code
2585 static int mgsl_txenable(struct mgsl_struct
* info
, int enable
)
2587 unsigned long flags
;
2589 if (debug_level
>= DEBUG_LEVEL_INFO
)
2590 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__
,__LINE__
,
2591 info
->device_name
, enable
);
2593 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2595 if ( !info
->tx_enabled
) {
2597 usc_start_transmitter(info
);
2598 /*--------------------------------------------------
2599 * if HDLC/SDLC Loop mode, attempt to insert the
2600 * station in the 'loop' by setting CMR:13. Upon
2601 * receipt of the next GoAhead (RxAbort) sequence,
2602 * the OnLoop indicator (CCSR:7) should go active
2603 * to indicate that we are on the loop
2604 *--------------------------------------------------*/
2605 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
2606 usc_loopmode_insert_request( info
);
2609 if ( info
->tx_enabled
)
2610 usc_stop_transmitter(info
);
2612 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2615 } /* end of mgsl_txenable() */
2617 /* mgsl_txabort() abort send HDLC frame
2619 * Arguments: info pointer to device instance data
2620 * Return Value: 0 if success, otherwise error code
2622 static int mgsl_txabort(struct mgsl_struct
* info
)
2624 unsigned long flags
;
2626 if (debug_level
>= DEBUG_LEVEL_INFO
)
2627 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__
,__LINE__
,
2630 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2631 if ( info
->tx_active
&& info
->params
.mode
== MGSL_MODE_HDLC
)
2633 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
2634 usc_loopmode_cancel_transmit( info
);
2636 usc_TCmd(info
,TCmd_SendAbort
);
2638 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2641 } /* end of mgsl_txabort() */
2643 /* mgsl_rxenable() enable or disable the receiver
2645 * Arguments: info pointer to device instance data
2646 * enable 1 = enable, 0 = disable
2647 * Return Value: 0 if success, otherwise error code
2649 static int mgsl_rxenable(struct mgsl_struct
* info
, int enable
)
2651 unsigned long flags
;
2653 if (debug_level
>= DEBUG_LEVEL_INFO
)
2654 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__
,__LINE__
,
2655 info
->device_name
, enable
);
2657 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2659 if ( !info
->rx_enabled
)
2660 usc_start_receiver(info
);
2662 if ( info
->rx_enabled
)
2663 usc_stop_receiver(info
);
2665 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2668 } /* end of mgsl_rxenable() */
2670 /* mgsl_wait_event() wait for specified event to occur
2672 * Arguments: info pointer to device instance data
2673 * mask pointer to bitmask of events to wait for
2674 * Return Value: 0 if successful and bit mask updated with
2675 * of events triggerred,
2676 * otherwise error code
2678 static int mgsl_wait_event(struct mgsl_struct
* info
, int __user
* mask_ptr
)
2680 unsigned long flags
;
2683 struct mgsl_icount cprev
, cnow
;
2686 struct _input_signal_events oldsigs
, newsigs
;
2687 DECLARE_WAITQUEUE(wait
, current
);
2689 COPY_FROM_USER(rc
,&mask
, mask_ptr
, sizeof(int));
2694 if (debug_level
>= DEBUG_LEVEL_INFO
)
2695 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__
,__LINE__
,
2696 info
->device_name
, mask
);
2698 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2700 /* return immediately if state matches requested events */
2701 usc_get_serial_signals(info
);
2702 s
= info
->serial_signals
;
2704 ( ((s
& SerialSignal_DSR
) ? MgslEvent_DsrActive
:MgslEvent_DsrInactive
) +
2705 ((s
& SerialSignal_DCD
) ? MgslEvent_DcdActive
:MgslEvent_DcdInactive
) +
2706 ((s
& SerialSignal_CTS
) ? MgslEvent_CtsActive
:MgslEvent_CtsInactive
) +
2707 ((s
& SerialSignal_RI
) ? MgslEvent_RiActive
:MgslEvent_RiInactive
) );
2709 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2713 /* save current irq counts */
2714 cprev
= info
->icount
;
2715 oldsigs
= info
->input_signal_events
;
2717 /* enable hunt and idle irqs if needed */
2718 if (mask
& (MgslEvent_ExitHuntMode
+ MgslEvent_IdleReceived
)) {
2719 u16 oldreg
= usc_InReg(info
,RICR
);
2720 u16 newreg
= oldreg
+
2721 (mask
& MgslEvent_ExitHuntMode
? RXSTATUS_EXITED_HUNT
:0) +
2722 (mask
& MgslEvent_IdleReceived
? RXSTATUS_IDLE_RECEIVED
:0);
2723 if (oldreg
!= newreg
)
2724 usc_OutReg(info
, RICR
, newreg
);
2727 set_current_state(TASK_INTERRUPTIBLE
);
2728 add_wait_queue(&info
->event_wait_q
, &wait
);
2730 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2735 if (signal_pending(current
)) {
2740 /* get current irq counts */
2741 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2742 cnow
= info
->icount
;
2743 newsigs
= info
->input_signal_events
;
2744 set_current_state(TASK_INTERRUPTIBLE
);
2745 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2747 /* if no change, wait aborted for some reason */
2748 if (newsigs
.dsr_up
== oldsigs
.dsr_up
&&
2749 newsigs
.dsr_down
== oldsigs
.dsr_down
&&
2750 newsigs
.dcd_up
== oldsigs
.dcd_up
&&
2751 newsigs
.dcd_down
== oldsigs
.dcd_down
&&
2752 newsigs
.cts_up
== oldsigs
.cts_up
&&
2753 newsigs
.cts_down
== oldsigs
.cts_down
&&
2754 newsigs
.ri_up
== oldsigs
.ri_up
&&
2755 newsigs
.ri_down
== oldsigs
.ri_down
&&
2756 cnow
.exithunt
== cprev
.exithunt
&&
2757 cnow
.rxidle
== cprev
.rxidle
) {
2763 ( (newsigs
.dsr_up
!= oldsigs
.dsr_up
? MgslEvent_DsrActive
:0) +
2764 (newsigs
.dsr_down
!= oldsigs
.dsr_down
? MgslEvent_DsrInactive
:0) +
2765 (newsigs
.dcd_up
!= oldsigs
.dcd_up
? MgslEvent_DcdActive
:0) +
2766 (newsigs
.dcd_down
!= oldsigs
.dcd_down
? MgslEvent_DcdInactive
:0) +
2767 (newsigs
.cts_up
!= oldsigs
.cts_up
? MgslEvent_CtsActive
:0) +
2768 (newsigs
.cts_down
!= oldsigs
.cts_down
? MgslEvent_CtsInactive
:0) +
2769 (newsigs
.ri_up
!= oldsigs
.ri_up
? MgslEvent_RiActive
:0) +
2770 (newsigs
.ri_down
!= oldsigs
.ri_down
? MgslEvent_RiInactive
:0) +
2771 (cnow
.exithunt
!= cprev
.exithunt
? MgslEvent_ExitHuntMode
:0) +
2772 (cnow
.rxidle
!= cprev
.rxidle
? MgslEvent_IdleReceived
:0) );
2780 remove_wait_queue(&info
->event_wait_q
, &wait
);
2781 set_current_state(TASK_RUNNING
);
2783 if (mask
& (MgslEvent_ExitHuntMode
+ MgslEvent_IdleReceived
)) {
2784 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2785 if (!waitqueue_active(&info
->event_wait_q
)) {
2786 /* disable enable exit hunt mode/idle rcvd IRQs */
2787 usc_OutReg(info
, RICR
, usc_InReg(info
,RICR
) &
2788 ~(RXSTATUS_EXITED_HUNT
+ RXSTATUS_IDLE_RECEIVED
));
2790 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2794 PUT_USER(rc
, events
, mask_ptr
);
2798 } /* end of mgsl_wait_event() */
2800 static int modem_input_wait(struct mgsl_struct
*info
,int arg
)
2802 unsigned long flags
;
2804 struct mgsl_icount cprev
, cnow
;
2805 DECLARE_WAITQUEUE(wait
, current
);
2807 /* save current irq counts */
2808 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2809 cprev
= info
->icount
;
2810 add_wait_queue(&info
->status_event_wait_q
, &wait
);
2811 set_current_state(TASK_INTERRUPTIBLE
);
2812 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2816 if (signal_pending(current
)) {
2821 /* get new irq counts */
2822 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2823 cnow
= info
->icount
;
2824 set_current_state(TASK_INTERRUPTIBLE
);
2825 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2827 /* if no change, wait aborted for some reason */
2828 if (cnow
.rng
== cprev
.rng
&& cnow
.dsr
== cprev
.dsr
&&
2829 cnow
.dcd
== cprev
.dcd
&& cnow
.cts
== cprev
.cts
) {
2834 /* check for change in caller specified modem input */
2835 if ((arg
& TIOCM_RNG
&& cnow
.rng
!= cprev
.rng
) ||
2836 (arg
& TIOCM_DSR
&& cnow
.dsr
!= cprev
.dsr
) ||
2837 (arg
& TIOCM_CD
&& cnow
.dcd
!= cprev
.dcd
) ||
2838 (arg
& TIOCM_CTS
&& cnow
.cts
!= cprev
.cts
)) {
2845 remove_wait_queue(&info
->status_event_wait_q
, &wait
);
2846 set_current_state(TASK_RUNNING
);
2850 /* return the state of the serial control and status signals
2852 static int tiocmget(struct tty_struct
*tty
, struct file
*file
)
2854 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2855 unsigned int result
;
2856 unsigned long flags
;
2858 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2859 usc_get_serial_signals(info
);
2860 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2862 result
= ((info
->serial_signals
& SerialSignal_RTS
) ? TIOCM_RTS
:0) +
2863 ((info
->serial_signals
& SerialSignal_DTR
) ? TIOCM_DTR
:0) +
2864 ((info
->serial_signals
& SerialSignal_DCD
) ? TIOCM_CAR
:0) +
2865 ((info
->serial_signals
& SerialSignal_RI
) ? TIOCM_RNG
:0) +
2866 ((info
->serial_signals
& SerialSignal_DSR
) ? TIOCM_DSR
:0) +
2867 ((info
->serial_signals
& SerialSignal_CTS
) ? TIOCM_CTS
:0);
2869 if (debug_level
>= DEBUG_LEVEL_INFO
)
2870 printk("%s(%d):%s tiocmget() value=%08X\n",
2871 __FILE__
,__LINE__
, info
->device_name
, result
);
2875 /* set modem control signals (DTR/RTS)
2877 static int tiocmset(struct tty_struct
*tty
, struct file
*file
,
2878 unsigned int set
, unsigned int clear
)
2880 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2881 unsigned long flags
;
2883 if (debug_level
>= DEBUG_LEVEL_INFO
)
2884 printk("%s(%d):%s tiocmset(%x,%x)\n",
2885 __FILE__
,__LINE__
,info
->device_name
, set
, clear
);
2887 if (set
& TIOCM_RTS
)
2888 info
->serial_signals
|= SerialSignal_RTS
;
2889 if (set
& TIOCM_DTR
)
2890 info
->serial_signals
|= SerialSignal_DTR
;
2891 if (clear
& TIOCM_RTS
)
2892 info
->serial_signals
&= ~SerialSignal_RTS
;
2893 if (clear
& TIOCM_DTR
)
2894 info
->serial_signals
&= ~SerialSignal_DTR
;
2896 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2897 usc_set_serial_signals(info
);
2898 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2903 /* mgsl_break() Set or clear transmit break condition
2905 * Arguments: tty pointer to tty instance data
2906 * break_state -1=set break condition, 0=clear
2907 * Return Value: None
2909 static void mgsl_break(struct tty_struct
*tty
, int break_state
)
2911 struct mgsl_struct
* info
= (struct mgsl_struct
*)tty
->driver_data
;
2912 unsigned long flags
;
2914 if (debug_level
>= DEBUG_LEVEL_INFO
)
2915 printk("%s(%d):mgsl_break(%s,%d)\n",
2916 __FILE__
,__LINE__
, info
->device_name
, break_state
);
2918 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_break"))
2921 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2922 if (break_state
== -1)
2923 usc_OutReg(info
,IOCR
,(u16
)(usc_InReg(info
,IOCR
) | BIT7
));
2925 usc_OutReg(info
,IOCR
,(u16
)(usc_InReg(info
,IOCR
) & ~BIT7
));
2926 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2928 } /* end of mgsl_break() */
2930 /* mgsl_ioctl() Service an IOCTL request
2934 * tty pointer to tty instance data
2935 * file pointer to associated file object for device
2936 * cmd IOCTL command code
2937 * arg command argument/context
2939 * Return Value: 0 if success, otherwise error code
2941 static int mgsl_ioctl(struct tty_struct
*tty
, struct file
* file
,
2942 unsigned int cmd
, unsigned long arg
)
2944 struct mgsl_struct
* info
= (struct mgsl_struct
*)tty
->driver_data
;
2946 if (debug_level
>= DEBUG_LEVEL_INFO
)
2947 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__
,__LINE__
,
2948 info
->device_name
, cmd
);
2950 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_ioctl"))
2953 if ((cmd
!= TIOCGSERIAL
) && (cmd
!= TIOCSSERIAL
) &&
2954 (cmd
!= TIOCMIWAIT
) && (cmd
!= TIOCGICOUNT
)) {
2955 if (tty
->flags
& (1 << TTY_IO_ERROR
))
2959 return mgsl_ioctl_common(info
, cmd
, arg
);
2962 static int mgsl_ioctl_common(struct mgsl_struct
*info
, unsigned int cmd
, unsigned long arg
)
2965 struct mgsl_icount cnow
; /* kernel counter temps */
2966 void __user
*argp
= (void __user
*)arg
;
2967 struct serial_icounter_struct __user
*p_cuser
; /* user space */
2968 unsigned long flags
;
2971 case MGSL_IOCGPARAMS
:
2972 return mgsl_get_params(info
, argp
);
2973 case MGSL_IOCSPARAMS
:
2974 return mgsl_set_params(info
, argp
);
2975 case MGSL_IOCGTXIDLE
:
2976 return mgsl_get_txidle(info
, argp
);
2977 case MGSL_IOCSTXIDLE
:
2978 return mgsl_set_txidle(info
,(int)arg
);
2979 case MGSL_IOCTXENABLE
:
2980 return mgsl_txenable(info
,(int)arg
);
2981 case MGSL_IOCRXENABLE
:
2982 return mgsl_rxenable(info
,(int)arg
);
2983 case MGSL_IOCTXABORT
:
2984 return mgsl_txabort(info
);
2985 case MGSL_IOCGSTATS
:
2986 return mgsl_get_stats(info
, argp
);
2987 case MGSL_IOCWAITEVENT
:
2988 return mgsl_wait_event(info
, argp
);
2989 case MGSL_IOCLOOPTXDONE
:
2990 return mgsl_loopmode_send_done(info
);
2991 /* Wait for modem input (DCD,RI,DSR,CTS) change
2992 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
2995 return modem_input_wait(info
,(int)arg
);
2998 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
2999 * Return: write counters to the user passed counter struct
3000 * NB: both 1->0 and 0->1 transitions are counted except for
3001 * RI where only 0->1 is counted.
3004 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3005 cnow
= info
->icount
;
3006 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3008 PUT_USER(error
,cnow
.cts
, &p_cuser
->cts
);
3009 if (error
) return error
;
3010 PUT_USER(error
,cnow
.dsr
, &p_cuser
->dsr
);
3011 if (error
) return error
;
3012 PUT_USER(error
,cnow
.rng
, &p_cuser
->rng
);
3013 if (error
) return error
;
3014 PUT_USER(error
,cnow
.dcd
, &p_cuser
->dcd
);
3015 if (error
) return error
;
3016 PUT_USER(error
,cnow
.rx
, &p_cuser
->rx
);
3017 if (error
) return error
;
3018 PUT_USER(error
,cnow
.tx
, &p_cuser
->tx
);
3019 if (error
) return error
;
3020 PUT_USER(error
,cnow
.frame
, &p_cuser
->frame
);
3021 if (error
) return error
;
3022 PUT_USER(error
,cnow
.overrun
, &p_cuser
->overrun
);
3023 if (error
) return error
;
3024 PUT_USER(error
,cnow
.parity
, &p_cuser
->parity
);
3025 if (error
) return error
;
3026 PUT_USER(error
,cnow
.brk
, &p_cuser
->brk
);
3027 if (error
) return error
;
3028 PUT_USER(error
,cnow
.buf_overrun
, &p_cuser
->buf_overrun
);
3029 if (error
) return error
;
3032 return -ENOIOCTLCMD
;
3037 /* mgsl_set_termios()
3039 * Set new termios settings
3043 * tty pointer to tty structure
3044 * termios pointer to buffer to hold returned old termios
3046 * Return Value: None
3048 static void mgsl_set_termios(struct tty_struct
*tty
, struct ktermios
*old_termios
)
3050 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
3051 unsigned long flags
;
3053 if (debug_level
>= DEBUG_LEVEL_INFO
)
3054 printk("%s(%d):mgsl_set_termios %s\n", __FILE__
,__LINE__
,
3055 tty
->driver
->name
);
3057 mgsl_change_params(info
);
3059 /* Handle transition to B0 status */
3060 if (old_termios
->c_cflag
& CBAUD
&&
3061 !(tty
->termios
->c_cflag
& CBAUD
)) {
3062 info
->serial_signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
3063 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3064 usc_set_serial_signals(info
);
3065 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3068 /* Handle transition away from B0 status */
3069 if (!(old_termios
->c_cflag
& CBAUD
) &&
3070 tty
->termios
->c_cflag
& CBAUD
) {
3071 info
->serial_signals
|= SerialSignal_DTR
;
3072 if (!(tty
->termios
->c_cflag
& CRTSCTS
) ||
3073 !test_bit(TTY_THROTTLED
, &tty
->flags
)) {
3074 info
->serial_signals
|= SerialSignal_RTS
;
3076 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3077 usc_set_serial_signals(info
);
3078 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3081 /* Handle turning off CRTSCTS */
3082 if (old_termios
->c_cflag
& CRTSCTS
&&
3083 !(tty
->termios
->c_cflag
& CRTSCTS
)) {
3084 tty
->hw_stopped
= 0;
3088 } /* end of mgsl_set_termios() */
3092 * Called when port is closed. Wait for remaining data to be
3093 * sent. Disable port and free resources.
3097 * tty pointer to open tty structure
3098 * filp pointer to open file object
3100 * Return Value: None
3102 static void mgsl_close(struct tty_struct
*tty
, struct file
* filp
)
3104 struct mgsl_struct
* info
= (struct mgsl_struct
*)tty
->driver_data
;
3106 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_close"))
3109 if (debug_level
>= DEBUG_LEVEL_INFO
)
3110 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3111 __FILE__
,__LINE__
, info
->device_name
, info
->count
);
3116 if (tty_hung_up_p(filp
))
3119 if ((tty
->count
== 1) && (info
->count
!= 1)) {
3121 * tty->count is 1 and the tty structure will be freed.
3122 * info->count should be one in this case.
3123 * if it's not, correct it so that the port is shutdown.
3125 printk("mgsl_close: bad refcount; tty->count is 1, "
3126 "info->count is %d\n", info
->count
);
3132 /* if at least one open remaining, leave hardware active */
3136 info
->flags
|= ASYNC_CLOSING
;
3138 /* set tty->closing to notify line discipline to
3139 * only process XON/XOFF characters. Only the N_TTY
3140 * discipline appears to use this (ppp does not).
3144 /* wait for transmit data to clear all layers */
3146 if (info
->closing_wait
!= ASYNC_CLOSING_WAIT_NONE
) {
3147 if (debug_level
>= DEBUG_LEVEL_INFO
)
3148 printk("%s(%d):mgsl_close(%s) calling tty_wait_until_sent\n",
3149 __FILE__
,__LINE__
, info
->device_name
);
3150 tty_wait_until_sent(tty
, info
->closing_wait
);
3153 if (info
->flags
& ASYNC_INITIALIZED
)
3154 mgsl_wait_until_sent(tty
, info
->timeout
);
3156 if (tty
->driver
->flush_buffer
)
3157 tty
->driver
->flush_buffer(tty
);
3159 tty_ldisc_flush(tty
);
3166 if (info
->blocked_open
) {
3167 if (info
->close_delay
) {
3168 msleep_interruptible(jiffies_to_msecs(info
->close_delay
));
3170 wake_up_interruptible(&info
->open_wait
);
3173 info
->flags
&= ~(ASYNC_NORMAL_ACTIVE
|ASYNC_CLOSING
);
3175 wake_up_interruptible(&info
->close_wait
);
3178 if (debug_level
>= DEBUG_LEVEL_INFO
)
3179 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__
,__LINE__
,
3180 tty
->driver
->name
, info
->count
);
3182 } /* end of mgsl_close() */
3184 /* mgsl_wait_until_sent()
3186 * Wait until the transmitter is empty.
3190 * tty pointer to tty info structure
3191 * timeout time to wait for send completion
3193 * Return Value: None
3195 static void mgsl_wait_until_sent(struct tty_struct
*tty
, int timeout
)
3197 struct mgsl_struct
* info
= (struct mgsl_struct
*)tty
->driver_data
;
3198 unsigned long orig_jiffies
, char_time
;
3203 if (debug_level
>= DEBUG_LEVEL_INFO
)
3204 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3205 __FILE__
,__LINE__
, info
->device_name
);
3207 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_wait_until_sent"))
3210 if (!(info
->flags
& ASYNC_INITIALIZED
))
3213 orig_jiffies
= jiffies
;
3215 /* Set check interval to 1/5 of estimated time to
3216 * send a character, and make it at least 1. The check
3217 * interval should also be less than the timeout.
3218 * Note: use tight timings here to satisfy the NIST-PCTS.
3221 if ( info
->params
.data_rate
) {
3222 char_time
= info
->timeout
/(32 * 5);
3229 char_time
= min_t(unsigned long, char_time
, timeout
);
3231 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
3232 info
->params
.mode
== MGSL_MODE_RAW
) {
3233 while (info
->tx_active
) {
3234 msleep_interruptible(jiffies_to_msecs(char_time
));
3235 if (signal_pending(current
))
3237 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
3241 while (!(usc_InReg(info
,TCSR
) & TXSTATUS_ALL_SENT
) &&
3243 msleep_interruptible(jiffies_to_msecs(char_time
));
3244 if (signal_pending(current
))
3246 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
3252 if (debug_level
>= DEBUG_LEVEL_INFO
)
3253 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3254 __FILE__
,__LINE__
, info
->device_name
);
3256 } /* end of mgsl_wait_until_sent() */
3260 * Called by tty_hangup() when a hangup is signaled.
3261 * This is the same as to closing all open files for the port.
3263 * Arguments: tty pointer to associated tty object
3264 * Return Value: None
3266 static void mgsl_hangup(struct tty_struct
*tty
)
3268 struct mgsl_struct
* info
= (struct mgsl_struct
*)tty
->driver_data
;
3270 if (debug_level
>= DEBUG_LEVEL_INFO
)
3271 printk("%s(%d):mgsl_hangup(%s)\n",
3272 __FILE__
,__LINE__
, info
->device_name
);
3274 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_hangup"))
3277 mgsl_flush_buffer(tty
);
3281 info
->flags
&= ~ASYNC_NORMAL_ACTIVE
;
3284 wake_up_interruptible(&info
->open_wait
);
3286 } /* end of mgsl_hangup() */
3288 /* block_til_ready()
3290 * Block the current process until the specified port
3291 * is ready to be opened.
3295 * tty pointer to tty info structure
3296 * filp pointer to open file object
3297 * info pointer to device instance data
3299 * Return Value: 0 if success, otherwise error code
3301 static int block_til_ready(struct tty_struct
*tty
, struct file
* filp
,
3302 struct mgsl_struct
*info
)
3304 DECLARE_WAITQUEUE(wait
, current
);
3306 int do_clocal
= 0, extra_count
= 0;
3307 unsigned long flags
;
3309 if (debug_level
>= DEBUG_LEVEL_INFO
)
3310 printk("%s(%d):block_til_ready on %s\n",
3311 __FILE__
,__LINE__
, tty
->driver
->name
);
3313 if (filp
->f_flags
& O_NONBLOCK
|| tty
->flags
& (1 << TTY_IO_ERROR
)){
3314 /* nonblock mode is set or port is not enabled */
3315 info
->flags
|= ASYNC_NORMAL_ACTIVE
;
3319 if (tty
->termios
->c_cflag
& CLOCAL
)
3322 /* Wait for carrier detect and the line to become
3323 * free (i.e., not in use by the callout). While we are in
3324 * this loop, info->count is dropped by one, so that
3325 * mgsl_close() knows when to free things. We restore it upon
3326 * exit, either normal or abnormal.
3330 add_wait_queue(&info
->open_wait
, &wait
);
3332 if (debug_level
>= DEBUG_LEVEL_INFO
)
3333 printk("%s(%d):block_til_ready before block on %s count=%d\n",
3334 __FILE__
,__LINE__
, tty
->driver
->name
, info
->count
);
3336 spin_lock_irqsave(&info
->irq_spinlock
, flags
);
3337 if (!tty_hung_up_p(filp
)) {
3341 spin_unlock_irqrestore(&info
->irq_spinlock
, flags
);
3342 info
->blocked_open
++;
3345 if (tty
->termios
->c_cflag
& CBAUD
) {
3346 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3347 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
3348 usc_set_serial_signals(info
);
3349 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3352 set_current_state(TASK_INTERRUPTIBLE
);
3354 if (tty_hung_up_p(filp
) || !(info
->flags
& ASYNC_INITIALIZED
)){
3355 retval
= (info
->flags
& ASYNC_HUP_NOTIFY
) ?
3356 -EAGAIN
: -ERESTARTSYS
;
3360 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3361 usc_get_serial_signals(info
);
3362 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3364 if (!(info
->flags
& ASYNC_CLOSING
) &&
3365 (do_clocal
|| (info
->serial_signals
& SerialSignal_DCD
)) ) {
3369 if (signal_pending(current
)) {
3370 retval
= -ERESTARTSYS
;
3374 if (debug_level
>= DEBUG_LEVEL_INFO
)
3375 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3376 __FILE__
,__LINE__
, tty
->driver
->name
, info
->count
);
3381 set_current_state(TASK_RUNNING
);
3382 remove_wait_queue(&info
->open_wait
, &wait
);
3386 info
->blocked_open
--;
3388 if (debug_level
>= DEBUG_LEVEL_INFO
)
3389 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3390 __FILE__
,__LINE__
, tty
->driver
->name
, info
->count
);
3393 info
->flags
|= ASYNC_NORMAL_ACTIVE
;
3397 } /* end of block_til_ready() */
3401 * Called when a port is opened. Init and enable port.
3402 * Perform serial-specific initialization for the tty structure.
3404 * Arguments: tty pointer to tty info structure
3405 * filp associated file pointer
3407 * Return Value: 0 if success, otherwise error code
3409 static int mgsl_open(struct tty_struct
*tty
, struct file
* filp
)
3411 struct mgsl_struct
*info
;
3413 unsigned long flags
;
3415 /* verify range of specified line number */
3417 if ((line
< 0) || (line
>= mgsl_device_count
)) {
3418 printk("%s(%d):mgsl_open with invalid line #%d.\n",
3419 __FILE__
,__LINE__
,line
);
3423 /* find the info structure for the specified line */
3424 info
= mgsl_device_list
;
3425 while(info
&& info
->line
!= line
)
3426 info
= info
->next_device
;
3427 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_open"))
3430 tty
->driver_data
= info
;
3433 if (debug_level
>= DEBUG_LEVEL_INFO
)
3434 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3435 __FILE__
,__LINE__
,tty
->driver
->name
, info
->count
);
3437 /* If port is closing, signal caller to try again */
3438 if (tty_hung_up_p(filp
) || info
->flags
& ASYNC_CLOSING
){
3439 if (info
->flags
& ASYNC_CLOSING
)
3440 interruptible_sleep_on(&info
->close_wait
);
3441 retval
= ((info
->flags
& ASYNC_HUP_NOTIFY
) ?
3442 -EAGAIN
: -ERESTARTSYS
);
3446 info
->tty
->low_latency
= (info
->flags
& ASYNC_LOW_LATENCY
) ? 1 : 0;
3448 spin_lock_irqsave(&info
->netlock
, flags
);
3449 if (info
->netcount
) {
3451 spin_unlock_irqrestore(&info
->netlock
, flags
);
3455 spin_unlock_irqrestore(&info
->netlock
, flags
);
3457 if (info
->count
== 1) {
3458 /* 1st open on this device, init hardware */
3459 retval
= startup(info
);
3464 retval
= block_til_ready(tty
, filp
, info
);
3466 if (debug_level
>= DEBUG_LEVEL_INFO
)
3467 printk("%s(%d):block_til_ready(%s) returned %d\n",
3468 __FILE__
,__LINE__
, info
->device_name
, retval
);
3472 if (debug_level
>= DEBUG_LEVEL_INFO
)
3473 printk("%s(%d):mgsl_open(%s) success\n",
3474 __FILE__
,__LINE__
, info
->device_name
);
3479 if (tty
->count
== 1)
3480 info
->tty
= NULL
; /* tty layer will release tty struct */
3487 } /* end of mgsl_open() */
3490 * /proc fs routines....
3493 static inline int line_info(char *buf
, struct mgsl_struct
*info
)
3497 unsigned long flags
;
3499 if (info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3500 ret
= sprintf(buf
, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3501 info
->device_name
, info
->io_base
, info
->irq_level
,
3502 info
->phys_memory_base
, info
->phys_lcr_base
);
3504 ret
= sprintf(buf
, "%s:(E)ISA io:%04X irq:%d dma:%d",
3505 info
->device_name
, info
->io_base
,
3506 info
->irq_level
, info
->dma_level
);
3509 /* output current serial signal states */
3510 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3511 usc_get_serial_signals(info
);
3512 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3516 if (info
->serial_signals
& SerialSignal_RTS
)
3517 strcat(stat_buf
, "|RTS");
3518 if (info
->serial_signals
& SerialSignal_CTS
)
3519 strcat(stat_buf
, "|CTS");
3520 if (info
->serial_signals
& SerialSignal_DTR
)
3521 strcat(stat_buf
, "|DTR");
3522 if (info
->serial_signals
& SerialSignal_DSR
)
3523 strcat(stat_buf
, "|DSR");
3524 if (info
->serial_signals
& SerialSignal_DCD
)
3525 strcat(stat_buf
, "|CD");
3526 if (info
->serial_signals
& SerialSignal_RI
)
3527 strcat(stat_buf
, "|RI");
3529 if (info
->params
.mode
== MGSL_MODE_HDLC
||
3530 info
->params
.mode
== MGSL_MODE_RAW
) {
3531 ret
+= sprintf(buf
+ret
, " HDLC txok:%d rxok:%d",
3532 info
->icount
.txok
, info
->icount
.rxok
);
3533 if (info
->icount
.txunder
)
3534 ret
+= sprintf(buf
+ret
, " txunder:%d", info
->icount
.txunder
);
3535 if (info
->icount
.txabort
)
3536 ret
+= sprintf(buf
+ret
, " txabort:%d", info
->icount
.txabort
);
3537 if (info
->icount
.rxshort
)
3538 ret
+= sprintf(buf
+ret
, " rxshort:%d", info
->icount
.rxshort
);
3539 if (info
->icount
.rxlong
)
3540 ret
+= sprintf(buf
+ret
, " rxlong:%d", info
->icount
.rxlong
);
3541 if (info
->icount
.rxover
)
3542 ret
+= sprintf(buf
+ret
, " rxover:%d", info
->icount
.rxover
);
3543 if (info
->icount
.rxcrc
)
3544 ret
+= sprintf(buf
+ret
, " rxcrc:%d", info
->icount
.rxcrc
);
3546 ret
+= sprintf(buf
+ret
, " ASYNC tx:%d rx:%d",
3547 info
->icount
.tx
, info
->icount
.rx
);
3548 if (info
->icount
.frame
)
3549 ret
+= sprintf(buf
+ret
, " fe:%d", info
->icount
.frame
);
3550 if (info
->icount
.parity
)
3551 ret
+= sprintf(buf
+ret
, " pe:%d", info
->icount
.parity
);
3552 if (info
->icount
.brk
)
3553 ret
+= sprintf(buf
+ret
, " brk:%d", info
->icount
.brk
);
3554 if (info
->icount
.overrun
)
3555 ret
+= sprintf(buf
+ret
, " oe:%d", info
->icount
.overrun
);
3558 /* Append serial signal status to end */
3559 ret
+= sprintf(buf
+ret
, " %s\n", stat_buf
+1);
3561 ret
+= sprintf(buf
+ret
, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3562 info
->tx_active
,info
->bh_requested
,info
->bh_running
,
3565 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3567 u16 Tcsr
= usc_InReg( info
, TCSR
);
3568 u16 Tdmr
= usc_InDmaReg( info
, TDMR
);
3569 u16 Ticr
= usc_InReg( info
, TICR
);
3570 u16 Rscr
= usc_InReg( info
, RCSR
);
3571 u16 Rdmr
= usc_InDmaReg( info
, RDMR
);
3572 u16 Ricr
= usc_InReg( info
, RICR
);
3573 u16 Icr
= usc_InReg( info
, ICR
);
3574 u16 Dccr
= usc_InReg( info
, DCCR
);
3575 u16 Tmr
= usc_InReg( info
, TMR
);
3576 u16 Tccr
= usc_InReg( info
, TCCR
);
3577 u16 Ccar
= inw( info
->io_base
+ CCAR
);
3578 ret
+= sprintf(buf
+ret
, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3579 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3580 Tcsr
,Tdmr
,Ticr
,Rscr
,Rdmr
,Ricr
,Icr
,Dccr
,Tmr
,Tccr
,Ccar
);
3582 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3586 } /* end of line_info() */
3590 * Called to print information about devices
3593 * page page of memory to hold returned info
3602 static int mgsl_read_proc(char *page
, char **start
, off_t off
, int count
,
3603 int *eof
, void *data
)
3607 struct mgsl_struct
*info
;
3609 len
+= sprintf(page
, "synclink driver:%s\n", driver_version
);
3611 info
= mgsl_device_list
;
3613 l
= line_info(page
+ len
, info
);
3615 if (len
+begin
> off
+count
)
3617 if (len
+begin
< off
) {
3621 info
= info
->next_device
;
3626 if (off
>= len
+begin
)
3628 *start
= page
+ (off
-begin
);
3629 return ((count
< begin
+len
-off
) ? count
: begin
+len
-off
);
3631 } /* end of mgsl_read_proc() */
3633 /* mgsl_allocate_dma_buffers()
3635 * Allocate and format DMA buffers (ISA adapter)
3636 * or format shared memory buffers (PCI adapter).
3638 * Arguments: info pointer to device instance data
3639 * Return Value: 0 if success, otherwise error
3641 static int mgsl_allocate_dma_buffers(struct mgsl_struct
*info
)
3643 unsigned short BuffersPerFrame
;
3645 info
->last_mem_alloc
= 0;
3647 /* Calculate the number of DMA buffers necessary to hold the */
3648 /* largest allowable frame size. Note: If the max frame size is */
3649 /* not an even multiple of the DMA buffer size then we need to */
3650 /* round the buffer count per frame up one. */
3652 BuffersPerFrame
= (unsigned short)(info
->max_frame_size
/DMABUFFERSIZE
);
3653 if ( info
->max_frame_size
% DMABUFFERSIZE
)
3656 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3658 * The PCI adapter has 256KBytes of shared memory to use.
3659 * This is 64 PAGE_SIZE buffers.
3661 * The first page is used for padding at this time so the
3662 * buffer list does not begin at offset 0 of the PCI
3663 * adapter's shared memory.
3665 * The 2nd page is used for the buffer list. A 4K buffer
3666 * list can hold 128 DMA_BUFFER structures at 32 bytes
3669 * This leaves 62 4K pages.
3671 * The next N pages are used for transmit frame(s). We
3672 * reserve enough 4K page blocks to hold the required
3673 * number of transmit dma buffers (num_tx_dma_buffers),
3674 * each of MaxFrameSize size.
3676 * Of the remaining pages (62-N), determine how many can
3677 * be used to receive full MaxFrameSize inbound frames
3679 info
->tx_buffer_count
= info
->num_tx_dma_buffers
* BuffersPerFrame
;
3680 info
->rx_buffer_count
= 62 - info
->tx_buffer_count
;
3682 /* Calculate the number of PAGE_SIZE buffers needed for */
3683 /* receive and transmit DMA buffers. */
3686 /* Calculate the number of DMA buffers necessary to */
3687 /* hold 7 max size receive frames and one max size transmit frame. */
3688 /* The receive buffer count is bumped by one so we avoid an */
3689 /* End of List condition if all receive buffers are used when */
3690 /* using linked list DMA buffers. */
3692 info
->tx_buffer_count
= info
->num_tx_dma_buffers
* BuffersPerFrame
;
3693 info
->rx_buffer_count
= (BuffersPerFrame
* MAXRXFRAMES
) + 6;
3696 * limit total TxBuffers & RxBuffers to 62 4K total
3697 * (ala PCI Allocation)
3700 if ( (info
->tx_buffer_count
+ info
->rx_buffer_count
) > 62 )
3701 info
->rx_buffer_count
= 62 - info
->tx_buffer_count
;
3705 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3706 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3707 __FILE__
,__LINE__
, info
->tx_buffer_count
,info
->rx_buffer_count
);
3709 if ( mgsl_alloc_buffer_list_memory( info
) < 0 ||
3710 mgsl_alloc_frame_memory(info
, info
->rx_buffer_list
, info
->rx_buffer_count
) < 0 ||
3711 mgsl_alloc_frame_memory(info
, info
->tx_buffer_list
, info
->tx_buffer_count
) < 0 ||
3712 mgsl_alloc_intermediate_rxbuffer_memory(info
) < 0 ||
3713 mgsl_alloc_intermediate_txbuffer_memory(info
) < 0 ) {
3714 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__
,__LINE__
);
3718 mgsl_reset_rx_dma_buffers( info
);
3719 mgsl_reset_tx_dma_buffers( info
);
3723 } /* end of mgsl_allocate_dma_buffers() */
3726 * mgsl_alloc_buffer_list_memory()
3728 * Allocate a common DMA buffer for use as the
3729 * receive and transmit buffer lists.
3731 * A buffer list is a set of buffer entries where each entry contains
3732 * a pointer to an actual buffer and a pointer to the next buffer entry
3733 * (plus some other info about the buffer).
3735 * The buffer entries for a list are built to form a circular list so
3736 * that when the entire list has been traversed you start back at the
3739 * This function allocates memory for just the buffer entries.
3740 * The links (pointer to next entry) are filled in with the physical
3741 * address of the next entry so the adapter can navigate the list
3742 * using bus master DMA. The pointers to the actual buffers are filled
3743 * out later when the actual buffers are allocated.
3745 * Arguments: info pointer to device instance data
3746 * Return Value: 0 if success, otherwise error
3748 static int mgsl_alloc_buffer_list_memory( struct mgsl_struct
*info
)
3752 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3753 /* PCI adapter uses shared memory. */
3754 info
->buffer_list
= info
->memory_base
+ info
->last_mem_alloc
;
3755 info
->buffer_list_phys
= info
->last_mem_alloc
;
3756 info
->last_mem_alloc
+= BUFFERLISTSIZE
;
3758 /* ISA adapter uses system memory. */
3759 /* The buffer lists are allocated as a common buffer that both */
3760 /* the processor and adapter can access. This allows the driver to */
3761 /* inspect portions of the buffer while other portions are being */
3762 /* updated by the adapter using Bus Master DMA. */
3764 info
->buffer_list
= dma_alloc_coherent(NULL
, BUFFERLISTSIZE
, &info
->buffer_list_dma_addr
, GFP_KERNEL
);
3765 if (info
->buffer_list
== NULL
)
3767 info
->buffer_list_phys
= (u32
)(info
->buffer_list_dma_addr
);
3770 /* We got the memory for the buffer entry lists. */
3771 /* Initialize the memory block to all zeros. */
3772 memset( info
->buffer_list
, 0, BUFFERLISTSIZE
);
3774 /* Save virtual address pointers to the receive and */
3775 /* transmit buffer lists. (Receive 1st). These pointers will */
3776 /* be used by the processor to access the lists. */
3777 info
->rx_buffer_list
= (DMABUFFERENTRY
*)info
->buffer_list
;
3778 info
->tx_buffer_list
= (DMABUFFERENTRY
*)info
->buffer_list
;
3779 info
->tx_buffer_list
+= info
->rx_buffer_count
;
3782 * Build the links for the buffer entry lists such that
3783 * two circular lists are built. (Transmit and Receive).
3785 * Note: the links are physical addresses
3786 * which are read by the adapter to determine the next
3787 * buffer entry to use.
3790 for ( i
= 0; i
< info
->rx_buffer_count
; i
++ ) {
3791 /* calculate and store physical address of this buffer entry */
3792 info
->rx_buffer_list
[i
].phys_entry
=
3793 info
->buffer_list_phys
+ (i
* sizeof(DMABUFFERENTRY
));
3795 /* calculate and store physical address of */
3796 /* next entry in cirular list of entries */
3798 info
->rx_buffer_list
[i
].link
= info
->buffer_list_phys
;
3800 if ( i
< info
->rx_buffer_count
- 1 )
3801 info
->rx_buffer_list
[i
].link
+= (i
+ 1) * sizeof(DMABUFFERENTRY
);
3804 for ( i
= 0; i
< info
->tx_buffer_count
; i
++ ) {
3805 /* calculate and store physical address of this buffer entry */
3806 info
->tx_buffer_list
[i
].phys_entry
= info
->buffer_list_phys
+
3807 ((info
->rx_buffer_count
+ i
) * sizeof(DMABUFFERENTRY
));
3809 /* calculate and store physical address of */
3810 /* next entry in cirular list of entries */
3812 info
->tx_buffer_list
[i
].link
= info
->buffer_list_phys
+
3813 info
->rx_buffer_count
* sizeof(DMABUFFERENTRY
);
3815 if ( i
< info
->tx_buffer_count
- 1 )
3816 info
->tx_buffer_list
[i
].link
+= (i
+ 1) * sizeof(DMABUFFERENTRY
);
3821 } /* end of mgsl_alloc_buffer_list_memory() */
3823 /* Free DMA buffers allocated for use as the
3824 * receive and transmit buffer lists.
3827 * The data transfer buffers associated with the buffer list
3828 * MUST be freed before freeing the buffer list itself because
3829 * the buffer list contains the information necessary to free
3830 * the individual buffers!
3832 static void mgsl_free_buffer_list_memory( struct mgsl_struct
*info
)
3834 if (info
->buffer_list
&& info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
3835 dma_free_coherent(NULL
, BUFFERLISTSIZE
, info
->buffer_list
, info
->buffer_list_dma_addr
);
3837 info
->buffer_list
= NULL
;
3838 info
->rx_buffer_list
= NULL
;
3839 info
->tx_buffer_list
= NULL
;
3841 } /* end of mgsl_free_buffer_list_memory() */
3844 * mgsl_alloc_frame_memory()
3846 * Allocate the frame DMA buffers used by the specified buffer list.
3847 * Each DMA buffer will be one memory page in size. This is necessary
3848 * because memory can fragment enough that it may be impossible
3853 * info pointer to device instance data
3854 * BufferList pointer to list of buffer entries
3855 * Buffercount count of buffer entries in buffer list
3857 * Return Value: 0 if success, otherwise -ENOMEM
3859 static int mgsl_alloc_frame_memory(struct mgsl_struct
*info
,DMABUFFERENTRY
*BufferList
,int Buffercount
)
3864 /* Allocate page sized buffers for the receive buffer list */
3866 for ( i
= 0; i
< Buffercount
; i
++ ) {
3867 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3868 /* PCI adapter uses shared memory buffers. */
3869 BufferList
[i
].virt_addr
= info
->memory_base
+ info
->last_mem_alloc
;
3870 phys_addr
= info
->last_mem_alloc
;
3871 info
->last_mem_alloc
+= DMABUFFERSIZE
;
3873 /* ISA adapter uses system memory. */
3874 BufferList
[i
].virt_addr
= dma_alloc_coherent(NULL
, DMABUFFERSIZE
, &BufferList
[i
].dma_addr
, GFP_KERNEL
);
3875 if (BufferList
[i
].virt_addr
== NULL
)
3877 phys_addr
= (u32
)(BufferList
[i
].dma_addr
);
3879 BufferList
[i
].phys_addr
= phys_addr
;
3884 } /* end of mgsl_alloc_frame_memory() */
3887 * mgsl_free_frame_memory()
3889 * Free the buffers associated with
3890 * each buffer entry of a buffer list.
3894 * info pointer to device instance data
3895 * BufferList pointer to list of buffer entries
3896 * Buffercount count of buffer entries in buffer list
3898 * Return Value: None
3900 static void mgsl_free_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
, int Buffercount
)
3905 for ( i
= 0 ; i
< Buffercount
; i
++ ) {
3906 if ( BufferList
[i
].virt_addr
) {
3907 if ( info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
3908 dma_free_coherent(NULL
, DMABUFFERSIZE
, BufferList
[i
].virt_addr
, BufferList
[i
].dma_addr
);
3909 BufferList
[i
].virt_addr
= NULL
;
3914 } /* end of mgsl_free_frame_memory() */
3916 /* mgsl_free_dma_buffers()
3920 * Arguments: info pointer to device instance data
3921 * Return Value: None
3923 static void mgsl_free_dma_buffers( struct mgsl_struct
*info
)
3925 mgsl_free_frame_memory( info
, info
->rx_buffer_list
, info
->rx_buffer_count
);
3926 mgsl_free_frame_memory( info
, info
->tx_buffer_list
, info
->tx_buffer_count
);
3927 mgsl_free_buffer_list_memory( info
);
3929 } /* end of mgsl_free_dma_buffers() */
3933 * mgsl_alloc_intermediate_rxbuffer_memory()
3935 * Allocate a buffer large enough to hold max_frame_size. This buffer
3936 * is used to pass an assembled frame to the line discipline.
3940 * info pointer to device instance data
3942 * Return Value: 0 if success, otherwise -ENOMEM
3944 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct
*info
)
3946 info
->intermediate_rxbuffer
= kmalloc(info
->max_frame_size
, GFP_KERNEL
| GFP_DMA
);
3947 if ( info
->intermediate_rxbuffer
== NULL
)
3952 } /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
3955 * mgsl_free_intermediate_rxbuffer_memory()
3960 * info pointer to device instance data
3962 * Return Value: None
3964 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct
*info
)
3966 kfree(info
->intermediate_rxbuffer
);
3967 info
->intermediate_rxbuffer
= NULL
;
3969 } /* end of mgsl_free_intermediate_rxbuffer_memory() */
3972 * mgsl_alloc_intermediate_txbuffer_memory()
3974 * Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
3975 * This buffer is used to load transmit frames into the adapter's dma transfer
3976 * buffers when there is sufficient space.
3980 * info pointer to device instance data
3982 * Return Value: 0 if success, otherwise -ENOMEM
3984 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct
*info
)
3988 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3989 printk("%s %s(%d) allocating %d tx holding buffers\n",
3990 info
->device_name
, __FILE__
,__LINE__
,info
->num_tx_holding_buffers
);
3992 memset(info
->tx_holding_buffers
,0,sizeof(info
->tx_holding_buffers
));
3994 for ( i
=0; i
<info
->num_tx_holding_buffers
; ++i
) {
3995 info
->tx_holding_buffers
[i
].buffer
=
3996 kmalloc(info
->max_frame_size
, GFP_KERNEL
);
3997 if (info
->tx_holding_buffers
[i
].buffer
== NULL
) {
3998 for (--i
; i
>= 0; i
--) {
3999 kfree(info
->tx_holding_buffers
[i
].buffer
);
4000 info
->tx_holding_buffers
[i
].buffer
= NULL
;
4008 } /* end of mgsl_alloc_intermediate_txbuffer_memory() */
4011 * mgsl_free_intermediate_txbuffer_memory()
4016 * info pointer to device instance data
4018 * Return Value: None
4020 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct
*info
)
4024 for ( i
=0; i
<info
->num_tx_holding_buffers
; ++i
) {
4025 kfree(info
->tx_holding_buffers
[i
].buffer
);
4026 info
->tx_holding_buffers
[i
].buffer
= NULL
;
4029 info
->get_tx_holding_index
= 0;
4030 info
->put_tx_holding_index
= 0;
4031 info
->tx_holding_count
= 0;
4033 } /* end of mgsl_free_intermediate_txbuffer_memory() */
4037 * load_next_tx_holding_buffer()
4039 * attempts to load the next buffered tx request into the
4044 * info pointer to device instance data
4046 * Return Value: 1 if next buffered tx request loaded
4047 * into adapter's tx dma buffer,
4050 static int load_next_tx_holding_buffer(struct mgsl_struct
*info
)
4054 if ( info
->tx_holding_count
) {
4055 /* determine if we have enough tx dma buffers
4056 * to accommodate the next tx frame
4058 struct tx_holding_buffer
*ptx
=
4059 &info
->tx_holding_buffers
[info
->get_tx_holding_index
];
4060 int num_free
= num_free_tx_dma_buffers(info
);
4061 int num_needed
= ptx
->buffer_size
/ DMABUFFERSIZE
;
4062 if ( ptx
->buffer_size
% DMABUFFERSIZE
)
4065 if (num_needed
<= num_free
) {
4066 info
->xmit_cnt
= ptx
->buffer_size
;
4067 mgsl_load_tx_dma_buffer(info
,ptx
->buffer
,ptx
->buffer_size
);
4069 --info
->tx_holding_count
;
4070 if ( ++info
->get_tx_holding_index
>= info
->num_tx_holding_buffers
)
4071 info
->get_tx_holding_index
=0;
4073 /* restart transmit timer */
4074 mod_timer(&info
->tx_timer
, jiffies
+ msecs_to_jiffies(5000));
4084 * save_tx_buffer_request()
4086 * attempt to store transmit frame request for later transmission
4090 * info pointer to device instance data
4091 * Buffer pointer to buffer containing frame to load
4092 * BufferSize size in bytes of frame in Buffer
4094 * Return Value: 1 if able to store, 0 otherwise
4096 static int save_tx_buffer_request(struct mgsl_struct
*info
,const char *Buffer
, unsigned int BufferSize
)
4098 struct tx_holding_buffer
*ptx
;
4100 if ( info
->tx_holding_count
>= info
->num_tx_holding_buffers
) {
4101 return 0; /* all buffers in use */
4104 ptx
= &info
->tx_holding_buffers
[info
->put_tx_holding_index
];
4105 ptx
->buffer_size
= BufferSize
;
4106 memcpy( ptx
->buffer
, Buffer
, BufferSize
);
4108 ++info
->tx_holding_count
;
4109 if ( ++info
->put_tx_holding_index
>= info
->num_tx_holding_buffers
)
4110 info
->put_tx_holding_index
=0;
4115 static int mgsl_claim_resources(struct mgsl_struct
*info
)
4117 if (request_region(info
->io_base
,info
->io_addr_size
,"synclink") == NULL
) {
4118 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4119 __FILE__
,__LINE__
,info
->device_name
, info
->io_base
);
4122 info
->io_addr_requested
= 1;
4124 if ( request_irq(info
->irq_level
,mgsl_interrupt
,info
->irq_flags
,
4125 info
->device_name
, info
) < 0 ) {
4126 printk( "%s(%d):Cant request interrupt on device %s IRQ=%d\n",
4127 __FILE__
,__LINE__
,info
->device_name
, info
->irq_level
);
4130 info
->irq_requested
= 1;
4132 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
4133 if (request_mem_region(info
->phys_memory_base
,0x40000,"synclink") == NULL
) {
4134 printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4135 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4138 info
->shared_mem_requested
= 1;
4139 if (request_mem_region(info
->phys_lcr_base
+ info
->lcr_offset
,128,"synclink") == NULL
) {
4140 printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4141 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
+ info
->lcr_offset
);
4144 info
->lcr_mem_requested
= 1;
4146 info
->memory_base
= ioremap(info
->phys_memory_base
,0x40000);
4147 if (!info
->memory_base
) {
4148 printk( "%s(%d):Cant map shared memory on device %s MemAddr=%08X\n",
4149 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4153 if ( !mgsl_memory_test(info
) ) {
4154 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4155 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4159 info
->lcr_base
= ioremap(info
->phys_lcr_base
,PAGE_SIZE
) + info
->lcr_offset
;
4160 if (!info
->lcr_base
) {
4161 printk( "%s(%d):Cant map LCR memory on device %s MemAddr=%08X\n",
4162 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
);
4167 /* claim DMA channel */
4169 if (request_dma(info
->dma_level
,info
->device_name
) < 0){
4170 printk( "%s(%d):Cant request DMA channel on device %s DMA=%d\n",
4171 __FILE__
,__LINE__
,info
->device_name
, info
->dma_level
);
4172 mgsl_release_resources( info
);
4175 info
->dma_requested
= 1;
4177 /* ISA adapter uses bus master DMA */
4178 set_dma_mode(info
->dma_level
,DMA_MODE_CASCADE
);
4179 enable_dma(info
->dma_level
);
4182 if ( mgsl_allocate_dma_buffers(info
) < 0 ) {
4183 printk( "%s(%d):Cant allocate DMA buffers on device %s DMA=%d\n",
4184 __FILE__
,__LINE__
,info
->device_name
, info
->dma_level
);
4190 mgsl_release_resources(info
);
4193 } /* end of mgsl_claim_resources() */
4195 static void mgsl_release_resources(struct mgsl_struct
*info
)
4197 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4198 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4199 __FILE__
,__LINE__
,info
->device_name
);
4201 if ( info
->irq_requested
) {
4202 free_irq(info
->irq_level
, info
);
4203 info
->irq_requested
= 0;
4205 if ( info
->dma_requested
) {
4206 disable_dma(info
->dma_level
);
4207 free_dma(info
->dma_level
);
4208 info
->dma_requested
= 0;
4210 mgsl_free_dma_buffers(info
);
4211 mgsl_free_intermediate_rxbuffer_memory(info
);
4212 mgsl_free_intermediate_txbuffer_memory(info
);
4214 if ( info
->io_addr_requested
) {
4215 release_region(info
->io_base
,info
->io_addr_size
);
4216 info
->io_addr_requested
= 0;
4218 if ( info
->shared_mem_requested
) {
4219 release_mem_region(info
->phys_memory_base
,0x40000);
4220 info
->shared_mem_requested
= 0;
4222 if ( info
->lcr_mem_requested
) {
4223 release_mem_region(info
->phys_lcr_base
+ info
->lcr_offset
,128);
4224 info
->lcr_mem_requested
= 0;
4226 if (info
->memory_base
){
4227 iounmap(info
->memory_base
);
4228 info
->memory_base
= NULL
;
4230 if (info
->lcr_base
){
4231 iounmap(info
->lcr_base
- info
->lcr_offset
);
4232 info
->lcr_base
= NULL
;
4235 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4236 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4237 __FILE__
,__LINE__
,info
->device_name
);
4239 } /* end of mgsl_release_resources() */
4241 /* mgsl_add_device()
4243 * Add the specified device instance data structure to the
4244 * global linked list of devices and increment the device count.
4246 * Arguments: info pointer to device instance data
4247 * Return Value: None
4249 static void mgsl_add_device( struct mgsl_struct
*info
)
4251 info
->next_device
= NULL
;
4252 info
->line
= mgsl_device_count
;
4253 sprintf(info
->device_name
,"ttySL%d",info
->line
);
4255 if (info
->line
< MAX_TOTAL_DEVICES
) {
4256 if (maxframe
[info
->line
])
4257 info
->max_frame_size
= maxframe
[info
->line
];
4258 info
->dosyncppp
= dosyncppp
[info
->line
];
4260 if (txdmabufs
[info
->line
]) {
4261 info
->num_tx_dma_buffers
= txdmabufs
[info
->line
];
4262 if (info
->num_tx_dma_buffers
< 1)
4263 info
->num_tx_dma_buffers
= 1;
4266 if (txholdbufs
[info
->line
]) {
4267 info
->num_tx_holding_buffers
= txholdbufs
[info
->line
];
4268 if (info
->num_tx_holding_buffers
< 1)
4269 info
->num_tx_holding_buffers
= 1;
4270 else if (info
->num_tx_holding_buffers
> MAX_TX_HOLDING_BUFFERS
)
4271 info
->num_tx_holding_buffers
= MAX_TX_HOLDING_BUFFERS
;
4275 mgsl_device_count
++;
4277 if ( !mgsl_device_list
)
4278 mgsl_device_list
= info
;
4280 struct mgsl_struct
*current_dev
= mgsl_device_list
;
4281 while( current_dev
->next_device
)
4282 current_dev
= current_dev
->next_device
;
4283 current_dev
->next_device
= info
;
4286 if ( info
->max_frame_size
< 4096 )
4287 info
->max_frame_size
= 4096;
4288 else if ( info
->max_frame_size
> 65535 )
4289 info
->max_frame_size
= 65535;
4291 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
4292 printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4293 info
->hw_version
+ 1, info
->device_name
, info
->io_base
, info
->irq_level
,
4294 info
->phys_memory_base
, info
->phys_lcr_base
,
4295 info
->max_frame_size
);
4297 printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4298 info
->device_name
, info
->io_base
, info
->irq_level
, info
->dma_level
,
4299 info
->max_frame_size
);
4302 #if SYNCLINK_GENERIC_HDLC
4306 } /* end of mgsl_add_device() */
4308 /* mgsl_allocate_device()
4310 * Allocate and initialize a device instance structure
4313 * Return Value: pointer to mgsl_struct if success, otherwise NULL
4315 static struct mgsl_struct
* mgsl_allocate_device(void)
4317 struct mgsl_struct
*info
;
4319 info
= kzalloc(sizeof(struct mgsl_struct
),
4323 printk("Error can't allocate device instance data\n");
4325 info
->magic
= MGSL_MAGIC
;
4326 INIT_WORK(&info
->task
, mgsl_bh_handler
);
4327 info
->max_frame_size
= 4096;
4328 info
->close_delay
= 5*HZ
/10;
4329 info
->closing_wait
= 30*HZ
;
4330 init_waitqueue_head(&info
->open_wait
);
4331 init_waitqueue_head(&info
->close_wait
);
4332 init_waitqueue_head(&info
->status_event_wait_q
);
4333 init_waitqueue_head(&info
->event_wait_q
);
4334 spin_lock_init(&info
->irq_spinlock
);
4335 spin_lock_init(&info
->netlock
);
4336 memcpy(&info
->params
,&default_params
,sizeof(MGSL_PARAMS
));
4337 info
->idle_mode
= HDLC_TXIDLE_FLAGS
;
4338 info
->num_tx_dma_buffers
= 1;
4339 info
->num_tx_holding_buffers
= 0;
4344 } /* end of mgsl_allocate_device()*/
4346 static const struct tty_operations mgsl_ops
= {
4348 .close
= mgsl_close
,
4349 .write
= mgsl_write
,
4350 .put_char
= mgsl_put_char
,
4351 .flush_chars
= mgsl_flush_chars
,
4352 .write_room
= mgsl_write_room
,
4353 .chars_in_buffer
= mgsl_chars_in_buffer
,
4354 .flush_buffer
= mgsl_flush_buffer
,
4355 .ioctl
= mgsl_ioctl
,
4356 .throttle
= mgsl_throttle
,
4357 .unthrottle
= mgsl_unthrottle
,
4358 .send_xchar
= mgsl_send_xchar
,
4359 .break_ctl
= mgsl_break
,
4360 .wait_until_sent
= mgsl_wait_until_sent
,
4361 .read_proc
= mgsl_read_proc
,
4362 .set_termios
= mgsl_set_termios
,
4364 .start
= mgsl_start
,
4365 .hangup
= mgsl_hangup
,
4366 .tiocmget
= tiocmget
,
4367 .tiocmset
= tiocmset
,
4371 * perform tty device initialization
4373 static int mgsl_init_tty(void)
4377 serial_driver
= alloc_tty_driver(128);
4381 serial_driver
->owner
= THIS_MODULE
;
4382 serial_driver
->driver_name
= "synclink";
4383 serial_driver
->name
= "ttySL";
4384 serial_driver
->major
= ttymajor
;
4385 serial_driver
->minor_start
= 64;
4386 serial_driver
->type
= TTY_DRIVER_TYPE_SERIAL
;
4387 serial_driver
->subtype
= SERIAL_TYPE_NORMAL
;
4388 serial_driver
->init_termios
= tty_std_termios
;
4389 serial_driver
->init_termios
.c_cflag
=
4390 B9600
| CS8
| CREAD
| HUPCL
| CLOCAL
;
4391 serial_driver
->init_termios
.c_ispeed
= 9600;
4392 serial_driver
->init_termios
.c_ospeed
= 9600;
4393 serial_driver
->flags
= TTY_DRIVER_REAL_RAW
;
4394 tty_set_operations(serial_driver
, &mgsl_ops
);
4395 if ((rc
= tty_register_driver(serial_driver
)) < 0) {
4396 printk("%s(%d):Couldn't register serial driver\n",
4398 put_tty_driver(serial_driver
);
4399 serial_driver
= NULL
;
4403 printk("%s %s, tty major#%d\n",
4404 driver_name
, driver_version
,
4405 serial_driver
->major
);
4409 /* enumerate user specified ISA adapters
4411 static void mgsl_enum_isa_devices(void)
4413 struct mgsl_struct
*info
;
4416 /* Check for user specified ISA devices */
4418 for (i
=0 ;(i
< MAX_ISA_DEVICES
) && io
[i
] && irq
[i
]; i
++){
4419 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4420 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4421 io
[i
], irq
[i
], dma
[i
] );
4423 info
= mgsl_allocate_device();
4425 /* error allocating device instance data */
4426 if ( debug_level
>= DEBUG_LEVEL_ERROR
)
4427 printk( "can't allocate device instance data.\n");
4431 /* Copy user configuration info to device instance data */
4432 info
->io_base
= (unsigned int)io
[i
];
4433 info
->irq_level
= (unsigned int)irq
[i
];
4434 info
->irq_level
= irq_canonicalize(info
->irq_level
);
4435 info
->dma_level
= (unsigned int)dma
[i
];
4436 info
->bus_type
= MGSL_BUS_TYPE_ISA
;
4437 info
->io_addr_size
= 16;
4438 info
->irq_flags
= 0;
4440 mgsl_add_device( info
);
4444 static void synclink_cleanup(void)
4447 struct mgsl_struct
*info
;
4448 struct mgsl_struct
*tmp
;
4450 printk("Unloading %s: %s\n", driver_name
, driver_version
);
4452 if (serial_driver
) {
4453 if ((rc
= tty_unregister_driver(serial_driver
)))
4454 printk("%s(%d) failed to unregister tty driver err=%d\n",
4455 __FILE__
,__LINE__
,rc
);
4456 put_tty_driver(serial_driver
);
4459 info
= mgsl_device_list
;
4461 #if SYNCLINK_GENERIC_HDLC
4464 mgsl_release_resources(info
);
4466 info
= info
->next_device
;
4471 pci_unregister_driver(&synclink_pci_driver
);
4474 static int __init
synclink_init(void)
4478 if (break_on_load
) {
4479 mgsl_get_text_ptr();
4483 printk("%s %s\n", driver_name
, driver_version
);
4485 mgsl_enum_isa_devices();
4486 if ((rc
= pci_register_driver(&synclink_pci_driver
)) < 0)
4487 printk("%s:failed to register PCI driver, error=%d\n",__FILE__
,rc
);
4491 if ((rc
= mgsl_init_tty()) < 0)
4501 static void __exit
synclink_exit(void)
4506 module_init(synclink_init
);
4507 module_exit(synclink_exit
);
4512 * Issue a USC Receive/Transmit command to the
4513 * Channel Command/Address Register (CCAR).
4517 * The command is encoded in the most significant 5 bits <15..11>
4518 * of the CCAR value. Bits <10..7> of the CCAR must be preserved
4519 * and Bits <6..0> must be written as zeros.
4523 * info pointer to device information structure
4524 * Cmd command mask (use symbolic macros)
4530 static void usc_RTCmd( struct mgsl_struct
*info
, u16 Cmd
)
4532 /* output command to CCAR in bits <15..11> */
4533 /* preserve bits <10..7>, bits <6..0> must be zero */
4535 outw( Cmd
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4537 /* Read to flush write to CCAR */
4538 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4539 inw( info
->io_base
+ CCAR
);
4541 } /* end of usc_RTCmd() */
4546 * Issue a DMA command to the DMA Command/Address Register (DCAR).
4550 * info pointer to device information structure
4551 * Cmd DMA command mask (usc_DmaCmd_XX Macros)
4557 static void usc_DmaCmd( struct mgsl_struct
*info
, u16 Cmd
)
4559 /* write command mask to DCAR */
4560 outw( Cmd
+ info
->mbre_bit
, info
->io_base
);
4562 /* Read to flush write to DCAR */
4563 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4564 inw( info
->io_base
);
4566 } /* end of usc_DmaCmd() */
4571 * Write a 16-bit value to a USC DMA register
4575 * info pointer to device info structure
4576 * RegAddr register address (number) for write
4577 * RegValue 16-bit value to write to register
4584 static void usc_OutDmaReg( struct mgsl_struct
*info
, u16 RegAddr
, u16 RegValue
)
4586 /* Note: The DCAR is located at the adapter base address */
4587 /* Note: must preserve state of BIT8 in DCAR */
4589 outw( RegAddr
+ info
->mbre_bit
, info
->io_base
);
4590 outw( RegValue
, info
->io_base
);
4592 /* Read to flush write to DCAR */
4593 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4594 inw( info
->io_base
);
4596 } /* end of usc_OutDmaReg() */
4601 * Read a 16-bit value from a DMA register
4605 * info pointer to device info structure
4606 * RegAddr register address (number) to read from
4610 * The 16-bit value read from register
4613 static u16
usc_InDmaReg( struct mgsl_struct
*info
, u16 RegAddr
)
4615 /* Note: The DCAR is located at the adapter base address */
4616 /* Note: must preserve state of BIT8 in DCAR */
4618 outw( RegAddr
+ info
->mbre_bit
, info
->io_base
);
4619 return inw( info
->io_base
);
4621 } /* end of usc_InDmaReg() */
4627 * Write a 16-bit value to a USC serial channel register
4631 * info pointer to device info structure
4632 * RegAddr register address (number) to write to
4633 * RegValue 16-bit value to write to register
4640 static void usc_OutReg( struct mgsl_struct
*info
, u16 RegAddr
, u16 RegValue
)
4642 outw( RegAddr
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4643 outw( RegValue
, info
->io_base
+ CCAR
);
4645 /* Read to flush write to CCAR */
4646 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4647 inw( info
->io_base
+ CCAR
);
4649 } /* end of usc_OutReg() */
4654 * Reads a 16-bit value from a USC serial channel register
4658 * info pointer to device extension
4659 * RegAddr register address (number) to read from
4663 * 16-bit value read from register
4665 static u16
usc_InReg( struct mgsl_struct
*info
, u16 RegAddr
)
4667 outw( RegAddr
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4668 return inw( info
->io_base
+ CCAR
);
4670 } /* end of usc_InReg() */
4672 /* usc_set_sdlc_mode()
4674 * Set up the adapter for SDLC DMA communications.
4676 * Arguments: info pointer to device instance data
4677 * Return Value: NONE
4679 static void usc_set_sdlc_mode( struct mgsl_struct
*info
)
4685 * determine if the IUSC on the adapter is pre-SL1660. If
4686 * not, take advantage of the UnderWait feature of more
4687 * modern chips. If an underrun occurs and this bit is set,
4688 * the transmitter will idle the programmed idle pattern
4689 * until the driver has time to service the underrun. Otherwise,
4690 * the dma controller may get the cycles previously requested
4691 * and begin transmitting queued tx data.
4693 usc_OutReg(info
,TMCR
,0x1f);
4694 RegValue
=usc_InReg(info
,TMDR
);
4695 if ( RegValue
== IUSC_PRE_SL1660
)
4701 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
4704 ** Channel Mode Register (CMR)
4706 ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
4707 ** <13> 0 0 = Transmit Disabled (initially)
4708 ** <12> 0 1 = Consecutive Idles share common 0
4709 ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
4710 ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
4711 ** <3..0> 0110 Receiver Mode = HDLC/SDLC
4713 ** 1000 1110 0000 0110 = 0x8e06
4717 /*--------------------------------------------------
4718 * ignore user options for UnderRun Actions and
4720 *--------------------------------------------------*/
4724 /* Channel mode Register (CMR)
4726 * <15..14> 00 Tx Sub modes, Underrun Action
4727 * <13> 0 1 = Send Preamble before opening flag
4728 * <12> 0 1 = Consecutive Idles share common 0
4729 * <11..8> 0110 Transmitter mode = HDLC/SDLC
4730 * <7..4> 0000 Rx Sub modes, addr/ctrl field handling
4731 * <3..0> 0110 Receiver mode = HDLC/SDLC
4733 * 0000 0110 0000 0110 = 0x0606
4735 if (info
->params
.mode
== MGSL_MODE_RAW
) {
4736 RegValue
= 0x0001; /* Set Receive mode = external sync */
4738 usc_OutReg( info
, IOCR
, /* Set IOCR DCD is RxSync Detect Input */
4739 (unsigned short)((usc_InReg(info
, IOCR
) & ~(BIT13
|BIT12
)) | BIT12
));
4743 * CMR <15> 0 Don't send CRC on Tx Underrun
4744 * CMR <14> x undefined
4745 * CMR <13> 0 Send preamble before openning sync
4746 * CMR <12> 0 Send 8-bit syncs, 1=send Syncs per TxLength
4749 * CMR <11-8) 0100 MonoSync
4751 * 0x00 0100 xxxx xxxx 04xx
4759 if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_ABORT15
)
4761 else if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_FLAG
)
4763 else if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_CRC
)
4764 RegValue
|= BIT15
+ BIT14
;
4767 if ( info
->params
.preamble
!= HDLC_PREAMBLE_PATTERN_NONE
)
4771 if ( info
->params
.mode
== MGSL_MODE_HDLC
&&
4772 (info
->params
.flags
& HDLC_FLAG_SHARE_ZERO
) )
4775 if ( info
->params
.addr_filter
!= 0xff )
4777 /* set up receive address filtering */
4778 usc_OutReg( info
, RSR
, info
->params
.addr_filter
);
4782 usc_OutReg( info
, CMR
, RegValue
);
4783 info
->cmr_value
= RegValue
;
4785 /* Receiver mode Register (RMR)
4787 * <15..13> 000 encoding
4788 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4789 * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
4790 * <9> 0 1 = Include Receive chars in CRC
4791 * <8> 1 1 = Use Abort/PE bit as abort indicator
4792 * <7..6> 00 Even parity
4793 * <5> 0 parity disabled
4794 * <4..2> 000 Receive Char Length = 8 bits
4795 * <1..0> 00 Disable Receiver
4797 * 0000 0101 0000 0000 = 0x0500
4802 switch ( info
->params
.encoding
) {
4803 case HDLC_ENCODING_NRZB
: RegValue
|= BIT13
; break;
4804 case HDLC_ENCODING_NRZI_MARK
: RegValue
|= BIT14
; break;
4805 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT14
+ BIT13
; break;
4806 case HDLC_ENCODING_BIPHASE_MARK
: RegValue
|= BIT15
; break;
4807 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT15
+ BIT13
; break;
4808 case HDLC_ENCODING_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
; break;
4809 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
+ BIT13
; break;
4812 if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_16_CCITT
)
4814 else if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_32_CCITT
)
4815 RegValue
|= ( BIT12
| BIT10
| BIT9
);
4817 usc_OutReg( info
, RMR
, RegValue
);
4819 /* Set the Receive count Limit Register (RCLR) to 0xffff. */
4820 /* When an opening flag of an SDLC frame is recognized the */
4821 /* Receive Character count (RCC) is loaded with the value in */
4822 /* RCLR. The RCC is decremented for each received byte. The */
4823 /* value of RCC is stored after the closing flag of the frame */
4824 /* allowing the frame size to be computed. */
4826 usc_OutReg( info
, RCLR
, RCLRVALUE
);
4828 usc_RCmd( info
, RCmd_SelectRicrdma_level
);
4830 /* Receive Interrupt Control Register (RICR)
4832 * <15..8> ? RxFIFO DMA Request Level
4833 * <7> 0 Exited Hunt IA (Interrupt Arm)
4834 * <6> 0 Idle Received IA
4835 * <5> 0 Break/Abort IA
4837 * <3> 1 Queued status reflects oldest 2 bytes in FIFO
4839 * <1> 1 Rx Overrun IA
4840 * <0> 0 Select TC0 value for readback
4842 * 0000 0000 0000 1000 = 0x000a
4845 /* Carry over the Exit Hunt and Idle Received bits */
4846 /* in case they have been armed by usc_ArmEvents. */
4848 RegValue
= usc_InReg( info
, RICR
) & 0xc0;
4850 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4851 usc_OutReg( info
, RICR
, (u16
)(0x030a | RegValue
) );
4853 usc_OutReg( info
, RICR
, (u16
)(0x140a | RegValue
) );
4855 /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
4857 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
4858 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
4860 /* Transmit mode Register (TMR)
4862 * <15..13> 000 encoding
4863 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4864 * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
4865 * <9> 0 1 = Tx CRC Enabled
4866 * <8> 0 1 = Append CRC to end of transmit frame
4867 * <7..6> 00 Transmit parity Even
4868 * <5> 0 Transmit parity Disabled
4869 * <4..2> 000 Tx Char Length = 8 bits
4870 * <1..0> 00 Disable Transmitter
4872 * 0000 0100 0000 0000 = 0x0400
4877 switch ( info
->params
.encoding
) {
4878 case HDLC_ENCODING_NRZB
: RegValue
|= BIT13
; break;
4879 case HDLC_ENCODING_NRZI_MARK
: RegValue
|= BIT14
; break;
4880 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT14
+ BIT13
; break;
4881 case HDLC_ENCODING_BIPHASE_MARK
: RegValue
|= BIT15
; break;
4882 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT15
+ BIT13
; break;
4883 case HDLC_ENCODING_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
; break;
4884 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
+ BIT13
; break;
4887 if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_16_CCITT
)
4888 RegValue
|= BIT9
+ BIT8
;
4889 else if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_32_CCITT
)
4890 RegValue
|= ( BIT12
| BIT10
| BIT9
| BIT8
);
4892 usc_OutReg( info
, TMR
, RegValue
);
4894 usc_set_txidle( info
);
4897 usc_TCmd( info
, TCmd_SelectTicrdma_level
);
4899 /* Transmit Interrupt Control Register (TICR)
4901 * <15..8> ? Transmit FIFO DMA Level
4902 * <7> 0 Present IA (Interrupt Arm)
4903 * <6> 0 Idle Sent IA
4904 * <5> 1 Abort Sent IA
4905 * <4> 1 EOF/EOM Sent IA
4907 * <2> 1 1 = Wait for SW Trigger to Start Frame
4908 * <1> 1 Tx Underrun IA
4909 * <0> 0 TC0 constant on read back
4911 * 0000 0000 0011 0110 = 0x0036
4914 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4915 usc_OutReg( info
, TICR
, 0x0736 );
4917 usc_OutReg( info
, TICR
, 0x1436 );
4919 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
4920 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
4923 ** Transmit Command/Status Register (TCSR)
4925 ** <15..12> 0000 TCmd
4926 ** <11> 0/1 UnderWait
4927 ** <10..08> 000 TxIdle
4931 ** <4> x EOF/EOM Sent
4937 ** 0000 0000 0000 0000 = 0x0000
4939 info
->tcsr_value
= 0;
4942 info
->tcsr_value
|= TCSR_UNDERWAIT
;
4944 usc_OutReg( info
, TCSR
, info
->tcsr_value
);
4946 /* Clock mode Control Register (CMCR)
4948 * <15..14> 00 counter 1 Source = Disabled
4949 * <13..12> 00 counter 0 Source = Disabled
4950 * <11..10> 11 BRG1 Input is TxC Pin
4951 * <9..8> 11 BRG0 Input is TxC Pin
4952 * <7..6> 01 DPLL Input is BRG1 Output
4953 * <5..3> XXX TxCLK comes from Port 0
4954 * <2..0> XXX RxCLK comes from Port 1
4956 * 0000 1111 0111 0111 = 0x0f77
4961 if ( info
->params
.flags
& HDLC_FLAG_RXC_DPLL
)
4962 RegValue
|= 0x0003; /* RxCLK from DPLL */
4963 else if ( info
->params
.flags
& HDLC_FLAG_RXC_BRG
)
4964 RegValue
|= 0x0004; /* RxCLK from BRG0 */
4965 else if ( info
->params
.flags
& HDLC_FLAG_RXC_TXCPIN
)
4966 RegValue
|= 0x0006; /* RxCLK from TXC Input */
4968 RegValue
|= 0x0007; /* RxCLK from Port1 */
4970 if ( info
->params
.flags
& HDLC_FLAG_TXC_DPLL
)
4971 RegValue
|= 0x0018; /* TxCLK from DPLL */
4972 else if ( info
->params
.flags
& HDLC_FLAG_TXC_BRG
)
4973 RegValue
|= 0x0020; /* TxCLK from BRG0 */
4974 else if ( info
->params
.flags
& HDLC_FLAG_TXC_RXCPIN
)
4975 RegValue
|= 0x0038; /* RxCLK from TXC Input */
4977 RegValue
|= 0x0030; /* TxCLK from Port0 */
4979 usc_OutReg( info
, CMCR
, RegValue
);
4982 /* Hardware Configuration Register (HCR)
4984 * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
4985 * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
4986 * <12> 0 CVOK:0=report code violation in biphase
4987 * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
4988 * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
4989 * <7..6> 00 reserved
4990 * <5> 0 BRG1 mode:0=continuous,1=single cycle
4992 * <3..2> 00 reserved
4993 * <1> 0 BRG0 mode:0=continuous,1=single cycle
4999 if ( info
->params
.flags
& (HDLC_FLAG_RXC_DPLL
+ HDLC_FLAG_TXC_DPLL
) ) {
5004 /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
5005 /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
5007 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
5008 XtalSpeed
= 11059200;
5010 XtalSpeed
= 14745600;
5012 if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV16
) {
5016 else if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV8
) {
5023 /* Tc = (Xtal/Speed) - 1 */
5024 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5025 /* then rounding up gives a more precise time constant. Instead */
5026 /* of rounding up and then subtracting 1 we just don't subtract */
5027 /* the one in this case. */
5029 /*--------------------------------------------------
5030 * ejz: for DPLL mode, application should use the
5031 * same clock speed as the partner system, even
5032 * though clocking is derived from the input RxData.
5033 * In case the user uses a 0 for the clock speed,
5034 * default to 0xffffffff and don't try to divide by
5036 *--------------------------------------------------*/
5037 if ( info
->params
.clock_speed
)
5039 Tc
= (u16
)((XtalSpeed
/DpllDivisor
)/info
->params
.clock_speed
);
5040 if ( !((((XtalSpeed
/DpllDivisor
) % info
->params
.clock_speed
) * 2)
5041 / info
->params
.clock_speed
) )
5048 /* Write 16-bit Time Constant for BRG1 */
5049 usc_OutReg( info
, TC1R
, Tc
);
5051 RegValue
|= BIT4
; /* enable BRG1 */
5053 switch ( info
->params
.encoding
) {
5054 case HDLC_ENCODING_NRZ
:
5055 case HDLC_ENCODING_NRZB
:
5056 case HDLC_ENCODING_NRZI_MARK
:
5057 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT8
; break;
5058 case HDLC_ENCODING_BIPHASE_MARK
:
5059 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT9
; break;
5060 case HDLC_ENCODING_BIPHASE_LEVEL
:
5061 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT9
+ BIT8
; break;
5065 usc_OutReg( info
, HCR
, RegValue
);
5068 /* Channel Control/status Register (CCSR)
5070 * <15> X RCC FIFO Overflow status (RO)
5071 * <14> X RCC FIFO Not Empty status (RO)
5072 * <13> 0 1 = Clear RCC FIFO (WO)
5073 * <12> X DPLL Sync (RW)
5074 * <11> X DPLL 2 Missed Clocks status (RO)
5075 * <10> X DPLL 1 Missed Clock status (RO)
5076 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
5077 * <7> X SDLC Loop On status (RO)
5078 * <6> X SDLC Loop Send status (RO)
5079 * <5> 1 Bypass counters for TxClk and RxClk (RW)
5080 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
5081 * <1..0> 00 reserved
5083 * 0000 0000 0010 0000 = 0x0020
5086 usc_OutReg( info
, CCSR
, 0x1020 );
5089 if ( info
->params
.flags
& HDLC_FLAG_AUTO_CTS
) {
5090 usc_OutReg( info
, SICR
,
5091 (u16
)(usc_InReg(info
,SICR
) | SICR_CTS_INACTIVE
) );
5095 /* enable Master Interrupt Enable bit (MIE) */
5096 usc_EnableMasterIrqBit( info
);
5098 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
+ RECEIVE_DATA
+
5099 TRANSMIT_STATUS
+ TRANSMIT_DATA
+ MISC
);
5101 /* arm RCC underflow interrupt */
5102 usc_OutReg(info
, SICR
, (u16
)(usc_InReg(info
,SICR
) | BIT3
));
5103 usc_EnableInterrupts(info
, MISC
);
5106 outw( 0, info
->io_base
); /* clear Master Bus Enable (DCAR) */
5107 usc_DmaCmd( info
, DmaCmd_ResetAllChannels
); /* disable both DMA channels */
5108 info
->mbre_bit
= BIT8
;
5109 outw( BIT8
, info
->io_base
); /* set Master Bus Enable (DCAR) */
5111 if (info
->bus_type
== MGSL_BUS_TYPE_ISA
) {
5112 /* Enable DMAEN (Port 7, Bit 14) */
5113 /* This connects the DMA request signal to the ISA bus */
5114 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT15
) & ~BIT14
));
5117 /* DMA Control Register (DCR)
5119 * <15..14> 10 Priority mode = Alternating Tx/Rx
5120 * 01 Rx has priority
5121 * 00 Tx has priority
5123 * <13> 1 Enable Priority Preempt per DCR<15..14>
5124 * (WARNING DCR<11..10> must be 00 when this is 1)
5125 * 0 Choose activate channel per DCR<11..10>
5127 * <12> 0 Little Endian for Array/List
5128 * <11..10> 00 Both Channels can use each bus grant
5129 * <9..6> 0000 reserved
5130 * <5> 0 7 CLK - Minimum Bus Re-request Interval
5131 * <4> 0 1 = drive D/C and S/D pins
5132 * <3> 1 1 = Add one wait state to all DMA cycles.
5133 * <2> 0 1 = Strobe /UAS on every transfer.
5134 * <1..0> 11 Addr incrementing only affects LS24 bits
5136 * 0110 0000 0000 1011 = 0x600b
5139 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5140 /* PCI adapter does not need DMA wait state */
5141 usc_OutDmaReg( info
, DCR
, 0xa00b );
5144 usc_OutDmaReg( info
, DCR
, 0x800b );
5147 /* Receive DMA mode Register (RDMR)
5149 * <15..14> 11 DMA mode = Linked List Buffer mode
5150 * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
5151 * <12> 1 Clear count of List Entry after fetching
5152 * <11..10> 00 Address mode = Increment
5153 * <9> 1 Terminate Buffer on RxBound
5154 * <8> 0 Bus Width = 16bits
5155 * <7..0> ? status Bits (write as 0s)
5157 * 1111 0010 0000 0000 = 0xf200
5160 usc_OutDmaReg( info
, RDMR
, 0xf200 );
5163 /* Transmit DMA mode Register (TDMR)
5165 * <15..14> 11 DMA mode = Linked List Buffer mode
5166 * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
5167 * <12> 1 Clear count of List Entry after fetching
5168 * <11..10> 00 Address mode = Increment
5169 * <9> 1 Terminate Buffer on end of frame
5170 * <8> 0 Bus Width = 16bits
5171 * <7..0> ? status Bits (Read Only so write as 0)
5173 * 1111 0010 0000 0000 = 0xf200
5176 usc_OutDmaReg( info
, TDMR
, 0xf200 );
5179 /* DMA Interrupt Control Register (DICR)
5181 * <15> 1 DMA Interrupt Enable
5182 * <14> 0 1 = Disable IEO from USC
5183 * <13> 0 1 = Don't provide vector during IntAck
5184 * <12> 1 1 = Include status in Vector
5185 * <10..2> 0 reserved, Must be 0s
5186 * <1> 0 1 = Rx DMA Interrupt Enabled
5187 * <0> 0 1 = Tx DMA Interrupt Enabled
5189 * 1001 0000 0000 0000 = 0x9000
5192 usc_OutDmaReg( info
, DICR
, 0x9000 );
5194 usc_InDmaReg( info
, RDMR
); /* clear pending receive DMA IRQ bits */
5195 usc_InDmaReg( info
, TDMR
); /* clear pending transmit DMA IRQ bits */
5196 usc_OutDmaReg( info
, CDIR
, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
5198 /* Channel Control Register (CCR)
5200 * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
5201 * <13> 0 Trigger Tx on SW Command Disabled
5202 * <12> 0 Flag Preamble Disabled
5203 * <11..10> 00 Preamble Length
5204 * <9..8> 00 Preamble Pattern
5205 * <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
5206 * <5> 0 Trigger Rx on SW Command Disabled
5209 * 1000 0000 1000 0000 = 0x8080
5214 switch ( info
->params
.preamble_length
) {
5215 case HDLC_PREAMBLE_LENGTH_16BITS
: RegValue
|= BIT10
; break;
5216 case HDLC_PREAMBLE_LENGTH_32BITS
: RegValue
|= BIT11
; break;
5217 case HDLC_PREAMBLE_LENGTH_64BITS
: RegValue
|= BIT11
+ BIT10
; break;
5220 switch ( info
->params
.preamble
) {
5221 case HDLC_PREAMBLE_PATTERN_FLAGS
: RegValue
|= BIT8
+ BIT12
; break;
5222 case HDLC_PREAMBLE_PATTERN_ONES
: RegValue
|= BIT8
; break;
5223 case HDLC_PREAMBLE_PATTERN_10
: RegValue
|= BIT9
; break;
5224 case HDLC_PREAMBLE_PATTERN_01
: RegValue
|= BIT9
+ BIT8
; break;
5227 usc_OutReg( info
, CCR
, RegValue
);
5231 * Burst/Dwell Control Register
5233 * <15..8> 0x20 Maximum number of transfers per bus grant
5234 * <7..0> 0x00 Maximum number of clock cycles per bus grant
5237 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5238 /* don't limit bus occupancy on PCI adapter */
5239 usc_OutDmaReg( info
, BDCR
, 0x0000 );
5242 usc_OutDmaReg( info
, BDCR
, 0x2000 );
5244 usc_stop_transmitter(info
);
5245 usc_stop_receiver(info
);
5247 } /* end of usc_set_sdlc_mode() */
5249 /* usc_enable_loopback()
5251 * Set the 16C32 for internal loopback mode.
5252 * The TxCLK and RxCLK signals are generated from the BRG0 and
5253 * the TxD is looped back to the RxD internally.
5255 * Arguments: info pointer to device instance data
5256 * enable 1 = enable loopback, 0 = disable
5257 * Return Value: None
5259 static void usc_enable_loopback(struct mgsl_struct
*info
, int enable
)
5262 /* blank external TXD output */
5263 usc_OutReg(info
,IOCR
,usc_InReg(info
,IOCR
) | (BIT7
+BIT6
));
5265 /* Clock mode Control Register (CMCR)
5267 * <15..14> 00 counter 1 Disabled
5268 * <13..12> 00 counter 0 Disabled
5269 * <11..10> 11 BRG1 Input is TxC Pin
5270 * <9..8> 11 BRG0 Input is TxC Pin
5271 * <7..6> 01 DPLL Input is BRG1 Output
5272 * <5..3> 100 TxCLK comes from BRG0
5273 * <2..0> 100 RxCLK comes from BRG0
5275 * 0000 1111 0110 0100 = 0x0f64
5278 usc_OutReg( info
, CMCR
, 0x0f64 );
5280 /* Write 16-bit Time Constant for BRG0 */
5281 /* use clock speed if available, otherwise use 8 for diagnostics */
5282 if (info
->params
.clock_speed
) {
5283 if (info
->bus_type
== MGSL_BUS_TYPE_PCI
)
5284 usc_OutReg(info
, TC0R
, (u16
)((11059200/info
->params
.clock_speed
)-1));
5286 usc_OutReg(info
, TC0R
, (u16
)((14745600/info
->params
.clock_speed
)-1));
5288 usc_OutReg(info
, TC0R
, (u16
)8);
5290 /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
5291 mode = Continuous Set Bit 0 to enable BRG0. */
5292 usc_OutReg( info
, HCR
, (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
5294 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5295 usc_OutReg(info
, IOCR
, (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004));
5297 /* set Internal Data loopback mode */
5298 info
->loopback_bits
= 0x300;
5299 outw( 0x0300, info
->io_base
+ CCAR
);
5301 /* enable external TXD output */
5302 usc_OutReg(info
,IOCR
,usc_InReg(info
,IOCR
) & ~(BIT7
+BIT6
));
5304 /* clear Internal Data loopback mode */
5305 info
->loopback_bits
= 0;
5306 outw( 0,info
->io_base
+ CCAR
);
5309 } /* end of usc_enable_loopback() */
5311 /* usc_enable_aux_clock()
5313 * Enabled the AUX clock output at the specified frequency.
5317 * info pointer to device extension
5318 * data_rate data rate of clock in bits per second
5319 * A data rate of 0 disables the AUX clock.
5321 * Return Value: None
5323 static void usc_enable_aux_clock( struct mgsl_struct
*info
, u32 data_rate
)
5329 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
5330 XtalSpeed
= 11059200;
5332 XtalSpeed
= 14745600;
5335 /* Tc = (Xtal/Speed) - 1 */
5336 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5337 /* then rounding up gives a more precise time constant. Instead */
5338 /* of rounding up and then subtracting 1 we just don't subtract */
5339 /* the one in this case. */
5342 Tc
= (u16
)(XtalSpeed
/data_rate
);
5343 if ( !(((XtalSpeed
% data_rate
) * 2) / data_rate
) )
5346 /* Write 16-bit Time Constant for BRG0 */
5347 usc_OutReg( info
, TC0R
, Tc
);
5350 * Hardware Configuration Register (HCR)
5351 * Clear Bit 1, BRG0 mode = Continuous
5352 * Set Bit 0 to enable BRG0.
5355 usc_OutReg( info
, HCR
, (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
5357 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5358 usc_OutReg( info
, IOCR
, (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004) );
5360 /* data rate == 0 so turn off BRG0 */
5361 usc_OutReg( info
, HCR
, (u16
)(usc_InReg( info
, HCR
) & ~BIT0
) );
5364 } /* end of usc_enable_aux_clock() */
5368 * usc_process_rxoverrun_sync()
5370 * This function processes a receive overrun by resetting the
5371 * receive DMA buffers and issuing a Purge Rx FIFO command
5372 * to allow the receiver to continue receiving.
5376 * info pointer to device extension
5378 * Return Value: None
5380 static void usc_process_rxoverrun_sync( struct mgsl_struct
*info
)
5384 int frame_start_index
;
5385 int start_of_frame_found
= FALSE
;
5386 int end_of_frame_found
= FALSE
;
5387 int reprogram_dma
= FALSE
;
5389 DMABUFFERENTRY
*buffer_list
= info
->rx_buffer_list
;
5392 usc_DmaCmd( info
, DmaCmd_PauseRxChannel
);
5393 usc_RCmd( info
, RCmd_EnterHuntmode
);
5394 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5396 /* CurrentRxBuffer points to the 1st buffer of the next */
5397 /* possibly available receive frame. */
5399 frame_start_index
= start_index
= end_index
= info
->current_rx_buffer
;
5401 /* Search for an unfinished string of buffers. This means */
5402 /* that a receive frame started (at least one buffer with */
5403 /* count set to zero) but there is no terminiting buffer */
5404 /* (status set to non-zero). */
5406 while( !buffer_list
[end_index
].count
)
5408 /* Count field has been reset to zero by 16C32. */
5409 /* This buffer is currently in use. */
5411 if ( !start_of_frame_found
)
5413 start_of_frame_found
= TRUE
;
5414 frame_start_index
= end_index
;
5415 end_of_frame_found
= FALSE
;
5418 if ( buffer_list
[end_index
].status
)
5420 /* Status field has been set by 16C32. */
5421 /* This is the last buffer of a received frame. */
5423 /* We want to leave the buffers for this frame intact. */
5424 /* Move on to next possible frame. */
5426 start_of_frame_found
= FALSE
;
5427 end_of_frame_found
= TRUE
;
5430 /* advance to next buffer entry in linked list */
5432 if ( end_index
== info
->rx_buffer_count
)
5435 if ( start_index
== end_index
)
5437 /* The entire list has been searched with all Counts == 0 and */
5438 /* all Status == 0. The receive buffers are */
5439 /* completely screwed, reset all receive buffers! */
5440 mgsl_reset_rx_dma_buffers( info
);
5441 frame_start_index
= 0;
5442 start_of_frame_found
= FALSE
;
5443 reprogram_dma
= TRUE
;
5448 if ( start_of_frame_found
&& !end_of_frame_found
)
5450 /* There is an unfinished string of receive DMA buffers */
5451 /* as a result of the receiver overrun. */
5453 /* Reset the buffers for the unfinished frame */
5454 /* and reprogram the receive DMA controller to start */
5455 /* at the 1st buffer of unfinished frame. */
5457 start_index
= frame_start_index
;
5461 *((unsigned long *)&(info
->rx_buffer_list
[start_index
++].count
)) = DMABUFFERSIZE
;
5463 /* Adjust index for wrap around. */
5464 if ( start_index
== info
->rx_buffer_count
)
5467 } while( start_index
!= end_index
);
5469 reprogram_dma
= TRUE
;
5472 if ( reprogram_dma
)
5474 usc_UnlatchRxstatusBits(info
,RXSTATUS_ALL
);
5475 usc_ClearIrqPendingBits(info
, RECEIVE_DATA
|RECEIVE_STATUS
);
5476 usc_UnlatchRxstatusBits(info
, RECEIVE_DATA
|RECEIVE_STATUS
);
5478 usc_EnableReceiver(info
,DISABLE_UNCONDITIONAL
);
5480 /* This empties the receive FIFO and loads the RCC with RCLR */
5481 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5483 /* program 16C32 with physical address of 1st DMA buffer entry */
5484 phys_addr
= info
->rx_buffer_list
[frame_start_index
].phys_entry
;
5485 usc_OutDmaReg( info
, NRARL
, (u16
)phys_addr
);
5486 usc_OutDmaReg( info
, NRARU
, (u16
)(phys_addr
>> 16) );
5488 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5489 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5490 usc_EnableInterrupts( info
, RECEIVE_STATUS
);
5492 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5493 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5495 usc_OutDmaReg( info
, RDIAR
, BIT3
+ BIT2
);
5496 usc_OutDmaReg( info
, DICR
, (u16
)(usc_InDmaReg(info
,DICR
) | BIT1
) );
5497 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
5498 if ( info
->params
.flags
& HDLC_FLAG_AUTO_DCD
)
5499 usc_EnableReceiver(info
,ENABLE_AUTO_DCD
);
5501 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5505 /* This empties the receive FIFO and loads the RCC with RCLR */
5506 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5507 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5510 } /* end of usc_process_rxoverrun_sync() */
5512 /* usc_stop_receiver()
5514 * Disable USC receiver
5516 * Arguments: info pointer to device instance data
5517 * Return Value: None
5519 static void usc_stop_receiver( struct mgsl_struct
*info
)
5521 if (debug_level
>= DEBUG_LEVEL_ISR
)
5522 printk("%s(%d):usc_stop_receiver(%s)\n",
5523 __FILE__
,__LINE__
, info
->device_name
);
5525 /* Disable receive DMA channel. */
5526 /* This also disables receive DMA channel interrupts */
5527 usc_DmaCmd( info
, DmaCmd_ResetRxChannel
);
5529 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5530 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5531 usc_DisableInterrupts( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5533 usc_EnableReceiver(info
,DISABLE_UNCONDITIONAL
);
5535 /* This empties the receive FIFO and loads the RCC with RCLR */
5536 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5537 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5539 info
->rx_enabled
= 0;
5540 info
->rx_overflow
= 0;
5541 info
->rx_rcc_underrun
= 0;
5543 } /* end of stop_receiver() */
5545 /* usc_start_receiver()
5547 * Enable the USC receiver
5549 * Arguments: info pointer to device instance data
5550 * Return Value: None
5552 static void usc_start_receiver( struct mgsl_struct
*info
)
5556 if (debug_level
>= DEBUG_LEVEL_ISR
)
5557 printk("%s(%d):usc_start_receiver(%s)\n",
5558 __FILE__
,__LINE__
, info
->device_name
);
5560 mgsl_reset_rx_dma_buffers( info
);
5561 usc_stop_receiver( info
);
5563 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5564 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5566 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
5567 info
->params
.mode
== MGSL_MODE_RAW
) {
5568 /* DMA mode Transfers */
5569 /* Program the DMA controller. */
5570 /* Enable the DMA controller end of buffer interrupt. */
5572 /* program 16C32 with physical address of 1st DMA buffer entry */
5573 phys_addr
= info
->rx_buffer_list
[0].phys_entry
;
5574 usc_OutDmaReg( info
, NRARL
, (u16
)phys_addr
);
5575 usc_OutDmaReg( info
, NRARU
, (u16
)(phys_addr
>> 16) );
5577 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5578 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5579 usc_EnableInterrupts( info
, RECEIVE_STATUS
);
5581 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5582 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5584 usc_OutDmaReg( info
, RDIAR
, BIT3
+ BIT2
);
5585 usc_OutDmaReg( info
, DICR
, (u16
)(usc_InDmaReg(info
,DICR
) | BIT1
) );
5586 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
5587 if ( info
->params
.flags
& HDLC_FLAG_AUTO_DCD
)
5588 usc_EnableReceiver(info
,ENABLE_AUTO_DCD
);
5590 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5592 usc_UnlatchRxstatusBits(info
, RXSTATUS_ALL
);
5593 usc_ClearIrqPendingBits(info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5594 usc_EnableInterrupts(info
, RECEIVE_DATA
);
5596 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5597 usc_RCmd( info
, RCmd_EnterHuntmode
);
5599 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5602 usc_OutReg( info
, CCSR
, 0x1020 );
5604 info
->rx_enabled
= 1;
5606 } /* end of usc_start_receiver() */
5608 /* usc_start_transmitter()
5610 * Enable the USC transmitter and send a transmit frame if
5611 * one is loaded in the DMA buffers.
5613 * Arguments: info pointer to device instance data
5614 * Return Value: None
5616 static void usc_start_transmitter( struct mgsl_struct
*info
)
5619 unsigned int FrameSize
;
5621 if (debug_level
>= DEBUG_LEVEL_ISR
)
5622 printk("%s(%d):usc_start_transmitter(%s)\n",
5623 __FILE__
,__LINE__
, info
->device_name
);
5625 if ( info
->xmit_cnt
) {
5627 /* If auto RTS enabled and RTS is inactive, then assert */
5628 /* RTS and set a flag indicating that the driver should */
5629 /* negate RTS when the transmission completes. */
5631 info
->drop_rts_on_tx_done
= 0;
5633 if ( info
->params
.flags
& HDLC_FLAG_AUTO_RTS
) {
5634 usc_get_serial_signals( info
);
5635 if ( !(info
->serial_signals
& SerialSignal_RTS
) ) {
5636 info
->serial_signals
|= SerialSignal_RTS
;
5637 usc_set_serial_signals( info
);
5638 info
->drop_rts_on_tx_done
= 1;
5643 if ( info
->params
.mode
== MGSL_MODE_ASYNC
) {
5644 if ( !info
->tx_active
) {
5645 usc_UnlatchTxstatusBits(info
, TXSTATUS_ALL
);
5646 usc_ClearIrqPendingBits(info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5647 usc_EnableInterrupts(info
, TRANSMIT_DATA
);
5648 usc_load_txfifo(info
);
5651 /* Disable transmit DMA controller while programming. */
5652 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
5654 /* Transmit DMA buffer is loaded, so program USC */
5655 /* to send the frame contained in the buffers. */
5657 FrameSize
= info
->tx_buffer_list
[info
->start_tx_dma_buffer
].rcc
;
5659 /* if operating in Raw sync mode, reset the rcc component
5660 * of the tx dma buffer entry, otherwise, the serial controller
5661 * will send a closing sync char after this count.
5663 if ( info
->params
.mode
== MGSL_MODE_RAW
)
5664 info
->tx_buffer_list
[info
->start_tx_dma_buffer
].rcc
= 0;
5666 /* Program the Transmit Character Length Register (TCLR) */
5667 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
5668 usc_OutReg( info
, TCLR
, (u16
)FrameSize
);
5670 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
5672 /* Program the address of the 1st DMA Buffer Entry in linked list */
5673 phys_addr
= info
->tx_buffer_list
[info
->start_tx_dma_buffer
].phys_entry
;
5674 usc_OutDmaReg( info
, NTARL
, (u16
)phys_addr
);
5675 usc_OutDmaReg( info
, NTARU
, (u16
)(phys_addr
>> 16) );
5677 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
5678 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
5679 usc_EnableInterrupts( info
, TRANSMIT_STATUS
);
5681 if ( info
->params
.mode
== MGSL_MODE_RAW
&&
5682 info
->num_tx_dma_buffers
> 1 ) {
5683 /* When running external sync mode, attempt to 'stream' transmit */
5684 /* by filling tx dma buffers as they become available. To do this */
5685 /* we need to enable Tx DMA EOB Status interrupts : */
5687 /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
5688 /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
5690 usc_OutDmaReg( info
, TDIAR
, BIT2
|BIT3
);
5691 usc_OutDmaReg( info
, DICR
, (u16
)(usc_InDmaReg(info
,DICR
) | BIT0
) );
5694 /* Initialize Transmit DMA Channel */
5695 usc_DmaCmd( info
, DmaCmd_InitTxChannel
);
5697 usc_TCmd( info
, TCmd_SendFrame
);
5699 mod_timer(&info
->tx_timer
, jiffies
+
5700 msecs_to_jiffies(5000));
5702 info
->tx_active
= 1;
5705 if ( !info
->tx_enabled
) {
5706 info
->tx_enabled
= 1;
5707 if ( info
->params
.flags
& HDLC_FLAG_AUTO_CTS
)
5708 usc_EnableTransmitter(info
,ENABLE_AUTO_CTS
);
5710 usc_EnableTransmitter(info
,ENABLE_UNCONDITIONAL
);
5713 } /* end of usc_start_transmitter() */
5715 /* usc_stop_transmitter()
5717 * Stops the transmitter and DMA
5719 * Arguments: info pointer to device isntance data
5720 * Return Value: None
5722 static void usc_stop_transmitter( struct mgsl_struct
*info
)
5724 if (debug_level
>= DEBUG_LEVEL_ISR
)
5725 printk("%s(%d):usc_stop_transmitter(%s)\n",
5726 __FILE__
,__LINE__
, info
->device_name
);
5728 del_timer(&info
->tx_timer
);
5730 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
5731 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5732 usc_DisableInterrupts( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5734 usc_EnableTransmitter(info
,DISABLE_UNCONDITIONAL
);
5735 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
5736 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
5738 info
->tx_enabled
= 0;
5739 info
->tx_active
= 0;
5741 } /* end of usc_stop_transmitter() */
5743 /* usc_load_txfifo()
5745 * Fill the transmit FIFO until the FIFO is full or
5746 * there is no more data to load.
5748 * Arguments: info pointer to device extension (instance data)
5749 * Return Value: None
5751 static void usc_load_txfifo( struct mgsl_struct
*info
)
5756 if ( !info
->xmit_cnt
&& !info
->x_char
)
5759 /* Select transmit FIFO status readback in TICR */
5760 usc_TCmd( info
, TCmd_SelectTicrTxFifostatus
);
5762 /* load the Transmit FIFO until FIFOs full or all data sent */
5764 while( (Fifocount
= usc_InReg(info
, TICR
) >> 8) && info
->xmit_cnt
) {
5765 /* there is more space in the transmit FIFO and */
5766 /* there is more data in transmit buffer */
5768 if ( (info
->xmit_cnt
> 1) && (Fifocount
> 1) && !info
->x_char
) {
5769 /* write a 16-bit word from transmit buffer to 16C32 */
5771 TwoBytes
[0] = info
->xmit_buf
[info
->xmit_tail
++];
5772 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5773 TwoBytes
[1] = info
->xmit_buf
[info
->xmit_tail
++];
5774 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5776 outw( *((u16
*)TwoBytes
), info
->io_base
+ DATAREG
);
5778 info
->xmit_cnt
-= 2;
5779 info
->icount
.tx
+= 2;
5781 /* only 1 byte left to transmit or 1 FIFO slot left */
5783 outw( (inw( info
->io_base
+ CCAR
) & 0x0780) | (TDR
+LSBONLY
),
5784 info
->io_base
+ CCAR
);
5787 /* transmit pending high priority char */
5788 outw( info
->x_char
,info
->io_base
+ CCAR
);
5791 outw( info
->xmit_buf
[info
->xmit_tail
++],info
->io_base
+ CCAR
);
5792 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5799 } /* end of usc_load_txfifo() */
5803 * Reset the adapter to a known state and prepare it for further use.
5805 * Arguments: info pointer to device instance data
5806 * Return Value: None
5808 static void usc_reset( struct mgsl_struct
*info
)
5810 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5814 /* Set BIT30 of Misc Control Register */
5815 /* (Local Control Register 0x50) to force reset of USC. */
5817 volatile u32
*MiscCtrl
= (u32
*)(info
->lcr_base
+ 0x50);
5818 u32
*LCR0BRDR
= (u32
*)(info
->lcr_base
+ 0x28);
5820 info
->misc_ctrl_value
|= BIT30
;
5821 *MiscCtrl
= info
->misc_ctrl_value
;
5824 * Force at least 170ns delay before clearing
5825 * reset bit. Each read from LCR takes at least
5826 * 30ns so 10 times for 300ns to be safe.
5829 readval
= *MiscCtrl
;
5831 info
->misc_ctrl_value
&= ~BIT30
;
5832 *MiscCtrl
= info
->misc_ctrl_value
;
5834 *LCR0BRDR
= BUS_DESCRIPTOR(
5835 1, // Write Strobe Hold (0-3)
5836 2, // Write Strobe Delay (0-3)
5837 2, // Read Strobe Delay (0-3)
5838 0, // NWDD (Write data-data) (0-3)
5839 4, // NWAD (Write Addr-data) (0-31)
5840 0, // NXDA (Read/Write Data-Addr) (0-3)
5841 0, // NRDD (Read Data-Data) (0-3)
5842 5 // NRAD (Read Addr-Data) (0-31)
5846 outb( 0,info
->io_base
+ 8 );
5850 info
->loopback_bits
= 0;
5851 info
->usc_idle_mode
= 0;
5854 * Program the Bus Configuration Register (BCR)
5856 * <15> 0 Don't use separate address
5857 * <14..6> 0 reserved
5858 * <5..4> 00 IAckmode = Default, don't care
5859 * <3> 1 Bus Request Totem Pole output
5860 * <2> 1 Use 16 Bit data bus
5861 * <1> 0 IRQ Totem Pole output
5862 * <0> 0 Don't Shift Right Addr
5864 * 0000 0000 0000 1100 = 0x000c
5866 * By writing to io_base + SDPIN the Wait/Ack pin is
5867 * programmed to work as a Wait pin.
5870 outw( 0x000c,info
->io_base
+ SDPIN
);
5873 outw( 0,info
->io_base
);
5874 outw( 0,info
->io_base
+ CCAR
);
5876 /* select little endian byte ordering */
5877 usc_RTCmd( info
, RTCmd_SelectLittleEndian
);
5880 /* Port Control Register (PCR)
5882 * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
5883 * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
5884 * <11..10> 00 Port 5 is Input (No Connect, Don't Care)
5885 * <9..8> 00 Port 4 is Input (No Connect, Don't Care)
5886 * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
5887 * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
5888 * <3..2> 01 Port 1 is Input (Dedicated RxC)
5889 * <1..0> 01 Port 0 is Input (Dedicated TxC)
5891 * 1111 0000 1111 0101 = 0xf0f5
5894 usc_OutReg( info
, PCR
, 0xf0f5 );
5898 * Input/Output Control Register
5900 * <15..14> 00 CTS is active low input
5901 * <13..12> 00 DCD is active low input
5902 * <11..10> 00 TxREQ pin is input (DSR)
5903 * <9..8> 00 RxREQ pin is input (RI)
5904 * <7..6> 00 TxD is output (Transmit Data)
5905 * <5..3> 000 TxC Pin in Input (14.7456MHz Clock)
5906 * <2..0> 100 RxC is Output (drive with BRG0)
5908 * 0000 0000 0000 0100 = 0x0004
5911 usc_OutReg( info
, IOCR
, 0x0004 );
5913 } /* end of usc_reset() */
5915 /* usc_set_async_mode()
5917 * Program adapter for asynchronous communications.
5919 * Arguments: info pointer to device instance data
5920 * Return Value: None
5922 static void usc_set_async_mode( struct mgsl_struct
*info
)
5926 /* disable interrupts while programming USC */
5927 usc_DisableMasterIrqBit( info
);
5929 outw( 0, info
->io_base
); /* clear Master Bus Enable (DCAR) */
5930 usc_DmaCmd( info
, DmaCmd_ResetAllChannels
); /* disable both DMA channels */
5932 usc_loopback_frame( info
);
5934 /* Channel mode Register (CMR)
5936 * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit
5937 * <13..12> 00 00 = 16X Clock
5938 * <11..8> 0000 Transmitter mode = Asynchronous
5939 * <7..6> 00 reserved?
5940 * <5..4> 00 Rx Sub modes, 00 = 16X Clock
5941 * <3..0> 0000 Receiver mode = Asynchronous
5943 * 0000 0000 0000 0000 = 0x0
5947 if ( info
->params
.stop_bits
!= 1 )
5949 usc_OutReg( info
, CMR
, RegValue
);
5952 /* Receiver mode Register (RMR)
5954 * <15..13> 000 encoding = None
5955 * <12..08> 00000 reserved (Sync Only)
5956 * <7..6> 00 Even parity
5957 * <5> 0 parity disabled
5958 * <4..2> 000 Receive Char Length = 8 bits
5959 * <1..0> 00 Disable Receiver
5961 * 0000 0000 0000 0000 = 0x0
5966 if ( info
->params
.data_bits
!= 8 )
5967 RegValue
|= BIT4
+BIT3
+BIT2
;
5969 if ( info
->params
.parity
!= ASYNC_PARITY_NONE
) {
5971 if ( info
->params
.parity
!= ASYNC_PARITY_ODD
)
5975 usc_OutReg( info
, RMR
, RegValue
);
5978 /* Set IRQ trigger level */
5980 usc_RCmd( info
, RCmd_SelectRicrIntLevel
);
5983 /* Receive Interrupt Control Register (RICR)
5985 * <15..8> ? RxFIFO IRQ Request Level
5987 * Note: For async mode the receive FIFO level must be set
5988 * to 0 to avoid the situation where the FIFO contains fewer bytes
5989 * than the trigger level and no more data is expected.
5991 * <7> 0 Exited Hunt IA (Interrupt Arm)
5992 * <6> 0 Idle Received IA
5993 * <5> 0 Break/Abort IA
5995 * <3> 0 Queued status reflects oldest byte in FIFO
5997 * <1> 0 Rx Overrun IA
5998 * <0> 0 Select TC0 value for readback
6000 * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
6003 usc_OutReg( info
, RICR
, 0x0000 );
6005 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
6006 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
6009 /* Transmit mode Register (TMR)
6011 * <15..13> 000 encoding = None
6012 * <12..08> 00000 reserved (Sync Only)
6013 * <7..6> 00 Transmit parity Even
6014 * <5> 0 Transmit parity Disabled
6015 * <4..2> 000 Tx Char Length = 8 bits
6016 * <1..0> 00 Disable Transmitter
6018 * 0000 0000 0000 0000 = 0x0
6023 if ( info
->params
.data_bits
!= 8 )
6024 RegValue
|= BIT4
+BIT3
+BIT2
;
6026 if ( info
->params
.parity
!= ASYNC_PARITY_NONE
) {
6028 if ( info
->params
.parity
!= ASYNC_PARITY_ODD
)
6032 usc_OutReg( info
, TMR
, RegValue
);
6034 usc_set_txidle( info
);
6037 /* Set IRQ trigger level */
6039 usc_TCmd( info
, TCmd_SelectTicrIntLevel
);
6042 /* Transmit Interrupt Control Register (TICR)
6044 * <15..8> ? Transmit FIFO IRQ Level
6045 * <7> 0 Present IA (Interrupt Arm)
6046 * <6> 1 Idle Sent IA
6047 * <5> 0 Abort Sent IA
6048 * <4> 0 EOF/EOM Sent IA
6050 * <2> 0 1 = Wait for SW Trigger to Start Frame
6051 * <1> 0 Tx Underrun IA
6052 * <0> 0 TC0 constant on read back
6054 * 0000 0000 0100 0000 = 0x0040
6057 usc_OutReg( info
, TICR
, 0x1f40 );
6059 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
6060 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
6062 usc_enable_async_clock( info
, info
->params
.data_rate
);
6065 /* Channel Control/status Register (CCSR)
6067 * <15> X RCC FIFO Overflow status (RO)
6068 * <14> X RCC FIFO Not Empty status (RO)
6069 * <13> 0 1 = Clear RCC FIFO (WO)
6070 * <12> X DPLL in Sync status (RO)
6071 * <11> X DPLL 2 Missed Clocks status (RO)
6072 * <10> X DPLL 1 Missed Clock status (RO)
6073 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
6074 * <7> X SDLC Loop On status (RO)
6075 * <6> X SDLC Loop Send status (RO)
6076 * <5> 1 Bypass counters for TxClk and RxClk (RW)
6077 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
6078 * <1..0> 00 reserved
6080 * 0000 0000 0010 0000 = 0x0020
6083 usc_OutReg( info
, CCSR
, 0x0020 );
6085 usc_DisableInterrupts( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
+
6086 RECEIVE_DATA
+ RECEIVE_STATUS
);
6088 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
+
6089 RECEIVE_DATA
+ RECEIVE_STATUS
);
6091 usc_EnableMasterIrqBit( info
);
6093 if (info
->bus_type
== MGSL_BUS_TYPE_ISA
) {
6094 /* Enable INTEN (Port 6, Bit12) */
6095 /* This connects the IRQ request signal to the ISA bus */
6096 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
));
6099 if (info
->params
.loopback
) {
6100 info
->loopback_bits
= 0x300;
6101 outw(0x0300, info
->io_base
+ CCAR
);
6104 } /* end of usc_set_async_mode() */
6106 /* usc_loopback_frame()
6108 * Loop back a small (2 byte) dummy SDLC frame.
6109 * Interrupts and DMA are NOT used. The purpose of this is to
6110 * clear any 'stale' status info left over from running in async mode.
6112 * The 16C32 shows the strange behaviour of marking the 1st
6113 * received SDLC frame with a CRC error even when there is no
6114 * CRC error. To get around this a small dummy from of 2 bytes
6115 * is looped back when switching from async to sync mode.
6117 * Arguments: info pointer to device instance data
6118 * Return Value: None
6120 static void usc_loopback_frame( struct mgsl_struct
*info
)
6123 unsigned long oldmode
= info
->params
.mode
;
6125 info
->params
.mode
= MGSL_MODE_HDLC
;
6127 usc_DisableMasterIrqBit( info
);
6129 usc_set_sdlc_mode( info
);
6130 usc_enable_loopback( info
, 1 );
6132 /* Write 16-bit Time Constant for BRG0 */
6133 usc_OutReg( info
, TC0R
, 0 );
6135 /* Channel Control Register (CCR)
6137 * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
6138 * <13> 0 Trigger Tx on SW Command Disabled
6139 * <12> 0 Flag Preamble Disabled
6140 * <11..10> 00 Preamble Length = 8-Bits
6141 * <9..8> 01 Preamble Pattern = flags
6142 * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs)
6143 * <5> 0 Trigger Rx on SW Command Disabled
6146 * 0000 0001 0000 0000 = 0x0100
6149 usc_OutReg( info
, CCR
, 0x0100 );
6151 /* SETUP RECEIVER */
6152 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
6153 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
6155 /* SETUP TRANSMITTER */
6156 /* Program the Transmit Character Length Register (TCLR) */
6157 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6158 usc_OutReg( info
, TCLR
, 2 );
6159 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
6161 /* unlatch Tx status bits, and start transmit channel. */
6162 usc_UnlatchTxstatusBits(info
,TXSTATUS_ALL
);
6163 outw(0,info
->io_base
+ DATAREG
);
6165 /* ENABLE TRANSMITTER */
6166 usc_TCmd( info
, TCmd_SendFrame
);
6167 usc_EnableTransmitter(info
,ENABLE_UNCONDITIONAL
);
6169 /* WAIT FOR RECEIVE COMPLETE */
6170 for (i
=0 ; i
<1000 ; i
++)
6171 if (usc_InReg( info
, RCSR
) & (BIT8
+ BIT4
+ BIT3
+ BIT1
))
6174 /* clear Internal Data loopback mode */
6175 usc_enable_loopback(info
, 0);
6177 usc_EnableMasterIrqBit(info
);
6179 info
->params
.mode
= oldmode
;
6181 } /* end of usc_loopback_frame() */
6183 /* usc_set_sync_mode() Programs the USC for SDLC communications.
6185 * Arguments: info pointer to adapter info structure
6186 * Return Value: None
6188 static void usc_set_sync_mode( struct mgsl_struct
*info
)
6190 usc_loopback_frame( info
);
6191 usc_set_sdlc_mode( info
);
6193 if (info
->bus_type
== MGSL_BUS_TYPE_ISA
) {
6194 /* Enable INTEN (Port 6, Bit12) */
6195 /* This connects the IRQ request signal to the ISA bus */
6196 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
));
6199 usc_enable_aux_clock(info
, info
->params
.clock_speed
);
6201 if (info
->params
.loopback
)
6202 usc_enable_loopback(info
,1);
6204 } /* end of mgsl_set_sync_mode() */
6206 /* usc_set_txidle() Set the HDLC idle mode for the transmitter.
6208 * Arguments: info pointer to device instance data
6209 * Return Value: None
6211 static void usc_set_txidle( struct mgsl_struct
*info
)
6213 u16 usc_idle_mode
= IDLEMODE_FLAGS
;
6215 /* Map API idle mode to USC register bits */
6217 switch( info
->idle_mode
){
6218 case HDLC_TXIDLE_FLAGS
: usc_idle_mode
= IDLEMODE_FLAGS
; break;
6219 case HDLC_TXIDLE_ALT_ZEROS_ONES
: usc_idle_mode
= IDLEMODE_ALT_ONE_ZERO
; break;
6220 case HDLC_TXIDLE_ZEROS
: usc_idle_mode
= IDLEMODE_ZERO
; break;
6221 case HDLC_TXIDLE_ONES
: usc_idle_mode
= IDLEMODE_ONE
; break;
6222 case HDLC_TXIDLE_ALT_MARK_SPACE
: usc_idle_mode
= IDLEMODE_ALT_MARK_SPACE
; break;
6223 case HDLC_TXIDLE_SPACE
: usc_idle_mode
= IDLEMODE_SPACE
; break;
6224 case HDLC_TXIDLE_MARK
: usc_idle_mode
= IDLEMODE_MARK
; break;
6227 info
->usc_idle_mode
= usc_idle_mode
;
6228 //usc_OutReg(info, TCSR, usc_idle_mode);
6229 info
->tcsr_value
&= ~IDLEMODE_MASK
; /* clear idle mode bits */
6230 info
->tcsr_value
+= usc_idle_mode
;
6231 usc_OutReg(info
, TCSR
, info
->tcsr_value
);
6234 * if SyncLink WAN adapter is running in external sync mode, the
6235 * transmitter has been set to Monosync in order to try to mimic
6236 * a true raw outbound bit stream. Monosync still sends an open/close
6237 * sync char at the start/end of a frame. Try to match those sync
6238 * patterns to the idle mode set here
6240 if ( info
->params
.mode
== MGSL_MODE_RAW
) {
6241 unsigned char syncpat
= 0;
6242 switch( info
->idle_mode
) {
6243 case HDLC_TXIDLE_FLAGS
:
6246 case HDLC_TXIDLE_ALT_ZEROS_ONES
:
6249 case HDLC_TXIDLE_ZEROS
:
6250 case HDLC_TXIDLE_SPACE
:
6253 case HDLC_TXIDLE_ONES
:
6254 case HDLC_TXIDLE_MARK
:
6257 case HDLC_TXIDLE_ALT_MARK_SPACE
:
6262 usc_SetTransmitSyncChars(info
,syncpat
,syncpat
);
6265 } /* end of usc_set_txidle() */
6267 /* usc_get_serial_signals()
6269 * Query the adapter for the state of the V24 status (input) signals.
6271 * Arguments: info pointer to device instance data
6272 * Return Value: None
6274 static void usc_get_serial_signals( struct mgsl_struct
*info
)
6278 /* clear all serial signals except DTR and RTS */
6279 info
->serial_signals
&= SerialSignal_DTR
+ SerialSignal_RTS
;
6281 /* Read the Misc Interrupt status Register (MISR) to get */
6282 /* the V24 status signals. */
6284 status
= usc_InReg( info
, MISR
);
6286 /* set serial signal bits to reflect MISR */
6288 if ( status
& MISCSTATUS_CTS
)
6289 info
->serial_signals
|= SerialSignal_CTS
;
6291 if ( status
& MISCSTATUS_DCD
)
6292 info
->serial_signals
|= SerialSignal_DCD
;
6294 if ( status
& MISCSTATUS_RI
)
6295 info
->serial_signals
|= SerialSignal_RI
;
6297 if ( status
& MISCSTATUS_DSR
)
6298 info
->serial_signals
|= SerialSignal_DSR
;
6300 } /* end of usc_get_serial_signals() */
6302 /* usc_set_serial_signals()
6304 * Set the state of DTR and RTS based on contents of
6305 * serial_signals member of device extension.
6307 * Arguments: info pointer to device instance data
6308 * Return Value: None
6310 static void usc_set_serial_signals( struct mgsl_struct
*info
)
6313 unsigned char V24Out
= info
->serial_signals
;
6315 /* get the current value of the Port Control Register (PCR) */
6317 Control
= usc_InReg( info
, PCR
);
6319 if ( V24Out
& SerialSignal_RTS
)
6324 if ( V24Out
& SerialSignal_DTR
)
6329 usc_OutReg( info
, PCR
, Control
);
6331 } /* end of usc_set_serial_signals() */
6333 /* usc_enable_async_clock()
6335 * Enable the async clock at the specified frequency.
6337 * Arguments: info pointer to device instance data
6338 * data_rate data rate of clock in bps
6339 * 0 disables the AUX clock.
6340 * Return Value: None
6342 static void usc_enable_async_clock( struct mgsl_struct
*info
, u32 data_rate
)
6346 * Clock mode Control Register (CMCR)
6348 * <15..14> 00 counter 1 Disabled
6349 * <13..12> 00 counter 0 Disabled
6350 * <11..10> 11 BRG1 Input is TxC Pin
6351 * <9..8> 11 BRG0 Input is TxC Pin
6352 * <7..6> 01 DPLL Input is BRG1 Output
6353 * <5..3> 100 TxCLK comes from BRG0
6354 * <2..0> 100 RxCLK comes from BRG0
6356 * 0000 1111 0110 0100 = 0x0f64
6359 usc_OutReg( info
, CMCR
, 0x0f64 );
6363 * Write 16-bit Time Constant for BRG0
6364 * Time Constant = (ClkSpeed / data_rate) - 1
6365 * ClkSpeed = 921600 (ISA), 691200 (PCI)
6368 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
6369 usc_OutReg( info
, TC0R
, (u16
)((691200/data_rate
) - 1) );
6371 usc_OutReg( info
, TC0R
, (u16
)((921600/data_rate
) - 1) );
6375 * Hardware Configuration Register (HCR)
6376 * Clear Bit 1, BRG0 mode = Continuous
6377 * Set Bit 0 to enable BRG0.
6380 usc_OutReg( info
, HCR
,
6381 (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
6384 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
6386 usc_OutReg( info
, IOCR
,
6387 (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004) );
6389 /* data rate == 0 so turn off BRG0 */
6390 usc_OutReg( info
, HCR
, (u16
)(usc_InReg( info
, HCR
) & ~BIT0
) );
6393 } /* end of usc_enable_async_clock() */
6396 * Buffer Structures:
6398 * Normal memory access uses virtual addresses that can make discontiguous
6399 * physical memory pages appear to be contiguous in the virtual address
6400 * space (the processors memory mapping handles the conversions).
6402 * DMA transfers require physically contiguous memory. This is because
6403 * the DMA system controller and DMA bus masters deal with memory using
6404 * only physical addresses.
6406 * This causes a problem under Windows NT when large DMA buffers are
6407 * needed. Fragmentation of the nonpaged pool prevents allocations of
6408 * physically contiguous buffers larger than the PAGE_SIZE.
6410 * However the 16C32 supports Bus Master Scatter/Gather DMA which
6411 * allows DMA transfers to physically discontiguous buffers. Information
6412 * about each data transfer buffer is contained in a memory structure
6413 * called a 'buffer entry'. A list of buffer entries is maintained
6414 * to track and control the use of the data transfer buffers.
6416 * To support this strategy we will allocate sufficient PAGE_SIZE
6417 * contiguous memory buffers to allow for the total required buffer
6420 * The 16C32 accesses the list of buffer entries using Bus Master
6421 * DMA. Control information is read from the buffer entries by the
6422 * 16C32 to control data transfers. status information is written to
6423 * the buffer entries by the 16C32 to indicate the status of completed
6426 * The CPU writes control information to the buffer entries to control
6427 * the 16C32 and reads status information from the buffer entries to
6428 * determine information about received and transmitted frames.
6430 * Because the CPU and 16C32 (adapter) both need simultaneous access
6431 * to the buffer entries, the buffer entry memory is allocated with
6432 * HalAllocateCommonBuffer(). This restricts the size of the buffer
6433 * entry list to PAGE_SIZE.
6435 * The actual data buffers on the other hand will only be accessed
6436 * by the CPU or the adapter but not by both simultaneously. This allows
6437 * Scatter/Gather packet based DMA procedures for using physically
6438 * discontiguous pages.
6442 * mgsl_reset_tx_dma_buffers()
6444 * Set the count for all transmit buffers to 0 to indicate the
6445 * buffer is available for use and set the current buffer to the
6446 * first buffer. This effectively makes all buffers free and
6447 * discards any data in buffers.
6449 * Arguments: info pointer to device instance data
6450 * Return Value: None
6452 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct
*info
)
6456 for ( i
= 0; i
< info
->tx_buffer_count
; i
++ ) {
6457 *((unsigned long *)&(info
->tx_buffer_list
[i
].count
)) = 0;
6460 info
->current_tx_buffer
= 0;
6461 info
->start_tx_dma_buffer
= 0;
6462 info
->tx_dma_buffers_used
= 0;
6464 info
->get_tx_holding_index
= 0;
6465 info
->put_tx_holding_index
= 0;
6466 info
->tx_holding_count
= 0;
6468 } /* end of mgsl_reset_tx_dma_buffers() */
6471 * num_free_tx_dma_buffers()
6473 * returns the number of free tx dma buffers available
6475 * Arguments: info pointer to device instance data
6476 * Return Value: number of free tx dma buffers
6478 static int num_free_tx_dma_buffers(struct mgsl_struct
*info
)
6480 return info
->tx_buffer_count
- info
->tx_dma_buffers_used
;
6484 * mgsl_reset_rx_dma_buffers()
6486 * Set the count for all receive buffers to DMABUFFERSIZE
6487 * and set the current buffer to the first buffer. This effectively
6488 * makes all buffers free and discards any data in buffers.
6490 * Arguments: info pointer to device instance data
6491 * Return Value: None
6493 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct
*info
)
6497 for ( i
= 0; i
< info
->rx_buffer_count
; i
++ ) {
6498 *((unsigned long *)&(info
->rx_buffer_list
[i
].count
)) = DMABUFFERSIZE
;
6499 // info->rx_buffer_list[i].count = DMABUFFERSIZE;
6500 // info->rx_buffer_list[i].status = 0;
6503 info
->current_rx_buffer
= 0;
6505 } /* end of mgsl_reset_rx_dma_buffers() */
6508 * mgsl_free_rx_frame_buffers()
6510 * Free the receive buffers used by a received SDLC
6511 * frame such that the buffers can be reused.
6515 * info pointer to device instance data
6516 * StartIndex index of 1st receive buffer of frame
6517 * EndIndex index of last receive buffer of frame
6519 * Return Value: None
6521 static void mgsl_free_rx_frame_buffers( struct mgsl_struct
*info
, unsigned int StartIndex
, unsigned int EndIndex
)
6524 DMABUFFERENTRY
*pBufEntry
;
6527 /* Starting with 1st buffer entry of the frame clear the status */
6528 /* field and set the count field to DMA Buffer Size. */
6533 pBufEntry
= &(info
->rx_buffer_list
[Index
]);
6535 if ( Index
== EndIndex
) {
6536 /* This is the last buffer of the frame! */
6540 /* reset current buffer for reuse */
6541 // pBufEntry->status = 0;
6542 // pBufEntry->count = DMABUFFERSIZE;
6543 *((unsigned long *)&(pBufEntry
->count
)) = DMABUFFERSIZE
;
6545 /* advance to next buffer entry in linked list */
6547 if ( Index
== info
->rx_buffer_count
)
6551 /* set current buffer to next buffer after last buffer of frame */
6552 info
->current_rx_buffer
= Index
;
6554 } /* end of free_rx_frame_buffers() */
6556 /* mgsl_get_rx_frame()
6558 * This function attempts to return a received SDLC frame from the
6559 * receive DMA buffers. Only frames received without errors are returned.
6561 * Arguments: info pointer to device extension
6562 * Return Value: 1 if frame returned, otherwise 0
6564 static int mgsl_get_rx_frame(struct mgsl_struct
*info
)
6566 unsigned int StartIndex
, EndIndex
; /* index of 1st and last buffers of Rx frame */
6567 unsigned short status
;
6568 DMABUFFERENTRY
*pBufEntry
;
6569 unsigned int framesize
= 0;
6571 unsigned long flags
;
6572 struct tty_struct
*tty
= info
->tty
;
6573 int return_frame
= 0;
6576 * current_rx_buffer points to the 1st buffer of the next available
6577 * receive frame. To find the last buffer of the frame look for
6578 * a non-zero status field in the buffer entries. (The status
6579 * field is set by the 16C32 after completing a receive frame.
6582 StartIndex
= EndIndex
= info
->current_rx_buffer
;
6584 while( !info
->rx_buffer_list
[EndIndex
].status
) {
6586 * If the count field of the buffer entry is non-zero then
6587 * this buffer has not been used. (The 16C32 clears the count
6588 * field when it starts using the buffer.) If an unused buffer
6589 * is encountered then there are no frames available.
6592 if ( info
->rx_buffer_list
[EndIndex
].count
)
6595 /* advance to next buffer entry in linked list */
6597 if ( EndIndex
== info
->rx_buffer_count
)
6600 /* if entire list searched then no frame available */
6601 if ( EndIndex
== StartIndex
) {
6602 /* If this occurs then something bad happened,
6603 * all buffers have been 'used' but none mark
6604 * the end of a frame. Reset buffers and receiver.
6607 if ( info
->rx_enabled
){
6608 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6609 usc_start_receiver(info
);
6610 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6617 /* check status of receive frame */
6619 status
= info
->rx_buffer_list
[EndIndex
].status
;
6621 if ( status
& (RXSTATUS_SHORT_FRAME
+ RXSTATUS_OVERRUN
+
6622 RXSTATUS_CRC_ERROR
+ RXSTATUS_ABORT
) ) {
6623 if ( status
& RXSTATUS_SHORT_FRAME
)
6624 info
->icount
.rxshort
++;
6625 else if ( status
& RXSTATUS_ABORT
)
6626 info
->icount
.rxabort
++;
6627 else if ( status
& RXSTATUS_OVERRUN
)
6628 info
->icount
.rxover
++;
6630 info
->icount
.rxcrc
++;
6631 if ( info
->params
.crc_type
& HDLC_CRC_RETURN_EX
)
6635 #if SYNCLINK_GENERIC_HDLC
6637 struct net_device_stats
*stats
= hdlc_stats(info
->netdev
);
6639 stats
->rx_frame_errors
++;
6645 if ( return_frame
) {
6646 /* receive frame has no errors, get frame size.
6647 * The frame size is the starting value of the RCC (which was
6648 * set to 0xffff) minus the ending value of the RCC (decremented
6649 * once for each receive character) minus 2 for the 16-bit CRC.
6652 framesize
= RCLRVALUE
- info
->rx_buffer_list
[EndIndex
].rcc
;
6654 /* adjust frame size for CRC if any */
6655 if ( info
->params
.crc_type
== HDLC_CRC_16_CCITT
)
6657 else if ( info
->params
.crc_type
== HDLC_CRC_32_CCITT
)
6661 if ( debug_level
>= DEBUG_LEVEL_BH
)
6662 printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6663 __FILE__
,__LINE__
,info
->device_name
,status
,framesize
);
6665 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6666 mgsl_trace_block(info
,info
->rx_buffer_list
[StartIndex
].virt_addr
,
6667 min_t(int, framesize
, DMABUFFERSIZE
),0);
6670 if ( ( (info
->params
.crc_type
& HDLC_CRC_RETURN_EX
) &&
6671 ((framesize
+1) > info
->max_frame_size
) ) ||
6672 (framesize
> info
->max_frame_size
) )
6673 info
->icount
.rxlong
++;
6675 /* copy dma buffer(s) to contiguous intermediate buffer */
6676 int copy_count
= framesize
;
6677 int index
= StartIndex
;
6678 unsigned char *ptmp
= info
->intermediate_rxbuffer
;
6680 if ( !(status
& RXSTATUS_CRC_ERROR
))
6681 info
->icount
.rxok
++;
6685 if ( copy_count
> DMABUFFERSIZE
)
6686 partial_count
= DMABUFFERSIZE
;
6688 partial_count
= copy_count
;
6690 pBufEntry
= &(info
->rx_buffer_list
[index
]);
6691 memcpy( ptmp
, pBufEntry
->virt_addr
, partial_count
);
6692 ptmp
+= partial_count
;
6693 copy_count
-= partial_count
;
6695 if ( ++index
== info
->rx_buffer_count
)
6699 if ( info
->params
.crc_type
& HDLC_CRC_RETURN_EX
) {
6701 *ptmp
= (status
& RXSTATUS_CRC_ERROR
?
6705 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6706 printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
6707 __FILE__
,__LINE__
,info
->device_name
,
6711 #if SYNCLINK_GENERIC_HDLC
6713 hdlcdev_rx(info
,info
->intermediate_rxbuffer
,framesize
);
6716 ldisc_receive_buf(tty
, info
->intermediate_rxbuffer
, info
->flag_buf
, framesize
);
6719 /* Free the buffers used by this frame. */
6720 mgsl_free_rx_frame_buffers( info
, StartIndex
, EndIndex
);
6726 if ( info
->rx_enabled
&& info
->rx_overflow
) {
6727 /* The receiver needs to restarted because of
6728 * a receive overflow (buffer or FIFO). If the
6729 * receive buffers are now empty, then restart receiver.
6732 if ( !info
->rx_buffer_list
[EndIndex
].status
&&
6733 info
->rx_buffer_list
[EndIndex
].count
) {
6734 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6735 usc_start_receiver(info
);
6736 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6742 } /* end of mgsl_get_rx_frame() */
6744 /* mgsl_get_raw_rx_frame()
6746 * This function attempts to return a received frame from the
6747 * receive DMA buffers when running in external loop mode. In this mode,
6748 * we will return at most one DMABUFFERSIZE frame to the application.
6749 * The USC receiver is triggering off of DCD going active to start a new
6750 * frame, and DCD going inactive to terminate the frame (similar to
6751 * processing a closing flag character).
6753 * In this routine, we will return DMABUFFERSIZE "chunks" at a time.
6754 * If DCD goes inactive, the last Rx DMA Buffer will have a non-zero
6755 * status field and the RCC field will indicate the length of the
6756 * entire received frame. We take this RCC field and get the modulus
6757 * of RCC and DMABUFFERSIZE to determine if number of bytes in the
6758 * last Rx DMA buffer and return that last portion of the frame.
6760 * Arguments: info pointer to device extension
6761 * Return Value: 1 if frame returned, otherwise 0
6763 static int mgsl_get_raw_rx_frame(struct mgsl_struct
*info
)
6765 unsigned int CurrentIndex
, NextIndex
;
6766 unsigned short status
;
6767 DMABUFFERENTRY
*pBufEntry
;
6768 unsigned int framesize
= 0;
6770 unsigned long flags
;
6771 struct tty_struct
*tty
= info
->tty
;
6774 * current_rx_buffer points to the 1st buffer of the next available
6775 * receive frame. The status field is set by the 16C32 after
6776 * completing a receive frame. If the status field of this buffer
6777 * is zero, either the USC is still filling this buffer or this
6778 * is one of a series of buffers making up a received frame.
6780 * If the count field of this buffer is zero, the USC is either
6781 * using this buffer or has used this buffer. Look at the count
6782 * field of the next buffer. If that next buffer's count is
6783 * non-zero, the USC is still actively using the current buffer.
6784 * Otherwise, if the next buffer's count field is zero, the
6785 * current buffer is complete and the USC is using the next
6788 CurrentIndex
= NextIndex
= info
->current_rx_buffer
;
6790 if ( NextIndex
== info
->rx_buffer_count
)
6793 if ( info
->rx_buffer_list
[CurrentIndex
].status
!= 0 ||
6794 (info
->rx_buffer_list
[CurrentIndex
].count
== 0 &&
6795 info
->rx_buffer_list
[NextIndex
].count
== 0)) {
6797 * Either the status field of this dma buffer is non-zero
6798 * (indicating the last buffer of a receive frame) or the next
6799 * buffer is marked as in use -- implying this buffer is complete
6800 * and an intermediate buffer for this received frame.
6803 status
= info
->rx_buffer_list
[CurrentIndex
].status
;
6805 if ( status
& (RXSTATUS_SHORT_FRAME
+ RXSTATUS_OVERRUN
+
6806 RXSTATUS_CRC_ERROR
+ RXSTATUS_ABORT
) ) {
6807 if ( status
& RXSTATUS_SHORT_FRAME
)
6808 info
->icount
.rxshort
++;
6809 else if ( status
& RXSTATUS_ABORT
)
6810 info
->icount
.rxabort
++;
6811 else if ( status
& RXSTATUS_OVERRUN
)
6812 info
->icount
.rxover
++;
6814 info
->icount
.rxcrc
++;
6818 * A receive frame is available, get frame size and status.
6820 * The frame size is the starting value of the RCC (which was
6821 * set to 0xffff) minus the ending value of the RCC (decremented
6822 * once for each receive character) minus 2 or 4 for the 16-bit
6825 * If the status field is zero, this is an intermediate buffer.
6828 * If the DMA Buffer Entry's Status field is non-zero, the
6829 * receive operation completed normally (ie: DCD dropped). The
6830 * RCC field is valid and holds the received frame size.
6831 * It is possible that the RCC field will be zero on a DMA buffer
6832 * entry with a non-zero status. This can occur if the total
6833 * frame size (number of bytes between the time DCD goes active
6834 * to the time DCD goes inactive) exceeds 65535 bytes. In this
6835 * case the 16C32 has underrun on the RCC count and appears to
6836 * stop updating this counter to let us know the actual received
6837 * frame size. If this happens (non-zero status and zero RCC),
6838 * simply return the entire RxDMA Buffer
6842 * In the event that the final RxDMA Buffer is
6843 * terminated with a non-zero status and the RCC
6844 * field is zero, we interpret this as the RCC
6845 * having underflowed (received frame > 65535 bytes).
6847 * Signal the event to the user by passing back
6848 * a status of RxStatus_CrcError returning the full
6849 * buffer and let the app figure out what data is
6852 if ( info
->rx_buffer_list
[CurrentIndex
].rcc
)
6853 framesize
= RCLRVALUE
- info
->rx_buffer_list
[CurrentIndex
].rcc
;
6855 framesize
= DMABUFFERSIZE
;
6858 framesize
= DMABUFFERSIZE
;
6861 if ( framesize
> DMABUFFERSIZE
) {
6863 * if running in raw sync mode, ISR handler for
6864 * End Of Buffer events terminates all buffers at 4K.
6865 * If this frame size is said to be >4K, get the
6866 * actual number of bytes of the frame in this buffer.
6868 framesize
= framesize
% DMABUFFERSIZE
;
6872 if ( debug_level
>= DEBUG_LEVEL_BH
)
6873 printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
6874 __FILE__
,__LINE__
,info
->device_name
,status
,framesize
);
6876 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6877 mgsl_trace_block(info
,info
->rx_buffer_list
[CurrentIndex
].virt_addr
,
6878 min_t(int, framesize
, DMABUFFERSIZE
),0);
6881 /* copy dma buffer(s) to contiguous intermediate buffer */
6882 /* NOTE: we never copy more than DMABUFFERSIZE bytes */
6884 pBufEntry
= &(info
->rx_buffer_list
[CurrentIndex
]);
6885 memcpy( info
->intermediate_rxbuffer
, pBufEntry
->virt_addr
, framesize
);
6886 info
->icount
.rxok
++;
6888 ldisc_receive_buf(tty
, info
->intermediate_rxbuffer
, info
->flag_buf
, framesize
);
6891 /* Free the buffers used by this frame. */
6892 mgsl_free_rx_frame_buffers( info
, CurrentIndex
, CurrentIndex
);
6898 if ( info
->rx_enabled
&& info
->rx_overflow
) {
6899 /* The receiver needs to restarted because of
6900 * a receive overflow (buffer or FIFO). If the
6901 * receive buffers are now empty, then restart receiver.
6904 if ( !info
->rx_buffer_list
[CurrentIndex
].status
&&
6905 info
->rx_buffer_list
[CurrentIndex
].count
) {
6906 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6907 usc_start_receiver(info
);
6908 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6914 } /* end of mgsl_get_raw_rx_frame() */
6916 /* mgsl_load_tx_dma_buffer()
6918 * Load the transmit DMA buffer with the specified data.
6922 * info pointer to device extension
6923 * Buffer pointer to buffer containing frame to load
6924 * BufferSize size in bytes of frame in Buffer
6926 * Return Value: None
6928 static void mgsl_load_tx_dma_buffer(struct mgsl_struct
*info
,
6929 const char *Buffer
, unsigned int BufferSize
)
6931 unsigned short Copycount
;
6933 DMABUFFERENTRY
*pBufEntry
;
6935 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6936 mgsl_trace_block(info
,Buffer
, min_t(int, BufferSize
, DMABUFFERSIZE
), 1);
6938 if (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) {
6939 /* set CMR:13 to start transmit when
6940 * next GoAhead (abort) is received
6942 info
->cmr_value
|= BIT13
;
6945 /* begin loading the frame in the next available tx dma
6946 * buffer, remember it's starting location for setting
6947 * up tx dma operation
6949 i
= info
->current_tx_buffer
;
6950 info
->start_tx_dma_buffer
= i
;
6952 /* Setup the status and RCC (Frame Size) fields of the 1st */
6953 /* buffer entry in the transmit DMA buffer list. */
6955 info
->tx_buffer_list
[i
].status
= info
->cmr_value
& 0xf000;
6956 info
->tx_buffer_list
[i
].rcc
= BufferSize
;
6957 info
->tx_buffer_list
[i
].count
= BufferSize
;
6959 /* Copy frame data from 1st source buffer to the DMA buffers. */
6960 /* The frame data may span multiple DMA buffers. */
6962 while( BufferSize
){
6963 /* Get a pointer to next DMA buffer entry. */
6964 pBufEntry
= &info
->tx_buffer_list
[i
++];
6966 if ( i
== info
->tx_buffer_count
)
6969 /* Calculate the number of bytes that can be copied from */
6970 /* the source buffer to this DMA buffer. */
6971 if ( BufferSize
> DMABUFFERSIZE
)
6972 Copycount
= DMABUFFERSIZE
;
6974 Copycount
= BufferSize
;
6976 /* Actually copy data from source buffer to DMA buffer. */
6977 /* Also set the data count for this individual DMA buffer. */
6978 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
6979 mgsl_load_pci_memory(pBufEntry
->virt_addr
, Buffer
,Copycount
);
6981 memcpy(pBufEntry
->virt_addr
, Buffer
, Copycount
);
6983 pBufEntry
->count
= Copycount
;
6985 /* Advance source pointer and reduce remaining data count. */
6986 Buffer
+= Copycount
;
6987 BufferSize
-= Copycount
;
6989 ++info
->tx_dma_buffers_used
;
6992 /* remember next available tx dma buffer */
6993 info
->current_tx_buffer
= i
;
6995 } /* end of mgsl_load_tx_dma_buffer() */
6998 * mgsl_register_test()
7000 * Performs a register test of the 16C32.
7002 * Arguments: info pointer to device instance data
7003 * Return Value: TRUE if test passed, otherwise FALSE
7005 static BOOLEAN
mgsl_register_test( struct mgsl_struct
*info
)
7007 static unsigned short BitPatterns
[] =
7008 { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
7009 static unsigned int Patterncount
= ARRAY_SIZE(BitPatterns
);
7012 unsigned long flags
;
7014 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7017 /* Verify the reset state of some registers. */
7019 if ( (usc_InReg( info
, SICR
) != 0) ||
7020 (usc_InReg( info
, IVR
) != 0) ||
7021 (usc_InDmaReg( info
, DIVR
) != 0) ){
7026 /* Write bit patterns to various registers but do it out of */
7027 /* sync, then read back and verify values. */
7029 for ( i
= 0 ; i
< Patterncount
; i
++ ) {
7030 usc_OutReg( info
, TC0R
, BitPatterns
[i
] );
7031 usc_OutReg( info
, TC1R
, BitPatterns
[(i
+1)%Patterncount
] );
7032 usc_OutReg( info
, TCLR
, BitPatterns
[(i
+2)%Patterncount
] );
7033 usc_OutReg( info
, RCLR
, BitPatterns
[(i
+3)%Patterncount
] );
7034 usc_OutReg( info
, RSR
, BitPatterns
[(i
+4)%Patterncount
] );
7035 usc_OutDmaReg( info
, TBCR
, BitPatterns
[(i
+5)%Patterncount
] );
7037 if ( (usc_InReg( info
, TC0R
) != BitPatterns
[i
]) ||
7038 (usc_InReg( info
, TC1R
) != BitPatterns
[(i
+1)%Patterncount
]) ||
7039 (usc_InReg( info
, TCLR
) != BitPatterns
[(i
+2)%Patterncount
]) ||
7040 (usc_InReg( info
, RCLR
) != BitPatterns
[(i
+3)%Patterncount
]) ||
7041 (usc_InReg( info
, RSR
) != BitPatterns
[(i
+4)%Patterncount
]) ||
7042 (usc_InDmaReg( info
, TBCR
) != BitPatterns
[(i
+5)%Patterncount
]) ){
7050 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7054 } /* end of mgsl_register_test() */
7056 /* mgsl_irq_test() Perform interrupt test of the 16C32.
7058 * Arguments: info pointer to device instance data
7059 * Return Value: TRUE if test passed, otherwise FALSE
7061 static BOOLEAN
mgsl_irq_test( struct mgsl_struct
*info
)
7063 unsigned long EndTime
;
7064 unsigned long flags
;
7066 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7070 * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition.
7071 * The ISR sets irq_occurred to 1.
7074 info
->irq_occurred
= FALSE
;
7076 /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
7077 /* Enable INTEN (Port 6, Bit12) */
7078 /* This connects the IRQ request signal to the ISA bus */
7079 /* on the ISA adapter. This has no effect for the PCI adapter */
7080 usc_OutReg( info
, PCR
, (unsigned short)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
) );
7082 usc_EnableMasterIrqBit(info
);
7083 usc_EnableInterrupts(info
, IO_PIN
);
7084 usc_ClearIrqPendingBits(info
, IO_PIN
);
7086 usc_UnlatchIostatusBits(info
, MISCSTATUS_TXC_LATCHED
);
7087 usc_EnableStatusIrqs(info
, SICR_TXC_ACTIVE
+ SICR_TXC_INACTIVE
);
7089 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7092 while( EndTime
-- && !info
->irq_occurred
) {
7093 msleep_interruptible(10);
7096 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7098 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7100 if ( !info
->irq_occurred
)
7105 } /* end of mgsl_irq_test() */
7109 * Perform a DMA test of the 16C32. A small frame is
7110 * transmitted via DMA from a transmit buffer to a receive buffer
7111 * using single buffer DMA mode.
7113 * Arguments: info pointer to device instance data
7114 * Return Value: TRUE if test passed, otherwise FALSE
7116 static BOOLEAN
mgsl_dma_test( struct mgsl_struct
*info
)
7118 unsigned short FifoLevel
;
7119 unsigned long phys_addr
;
7120 unsigned int FrameSize
;
7124 unsigned short status
=0;
7125 unsigned long EndTime
;
7126 unsigned long flags
;
7127 MGSL_PARAMS tmp_params
;
7129 /* save current port options */
7130 memcpy(&tmp_params
,&info
->params
,sizeof(MGSL_PARAMS
));
7131 /* load default port options */
7132 memcpy(&info
->params
,&default_params
,sizeof(MGSL_PARAMS
));
7134 #define TESTFRAMESIZE 40
7136 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7138 /* setup 16C32 for SDLC DMA transfer mode */
7141 usc_set_sdlc_mode(info
);
7142 usc_enable_loopback(info
,1);
7144 /* Reprogram the RDMR so that the 16C32 does NOT clear the count
7145 * field of the buffer entry after fetching buffer address. This
7146 * way we can detect a DMA failure for a DMA read (which should be
7147 * non-destructive to system memory) before we try and write to
7148 * memory (where a failure could corrupt system memory).
7151 /* Receive DMA mode Register (RDMR)
7153 * <15..14> 11 DMA mode = Linked List Buffer mode
7154 * <13> 1 RSBinA/L = store Rx status Block in List entry
7155 * <12> 0 1 = Clear count of List Entry after fetching
7156 * <11..10> 00 Address mode = Increment
7157 * <9> 1 Terminate Buffer on RxBound
7158 * <8> 0 Bus Width = 16bits
7159 * <7..0> ? status Bits (write as 0s)
7161 * 1110 0010 0000 0000 = 0xe200
7164 usc_OutDmaReg( info
, RDMR
, 0xe200 );
7166 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7169 /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
7171 FrameSize
= TESTFRAMESIZE
;
7173 /* setup 1st transmit buffer entry: */
7174 /* with frame size and transmit control word */
7176 info
->tx_buffer_list
[0].count
= FrameSize
;
7177 info
->tx_buffer_list
[0].rcc
= FrameSize
;
7178 info
->tx_buffer_list
[0].status
= 0x4000;
7180 /* build a transmit frame in 1st transmit DMA buffer */
7182 TmpPtr
= info
->tx_buffer_list
[0].virt_addr
;
7183 for (i
= 0; i
< FrameSize
; i
++ )
7186 /* setup 1st receive buffer entry: */
7187 /* clear status, set max receive buffer size */
7189 info
->rx_buffer_list
[0].status
= 0;
7190 info
->rx_buffer_list
[0].count
= FrameSize
+ 4;
7192 /* zero out the 1st receive buffer */
7194 memset( info
->rx_buffer_list
[0].virt_addr
, 0, FrameSize
+ 4 );
7196 /* Set count field of next buffer entries to prevent */
7197 /* 16C32 from using buffers after the 1st one. */
7199 info
->tx_buffer_list
[1].count
= 0;
7200 info
->rx_buffer_list
[1].count
= 0;
7203 /***************************/
7204 /* Program 16C32 receiver. */
7205 /***************************/
7207 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7209 /* setup DMA transfers */
7210 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
7212 /* program 16C32 receiver with physical address of 1st DMA buffer entry */
7213 phys_addr
= info
->rx_buffer_list
[0].phys_entry
;
7214 usc_OutDmaReg( info
, NRARL
, (unsigned short)phys_addr
);
7215 usc_OutDmaReg( info
, NRARU
, (unsigned short)(phys_addr
>> 16) );
7217 /* Clear the Rx DMA status bits (read RDMR) and start channel */
7218 usc_InDmaReg( info
, RDMR
);
7219 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
7221 /* Enable Receiver (RMR <1..0> = 10) */
7222 usc_OutReg( info
, RMR
, (unsigned short)((usc_InReg(info
, RMR
) & 0xfffc) | 0x0002) );
7224 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7227 /*************************************************************/
7228 /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
7229 /*************************************************************/
7231 /* Wait 100ms for interrupt. */
7232 EndTime
= jiffies
+ msecs_to_jiffies(100);
7235 if (time_after(jiffies
, EndTime
)) {
7240 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7241 status
= usc_InDmaReg( info
, RDMR
);
7242 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7244 if ( !(status
& BIT4
) && (status
& BIT5
) ) {
7245 /* INITG (BIT 4) is inactive (no entry read in progress) AND */
7246 /* BUSY (BIT 5) is active (channel still active). */
7247 /* This means the buffer entry read has completed. */
7253 /******************************/
7254 /* Program 16C32 transmitter. */
7255 /******************************/
7257 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7259 /* Program the Transmit Character Length Register (TCLR) */
7260 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
7262 usc_OutReg( info
, TCLR
, (unsigned short)info
->tx_buffer_list
[0].count
);
7263 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
7265 /* Program the address of the 1st DMA Buffer Entry in linked list */
7267 phys_addr
= info
->tx_buffer_list
[0].phys_entry
;
7268 usc_OutDmaReg( info
, NTARL
, (unsigned short)phys_addr
);
7269 usc_OutDmaReg( info
, NTARU
, (unsigned short)(phys_addr
>> 16) );
7271 /* unlatch Tx status bits, and start transmit channel. */
7273 usc_OutReg( info
, TCSR
, (unsigned short)(( usc_InReg(info
, TCSR
) & 0x0f00) | 0xfa) );
7274 usc_DmaCmd( info
, DmaCmd_InitTxChannel
);
7276 /* wait for DMA controller to fill transmit FIFO */
7278 usc_TCmd( info
, TCmd_SelectTicrTxFifostatus
);
7280 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7283 /**********************************/
7284 /* WAIT FOR TRANSMIT FIFO TO FILL */
7285 /**********************************/
7288 EndTime
= jiffies
+ msecs_to_jiffies(100);
7291 if (time_after(jiffies
, EndTime
)) {
7296 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7297 FifoLevel
= usc_InReg(info
, TICR
) >> 8;
7298 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7300 if ( FifoLevel
< 16 )
7303 if ( FrameSize
< 32 ) {
7304 /* This frame is smaller than the entire transmit FIFO */
7305 /* so wait for the entire frame to be loaded. */
7306 if ( FifoLevel
<= (32 - FrameSize
) )
7314 /* Enable 16C32 transmitter. */
7316 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7318 /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
7319 usc_TCmd( info
, TCmd_SendFrame
);
7320 usc_OutReg( info
, TMR
, (unsigned short)((usc_InReg(info
, TMR
) & 0xfffc) | 0x0002) );
7322 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7325 /******************************/
7326 /* WAIT FOR TRANSMIT COMPLETE */
7327 /******************************/
7330 EndTime
= jiffies
+ msecs_to_jiffies(100);
7332 /* While timer not expired wait for transmit complete */
7334 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7335 status
= usc_InReg( info
, TCSR
);
7336 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7338 while ( !(status
& (BIT6
+BIT5
+BIT4
+BIT2
+BIT1
)) ) {
7339 if (time_after(jiffies
, EndTime
)) {
7344 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7345 status
= usc_InReg( info
, TCSR
);
7346 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7352 /* CHECK FOR TRANSMIT ERRORS */
7353 if ( status
& (BIT5
+ BIT1
) )
7358 /* WAIT FOR RECEIVE COMPLETE */
7361 EndTime
= jiffies
+ msecs_to_jiffies(100);
7363 /* Wait for 16C32 to write receive status to buffer entry. */
7364 status
=info
->rx_buffer_list
[0].status
;
7365 while ( status
== 0 ) {
7366 if (time_after(jiffies
, EndTime
)) {
7370 status
=info
->rx_buffer_list
[0].status
;
7376 /* CHECK FOR RECEIVE ERRORS */
7377 status
= info
->rx_buffer_list
[0].status
;
7379 if ( status
& (BIT8
+ BIT3
+ BIT1
) ) {
7380 /* receive error has occurred */
7383 if ( memcmp( info
->tx_buffer_list
[0].virt_addr
,
7384 info
->rx_buffer_list
[0].virt_addr
, FrameSize
) ){
7390 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7392 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7394 /* restore current port options */
7395 memcpy(&info
->params
,&tmp_params
,sizeof(MGSL_PARAMS
));
7399 } /* end of mgsl_dma_test() */
7401 /* mgsl_adapter_test()
7403 * Perform the register, IRQ, and DMA tests for the 16C32.
7405 * Arguments: info pointer to device instance data
7406 * Return Value: 0 if success, otherwise -ENODEV
7408 static int mgsl_adapter_test( struct mgsl_struct
*info
)
7410 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7411 printk( "%s(%d):Testing device %s\n",
7412 __FILE__
,__LINE__
,info
->device_name
);
7414 if ( !mgsl_register_test( info
) ) {
7415 info
->init_error
= DiagStatus_AddressFailure
;
7416 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7417 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->io_base
) );
7421 if ( !mgsl_irq_test( info
) ) {
7422 info
->init_error
= DiagStatus_IrqFailure
;
7423 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7424 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->irq_level
) );
7428 if ( !mgsl_dma_test( info
) ) {
7429 info
->init_error
= DiagStatus_DmaFailure
;
7430 printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7431 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->dma_level
) );
7435 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7436 printk( "%s(%d):device %s passed diagnostics\n",
7437 __FILE__
,__LINE__
,info
->device_name
);
7441 } /* end of mgsl_adapter_test() */
7443 /* mgsl_memory_test()
7445 * Test the shared memory on a PCI adapter.
7447 * Arguments: info pointer to device instance data
7448 * Return Value: TRUE if test passed, otherwise FALSE
7450 static BOOLEAN
mgsl_memory_test( struct mgsl_struct
*info
)
7452 static unsigned long BitPatterns
[] =
7453 { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7454 unsigned long Patterncount
= ARRAY_SIZE(BitPatterns
);
7456 unsigned long TestLimit
= SHARED_MEM_ADDRESS_SIZE
/sizeof(unsigned long);
7457 unsigned long * TestAddr
;
7459 if ( info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
7462 TestAddr
= (unsigned long *)info
->memory_base
;
7464 /* Test data lines with test pattern at one location. */
7466 for ( i
= 0 ; i
< Patterncount
; i
++ ) {
7467 *TestAddr
= BitPatterns
[i
];
7468 if ( *TestAddr
!= BitPatterns
[i
] )
7472 /* Test address lines with incrementing pattern over */
7473 /* entire address range. */
7475 for ( i
= 0 ; i
< TestLimit
; i
++ ) {
7480 TestAddr
= (unsigned long *)info
->memory_base
;
7482 for ( i
= 0 ; i
< TestLimit
; i
++ ) {
7483 if ( *TestAddr
!= i
* 4 )
7488 memset( info
->memory_base
, 0, SHARED_MEM_ADDRESS_SIZE
);
7492 } /* End Of mgsl_memory_test() */
7495 /* mgsl_load_pci_memory()
7497 * Load a large block of data into the PCI shared memory.
7498 * Use this instead of memcpy() or memmove() to move data
7499 * into the PCI shared memory.
7503 * This function prevents the PCI9050 interface chip from hogging
7504 * the adapter local bus, which can starve the 16C32 by preventing
7505 * 16C32 bus master cycles.
7507 * The PCI9050 documentation says that the 9050 will always release
7508 * control of the local bus after completing the current read
7509 * or write operation.
7511 * It appears that as long as the PCI9050 write FIFO is full, the
7512 * PCI9050 treats all of the writes as a single burst transaction
7513 * and will not release the bus. This causes DMA latency problems
7514 * at high speeds when copying large data blocks to the shared
7517 * This function in effect, breaks the a large shared memory write
7518 * into multiple transations by interleaving a shared memory read
7519 * which will flush the write FIFO and 'complete' the write
7520 * transation. This allows any pending DMA request to gain control
7521 * of the local bus in a timely fasion.
7525 * TargetPtr pointer to target address in PCI shared memory
7526 * SourcePtr pointer to source buffer for data
7527 * count count in bytes of data to copy
7529 * Return Value: None
7531 static void mgsl_load_pci_memory( char* TargetPtr
, const char* SourcePtr
,
7532 unsigned short count
)
7534 /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */
7535 #define PCI_LOAD_INTERVAL 64
7537 unsigned short Intervalcount
= count
/ PCI_LOAD_INTERVAL
;
7538 unsigned short Index
;
7539 unsigned long Dummy
;
7541 for ( Index
= 0 ; Index
< Intervalcount
; Index
++ )
7543 memcpy(TargetPtr
, SourcePtr
, PCI_LOAD_INTERVAL
);
7544 Dummy
= *((volatile unsigned long *)TargetPtr
);
7545 TargetPtr
+= PCI_LOAD_INTERVAL
;
7546 SourcePtr
+= PCI_LOAD_INTERVAL
;
7549 memcpy( TargetPtr
, SourcePtr
, count
% PCI_LOAD_INTERVAL
);
7551 } /* End Of mgsl_load_pci_memory() */
7553 static void mgsl_trace_block(struct mgsl_struct
*info
,const char* data
, int count
, int xmit
)
7558 printk("%s tx data:\n",info
->device_name
);
7560 printk("%s rx data:\n",info
->device_name
);
7568 for(i
=0;i
<linecount
;i
++)
7569 printk("%02X ",(unsigned char)data
[i
]);
7572 for(i
=0;i
<linecount
;i
++) {
7573 if (data
[i
]>=040 && data
[i
]<=0176)
7574 printk("%c",data
[i
]);
7583 } /* end of mgsl_trace_block() */
7585 /* mgsl_tx_timeout()
7587 * called when HDLC frame times out
7588 * update stats and do tx completion processing
7590 * Arguments: context pointer to device instance data
7591 * Return Value: None
7593 static void mgsl_tx_timeout(unsigned long context
)
7595 struct mgsl_struct
*info
= (struct mgsl_struct
*)context
;
7596 unsigned long flags
;
7598 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7599 printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7600 __FILE__
,__LINE__
,info
->device_name
);
7601 if(info
->tx_active
&&
7602 (info
->params
.mode
== MGSL_MODE_HDLC
||
7603 info
->params
.mode
== MGSL_MODE_RAW
) ) {
7604 info
->icount
.txtimeout
++;
7606 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7607 info
->tx_active
= 0;
7608 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
7610 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
7611 usc_loopmode_cancel_transmit( info
);
7613 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7615 #if SYNCLINK_GENERIC_HDLC
7617 hdlcdev_tx_done(info
);
7620 mgsl_bh_transmit(info
);
7622 } /* end of mgsl_tx_timeout() */
7624 /* signal that there are no more frames to send, so that
7625 * line is 'released' by echoing RxD to TxD when current
7626 * transmission is complete (or immediately if no tx in progress).
7628 static int mgsl_loopmode_send_done( struct mgsl_struct
* info
)
7630 unsigned long flags
;
7632 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7633 if (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) {
7634 if (info
->tx_active
)
7635 info
->loopmode_send_done_requested
= TRUE
;
7637 usc_loopmode_send_done(info
);
7639 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7644 /* release the line by echoing RxD to TxD
7645 * upon completion of a transmit frame
7647 static void usc_loopmode_send_done( struct mgsl_struct
* info
)
7649 info
->loopmode_send_done_requested
= FALSE
;
7650 /* clear CMR:13 to 0 to start echoing RxData to TxData */
7651 info
->cmr_value
&= ~BIT13
;
7652 usc_OutReg(info
, CMR
, info
->cmr_value
);
7655 /* abort a transmit in progress while in HDLC LoopMode
7657 static void usc_loopmode_cancel_transmit( struct mgsl_struct
* info
)
7659 /* reset tx dma channel and purge TxFifo */
7660 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
7661 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
7662 usc_loopmode_send_done( info
);
7665 /* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
7666 * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
7667 * we must clear CMR:13 to begin repeating TxData to RxData
7669 static void usc_loopmode_insert_request( struct mgsl_struct
* info
)
7671 info
->loopmode_insert_requested
= TRUE
;
7673 /* enable RxAbort irq. On next RxAbort, clear CMR:13 to
7674 * begin repeating TxData on RxData (complete insertion)
7676 usc_OutReg( info
, RICR
,
7677 (usc_InReg( info
, RICR
) | RXSTATUS_ABORT_RECEIVED
) );
7679 /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
7680 info
->cmr_value
|= BIT13
;
7681 usc_OutReg(info
, CMR
, info
->cmr_value
);
7684 /* return 1 if station is inserted into the loop, otherwise 0
7686 static int usc_loopmode_active( struct mgsl_struct
* info
)
7688 return usc_InReg( info
, CCSR
) & BIT7
? 1 : 0 ;
7691 #if SYNCLINK_GENERIC_HDLC
7694 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
7695 * set encoding and frame check sequence (FCS) options
7697 * dev pointer to network device structure
7698 * encoding serial encoding setting
7699 * parity FCS setting
7701 * returns 0 if success, otherwise error code
7703 static int hdlcdev_attach(struct net_device
*dev
, unsigned short encoding
,
7704 unsigned short parity
)
7706 struct mgsl_struct
*info
= dev_to_port(dev
);
7707 unsigned char new_encoding
;
7708 unsigned short new_crctype
;
7710 /* return error if TTY interface open */
7716 case ENCODING_NRZ
: new_encoding
= HDLC_ENCODING_NRZ
; break;
7717 case ENCODING_NRZI
: new_encoding
= HDLC_ENCODING_NRZI_SPACE
; break;
7718 case ENCODING_FM_MARK
: new_encoding
= HDLC_ENCODING_BIPHASE_MARK
; break;
7719 case ENCODING_FM_SPACE
: new_encoding
= HDLC_ENCODING_BIPHASE_SPACE
; break;
7720 case ENCODING_MANCHESTER
: new_encoding
= HDLC_ENCODING_BIPHASE_LEVEL
; break;
7721 default: return -EINVAL
;
7726 case PARITY_NONE
: new_crctype
= HDLC_CRC_NONE
; break;
7727 case PARITY_CRC16_PR1_CCITT
: new_crctype
= HDLC_CRC_16_CCITT
; break;
7728 case PARITY_CRC32_PR1_CCITT
: new_crctype
= HDLC_CRC_32_CCITT
; break;
7729 default: return -EINVAL
;
7732 info
->params
.encoding
= new_encoding
;
7733 info
->params
.crc_type
= new_crctype
;
7735 /* if network interface up, reprogram hardware */
7737 mgsl_program_hw(info
);
7743 * called by generic HDLC layer to send frame
7745 * skb socket buffer containing HDLC frame
7746 * dev pointer to network device structure
7748 * returns 0 if success, otherwise error code
7750 static int hdlcdev_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
7752 struct mgsl_struct
*info
= dev_to_port(dev
);
7753 struct net_device_stats
*stats
= hdlc_stats(dev
);
7754 unsigned long flags
;
7756 if (debug_level
>= DEBUG_LEVEL_INFO
)
7757 printk(KERN_INFO
"%s:hdlc_xmit(%s)\n",__FILE__
,dev
->name
);
7759 /* stop sending until this frame completes */
7760 netif_stop_queue(dev
);
7762 /* copy data to device buffers */
7763 info
->xmit_cnt
= skb
->len
;
7764 mgsl_load_tx_dma_buffer(info
, skb
->data
, skb
->len
);
7766 /* update network statistics */
7767 stats
->tx_packets
++;
7768 stats
->tx_bytes
+= skb
->len
;
7770 /* done with socket buffer, so free it */
7773 /* save start time for transmit timeout detection */
7774 dev
->trans_start
= jiffies
;
7776 /* start hardware transmitter if necessary */
7777 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7778 if (!info
->tx_active
)
7779 usc_start_transmitter(info
);
7780 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7786 * called by network layer when interface enabled
7787 * claim resources and initialize hardware
7789 * dev pointer to network device structure
7791 * returns 0 if success, otherwise error code
7793 static int hdlcdev_open(struct net_device
*dev
)
7795 struct mgsl_struct
*info
= dev_to_port(dev
);
7797 unsigned long flags
;
7799 if (debug_level
>= DEBUG_LEVEL_INFO
)
7800 printk("%s:hdlcdev_open(%s)\n",__FILE__
,dev
->name
);
7802 /* generic HDLC layer open processing */
7803 if ((rc
= hdlc_open(dev
)))
7806 /* arbitrate between network and tty opens */
7807 spin_lock_irqsave(&info
->netlock
, flags
);
7808 if (info
->count
!= 0 || info
->netcount
!= 0) {
7809 printk(KERN_WARNING
"%s: hdlc_open returning busy\n", dev
->name
);
7810 spin_unlock_irqrestore(&info
->netlock
, flags
);
7814 spin_unlock_irqrestore(&info
->netlock
, flags
);
7816 /* claim resources and init adapter */
7817 if ((rc
= startup(info
)) != 0) {
7818 spin_lock_irqsave(&info
->netlock
, flags
);
7820 spin_unlock_irqrestore(&info
->netlock
, flags
);
7824 /* assert DTR and RTS, apply hardware settings */
7825 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
7826 mgsl_program_hw(info
);
7828 /* enable network layer transmit */
7829 dev
->trans_start
= jiffies
;
7830 netif_start_queue(dev
);
7832 /* inform generic HDLC layer of current DCD status */
7833 spin_lock_irqsave(&info
->irq_spinlock
, flags
);
7834 usc_get_serial_signals(info
);
7835 spin_unlock_irqrestore(&info
->irq_spinlock
, flags
);
7836 if (info
->serial_signals
& SerialSignal_DCD
)
7837 netif_carrier_on(dev
);
7839 netif_carrier_off(dev
);
7844 * called by network layer when interface is disabled
7845 * shutdown hardware and release resources
7847 * dev pointer to network device structure
7849 * returns 0 if success, otherwise error code
7851 static int hdlcdev_close(struct net_device
*dev
)
7853 struct mgsl_struct
*info
= dev_to_port(dev
);
7854 unsigned long flags
;
7856 if (debug_level
>= DEBUG_LEVEL_INFO
)
7857 printk("%s:hdlcdev_close(%s)\n",__FILE__
,dev
->name
);
7859 netif_stop_queue(dev
);
7861 /* shutdown adapter and release resources */
7866 spin_lock_irqsave(&info
->netlock
, flags
);
7868 spin_unlock_irqrestore(&info
->netlock
, flags
);
7874 * called by network layer to process IOCTL call to network device
7876 * dev pointer to network device structure
7877 * ifr pointer to network interface request structure
7878 * cmd IOCTL command code
7880 * returns 0 if success, otherwise error code
7882 static int hdlcdev_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
7884 const size_t size
= sizeof(sync_serial_settings
);
7885 sync_serial_settings new_line
;
7886 sync_serial_settings __user
*line
= ifr
->ifr_settings
.ifs_ifsu
.sync
;
7887 struct mgsl_struct
*info
= dev_to_port(dev
);
7890 if (debug_level
>= DEBUG_LEVEL_INFO
)
7891 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__
,dev
->name
);
7893 /* return error if TTY interface open */
7897 if (cmd
!= SIOCWANDEV
)
7898 return hdlc_ioctl(dev
, ifr
, cmd
);
7900 switch(ifr
->ifr_settings
.type
) {
7901 case IF_GET_IFACE
: /* return current sync_serial_settings */
7903 ifr
->ifr_settings
.type
= IF_IFACE_SYNC_SERIAL
;
7904 if (ifr
->ifr_settings
.size
< size
) {
7905 ifr
->ifr_settings
.size
= size
; /* data size wanted */
7909 flags
= info
->params
.flags
& (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
7910 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
7911 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
7912 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
7915 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
): new_line
.clock_type
= CLOCK_EXT
; break;
7916 case (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_INT
; break;
7917 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_TXINT
; break;
7918 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
): new_line
.clock_type
= CLOCK_TXFROMRX
; break;
7919 default: new_line
.clock_type
= CLOCK_DEFAULT
;
7922 new_line
.clock_rate
= info
->params
.clock_speed
;
7923 new_line
.loopback
= info
->params
.loopback
? 1:0;
7925 if (copy_to_user(line
, &new_line
, size
))
7929 case IF_IFACE_SYNC_SERIAL
: /* set sync_serial_settings */
7931 if(!capable(CAP_NET_ADMIN
))
7933 if (copy_from_user(&new_line
, line
, size
))
7936 switch (new_line
.clock_type
)
7938 case CLOCK_EXT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
; break;
7939 case CLOCK_TXFROMRX
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
; break;
7940 case CLOCK_INT
: flags
= HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
; break;
7941 case CLOCK_TXINT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
; break;
7942 case CLOCK_DEFAULT
: flags
= info
->params
.flags
&
7943 (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
7944 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
7945 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
7946 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
); break;
7947 default: return -EINVAL
;
7950 if (new_line
.loopback
!= 0 && new_line
.loopback
!= 1)
7953 info
->params
.flags
&= ~(HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
7954 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
7955 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
7956 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
7957 info
->params
.flags
|= flags
;
7959 info
->params
.loopback
= new_line
.loopback
;
7961 if (flags
& (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
))
7962 info
->params
.clock_speed
= new_line
.clock_rate
;
7964 info
->params
.clock_speed
= 0;
7966 /* if network interface up, reprogram hardware */
7968 mgsl_program_hw(info
);
7972 return hdlc_ioctl(dev
, ifr
, cmd
);
7977 * called by network layer when transmit timeout is detected
7979 * dev pointer to network device structure
7981 static void hdlcdev_tx_timeout(struct net_device
*dev
)
7983 struct mgsl_struct
*info
= dev_to_port(dev
);
7984 struct net_device_stats
*stats
= hdlc_stats(dev
);
7985 unsigned long flags
;
7987 if (debug_level
>= DEBUG_LEVEL_INFO
)
7988 printk("hdlcdev_tx_timeout(%s)\n",dev
->name
);
7991 stats
->tx_aborted_errors
++;
7993 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7994 usc_stop_transmitter(info
);
7995 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7997 netif_wake_queue(dev
);
8001 * called by device driver when transmit completes
8002 * reenable network layer transmit if stopped
8004 * info pointer to device instance information
8006 static void hdlcdev_tx_done(struct mgsl_struct
*info
)
8008 if (netif_queue_stopped(info
->netdev
))
8009 netif_wake_queue(info
->netdev
);
8013 * called by device driver when frame received
8014 * pass frame to network layer
8016 * info pointer to device instance information
8017 * buf pointer to buffer contianing frame data
8018 * size count of data bytes in buf
8020 static void hdlcdev_rx(struct mgsl_struct
*info
, char *buf
, int size
)
8022 struct sk_buff
*skb
= dev_alloc_skb(size
);
8023 struct net_device
*dev
= info
->netdev
;
8024 struct net_device_stats
*stats
= hdlc_stats(dev
);
8026 if (debug_level
>= DEBUG_LEVEL_INFO
)
8027 printk("hdlcdev_rx(%s)\n",dev
->name
);
8030 printk(KERN_NOTICE
"%s: can't alloc skb, dropping packet\n", dev
->name
);
8031 stats
->rx_dropped
++;
8035 memcpy(skb_put(skb
, size
),buf
,size
);
8037 skb
->protocol
= hdlc_type_trans(skb
, info
->netdev
);
8039 stats
->rx_packets
++;
8040 stats
->rx_bytes
+= size
;
8044 info
->netdev
->last_rx
= jiffies
;
8048 * called by device driver when adding device instance
8049 * do generic HDLC initialization
8051 * info pointer to device instance information
8053 * returns 0 if success, otherwise error code
8055 static int hdlcdev_init(struct mgsl_struct
*info
)
8058 struct net_device
*dev
;
8061 /* allocate and initialize network and HDLC layer objects */
8063 if (!(dev
= alloc_hdlcdev(info
))) {
8064 printk(KERN_ERR
"%s:hdlc device allocation failure\n",__FILE__
);
8068 /* for network layer reporting purposes only */
8069 dev
->base_addr
= info
->io_base
;
8070 dev
->irq
= info
->irq_level
;
8071 dev
->dma
= info
->dma_level
;
8073 /* network layer callbacks and settings */
8074 dev
->do_ioctl
= hdlcdev_ioctl
;
8075 dev
->open
= hdlcdev_open
;
8076 dev
->stop
= hdlcdev_close
;
8077 dev
->tx_timeout
= hdlcdev_tx_timeout
;
8078 dev
->watchdog_timeo
= 10*HZ
;
8079 dev
->tx_queue_len
= 50;
8081 /* generic HDLC layer callbacks and settings */
8082 hdlc
= dev_to_hdlc(dev
);
8083 hdlc
->attach
= hdlcdev_attach
;
8084 hdlc
->xmit
= hdlcdev_xmit
;
8086 /* register objects with HDLC layer */
8087 if ((rc
= register_hdlc_device(dev
))) {
8088 printk(KERN_WARNING
"%s:unable to register hdlc device\n",__FILE__
);
8098 * called by device driver when removing device instance
8099 * do generic HDLC cleanup
8101 * info pointer to device instance information
8103 static void hdlcdev_exit(struct mgsl_struct
*info
)
8105 unregister_hdlc_device(info
->netdev
);
8106 free_netdev(info
->netdev
);
8107 info
->netdev
= NULL
;
8110 #endif /* CONFIG_HDLC */
8113 static int __devinit
synclink_init_one (struct pci_dev
*dev
,
8114 const struct pci_device_id
*ent
)
8116 struct mgsl_struct
*info
;
8118 if (pci_enable_device(dev
)) {
8119 printk("error enabling pci device %p\n", dev
);
8123 if (!(info
= mgsl_allocate_device())) {
8124 printk("can't allocate device instance data.\n");
8128 /* Copy user configuration info to device instance data */
8130 info
->io_base
= pci_resource_start(dev
, 2);
8131 info
->irq_level
= dev
->irq
;
8132 info
->phys_memory_base
= pci_resource_start(dev
, 3);
8134 /* Because veremap only works on page boundaries we must map
8135 * a larger area than is actually implemented for the LCR
8136 * memory range. We map a full page starting at the page boundary.
8138 info
->phys_lcr_base
= pci_resource_start(dev
, 0);
8139 info
->lcr_offset
= info
->phys_lcr_base
& (PAGE_SIZE
-1);
8140 info
->phys_lcr_base
&= ~(PAGE_SIZE
-1);
8142 info
->bus_type
= MGSL_BUS_TYPE_PCI
;
8143 info
->io_addr_size
= 8;
8144 info
->irq_flags
= IRQF_SHARED
;
8146 if (dev
->device
== 0x0210) {
8147 /* Version 1 PCI9030 based universal PCI adapter */
8148 info
->misc_ctrl_value
= 0x007c4080;
8149 info
->hw_version
= 1;
8151 /* Version 0 PCI9050 based 5V PCI adapter
8152 * A PCI9050 bug prevents reading LCR registers if
8153 * LCR base address bit 7 is set. Maintain shadow
8154 * value so we can write to LCR misc control reg.
8156 info
->misc_ctrl_value
= 0x087e4546;
8157 info
->hw_version
= 0;
8160 mgsl_add_device(info
);
8165 static void __devexit
synclink_remove_one (struct pci_dev
*dev
)