usbfs: don't store bad pointers in registration
[linux-2.6/mini2440.git] / include / asm-x86 / apicdef.h
blob6b9008c787319d1040c9520c137a454f24afc06a
1 #ifndef _ASM_X86_APICDEF_H
2 #define _ASM_X86_APICDEF_H
4 /*
5 * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
7 * Alan Cox <Alan.Cox@linux.org>, 1995.
8 * Ingo Molnar <mingo@redhat.com>, 1999, 2000
9 */
11 #define APIC_DEFAULT_PHYS_BASE 0xfee00000
13 #define APIC_ID 0x20
15 #define APIC_LVR 0x30
16 #define APIC_LVR_MASK 0xFF00FF
17 #define GET_APIC_VERSION(x) ((x) & 0xFFu)
18 #define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu)
19 #ifdef CONFIG_X86_32
20 # define APIC_INTEGRATED(x) ((x) & 0xF0u)
21 #else
22 # define APIC_INTEGRATED(x) (1)
23 #endif
24 #define APIC_XAPIC(x) ((x) >= 0x14)
25 #define APIC_TASKPRI 0x80
26 #define APIC_TPRI_MASK 0xFFu
27 #define APIC_ARBPRI 0x90
28 #define APIC_ARBPRI_MASK 0xFFu
29 #define APIC_PROCPRI 0xA0
30 #define APIC_EOI 0xB0
31 #define APIC_EIO_ACK 0x0
32 #define APIC_RRR 0xC0
33 #define APIC_LDR 0xD0
34 #define APIC_LDR_MASK (0xFFu << 24)
35 #define GET_APIC_LOGICAL_ID(x) (((x) >> 24) & 0xFFu)
36 #define SET_APIC_LOGICAL_ID(x) (((x) << 24))
37 #define APIC_ALL_CPUS 0xFFu
38 #define APIC_DFR 0xE0
39 #define APIC_DFR_CLUSTER 0x0FFFFFFFul
40 #define APIC_DFR_FLAT 0xFFFFFFFFul
41 #define APIC_SPIV 0xF0
42 #define APIC_SPIV_FOCUS_DISABLED (1 << 9)
43 #define APIC_SPIV_APIC_ENABLED (1 << 8)
44 #define APIC_ISR 0x100
45 #define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */
46 #define APIC_TMR 0x180
47 #define APIC_IRR 0x200
48 #define APIC_ESR 0x280
49 #define APIC_ESR_SEND_CS 0x00001
50 #define APIC_ESR_RECV_CS 0x00002
51 #define APIC_ESR_SEND_ACC 0x00004
52 #define APIC_ESR_RECV_ACC 0x00008
53 #define APIC_ESR_SENDILL 0x00020
54 #define APIC_ESR_RECVILL 0x00040
55 #define APIC_ESR_ILLREGA 0x00080
56 #define APIC_ICR 0x300
57 #define APIC_DEST_SELF 0x40000
58 #define APIC_DEST_ALLINC 0x80000
59 #define APIC_DEST_ALLBUT 0xC0000
60 #define APIC_ICR_RR_MASK 0x30000
61 #define APIC_ICR_RR_INVALID 0x00000
62 #define APIC_ICR_RR_INPROG 0x10000
63 #define APIC_ICR_RR_VALID 0x20000
64 #define APIC_INT_LEVELTRIG 0x08000
65 #define APIC_INT_ASSERT 0x04000
66 #define APIC_ICR_BUSY 0x01000
67 #define APIC_DEST_LOGICAL 0x00800
68 #define APIC_DEST_PHYSICAL 0x00000
69 #define APIC_DM_FIXED 0x00000
70 #define APIC_DM_LOWEST 0x00100
71 #define APIC_DM_SMI 0x00200
72 #define APIC_DM_REMRD 0x00300
73 #define APIC_DM_NMI 0x00400
74 #define APIC_DM_INIT 0x00500
75 #define APIC_DM_STARTUP 0x00600
76 #define APIC_DM_EXTINT 0x00700
77 #define APIC_VECTOR_MASK 0x000FF
78 #define APIC_ICR2 0x310
79 #define GET_APIC_DEST_FIELD(x) (((x) >> 24) & 0xFF)
80 #define SET_APIC_DEST_FIELD(x) ((x) << 24)
81 #define APIC_LVTT 0x320
82 #define APIC_LVTTHMR 0x330
83 #define APIC_LVTPC 0x340
84 #define APIC_LVT0 0x350
85 #define APIC_LVT_TIMER_BASE_MASK (0x3 << 18)
86 #define GET_APIC_TIMER_BASE(x) (((x) >> 18) & 0x3)
87 #define SET_APIC_TIMER_BASE(x) (((x) << 18))
88 #define APIC_TIMER_BASE_CLKIN 0x0
89 #define APIC_TIMER_BASE_TMBASE 0x1
90 #define APIC_TIMER_BASE_DIV 0x2
91 #define APIC_LVT_TIMER_PERIODIC (1 << 17)
92 #define APIC_LVT_MASKED (1 << 16)
93 #define APIC_LVT_LEVEL_TRIGGER (1 << 15)
94 #define APIC_LVT_REMOTE_IRR (1 << 14)
95 #define APIC_INPUT_POLARITY (1 << 13)
96 #define APIC_SEND_PENDING (1 << 12)
97 #define APIC_MODE_MASK 0x700
98 #define GET_APIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7)
99 #define SET_APIC_DELIVERY_MODE(x, y) (((x) & ~0x700) | ((y) << 8))
100 #define APIC_MODE_FIXED 0x0
101 #define APIC_MODE_NMI 0x4
102 #define APIC_MODE_EXTINT 0x7
103 #define APIC_LVT1 0x360
104 #define APIC_LVTERR 0x370
105 #define APIC_TMICT 0x380
106 #define APIC_TMCCT 0x390
107 #define APIC_TDCR 0x3E0
108 #define APIC_TDR_DIV_TMBASE (1 << 2)
109 #define APIC_TDR_DIV_1 0xB
110 #define APIC_TDR_DIV_2 0x0
111 #define APIC_TDR_DIV_4 0x1
112 #define APIC_TDR_DIV_8 0x2
113 #define APIC_TDR_DIV_16 0x3
114 #define APIC_TDR_DIV_32 0x8
115 #define APIC_TDR_DIV_64 0x9
116 #define APIC_TDR_DIV_128 0xA
117 #define APIC_EILVT0 0x500
118 #define APIC_EILVT_NR_AMD_K8 1 /* # of extended interrupts */
119 #define APIC_EILVT_NR_AMD_10H 4
120 #define APIC_EILVT_LVTOFF(x) (((x) >> 4) & 0xF)
121 #define APIC_EILVT_MSG_FIX 0x0
122 #define APIC_EILVT_MSG_SMI 0x2
123 #define APIC_EILVT_MSG_NMI 0x4
124 #define APIC_EILVT_MSG_EXT 0x7
125 #define APIC_EILVT_MASKED (1 << 16)
126 #define APIC_EILVT1 0x510
127 #define APIC_EILVT2 0x520
128 #define APIC_EILVT3 0x530
130 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
132 #ifdef CONFIG_X86_32
133 # define MAX_IO_APICS 64
134 #else
135 # define MAX_IO_APICS 128
136 # define MAX_LOCAL_APIC 32768
137 #endif
140 * All x86-64 systems are xAPIC compatible.
141 * In the following, "apicid" is a physical APIC ID.
143 #define XAPIC_DEST_CPUS_SHIFT 4
144 #define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
145 #define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
146 #define APIC_CLUSTER(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK)
147 #define APIC_CLUSTERID(apicid) (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT)
148 #define APIC_CPUID(apicid) ((apicid) & XAPIC_DEST_CPUS_MASK)
149 #define NUM_APIC_CLUSTERS ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT)
152 * the local APIC register structure, memory mapped. Not terribly well
153 * tested, but we might eventually use this one in the future - the
154 * problem why we cannot use it right now is the P5 APIC, it has an
155 * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
157 #define u32 unsigned int
159 struct local_apic {
161 /*000*/ struct { u32 __reserved[4]; } __reserved_01;
163 /*010*/ struct { u32 __reserved[4]; } __reserved_02;
165 /*020*/ struct { /* APIC ID Register */
166 u32 __reserved_1 : 24,
167 phys_apic_id : 4,
168 __reserved_2 : 4;
169 u32 __reserved[3];
170 } id;
172 /*030*/ const
173 struct { /* APIC Version Register */
174 u32 version : 8,
175 __reserved_1 : 8,
176 max_lvt : 8,
177 __reserved_2 : 8;
178 u32 __reserved[3];
179 } version;
181 /*040*/ struct { u32 __reserved[4]; } __reserved_03;
183 /*050*/ struct { u32 __reserved[4]; } __reserved_04;
185 /*060*/ struct { u32 __reserved[4]; } __reserved_05;
187 /*070*/ struct { u32 __reserved[4]; } __reserved_06;
189 /*080*/ struct { /* Task Priority Register */
190 u32 priority : 8,
191 __reserved_1 : 24;
192 u32 __reserved_2[3];
193 } tpr;
195 /*090*/ const
196 struct { /* Arbitration Priority Register */
197 u32 priority : 8,
198 __reserved_1 : 24;
199 u32 __reserved_2[3];
200 } apr;
202 /*0A0*/ const
203 struct { /* Processor Priority Register */
204 u32 priority : 8,
205 __reserved_1 : 24;
206 u32 __reserved_2[3];
207 } ppr;
209 /*0B0*/ struct { /* End Of Interrupt Register */
210 u32 eoi;
211 u32 __reserved[3];
212 } eoi;
214 /*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
216 /*0D0*/ struct { /* Logical Destination Register */
217 u32 __reserved_1 : 24,
218 logical_dest : 8;
219 u32 __reserved_2[3];
220 } ldr;
222 /*0E0*/ struct { /* Destination Format Register */
223 u32 __reserved_1 : 28,
224 model : 4;
225 u32 __reserved_2[3];
226 } dfr;
228 /*0F0*/ struct { /* Spurious Interrupt Vector Register */
229 u32 spurious_vector : 8,
230 apic_enabled : 1,
231 focus_cpu : 1,
232 __reserved_2 : 22;
233 u32 __reserved_3[3];
234 } svr;
236 /*100*/ struct { /* In Service Register */
237 /*170*/ u32 bitfield;
238 u32 __reserved[3];
239 } isr [8];
241 /*180*/ struct { /* Trigger Mode Register */
242 /*1F0*/ u32 bitfield;
243 u32 __reserved[3];
244 } tmr [8];
246 /*200*/ struct { /* Interrupt Request Register */
247 /*270*/ u32 bitfield;
248 u32 __reserved[3];
249 } irr [8];
251 /*280*/ union { /* Error Status Register */
252 struct {
253 u32 send_cs_error : 1,
254 receive_cs_error : 1,
255 send_accept_error : 1,
256 receive_accept_error : 1,
257 __reserved_1 : 1,
258 send_illegal_vector : 1,
259 receive_illegal_vector : 1,
260 illegal_register_address : 1,
261 __reserved_2 : 24;
262 u32 __reserved_3[3];
263 } error_bits;
264 struct {
265 u32 errors;
266 u32 __reserved_3[3];
267 } all_errors;
268 } esr;
270 /*290*/ struct { u32 __reserved[4]; } __reserved_08;
272 /*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
274 /*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
276 /*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
278 /*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
280 /*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
282 /*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
284 /*300*/ struct { /* Interrupt Command Register 1 */
285 u32 vector : 8,
286 delivery_mode : 3,
287 destination_mode : 1,
288 delivery_status : 1,
289 __reserved_1 : 1,
290 level : 1,
291 trigger : 1,
292 __reserved_2 : 2,
293 shorthand : 2,
294 __reserved_3 : 12;
295 u32 __reserved_4[3];
296 } icr1;
298 /*310*/ struct { /* Interrupt Command Register 2 */
299 union {
300 u32 __reserved_1 : 24,
301 phys_dest : 4,
302 __reserved_2 : 4;
303 u32 __reserved_3 : 24,
304 logical_dest : 8;
305 } dest;
306 u32 __reserved_4[3];
307 } icr2;
309 /*320*/ struct { /* LVT - Timer */
310 u32 vector : 8,
311 __reserved_1 : 4,
312 delivery_status : 1,
313 __reserved_2 : 3,
314 mask : 1,
315 timer_mode : 1,
316 __reserved_3 : 14;
317 u32 __reserved_4[3];
318 } lvt_timer;
320 /*330*/ struct { /* LVT - Thermal Sensor */
321 u32 vector : 8,
322 delivery_mode : 3,
323 __reserved_1 : 1,
324 delivery_status : 1,
325 __reserved_2 : 3,
326 mask : 1,
327 __reserved_3 : 15;
328 u32 __reserved_4[3];
329 } lvt_thermal;
331 /*340*/ struct { /* LVT - Performance Counter */
332 u32 vector : 8,
333 delivery_mode : 3,
334 __reserved_1 : 1,
335 delivery_status : 1,
336 __reserved_2 : 3,
337 mask : 1,
338 __reserved_3 : 15;
339 u32 __reserved_4[3];
340 } lvt_pc;
342 /*350*/ struct { /* LVT - LINT0 */
343 u32 vector : 8,
344 delivery_mode : 3,
345 __reserved_1 : 1,
346 delivery_status : 1,
347 polarity : 1,
348 remote_irr : 1,
349 trigger : 1,
350 mask : 1,
351 __reserved_2 : 15;
352 u32 __reserved_3[3];
353 } lvt_lint0;
355 /*360*/ struct { /* LVT - LINT1 */
356 u32 vector : 8,
357 delivery_mode : 3,
358 __reserved_1 : 1,
359 delivery_status : 1,
360 polarity : 1,
361 remote_irr : 1,
362 trigger : 1,
363 mask : 1,
364 __reserved_2 : 15;
365 u32 __reserved_3[3];
366 } lvt_lint1;
368 /*370*/ struct { /* LVT - Error */
369 u32 vector : 8,
370 __reserved_1 : 4,
371 delivery_status : 1,
372 __reserved_2 : 3,
373 mask : 1,
374 __reserved_3 : 15;
375 u32 __reserved_4[3];
376 } lvt_error;
378 /*380*/ struct { /* Timer Initial Count Register */
379 u32 initial_count;
380 u32 __reserved_2[3];
381 } timer_icr;
383 /*390*/ const
384 struct { /* Timer Current Count Register */
385 u32 curr_count;
386 u32 __reserved_2[3];
387 } timer_ccr;
389 /*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
391 /*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
393 /*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
395 /*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
397 /*3E0*/ struct { /* Timer Divide Configuration Register */
398 u32 divisor : 4,
399 __reserved_1 : 28;
400 u32 __reserved_2[3];
401 } timer_dcr;
403 /*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
405 } __attribute__ ((packed));
407 #undef u32
409 #ifdef CONFIG_X86_32
410 #define BAD_APICID 0xFFu
411 #else
412 #define BAD_APICID 0xFFFFu
413 #endif
414 #endif