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[MTD] [NAND] au1550nd.c: remove unused #include <version.h>
[linux-2.6/mini2440.git] / drivers / char / synclink_gt.c
blob509c89ac5bd3292d5ac2a3f9da77902cc2a28280
1 /*
2 * $Id: synclink_gt.c,v 4.50 2007/07/25 19:29:25 paulkf Exp $
3 *
4 * Device driver for Microgate SyncLink GT serial adapters.
5 *
6 * written by Paul Fulghum for Microgate Corporation
7 * paulkf@microgate.com
8 *
9 * Microgate and SyncLink are trademarks of Microgate Corporation
10 *
11 * This code is released under the GNU General Public License (GPL)
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
17 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
19 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
21 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
22 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
23 * OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25
26 /*
27 * DEBUG OUTPUT DEFINITIONS
28 *
29 * uncomment lines below to enable specific types of debug output
30 *
31 * DBGINFO information - most verbose output
32 * DBGERR serious errors
33 * DBGBH bottom half service routine debugging
34 * DBGISR interrupt service routine debugging
35 * DBGDATA output receive and transmit data
36 * DBGTBUF output transmit DMA buffers and registers
37 * DBGRBUF output receive DMA buffers and registers
38 */
39
40 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
41 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
42 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
43 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
44 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
45 //#define DBGTBUF(info) dump_tbufs(info)
46 //#define DBGRBUF(info) dump_rbufs(info)
47
48
49 #include <linux/module.h>
50 #include <linux/version.h>
51 #include <linux/errno.h>
52 #include <linux/signal.h>
53 #include <linux/sched.h>
54 #include <linux/timer.h>
55 #include <linux/interrupt.h>
56 #include <linux/pci.h>
57 #include <linux/tty.h>
58 #include <linux/tty_flip.h>
59 #include <linux/serial.h>
60 #include <linux/major.h>
61 #include <linux/string.h>
62 #include <linux/fcntl.h>
63 #include <linux/ptrace.h>
64 #include <linux/ioport.h>
65 #include <linux/mm.h>
66 #include <linux/slab.h>
67 #include <linux/netdevice.h>
68 #include <linux/vmalloc.h>
69 #include <linux/init.h>
70 #include <linux/delay.h>
71 #include <linux/ioctl.h>
72 #include <linux/termios.h>
73 #include <linux/bitops.h>
74 #include <linux/workqueue.h>
75 #include <linux/hdlc.h>
76 #include <linux/synclink.h>
77
78 #include <asm/system.h>
79 #include <asm/io.h>
80 #include <asm/irq.h>
81 #include <asm/dma.h>
82 #include <asm/types.h>
83 #include <asm/uaccess.h>
84
85 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
86 #define SYNCLINK_GENERIC_HDLC 1
87 #else
88 #define SYNCLINK_GENERIC_HDLC 0
89 #endif
90
91 /*
92 * module identification
93 */
94 static char *driver_name = "SyncLink GT";
95 static char *driver_version = "$Revision: 4.50 $";
96 static char *tty_driver_name = "synclink_gt";
97 static char *tty_dev_prefix = "ttySLG";
98 MODULE_LICENSE("GPL");
99 #define MGSL_MAGIC 0x5401
100 #define MAX_DEVICES 32
101
102 static struct pci_device_id pci_table[] = {
103 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
104 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
105 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
106 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
107 {0,}, /* terminate list */
108 };
109 MODULE_DEVICE_TABLE(pci, pci_table);
110
111 static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
112 static void remove_one(struct pci_dev *dev);
113 static struct pci_driver pci_driver = {
114 .name = "synclink_gt",
115 .id_table = pci_table,
116 .probe = init_one,
117 .remove = __devexit_p(remove_one),
118 };
119
120 static bool pci_registered;
121
122 /*
123 * module configuration and status
124 */
125 static struct slgt_info *slgt_device_list;
126 static int slgt_device_count;
127
128 static int ttymajor;
129 static int debug_level;
130 static int maxframe[MAX_DEVICES];
131
132 module_param(ttymajor, int, 0);
133 module_param(debug_level, int, 0);
134 module_param_array(maxframe, int, NULL, 0);
135
136 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
137 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
138 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
139
140 /*
141 * tty support and callbacks
142 */
143 static struct tty_driver *serial_driver;
144
145 static int open(struct tty_struct *tty, struct file * filp);
146 static void close(struct tty_struct *tty, struct file * filp);
147 static void hangup(struct tty_struct *tty);
148 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
149
150 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
151 static int put_char(struct tty_struct *tty, unsigned char ch);
152 static void send_xchar(struct tty_struct *tty, char ch);
153 static void wait_until_sent(struct tty_struct *tty, int timeout);
154 static int write_room(struct tty_struct *tty);
155 static void flush_chars(struct tty_struct *tty);
156 static void flush_buffer(struct tty_struct *tty);
157 static void tx_hold(struct tty_struct *tty);
158 static void tx_release(struct tty_struct *tty);
159
160 static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
161 static int read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
162 static int chars_in_buffer(struct tty_struct *tty);
163 static void throttle(struct tty_struct * tty);
164 static void unthrottle(struct tty_struct * tty);
165 static int set_break(struct tty_struct *tty, int break_state);
166
167 /*
168 * generic HDLC support and callbacks
169 */
170 #if SYNCLINK_GENERIC_HDLC
171 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
172 static void hdlcdev_tx_done(struct slgt_info *info);
173 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
174 static int hdlcdev_init(struct slgt_info *info);
175 static void hdlcdev_exit(struct slgt_info *info);
176 #endif
177
178
179 /*
180 * device specific structures, macros and functions
181 */
182
183 #define SLGT_MAX_PORTS 4
184 #define SLGT_REG_SIZE 256
185
186 /*
187 * conditional wait facility
188 */
189 struct cond_wait {
190 struct cond_wait *next;
191 wait_queue_head_t q;
192 wait_queue_t wait;
193 unsigned int data;
194 };
195 static void init_cond_wait(struct cond_wait *w, unsigned int data);
196 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
197 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
198 static void flush_cond_wait(struct cond_wait **head);
199
200 /*
201 * DMA buffer descriptor and access macros
202 */
203 struct slgt_desc
204 {
205 __le16 count;
206 __le16 status;
207 __le32 pbuf; /* physical address of data buffer */
208 __le32 next; /* physical address of next descriptor */
209
210 /* driver book keeping */
211 char *buf; /* virtual address of data buffer */
212 unsigned int pdesc; /* physical address of this descriptor */
213 dma_addr_t buf_dma_addr;
214 unsigned short buf_count;
215 };
216
217 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
218 #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
219 #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
220 #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
221 #define desc_count(a) (le16_to_cpu((a).count))
222 #define desc_status(a) (le16_to_cpu((a).status))
223 #define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
224 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
225 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
226 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
227 #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
228
229 struct _input_signal_events {
230 int ri_up;
231 int ri_down;
232 int dsr_up;
233 int dsr_down;
234 int dcd_up;
235 int dcd_down;
236 int cts_up;
237 int cts_down;
238 };
239
240 /*
241 * device instance data structure
242 */
243 struct slgt_info {
244 void *if_ptr; /* General purpose pointer (used by SPPP) */
245 struct tty_port port;
246
247 struct slgt_info *next_device; /* device list link */
248
249 int magic;
250
251 char device_name[25];
252 struct pci_dev *pdev;
253
254 int port_count; /* count of ports on adapter */
255 int adapter_num; /* adapter instance number */
256 int port_num; /* port instance number */
257
258 /* array of pointers to port contexts on this adapter */
259 struct slgt_info *port_array[SLGT_MAX_PORTS];
260
261 int line; /* tty line instance number */
262
263 struct mgsl_icount icount;
264
265 int timeout;
266 int x_char; /* xon/xoff character */
267 unsigned int read_status_mask;
268 unsigned int ignore_status_mask;
269
270 wait_queue_head_t status_event_wait_q;
271 wait_queue_head_t event_wait_q;
272 struct timer_list tx_timer;
273 struct timer_list rx_timer;
274
275 unsigned int gpio_present;
276 struct cond_wait *gpio_wait_q;
277
278 spinlock_t lock; /* spinlock for synchronizing with ISR */
279
280 struct work_struct task;
281 u32 pending_bh;
282 bool bh_requested;
283 bool bh_running;
284
285 int isr_overflow;
286 bool irq_requested; /* true if IRQ requested */
287 bool irq_occurred; /* for diagnostics use */
288
289 /* device configuration */
290
291 unsigned int bus_type;
292 unsigned int irq_level;
293 unsigned long irq_flags;
294
295 unsigned char __iomem * reg_addr; /* memory mapped registers address */
296 u32 phys_reg_addr;
297 bool reg_addr_requested;
298
299 MGSL_PARAMS params; /* communications parameters */
300 u32 idle_mode;
301 u32 max_frame_size; /* as set by device config */
302
303 unsigned int rbuf_fill_level;
304 unsigned int if_mode;
305
306 /* device status */
307
308 bool rx_enabled;
309 bool rx_restart;
310
311 bool tx_enabled;
312 bool tx_active;
313
314 unsigned char signals; /* serial signal states */
315 int init_error; /* initialization error */
316
317 unsigned char *tx_buf;
318 int tx_count;
319
320 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
321 char char_buf[MAX_ASYNC_BUFFER_SIZE];
322 bool drop_rts_on_tx_done;
323 struct _input_signal_events input_signal_events;
324
325 int dcd_chkcount; /* check counts to prevent */
326 int cts_chkcount; /* too many IRQs if a signal */
327 int dsr_chkcount; /* is floating */
328 int ri_chkcount;
329
330 char *bufs; /* virtual address of DMA buffer lists */
331 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
332
333 unsigned int rbuf_count;
334 struct slgt_desc *rbufs;
335 unsigned int rbuf_current;
336 unsigned int rbuf_index;
337
338 unsigned int tbuf_count;
339 struct slgt_desc *tbufs;
340 unsigned int tbuf_current;
341 unsigned int tbuf_start;
342
343 unsigned char *tmp_rbuf;
344 unsigned int tmp_rbuf_count;
345
346 /* SPPP/Cisco HDLC device parts */
347
348 int netcount;
349 spinlock_t netlock;
350 #if SYNCLINK_GENERIC_HDLC
351 struct net_device *netdev;
352 #endif
353
354 };
355
356 static MGSL_PARAMS default_params = {
357 .mode = MGSL_MODE_HDLC,
358 .loopback = 0,
359 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
360 .encoding = HDLC_ENCODING_NRZI_SPACE,
361 .clock_speed = 0,
362 .addr_filter = 0xff,
363 .crc_type = HDLC_CRC_16_CCITT,
364 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
365 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
366 .data_rate = 9600,
367 .data_bits = 8,
368 .stop_bits = 1,
369 .parity = ASYNC_PARITY_NONE
370 };
371
372
373 #define BH_RECEIVE 1
374 #define BH_TRANSMIT 2
375 #define BH_STATUS 4
376 #define IO_PIN_SHUTDOWN_LIMIT 100
377
378 #define DMABUFSIZE 256
379 #define DESC_LIST_SIZE 4096
380
381 #define MASK_PARITY BIT1
382 #define MASK_FRAMING BIT0
383 #define MASK_BREAK BIT14
384 #define MASK_OVERRUN BIT4
385
386 #define GSR 0x00 /* global status */
387 #define JCR 0x04 /* JTAG control */
388 #define IODR 0x08 /* GPIO direction */
389 #define IOER 0x0c /* GPIO interrupt enable */
390 #define IOVR 0x10 /* GPIO value */
391 #define IOSR 0x14 /* GPIO interrupt status */
392 #define TDR 0x80 /* tx data */
393 #define RDR 0x80 /* rx data */
394 #define TCR 0x82 /* tx control */
395 #define TIR 0x84 /* tx idle */
396 #define TPR 0x85 /* tx preamble */
397 #define RCR 0x86 /* rx control */
398 #define VCR 0x88 /* V.24 control */
399 #define CCR 0x89 /* clock control */
400 #define BDR 0x8a /* baud divisor */
401 #define SCR 0x8c /* serial control */
402 #define SSR 0x8e /* serial status */
403 #define RDCSR 0x90 /* rx DMA control/status */
404 #define TDCSR 0x94 /* tx DMA control/status */
405 #define RDDAR 0x98 /* rx DMA descriptor address */
406 #define TDDAR 0x9c /* tx DMA descriptor address */
407
408 #define RXIDLE BIT14
409 #define RXBREAK BIT14
410 #define IRQ_TXDATA BIT13
411 #define IRQ_TXIDLE BIT12
412 #define IRQ_TXUNDER BIT11 /* HDLC */
413 #define IRQ_RXDATA BIT10
414 #define IRQ_RXIDLE BIT9 /* HDLC */
415 #define IRQ_RXBREAK BIT9 /* async */
416 #define IRQ_RXOVER BIT8
417 #define IRQ_DSR BIT7
418 #define IRQ_CTS BIT6
419 #define IRQ_DCD BIT5
420 #define IRQ_RI BIT4
421 #define IRQ_ALL 0x3ff0
422 #define IRQ_MASTER BIT0
423
424 #define slgt_irq_on(info, mask) \
425 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
426 #define slgt_irq_off(info, mask) \
427 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
428
429 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
430 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
431 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
432 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
433 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
434 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
435
436 static void msc_set_vcr(struct slgt_info *info);
437
438 static int startup(struct slgt_info *info);
439 static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
440 static void shutdown(struct slgt_info *info);
441 static void program_hw(struct slgt_info *info);
442 static void change_params(struct slgt_info *info);
443
444 static int register_test(struct slgt_info *info);
445 static int irq_test(struct slgt_info *info);
446 static int loopback_test(struct slgt_info *info);
447 static int adapter_test(struct slgt_info *info);
448
449 static void reset_adapter(struct slgt_info *info);
450 static void reset_port(struct slgt_info *info);
451 static void async_mode(struct slgt_info *info);
452 static void sync_mode(struct slgt_info *info);
453
454 static void rx_stop(struct slgt_info *info);
455 static void rx_start(struct slgt_info *info);
456 static void reset_rbufs(struct slgt_info *info);
457 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
458 static void rdma_reset(struct slgt_info *info);
459 static bool rx_get_frame(struct slgt_info *info);
460 static bool rx_get_buf(struct slgt_info *info);
461
462 static void tx_start(struct slgt_info *info);
463 static void tx_stop(struct slgt_info *info);
464 static void tx_set_idle(struct slgt_info *info);
465 static unsigned int free_tbuf_count(struct slgt_info *info);
466 static unsigned int tbuf_bytes(struct slgt_info *info);
467 static void reset_tbufs(struct slgt_info *info);
468 static void tdma_reset(struct slgt_info *info);
469 static void tdma_start(struct slgt_info *info);
470 static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
471
472 static void get_signals(struct slgt_info *info);
473 static void set_signals(struct slgt_info *info);
474 static void enable_loopback(struct slgt_info *info);
475 static void set_rate(struct slgt_info *info, u32 data_rate);
476
477 static int bh_action(struct slgt_info *info);
478 static void bh_handler(struct work_struct *work);
479 static void bh_transmit(struct slgt_info *info);
480 static void isr_serial(struct slgt_info *info);
481 static void isr_rdma(struct slgt_info *info);
482 static void isr_txeom(struct slgt_info *info, unsigned short status);
483 static void isr_tdma(struct slgt_info *info);
484
485 static int alloc_dma_bufs(struct slgt_info *info);
486 static void free_dma_bufs(struct slgt_info *info);
487 static int alloc_desc(struct slgt_info *info);
488 static void free_desc(struct slgt_info *info);
489 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
490 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
491
492 static int alloc_tmp_rbuf(struct slgt_info *info);
493 static void free_tmp_rbuf(struct slgt_info *info);
494
495 static void tx_timeout(unsigned long context);
496 static void rx_timeout(unsigned long context);
497
498 /*
499 * ioctl handlers
500 */
501 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
502 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
503 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
504 static int get_txidle(struct slgt_info *info, int __user *idle_mode);
505 static int set_txidle(struct slgt_info *info, int idle_mode);
506 static int tx_enable(struct slgt_info *info, int enable);
507 static int tx_abort(struct slgt_info *info);
508 static int rx_enable(struct slgt_info *info, int enable);
509 static int modem_input_wait(struct slgt_info *info,int arg);
510 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
511 static int tiocmget(struct tty_struct *tty, struct file *file);
512 static int tiocmset(struct tty_struct *tty, struct file *file,
513 unsigned int set, unsigned int clear);
514 static int set_break(struct tty_struct *tty, int break_state);
515 static int get_interface(struct slgt_info *info, int __user *if_mode);
516 static int set_interface(struct slgt_info *info, int if_mode);
517 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
518 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
519 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
520
521 /*
522 * driver functions
523 */
524 static void add_device(struct slgt_info *info);
525 static void device_init(int adapter_num, struct pci_dev *pdev);
526 static int claim_resources(struct slgt_info *info);
527 static void release_resources(struct slgt_info *info);
528
529 /*
530 * DEBUG OUTPUT CODE
531 */
532 #ifndef DBGINFO
533 #define DBGINFO(fmt)
534 #endif
535 #ifndef DBGERR
536 #define DBGERR(fmt)
537 #endif
538 #ifndef DBGBH
539 #define DBGBH(fmt)
540 #endif
541 #ifndef DBGISR
542 #define DBGISR(fmt)
543 #endif
544
545 #ifdef DBGDATA
546 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
547 {
548 int i;
549 int linecount;
550 printk("%s %s data:\n",info->device_name, label);
551 while(count) {
552 linecount = (count > 16) ? 16 : count;
553 for(i=0; i < linecount; i++)
554 printk("%02X ",(unsigned char)data[i]);
555 for(;i<17;i++)
556 printk(" ");
557 for(i=0;i<linecount;i++) {
558 if (data[i]>=040 && data[i]<=0176)
559 printk("%c",data[i]);
560 else
561 printk(".");
562 }
563 printk("\n");
564 data += linecount;
565 count -= linecount;
566 }
567 }
568 #else
569 #define DBGDATA(info, buf, size, label)
570 #endif
571
572 #ifdef DBGTBUF
573 static void dump_tbufs(struct slgt_info *info)
574 {
575 int i;
576 printk("tbuf_current=%d\n", info->tbuf_current);
577 for (i=0 ; i < info->tbuf_count ; i++) {
578 printk("%d: count=%04X status=%04X\n",
579 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
580 }
581 }
582 #else
583 #define DBGTBUF(info)
584 #endif
585
586 #ifdef DBGRBUF
587 static void dump_rbufs(struct slgt_info *info)
588 {
589 int i;
590 printk("rbuf_current=%d\n", info->rbuf_current);
591 for (i=0 ; i < info->rbuf_count ; i++) {
592 printk("%d: count=%04X status=%04X\n",
593 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
594 }
595 }
596 #else
597 #define DBGRBUF(info)
598 #endif
599
600 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
601 {
602 #ifdef SANITY_CHECK
603 if (!info) {
604 printk("null struct slgt_info for (%s) in %s\n", devname, name);
605 return 1;
606 }
607 if (info->magic != MGSL_MAGIC) {
608 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
609 return 1;
610 }
611 #else
612 if (!info)
613 return 1;
614 #endif
615 return 0;
616 }
617
618 /**
619 * line discipline callback wrappers
620 *
621 * The wrappers maintain line discipline references
622 * while calling into the line discipline.
623 *
624 * ldisc_receive_buf - pass receive data to line discipline
625 */
626 static void ldisc_receive_buf(struct tty_struct *tty,
627 const __u8 *data, char *flags, int count)
628 {
629 struct tty_ldisc *ld;
630 if (!tty)
631 return;
632 ld = tty_ldisc_ref(tty);
633 if (ld) {
634 if (ld->ops->receive_buf)
635 ld->ops->receive_buf(tty, data, flags, count);
636 tty_ldisc_deref(ld);
637 }
638 }
639
640 /* tty callbacks */
641
642 static int open(struct tty_struct *tty, struct file *filp)
643 {
644 struct slgt_info *info;
645 int retval, line;
646 unsigned long flags;
647
648 line = tty->index;
649 if ((line < 0) || (line >= slgt_device_count)) {
650 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
651 return -ENODEV;
652 }
653
654 info = slgt_device_list;
655 while(info && info->line != line)
656 info = info->next_device;
657 if (sanity_check(info, tty->name, "open"))
658 return -ENODEV;
659 if (info->init_error) {
660 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
661 return -ENODEV;
662 }
663
664 tty->driver_data = info;
665 info->port.tty = tty;
666
667 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
668
669 /* If port is closing, signal caller to try again */
670 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
671 if (info->port.flags & ASYNC_CLOSING)
672 interruptible_sleep_on(&info->port.close_wait);
673 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
674 -EAGAIN : -ERESTARTSYS);
675 goto cleanup;
676 }
677
678 info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
679
680 spin_lock_irqsave(&info->netlock, flags);
681 if (info->netcount) {
682 retval = -EBUSY;
683 spin_unlock_irqrestore(&info->netlock, flags);
684 goto cleanup;
685 }
686 info->port.count++;
687 spin_unlock_irqrestore(&info->netlock, flags);
688
689 if (info->port.count == 1) {
690 /* 1st open on this device, init hardware */
691 retval = startup(info);
692 if (retval < 0)
693 goto cleanup;
694 }
695
696 retval = block_til_ready(tty, filp, info);
697 if (retval) {
698 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
699 goto cleanup;
700 }
701
702 retval = 0;
703
704 cleanup:
705 if (retval) {
706 if (tty->count == 1)
707 info->port.tty = NULL; /* tty layer will release tty struct */
708 if(info->port.count)
709 info->port.count--;
710 }
711
712 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
713 return retval;
714 }
715
716 static void close(struct tty_struct *tty, struct file *filp)
717 {
718 struct slgt_info *info = tty->driver_data;
719
720 if (sanity_check(info, tty->name, "close"))
721 return;
722 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
723
724 if (!info->port.count)
725 return;
726
727 if (tty_hung_up_p(filp))
728 goto cleanup;
729
730 if ((tty->count == 1) && (info->port.count != 1)) {
731 /*
732 * tty->count is 1 and the tty structure will be freed.
733 * info->port.count should be one in this case.
734 * if it's not, correct it so that the port is shutdown.
735 */
736 DBGERR(("%s close: bad refcount; tty->count=1, "
737 "info->port.count=%d\n", info->device_name, info->port.count));
738 info->port.count = 1;
739 }
740
741 info->port.count--;
742
743 /* if at least one open remaining, leave hardware active */
744 if (info->port.count)
745 goto cleanup;
746
747 info->port.flags |= ASYNC_CLOSING;
748
749 /* set tty->closing to notify line discipline to
750 * only process XON/XOFF characters. Only the N_TTY
751 * discipline appears to use this (ppp does not).
752 */
753 tty->closing = 1;
754
755 /* wait for transmit data to clear all layers */
756
757 if (info->port.closing_wait != ASYNC_CLOSING_WAIT_NONE) {
758 DBGINFO(("%s call tty_wait_until_sent\n", info->device_name));
759 tty_wait_until_sent(tty, info->port.closing_wait);
760 }
761
762 if (info->port.flags & ASYNC_INITIALIZED)
763 wait_until_sent(tty, info->timeout);
764 flush_buffer(tty);
765 tty_ldisc_flush(tty);
766
767 shutdown(info);
768
769 tty->closing = 0;
770 info->port.tty = NULL;
771
772 if (info->port.blocked_open) {
773 if (info->port.close_delay) {
774 msleep_interruptible(jiffies_to_msecs(info->port.close_delay));
775 }
776 wake_up_interruptible(&info->port.open_wait);
777 }
778
779 info->port.flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
780
781 wake_up_interruptible(&info->port.close_wait);
782
783 cleanup:
784 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
785 }
786
787 static void hangup(struct tty_struct *tty)
788 {
789 struct slgt_info *info = tty->driver_data;
790
791 if (sanity_check(info, tty->name, "hangup"))
792 return;
793 DBGINFO(("%s hangup\n", info->device_name));
794
795 flush_buffer(tty);
796 shutdown(info);
797
798 info->port.count = 0;
799 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
800 info->port.tty = NULL;
801
802 wake_up_interruptible(&info->port.open_wait);
803 }
804
805 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
806 {
807 struct slgt_info *info = tty->driver_data;
808 unsigned long flags;
809
810 DBGINFO(("%s set_termios\n", tty->driver->name));
811
812 change_params(info);
813
814 /* Handle transition to B0 status */
815 if (old_termios->c_cflag & CBAUD &&
816 !(tty->termios->c_cflag & CBAUD)) {
817 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
818 spin_lock_irqsave(&info->lock,flags);
819 set_signals(info);
820 spin_unlock_irqrestore(&info->lock,flags);
821 }
822
823 /* Handle transition away from B0 status */
824 if (!(old_termios->c_cflag & CBAUD) &&
825 tty->termios->c_cflag & CBAUD) {
826 info->signals |= SerialSignal_DTR;
827 if (!(tty->termios->c_cflag & CRTSCTS) ||
828 !test_bit(TTY_THROTTLED, &tty->flags)) {
829 info->signals |= SerialSignal_RTS;
830 }
831 spin_lock_irqsave(&info->lock,flags);
832 set_signals(info);
833 spin_unlock_irqrestore(&info->lock,flags);
834 }
835
836 /* Handle turning off CRTSCTS */
837 if (old_termios->c_cflag & CRTSCTS &&
838 !(tty->termios->c_cflag & CRTSCTS)) {
839 tty->hw_stopped = 0;
840 tx_release(tty);
841 }
842 }
843
844 static int write(struct tty_struct *tty,
845 const unsigned char *buf, int count)
846 {
847 int ret = 0;
848 struct slgt_info *info = tty->driver_data;
849 unsigned long flags;
850 unsigned int bufs_needed;
851
852 if (sanity_check(info, tty->name, "write"))
853 goto cleanup;
854 DBGINFO(("%s write count=%d\n", info->device_name, count));
855
856 if (!info->tx_buf)
857 goto cleanup;
858
859 if (count > info->max_frame_size) {
860 ret = -EIO;
861 goto cleanup;
862 }
863
864 if (!count)
865 goto cleanup;
866
867 if (!info->tx_active && info->tx_count) {
868 /* send accumulated data from send_char() */
869 tx_load(info, info->tx_buf, info->tx_count);
870 goto start;
871 }
872 bufs_needed = (count/DMABUFSIZE);
873 if (count % DMABUFSIZE)
874 ++bufs_needed;
875 if (bufs_needed > free_tbuf_count(info))
876 goto cleanup;
877
878 ret = info->tx_count = count;
879 tx_load(info, buf, count);
880 goto start;
881
882 start:
883 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
884 spin_lock_irqsave(&info->lock,flags);
885 if (!info->tx_active)
886 tx_start(info);
887 else
888 tdma_start(info);
889 spin_unlock_irqrestore(&info->lock,flags);
890 }
891
892 cleanup:
893 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
894 return ret;
895 }
896
897 static int put_char(struct tty_struct *tty, unsigned char ch)
898 {
899 struct slgt_info *info = tty->driver_data;
900 unsigned long flags;
901 int ret = 0;
902
903 if (sanity_check(info, tty->name, "put_char"))
904 return 0;
905 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
906 if (!info->tx_buf)
907 return 0;
908 spin_lock_irqsave(&info->lock,flags);
909 if (!info->tx_active && (info->tx_count < info->max_frame_size)) {
910 info->tx_buf[info->tx_count++] = ch;
911 ret = 1;
912 }
913 spin_unlock_irqrestore(&info->lock,flags);
914 return ret;
915 }
916
917 static void send_xchar(struct tty_struct *tty, char ch)
918 {
919 struct slgt_info *info = tty->driver_data;
920 unsigned long flags;
921
922 if (sanity_check(info, tty->name, "send_xchar"))
923 return;
924 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
925 info->x_char = ch;
926 if (ch) {
927 spin_lock_irqsave(&info->lock,flags);
928 if (!info->tx_enabled)
929 tx_start(info);
930 spin_unlock_irqrestore(&info->lock,flags);
931 }
932 }
933
934 static void wait_until_sent(struct tty_struct *tty, int timeout)
935 {
936 struct slgt_info *info = tty->driver_data;
937 unsigned long orig_jiffies, char_time;
938
939 if (!info )
940 return;
941 if (sanity_check(info, tty->name, "wait_until_sent"))
942 return;
943 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
944 if (!(info->port.flags & ASYNC_INITIALIZED))
945 goto exit;
946
947 orig_jiffies = jiffies;
948
949 /* Set check interval to 1/5 of estimated time to
950 * send a character, and make it at least 1. The check
951 * interval should also be less than the timeout.
952 * Note: use tight timings here to satisfy the NIST-PCTS.
953 */
954
955 lock_kernel();
956
957 if (info->params.data_rate) {
958 char_time = info->timeout/(32 * 5);
959 if (!char_time)
960 char_time++;
961 } else
962 char_time = 1;
963
964 if (timeout)
965 char_time = min_t(unsigned long, char_time, timeout);
966
967 while (info->tx_active) {
968 msleep_interruptible(jiffies_to_msecs(char_time));
969 if (signal_pending(current))
970 break;
971 if (timeout && time_after(jiffies, orig_jiffies + timeout))
972 break;
973 }
974 unlock_kernel();
975
976 exit:
977 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
978 }
979
980 static int write_room(struct tty_struct *tty)
981 {
982 struct slgt_info *info = tty->driver_data;
983 int ret;
984
985 if (sanity_check(info, tty->name, "write_room"))
986 return 0;
987 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
988 DBGINFO(("%s write_room=%d\n", info->device_name, ret));
989 return ret;
990 }
991
992 static void flush_chars(struct tty_struct *tty)
993 {
994 struct slgt_info *info = tty->driver_data;
995 unsigned long flags;
996
997 if (sanity_check(info, tty->name, "flush_chars"))
998 return;
999 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
1000
1001 if (info->tx_count <= 0 || tty->stopped ||
1002 tty->hw_stopped || !info->tx_buf)
1003 return;
1004
1005 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
1006
1007 spin_lock_irqsave(&info->lock,flags);
1008 if (!info->tx_active && info->tx_count) {
1009 tx_load(info, info->tx_buf,info->tx_count);
1010 tx_start(info);
1011 }
1012 spin_unlock_irqrestore(&info->lock,flags);
1013 }
1014
1015 static void flush_buffer(struct tty_struct *tty)
1016 {
1017 struct slgt_info *info = tty->driver_data;
1018 unsigned long flags;
1019
1020 if (sanity_check(info, tty->name, "flush_buffer"))
1021 return;
1022 DBGINFO(("%s flush_buffer\n", info->device_name));
1023
1024 spin_lock_irqsave(&info->lock,flags);
1025 if (!info->tx_active)
1026 info->tx_count = 0;
1027 spin_unlock_irqrestore(&info->lock,flags);
1028
1029 tty_wakeup(tty);
1030 }
1031
1032 /*
1033 * throttle (stop) transmitter
1034 */
1035 static void tx_hold(struct tty_struct *tty)
1036 {
1037 struct slgt_info *info = tty->driver_data;
1038 unsigned long flags;
1039
1040 if (sanity_check(info, tty->name, "tx_hold"))
1041 return;
1042 DBGINFO(("%s tx_hold\n", info->device_name));
1043 spin_lock_irqsave(&info->lock,flags);
1044 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1045 tx_stop(info);
1046 spin_unlock_irqrestore(&info->lock,flags);
1047 }
1048
1049 /*
1050 * release (start) transmitter
1051 */
1052 static void tx_release(struct tty_struct *tty)
1053 {
1054 struct slgt_info *info = tty->driver_data;
1055 unsigned long flags;
1056
1057 if (sanity_check(info, tty->name, "tx_release"))
1058 return;
1059 DBGINFO(("%s tx_release\n", info->device_name));
1060 spin_lock_irqsave(&info->lock,flags);
1061 if (!info->tx_active && info->tx_count) {
1062 tx_load(info, info->tx_buf, info->tx_count);
1063 tx_start(info);
1064 }
1065 spin_unlock_irqrestore(&info->lock,flags);
1066 }
1067
1068 /*
1069 * Service an IOCTL request
1070 *
1071 * Arguments
1072 *
1073 * tty pointer to tty instance data
1074 * file pointer to associated file object for device
1075 * cmd IOCTL command code
1076 * arg command argument/context
1077 *
1078 * Return 0 if success, otherwise error code
1079 */
1080 static int ioctl(struct tty_struct *tty, struct file *file,
1081 unsigned int cmd, unsigned long arg)
1082 {
1083 struct slgt_info *info = tty->driver_data;
1084 struct mgsl_icount cnow; /* kernel counter temps */
1085 struct serial_icounter_struct __user *p_cuser; /* user space */
1086 unsigned long flags;
1087 void __user *argp = (void __user *)arg;
1088 int ret;
1089
1090 if (sanity_check(info, tty->name, "ioctl"))
1091 return -ENODEV;
1092 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1093
1094 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1095 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1096 if (tty->flags & (1 << TTY_IO_ERROR))
1097 return -EIO;
1098 }
1099
1100 lock_kernel();
1101
1102 switch (cmd) {
1103 case MGSL_IOCGPARAMS:
1104 ret = get_params(info, argp);
1105 break;
1106 case MGSL_IOCSPARAMS:
1107 ret = set_params(info, argp);
1108 break;
1109 case MGSL_IOCGTXIDLE:
1110 ret = get_txidle(info, argp);
1111 break;
1112 case MGSL_IOCSTXIDLE:
1113 ret = set_txidle(info, (int)arg);
1114 break;
1115 case MGSL_IOCTXENABLE:
1116 ret = tx_enable(info, (int)arg);
1117 break;
1118 case MGSL_IOCRXENABLE:
1119 ret = rx_enable(info, (int)arg);
1120 break;
1121 case MGSL_IOCTXABORT:
1122 ret = tx_abort(info);
1123 break;
1124 case MGSL_IOCGSTATS:
1125 ret = get_stats(info, argp);
1126 break;
1127 case MGSL_IOCWAITEVENT:
1128 ret = wait_mgsl_event(info, argp);
1129 break;
1130 case TIOCMIWAIT:
1131 ret = modem_input_wait(info,(int)arg);
1132 break;
1133 case MGSL_IOCGIF:
1134 ret = get_interface(info, argp);
1135 break;
1136 case MGSL_IOCSIF:
1137 ret = set_interface(info,(int)arg);
1138 break;
1139 case MGSL_IOCSGPIO:
1140 ret = set_gpio(info, argp);
1141 break;
1142 case MGSL_IOCGGPIO:
1143 ret = get_gpio(info, argp);
1144 break;
1145 case MGSL_IOCWAITGPIO:
1146 ret = wait_gpio(info, argp);
1147 break;
1148 case TIOCGICOUNT:
1149 spin_lock_irqsave(&info->lock,flags);
1150 cnow = info->icount;
1151 spin_unlock_irqrestore(&info->lock,flags);
1152 p_cuser = argp;
1153 if (put_user(cnow.cts, &p_cuser->cts) ||
1154 put_user(cnow.dsr, &p_cuser->dsr) ||
1155 put_user(cnow.rng, &p_cuser->rng) ||
1156 put_user(cnow.dcd, &p_cuser->dcd) ||
1157 put_user(cnow.rx, &p_cuser->rx) ||
1158 put_user(cnow.tx, &p_cuser->tx) ||
1159 put_user(cnow.frame, &p_cuser->frame) ||
1160 put_user(cnow.overrun, &p_cuser->overrun) ||
1161 put_user(cnow.parity, &p_cuser->parity) ||
1162 put_user(cnow.brk, &p_cuser->brk) ||
1163 put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1164 ret = -EFAULT;
1165 ret = 0;
1166 break;
1167 default:
1168 ret = -ENOIOCTLCMD;
1169 }
1170 unlock_kernel();
1171 return ret;
1172 }
1173
1174 /*
1175 * support for 32 bit ioctl calls on 64 bit systems
1176 */
1177 #ifdef CONFIG_COMPAT
1178 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1179 {
1180 struct MGSL_PARAMS32 tmp_params;
1181
1182 DBGINFO(("%s get_params32\n", info->device_name));
1183 tmp_params.mode = (compat_ulong_t)info->params.mode;
1184 tmp_params.loopback = info->params.loopback;
1185 tmp_params.flags = info->params.flags;
1186 tmp_params.encoding = info->params.encoding;
1187 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1188 tmp_params.addr_filter = info->params.addr_filter;
1189 tmp_params.crc_type = info->params.crc_type;
1190 tmp_params.preamble_length = info->params.preamble_length;
1191 tmp_params.preamble = info->params.preamble;
1192 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1193 tmp_params.data_bits = info->params.data_bits;
1194 tmp_params.stop_bits = info->params.stop_bits;
1195 tmp_params.parity = info->params.parity;
1196 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1197 return -EFAULT;
1198 return 0;
1199 }
1200
1201 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1202 {
1203 struct MGSL_PARAMS32 tmp_params;
1204
1205 DBGINFO(("%s set_params32\n", info->device_name));
1206 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1207 return -EFAULT;
1208
1209 spin_lock(&info->lock);
1210 info->params.mode = tmp_params.mode;
1211 info->params.loopback = tmp_params.loopback;
1212 info->params.flags = tmp_params.flags;
1213 info->params.encoding = tmp_params.encoding;
1214 info->params.clock_speed = tmp_params.clock_speed;
1215 info->params.addr_filter = tmp_params.addr_filter;
1216 info->params.crc_type = tmp_params.crc_type;
1217 info->params.preamble_length = tmp_params.preamble_length;
1218 info->params.preamble = tmp_params.preamble;
1219 info->params.data_rate = tmp_params.data_rate;
1220 info->params.data_bits = tmp_params.data_bits;
1221 info->params.stop_bits = tmp_params.stop_bits;
1222 info->params.parity = tmp_params.parity;
1223 spin_unlock(&info->lock);
1224
1225 change_params(info);
1226
1227 return 0;
1228 }
1229
1230 static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file,
1231 unsigned int cmd, unsigned long arg)
1232 {
1233 struct slgt_info *info = tty->driver_data;
1234 int rc = -ENOIOCTLCMD;
1235
1236 if (sanity_check(info, tty->name, "compat_ioctl"))
1237 return -ENODEV;
1238 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1239
1240 switch (cmd) {
1241
1242 case MGSL_IOCSPARAMS32:
1243 rc = set_params32(info, compat_ptr(arg));
1244 break;
1245
1246 case MGSL_IOCGPARAMS32:
1247 rc = get_params32(info, compat_ptr(arg));
1248 break;
1249
1250 case MGSL_IOCGPARAMS:
1251 case MGSL_IOCSPARAMS:
1252 case MGSL_IOCGTXIDLE:
1253 case MGSL_IOCGSTATS:
1254 case MGSL_IOCWAITEVENT:
1255 case MGSL_IOCGIF:
1256 case MGSL_IOCSGPIO:
1257 case MGSL_IOCGGPIO:
1258 case MGSL_IOCWAITGPIO:
1259 case TIOCGICOUNT:
1260 rc = ioctl(tty, file, cmd, (unsigned long)(compat_ptr(arg)));
1261 break;
1262
1263 case MGSL_IOCSTXIDLE:
1264 case MGSL_IOCTXENABLE:
1265 case MGSL_IOCRXENABLE:
1266 case MGSL_IOCTXABORT:
1267 case TIOCMIWAIT:
1268 case MGSL_IOCSIF:
1269 rc = ioctl(tty, file, cmd, arg);
1270 break;
1271 }
1272
1273 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1274 return rc;
1275 }
1276 #else
1277 #define slgt_compat_ioctl NULL
1278 #endif /* ifdef CONFIG_COMPAT */
1279
1280 /*
1281 * proc fs support
1282 */
1283 static inline int line_info(char *buf, struct slgt_info *info)
1284 {
1285 char stat_buf[30];
1286 int ret;
1287 unsigned long flags;
1288
1289 ret = sprintf(buf, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1290 info->device_name, info->phys_reg_addr,
1291 info->irq_level, info->max_frame_size);
1292
1293 /* output current serial signal states */
1294 spin_lock_irqsave(&info->lock,flags);
1295 get_signals(info);
1296 spin_unlock_irqrestore(&info->lock,flags);
1297
1298 stat_buf[0] = 0;
1299 stat_buf[1] = 0;
1300 if (info->signals & SerialSignal_RTS)
1301 strcat(stat_buf, "|RTS");
1302 if (info->signals & SerialSignal_CTS)
1303 strcat(stat_buf, "|CTS");
1304 if (info->signals & SerialSignal_DTR)
1305 strcat(stat_buf, "|DTR");
1306 if (info->signals & SerialSignal_DSR)
1307 strcat(stat_buf, "|DSR");
1308 if (info->signals & SerialSignal_DCD)
1309 strcat(stat_buf, "|CD");
1310 if (info->signals & SerialSignal_RI)
1311 strcat(stat_buf, "|RI");
1312
1313 if (info->params.mode != MGSL_MODE_ASYNC) {
1314 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1315 info->icount.txok, info->icount.rxok);
1316 if (info->icount.txunder)
1317 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1318 if (info->icount.txabort)
1319 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1320 if (info->icount.rxshort)
1321 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1322 if (info->icount.rxlong)
1323 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1324 if (info->icount.rxover)
1325 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1326 if (info->icount.rxcrc)
1327 ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
1328 } else {
1329 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1330 info->icount.tx, info->icount.rx);
1331 if (info->icount.frame)
1332 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1333 if (info->icount.parity)
1334 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1335 if (info->icount.brk)
1336 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1337 if (info->icount.overrun)
1338 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1339 }
1340
1341 /* Append serial signal status to end */
1342 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1343
1344 ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1345 info->tx_active,info->bh_requested,info->bh_running,
1346 info->pending_bh);
1347
1348 return ret;
1349 }
1350
1351 /* Called to print information about devices
1352 */
1353 static int read_proc(char *page, char **start, off_t off, int count,
1354 int *eof, void *data)
1355 {
1356 int len = 0, l;
1357 off_t begin = 0;
1358 struct slgt_info *info;
1359
1360 len += sprintf(page, "synclink_gt driver:%s\n", driver_version);
1361
1362 info = slgt_device_list;
1363 while( info ) {
1364 l = line_info(page + len, info);
1365 len += l;
1366 if (len+begin > off+count)
1367 goto done;
1368 if (len+begin < off) {
1369 begin += len;
1370 len = 0;
1371 }
1372 info = info->next_device;
1373 }
1374
1375 *eof = 1;
1376 done:
1377 if (off >= len+begin)
1378 return 0;
1379 *start = page + (off-begin);
1380 return ((count < begin+len-off) ? count : begin+len-off);
1381 }
1382
1383 /*
1384 * return count of bytes in transmit buffer
1385 */
1386 static int chars_in_buffer(struct tty_struct *tty)
1387 {
1388 struct slgt_info *info = tty->driver_data;
1389 int count;
1390 if (sanity_check(info, tty->name, "chars_in_buffer"))
1391 return 0;
1392 count = tbuf_bytes(info);
1393 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1394 return count;
1395 }
1396
1397 /*
1398 * signal remote device to throttle send data (our receive data)
1399 */
1400 static void throttle(struct tty_struct * tty)
1401 {
1402 struct slgt_info *info = tty->driver_data;
1403 unsigned long flags;
1404
1405 if (sanity_check(info, tty->name, "throttle"))
1406 return;
1407 DBGINFO(("%s throttle\n", info->device_name));
1408 if (I_IXOFF(tty))
1409 send_xchar(tty, STOP_CHAR(tty));
1410 if (tty->termios->c_cflag & CRTSCTS) {
1411 spin_lock_irqsave(&info->lock,flags);
1412 info->signals &= ~SerialSignal_RTS;
1413 set_signals(info);
1414 spin_unlock_irqrestore(&info->lock,flags);
1415 }
1416 }
1417
1418 /*
1419 * signal remote device to stop throttling send data (our receive data)
1420 */
1421 static void unthrottle(struct tty_struct * tty)
1422 {
1423 struct slgt_info *info = tty->driver_data;
1424 unsigned long flags;
1425
1426 if (sanity_check(info, tty->name, "unthrottle"))
1427 return;
1428 DBGINFO(("%s unthrottle\n", info->device_name));
1429 if (I_IXOFF(tty)) {
1430 if (info->x_char)
1431 info->x_char = 0;
1432 else
1433 send_xchar(tty, START_CHAR(tty));
1434 }
1435 if (tty->termios->c_cflag & CRTSCTS) {
1436 spin_lock_irqsave(&info->lock,flags);
1437 info->signals |= SerialSignal_RTS;
1438 set_signals(info);
1439 spin_unlock_irqrestore(&info->lock,flags);
1440 }
1441 }
1442
1443 /*
1444 * set or clear transmit break condition
1445 * break_state -1=set break condition, 0=clear
1446 */
1447 static int set_break(struct tty_struct *tty, int break_state)
1448 {
1449 struct slgt_info *info = tty->driver_data;
1450 unsigned short value;
1451 unsigned long flags;
1452
1453 if (sanity_check(info, tty->name, "set_break"))
1454 return -EINVAL;
1455 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1456
1457 spin_lock_irqsave(&info->lock,flags);
1458 value = rd_reg16(info, TCR);
1459 if (break_state == -1)
1460 value |= BIT6;
1461 else
1462 value &= ~BIT6;
1463 wr_reg16(info, TCR, value);
1464 spin_unlock_irqrestore(&info->lock,flags);
1465 return 0;
1466 }
1467
1468 #if SYNCLINK_GENERIC_HDLC
1469
1470 /**
1471 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1472 * set encoding and frame check sequence (FCS) options
1473 *
1474 * dev pointer to network device structure
1475 * encoding serial encoding setting
1476 * parity FCS setting
1477 *
1478 * returns 0 if success, otherwise error code
1479 */
1480 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1481 unsigned short parity)
1482 {
1483 struct slgt_info *info = dev_to_port(dev);
1484 unsigned char new_encoding;
1485 unsigned short new_crctype;
1486
1487 /* return error if TTY interface open */
1488 if (info->port.count)
1489 return -EBUSY;
1490
1491 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1492
1493 switch (encoding)
1494 {
1495 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1496 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1497 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1498 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1499 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1500 default: return -EINVAL;
1501 }
1502
1503 switch (parity)
1504 {
1505 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1506 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1507 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1508 default: return -EINVAL;
1509 }
1510
1511 info->params.encoding = new_encoding;
1512 info->params.crc_type = new_crctype;
1513
1514 /* if network interface up, reprogram hardware */
1515 if (info->netcount)
1516 program_hw(info);
1517
1518 return 0;
1519 }
1520
1521 /**
1522 * called by generic HDLC layer to send frame
1523 *
1524 * skb socket buffer containing HDLC frame
1525 * dev pointer to network device structure
1526 *
1527 * returns 0 if success, otherwise error code
1528 */
1529 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1530 {
1531 struct slgt_info *info = dev_to_port(dev);
1532 unsigned long flags;
1533
1534 DBGINFO(("%s hdlc_xmit\n", dev->name));
1535
1536 /* stop sending until this frame completes */
1537 netif_stop_queue(dev);
1538
1539 /* copy data to device buffers */
1540 info->tx_count = skb->len;
1541 tx_load(info, skb->data, skb->len);
1542
1543 /* update network statistics */
1544 dev->stats.tx_packets++;
1545 dev->stats.tx_bytes += skb->len;
1546
1547 /* done with socket buffer, so free it */
1548 dev_kfree_skb(skb);
1549
1550 /* save start time for transmit timeout detection */
1551 dev->trans_start = jiffies;
1552
1553 /* start hardware transmitter if necessary */
1554 spin_lock_irqsave(&info->lock,flags);
1555 if (!info->tx_active)
1556 tx_start(info);
1557 spin_unlock_irqrestore(&info->lock,flags);
1558
1559 return 0;
1560 }
1561
1562 /**
1563 * called by network layer when interface enabled
1564 * claim resources and initialize hardware
1565 *
1566 * dev pointer to network device structure
1567 *
1568 * returns 0 if success, otherwise error code
1569 */
1570 static int hdlcdev_open(struct net_device *dev)
1571 {
1572 struct slgt_info *info = dev_to_port(dev);
1573 int rc;
1574 unsigned long flags;
1575
1576 if (!try_module_get(THIS_MODULE))
1577 return -EBUSY;
1578
1579 DBGINFO(("%s hdlcdev_open\n", dev->name));
1580
1581 /* generic HDLC layer open processing */
1582 if ((rc = hdlc_open(dev)))
1583 return rc;
1584
1585 /* arbitrate between network and tty opens */
1586 spin_lock_irqsave(&info->netlock, flags);
1587 if (info->port.count != 0 || info->netcount != 0) {
1588 DBGINFO(("%s hdlc_open busy\n", dev->name));
1589 spin_unlock_irqrestore(&info->netlock, flags);
1590 return -EBUSY;
1591 }
1592 info->netcount=1;
1593 spin_unlock_irqrestore(&info->netlock, flags);
1594
1595 /* claim resources and init adapter */
1596 if ((rc = startup(info)) != 0) {
1597 spin_lock_irqsave(&info->netlock, flags);
1598 info->netcount=0;
1599 spin_unlock_irqrestore(&info->netlock, flags);
1600 return rc;
1601 }
1602
1603 /* assert DTR and RTS, apply hardware settings */
1604 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1605 program_hw(info);
1606
1607 /* enable network layer transmit */
1608 dev->trans_start = jiffies;
1609 netif_start_queue(dev);
1610
1611 /* inform generic HDLC layer of current DCD status */
1612 spin_lock_irqsave(&info->lock, flags);
1613 get_signals(info);
1614 spin_unlock_irqrestore(&info->lock, flags);
1615 if (info->signals & SerialSignal_DCD)
1616 netif_carrier_on(dev);
1617 else
1618 netif_carrier_off(dev);
1619 return 0;
1620 }
1621
1622 /**
1623 * called by network layer when interface is disabled
1624 * shutdown hardware and release resources
1625 *
1626 * dev pointer to network device structure
1627 *
1628 * returns 0 if success, otherwise error code
1629 */
1630 static int hdlcdev_close(struct net_device *dev)
1631 {
1632 struct slgt_info *info = dev_to_port(dev);
1633 unsigned long flags;
1634
1635 DBGINFO(("%s hdlcdev_close\n", dev->name));
1636
1637 netif_stop_queue(dev);
1638
1639 /* shutdown adapter and release resources */
1640 shutdown(info);
1641
1642 hdlc_close(dev);
1643
1644 spin_lock_irqsave(&info->netlock, flags);
1645 info->netcount=0;
1646 spin_unlock_irqrestore(&info->netlock, flags);
1647
1648 module_put(THIS_MODULE);
1649 return 0;
1650 }
1651
1652 /**
1653 * called by network layer to process IOCTL call to network device
1654 *
1655 * dev pointer to network device structure
1656 * ifr pointer to network interface request structure
1657 * cmd IOCTL command code
1658 *
1659 * returns 0 if success, otherwise error code
1660 */
1661 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1662 {
1663 const size_t size = sizeof(sync_serial_settings);
1664 sync_serial_settings new_line;
1665 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1666 struct slgt_info *info = dev_to_port(dev);
1667 unsigned int flags;
1668
1669 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1670
1671 /* return error if TTY interface open */
1672 if (info->port.count)
1673 return -EBUSY;
1674
1675 if (cmd != SIOCWANDEV)
1676 return hdlc_ioctl(dev, ifr, cmd);
1677
1678 switch(ifr->ifr_settings.type) {
1679 case IF_GET_IFACE: /* return current sync_serial_settings */
1680
1681 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1682 if (ifr->ifr_settings.size < size) {
1683 ifr->ifr_settings.size = size; /* data size wanted */
1684 return -ENOBUFS;
1685 }
1686
1687 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1688 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1689 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1690 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1691
1692 switch (flags){
1693 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1694 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1695 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1696 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1697 default: new_line.clock_type = CLOCK_DEFAULT;
1698 }
1699
1700 new_line.clock_rate = info->params.clock_speed;
1701 new_line.loopback = info->params.loopback ? 1:0;
1702
1703 if (copy_to_user(line, &new_line, size))
1704 return -EFAULT;
1705 return 0;
1706
1707 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1708
1709 if(!capable(CAP_NET_ADMIN))
1710 return -EPERM;
1711 if (copy_from_user(&new_line, line, size))
1712 return -EFAULT;
1713
1714 switch (new_line.clock_type)
1715 {
1716 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1717 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1718 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1719 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1720 case CLOCK_DEFAULT: flags = info->params.flags &
1721 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1722 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1723 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1724 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1725 default: return -EINVAL;
1726 }
1727
1728 if (new_line.loopback != 0 && new_line.loopback != 1)
1729 return -EINVAL;
1730
1731 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1732 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1733 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1734 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1735 info->params.flags |= flags;
1736
1737 info->params.loopback = new_line.loopback;
1738
1739 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1740 info->params.clock_speed = new_line.clock_rate;
1741 else
1742 info->params.clock_speed = 0;
1743
1744 /* if network interface up, reprogram hardware */
1745 if (info->netcount)
1746 program_hw(info);
1747 return 0;
1748
1749 default:
1750 return hdlc_ioctl(dev, ifr, cmd);
1751 }
1752 }
1753
1754 /**
1755 * called by network layer when transmit timeout is detected
1756 *
1757 * dev pointer to network device structure
1758 */
1759 static void hdlcdev_tx_timeout(struct net_device *dev)
1760 {
1761 struct slgt_info *info = dev_to_port(dev);
1762 unsigned long flags;
1763
1764 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1765
1766 dev->stats.tx_errors++;
1767 dev->stats.tx_aborted_errors++;
1768
1769 spin_lock_irqsave(&info->lock,flags);
1770 tx_stop(info);
1771 spin_unlock_irqrestore(&info->lock,flags);
1772
1773 netif_wake_queue(dev);
1774 }
1775
1776 /**
1777 * called by device driver when transmit completes
1778 * reenable network layer transmit if stopped
1779 *
1780 * info pointer to device instance information
1781 */
1782 static void hdlcdev_tx_done(struct slgt_info *info)
1783 {
1784 if (netif_queue_stopped(info->netdev))
1785 netif_wake_queue(info->netdev);
1786 }
1787
1788 /**
1789 * called by device driver when frame received
1790 * pass frame to network layer
1791 *
1792 * info pointer to device instance information
1793 * buf pointer to buffer contianing frame data
1794 * size count of data bytes in buf
1795 */
1796 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1797 {
1798 struct sk_buff *skb = dev_alloc_skb(size);
1799 struct net_device *dev = info->netdev;
1800
1801 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1802
1803 if (skb == NULL) {
1804 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1805 dev->stats.rx_dropped++;
1806 return;
1807 }
1808
1809 memcpy(skb_put(skb, size), buf, size);
1810
1811 skb->protocol = hdlc_type_trans(skb, dev);
1812
1813 dev->stats.rx_packets++;
1814 dev->stats.rx_bytes += size;
1815
1816 netif_rx(skb);
1817
1818 dev->last_rx = jiffies;
1819 }
1820
1821 /**
1822 * called by device driver when adding device instance
1823 * do generic HDLC initialization
1824 *
1825 * info pointer to device instance information
1826 *
1827 * returns 0 if success, otherwise error code
1828 */
1829 static int hdlcdev_init(struct slgt_info *info)
1830 {
1831 int rc;
1832 struct net_device *dev;
1833 hdlc_device *hdlc;
1834
1835 /* allocate and initialize network and HDLC layer objects */
1836
1837 if (!(dev = alloc_hdlcdev(info))) {
1838 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1839 return -ENOMEM;
1840 }
1841
1842 /* for network layer reporting purposes only */
1843 dev->mem_start = info->phys_reg_addr;
1844 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1845 dev->irq = info->irq_level;
1846
1847 /* network layer callbacks and settings */
1848 dev->do_ioctl = hdlcdev_ioctl;
1849 dev->open = hdlcdev_open;
1850 dev->stop = hdlcdev_close;
1851 dev->tx_timeout = hdlcdev_tx_timeout;
1852 dev->watchdog_timeo = 10*HZ;
1853 dev->tx_queue_len = 50;
1854
1855 /* generic HDLC layer callbacks and settings */
1856 hdlc = dev_to_hdlc(dev);
1857 hdlc->attach = hdlcdev_attach;
1858 hdlc->xmit = hdlcdev_xmit;
1859
1860 /* register objects with HDLC layer */
1861 if ((rc = register_hdlc_device(dev))) {
1862 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1863 free_netdev(dev);
1864 return rc;
1865 }
1866
1867 info->netdev = dev;
1868 return 0;
1869 }
1870
1871 /**
1872 * called by device driver when removing device instance
1873 * do generic HDLC cleanup
1874 *
1875 * info pointer to device instance information
1876 */
1877 static void hdlcdev_exit(struct slgt_info *info)
1878 {
1879 unregister_hdlc_device(info->netdev);
1880 free_netdev(info->netdev);
1881 info->netdev = NULL;
1882 }
1883
1884 #endif /* ifdef CONFIG_HDLC */
1885
1886 /*
1887 * get async data from rx DMA buffers
1888 */
1889 static void rx_async(struct slgt_info *info)
1890 {
1891 struct tty_struct *tty = info->port.tty;
1892 struct mgsl_icount *icount = &info->icount;
1893 unsigned int start, end;
1894 unsigned char *p;
1895 unsigned char status;
1896 struct slgt_desc *bufs = info->rbufs;
1897 int i, count;
1898 int chars = 0;
1899 int stat;
1900 unsigned char ch;
1901
1902 start = end = info->rbuf_current;
1903
1904 while(desc_complete(bufs[end])) {
1905 count = desc_count(bufs[end]) - info->rbuf_index;
1906 p = bufs[end].buf + info->rbuf_index;
1907
1908 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1909 DBGDATA(info, p, count, "rx");
1910
1911 for(i=0 ; i < count; i+=2, p+=2) {
1912 ch = *p;
1913 icount->rx++;
1914
1915 stat = 0;
1916
1917 if ((status = *(p+1) & (BIT1 + BIT0))) {
1918 if (status & BIT1)
1919 icount->parity++;
1920 else if (status & BIT0)
1921 icount->frame++;
1922 /* discard char if tty control flags say so */
1923 if (status & info->ignore_status_mask)
1924 continue;
1925 if (status & BIT1)
1926 stat = TTY_PARITY;
1927 else if (status & BIT0)
1928 stat = TTY_FRAME;
1929 }
1930 if (tty) {
1931 tty_insert_flip_char(tty, ch, stat);
1932 chars++;
1933 }
1934 }
1935
1936 if (i < count) {
1937 /* receive buffer not completed */
1938 info->rbuf_index += i;
1939 mod_timer(&info->rx_timer, jiffies + 1);
1940 break;
1941 }
1942
1943 info->rbuf_index = 0;
1944 free_rbufs(info, end, end);
1945
1946 if (++end == info->rbuf_count)
1947 end = 0;
1948
1949 /* if entire list searched then no frame available */
1950 if (end == start)
1951 break;
1952 }
1953
1954 if (tty && chars)
1955 tty_flip_buffer_push(tty);
1956 }
1957
1958 /*
1959 * return next bottom half action to perform
1960 */
1961 static int bh_action(struct slgt_info *info)
1962 {
1963 unsigned long flags;
1964 int rc;
1965
1966 spin_lock_irqsave(&info->lock,flags);
1967
1968 if (info->pending_bh & BH_RECEIVE) {
1969 info->pending_bh &= ~BH_RECEIVE;
1970 rc = BH_RECEIVE;
1971 } else if (info->pending_bh & BH_TRANSMIT) {
1972 info->pending_bh &= ~BH_TRANSMIT;
1973 rc = BH_TRANSMIT;
1974 } else if (info->pending_bh & BH_STATUS) {
1975 info->pending_bh &= ~BH_STATUS;
1976 rc = BH_STATUS;
1977 } else {
1978 /* Mark BH routine as complete */
1979 info->bh_running = false;
1980 info->bh_requested = false;
1981 rc = 0;
1982 }
1983
1984 spin_unlock_irqrestore(&info->lock,flags);
1985
1986 return rc;
1987 }
1988
1989 /*
1990 * perform bottom half processing
1991 */
1992 static void bh_handler(struct work_struct *work)
1993 {
1994 struct slgt_info *info = container_of(work, struct slgt_info, task);
1995 int action;
1996
1997 if (!info)
1998 return;
1999 info->bh_running = true;
2000
2001 while((action = bh_action(info))) {
2002 switch (action) {
2003 case BH_RECEIVE:
2004 DBGBH(("%s bh receive\n", info->device_name));
2005 switch(info->params.mode) {
2006 case MGSL_MODE_ASYNC:
2007 rx_async(info);
2008 break;
2009 case MGSL_MODE_HDLC:
2010 while(rx_get_frame(info));
2011 break;
2012 case MGSL_MODE_RAW:
2013 case MGSL_MODE_MONOSYNC:
2014 case MGSL_MODE_BISYNC:
2015 while(rx_get_buf(info));
2016 break;
2017 }
2018 /* restart receiver if rx DMA buffers exhausted */
2019 if (info->rx_restart)
2020 rx_start(info);
2021 break;
2022 case BH_TRANSMIT:
2023 bh_transmit(info);
2024 break;
2025 case BH_STATUS:
2026 DBGBH(("%s bh status\n", info->device_name));
2027 info->ri_chkcount = 0;
2028 info->dsr_chkcount = 0;
2029 info->dcd_chkcount = 0;
2030 info->cts_chkcount = 0;
2031 break;
2032 default:
2033 DBGBH(("%s unknown action\n", info->device_name));
2034 break;
2035 }
2036 }
2037 DBGBH(("%s bh_handler exit\n", info->device_name));
2038 }
2039
2040 static void bh_transmit(struct slgt_info *info)
2041 {
2042 struct tty_struct *tty = info->port.tty;
2043
2044 DBGBH(("%s bh_transmit\n", info->device_name));
2045 if (tty)
2046 tty_wakeup(tty);
2047 }
2048
2049 static void dsr_change(struct slgt_info *info, unsigned short status)
2050 {
2051 if (status & BIT3) {
2052 info->signals |= SerialSignal_DSR;
2053 info->input_signal_events.dsr_up++;
2054 } else {
2055 info->signals &= ~SerialSignal_DSR;
2056 info->input_signal_events.dsr_down++;
2057 }
2058 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2059 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2060 slgt_irq_off(info, IRQ_DSR);
2061 return;
2062 }
2063 info->icount.dsr++;
2064 wake_up_interruptible(&info->status_event_wait_q);
2065 wake_up_interruptible(&info->event_wait_q);
2066 info->pending_bh |= BH_STATUS;
2067 }
2068
2069 static void cts_change(struct slgt_info *info, unsigned short status)
2070 {
2071 if (status & BIT2) {
2072 info->signals |= SerialSignal_CTS;
2073 info->input_signal_events.cts_up++;
2074 } else {
2075 info->signals &= ~SerialSignal_CTS;
2076 info->input_signal_events.cts_down++;
2077 }
2078 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2079 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2080 slgt_irq_off(info, IRQ_CTS);
2081 return;
2082 }
2083 info->icount.cts++;
2084 wake_up_interruptible(&info->status_event_wait_q);
2085 wake_up_interruptible(&info->event_wait_q);
2086 info->pending_bh |= BH_STATUS;
2087
2088 if (info->port.flags & ASYNC_CTS_FLOW) {
2089 if (info->port.tty) {
2090 if (info->port.tty->hw_stopped) {
2091 if (info->signals & SerialSignal_CTS) {
2092 info->port.tty->hw_stopped = 0;
2093 info->pending_bh |= BH_TRANSMIT;
2094 return;
2095 }
2096 } else {
2097 if (!(info->signals & SerialSignal_CTS))
2098 info->port.tty->hw_stopped = 1;
2099 }
2100 }
2101 }
2102 }
2103
2104 static void dcd_change(struct slgt_info *info, unsigned short status)
2105 {
2106 if (status & BIT1) {
2107 info->signals |= SerialSignal_DCD;
2108 info->input_signal_events.dcd_up++;
2109 } else {
2110 info->signals &= ~SerialSignal_DCD;
2111 info->input_signal_events.dcd_down++;
2112 }
2113 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2114 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2115 slgt_irq_off(info, IRQ_DCD);
2116 return;
2117 }
2118 info->icount.dcd++;
2119 #if SYNCLINK_GENERIC_HDLC
2120 if (info->netcount) {
2121 if (info->signals & SerialSignal_DCD)
2122 netif_carrier_on(info->netdev);
2123 else
2124 netif_carrier_off(info->netdev);
2125 }
2126 #endif
2127 wake_up_interruptible(&info->status_event_wait_q);
2128 wake_up_interruptible(&info->event_wait_q);
2129 info->pending_bh |= BH_STATUS;
2130
2131 if (info->port.flags & ASYNC_CHECK_CD) {
2132 if (info->signals & SerialSignal_DCD)
2133 wake_up_interruptible(&info->port.open_wait);
2134 else {
2135 if (info->port.tty)
2136 tty_hangup(info->port.tty);
2137 }
2138 }
2139 }
2140
2141 static void ri_change(struct slgt_info *info, unsigned short status)
2142 {
2143 if (status & BIT0) {
2144 info->signals |= SerialSignal_RI;
2145 info->input_signal_events.ri_up++;
2146 } else {
2147 info->signals &= ~SerialSignal_RI;
2148 info->input_signal_events.ri_down++;
2149 }
2150 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2151 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2152 slgt_irq_off(info, IRQ_RI);
2153 return;
2154 }
2155 info->icount.rng++;
2156 wake_up_interruptible(&info->status_event_wait_q);
2157 wake_up_interruptible(&info->event_wait_q);
2158 info->pending_bh |= BH_STATUS;
2159 }
2160
2161 static void isr_serial(struct slgt_info *info)
2162 {
2163 unsigned short status = rd_reg16(info, SSR);
2164
2165 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2166
2167 wr_reg16(info, SSR, status); /* clear pending */
2168
2169 info->irq_occurred = true;
2170
2171 if (info->params.mode == MGSL_MODE_ASYNC) {
2172 if (status & IRQ_TXIDLE) {
2173 if (info->tx_count)
2174 isr_txeom(info, status);
2175 }
2176 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2177 info->icount.brk++;
2178 /* process break detection if tty control allows */
2179 if (info->port.tty) {
2180 if (!(status & info->ignore_status_mask)) {
2181 if (info->read_status_mask & MASK_BREAK) {
2182 tty_insert_flip_char(info->port.tty, 0, TTY_BREAK);
2183 if (info->port.flags & ASYNC_SAK)
2184 do_SAK(info->port.tty);
2185 }
2186 }
2187 }
2188 }
2189 } else {
2190 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2191 isr_txeom(info, status);
2192
2193 if (status & IRQ_RXIDLE) {
2194 if (status & RXIDLE)
2195 info->icount.rxidle++;
2196 else
2197 info->icount.exithunt++;
2198 wake_up_interruptible(&info->event_wait_q);
2199 }
2200
2201 if (status & IRQ_RXOVER)
2202 rx_start(info);
2203 }
2204
2205 if (status & IRQ_DSR)
2206 dsr_change(info, status);
2207 if (status & IRQ_CTS)
2208 cts_change(info, status);
2209 if (status & IRQ_DCD)
2210 dcd_change(info, status);
2211 if (status & IRQ_RI)
2212 ri_change(info, status);
2213 }
2214
2215 static void isr_rdma(struct slgt_info *info)
2216 {
2217 unsigned int status = rd_reg32(info, RDCSR);
2218
2219 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2220
2221 /* RDCSR (rx DMA control/status)
2222 *
2223 * 31..07 reserved
2224 * 06 save status byte to DMA buffer
2225 * 05 error
2226 * 04 eol (end of list)
2227 * 03 eob (end of buffer)
2228 * 02 IRQ enable
2229 * 01 reset
2230 * 00 enable
2231 */
2232 wr_reg32(info, RDCSR, status); /* clear pending */
2233
2234 if (status & (BIT5 + BIT4)) {
2235 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2236 info->rx_restart = true;
2237 }
2238 info->pending_bh |= BH_RECEIVE;
2239 }
2240
2241 static void isr_tdma(struct slgt_info *info)
2242 {
2243 unsigned int status = rd_reg32(info, TDCSR);
2244
2245 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2246
2247 /* TDCSR (tx DMA control/status)
2248 *
2249 * 31..06 reserved
2250 * 05 error
2251 * 04 eol (end of list)
2252 * 03 eob (end of buffer)
2253 * 02 IRQ enable
2254 * 01 reset
2255 * 00 enable
2256 */
2257 wr_reg32(info, TDCSR, status); /* clear pending */
2258
2259 if (status & (BIT5 + BIT4 + BIT3)) {
2260 // another transmit buffer has completed
2261 // run bottom half to get more send data from user
2262 info->pending_bh |= BH_TRANSMIT;
2263 }
2264 }
2265
2266 static void isr_txeom(struct slgt_info *info, unsigned short status)
2267 {
2268 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2269
2270 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2271 tdma_reset(info);
2272 reset_tbufs(info);
2273 if (status & IRQ_TXUNDER) {
2274 unsigned short val = rd_reg16(info, TCR);
2275 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2276 wr_reg16(info, TCR, val); /* clear reset bit */
2277 }
2278
2279 if (info->tx_active) {
2280 if (info->params.mode != MGSL_MODE_ASYNC) {
2281 if (status & IRQ_TXUNDER)
2282 info->icount.txunder++;
2283 else if (status & IRQ_TXIDLE)
2284 info->icount.txok++;
2285 }
2286
2287 info->tx_active = false;
2288 info->tx_count = 0;
2289
2290 del_timer(&info->tx_timer);
2291
2292 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2293 info->signals &= ~SerialSignal_RTS;
2294 info->drop_rts_on_tx_done = false;
2295 set_signals(info);
2296 }
2297
2298 #if SYNCLINK_GENERIC_HDLC
2299 if (info->netcount)
2300 hdlcdev_tx_done(info);
2301 else
2302 #endif
2303 {
2304 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2305 tx_stop(info);
2306 return;
2307 }
2308 info->pending_bh |= BH_TRANSMIT;
2309 }
2310 }
2311 }
2312
2313 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2314 {
2315 struct cond_wait *w, *prev;
2316
2317 /* wake processes waiting for specific transitions */
2318 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2319 if (w->data & changed) {
2320 w->data = state;
2321 wake_up_interruptible(&w->q);
2322 if (prev != NULL)
2323 prev->next = w->next;
2324 else
2325 info->gpio_wait_q = w->next;
2326 } else
2327 prev = w;
2328 }
2329 }
2330
2331 /* interrupt service routine
2332 *
2333 * irq interrupt number
2334 * dev_id device ID supplied during interrupt registration
2335 */
2336 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2337 {
2338 struct slgt_info *info = dev_id;
2339 unsigned int gsr;
2340 unsigned int i;
2341
2342 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2343
2344 spin_lock(&info->lock);
2345
2346 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2347 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2348 info->irq_occurred = true;
2349 for(i=0; i < info->port_count ; i++) {
2350 if (info->port_array[i] == NULL)
2351 continue;
2352 if (gsr & (BIT8 << i))
2353 isr_serial(info->port_array[i]);
2354 if (gsr & (BIT16 << (i*2)))
2355 isr_rdma(info->port_array[i]);
2356 if (gsr & (BIT17 << (i*2)))
2357 isr_tdma(info->port_array[i]);
2358 }
2359 }
2360
2361 if (info->gpio_present) {
2362 unsigned int state;
2363 unsigned int changed;
2364 while ((changed = rd_reg32(info, IOSR)) != 0) {
2365 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2366 /* read latched state of GPIO signals */
2367 state = rd_reg32(info, IOVR);
2368 /* clear pending GPIO interrupt bits */
2369 wr_reg32(info, IOSR, changed);
2370 for (i=0 ; i < info->port_count ; i++) {
2371 if (info->port_array[i] != NULL)
2372 isr_gpio(info->port_array[i], changed, state);
2373 }
2374 }
2375 }
2376
2377 for(i=0; i < info->port_count ; i++) {
2378 struct slgt_info *port = info->port_array[i];
2379
2380 if (port && (port->port.count || port->netcount) &&
2381 port->pending_bh && !port->bh_running &&
2382 !port->bh_requested) {
2383 DBGISR(("%s bh queued\n", port->device_name));
2384 schedule_work(&port->task);
2385 port->bh_requested = true;
2386 }
2387 }
2388
2389 spin_unlock(&info->lock);
2390
2391 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2392 return IRQ_HANDLED;
2393 }
2394
2395 static int startup(struct slgt_info *info)
2396 {
2397 DBGINFO(("%s startup\n", info->device_name));
2398
2399 if (info->port.flags & ASYNC_INITIALIZED)
2400 return 0;
2401
2402 if (!info->tx_buf) {
2403 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2404 if (!info->tx_buf) {
2405 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2406 return -ENOMEM;
2407 }
2408 }
2409
2410 info->pending_bh = 0;
2411
2412 memset(&info->icount, 0, sizeof(info->icount));
2413
2414 /* program hardware for current parameters */
2415 change_params(info);
2416
2417 if (info->port.tty)
2418 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2419
2420 info->port.flags |= ASYNC_INITIALIZED;
2421
2422 return 0;
2423 }
2424
2425 /*
2426 * called by close() and hangup() to shutdown hardware
2427 */
2428 static void shutdown(struct slgt_info *info)
2429 {
2430 unsigned long flags;
2431
2432 if (!(info->port.flags & ASYNC_INITIALIZED))
2433 return;
2434
2435 DBGINFO(("%s shutdown\n", info->device_name));
2436
2437 /* clear status wait queue because status changes */
2438 /* can't happen after shutting down the hardware */
2439 wake_up_interruptible(&info->status_event_wait_q);
2440 wake_up_interruptible(&info->event_wait_q);
2441
2442 del_timer_sync(&info->tx_timer);
2443 del_timer_sync(&info->rx_timer);
2444
2445 kfree(info->tx_buf);
2446 info->tx_buf = NULL;
2447
2448 spin_lock_irqsave(&info->lock,flags);
2449
2450 tx_stop(info);
2451 rx_stop(info);
2452
2453 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2454
2455 if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2456 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2457 set_signals(info);
2458 }
2459
2460 flush_cond_wait(&info->gpio_wait_q);
2461
2462 spin_unlock_irqrestore(&info->lock,flags);
2463
2464 if (info->port.tty)
2465 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2466
2467 info->port.flags &= ~ASYNC_INITIALIZED;
2468 }
2469
2470 static void program_hw(struct slgt_info *info)
2471 {
2472 unsigned long flags;
2473
2474 spin_lock_irqsave(&info->lock,flags);
2475
2476 rx_stop(info);
2477 tx_stop(info);
2478
2479 if (info->params.mode != MGSL_MODE_ASYNC ||
2480 info->netcount)
2481 sync_mode(info);
2482 else
2483 async_mode(info);
2484
2485 set_signals(info);
2486
2487 info->dcd_chkcount = 0;
2488 info->cts_chkcount = 0;
2489 info->ri_chkcount = 0;
2490 info->dsr_chkcount = 0;
2491
2492 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR);
2493 get_signals(info);
2494
2495 if (info->netcount ||
2496 (info->port.tty && info->port.tty->termios->c_cflag & CREAD))
2497 rx_start(info);
2498
2499 spin_unlock_irqrestore(&info->lock,flags);
2500 }
2501
2502 /*
2503 * reconfigure adapter based on new parameters
2504 */
2505 static void change_params(struct slgt_info *info)
2506 {
2507 unsigned cflag;
2508 int bits_per_char;
2509
2510 if (!info->port.tty || !info->port.tty->termios)
2511 return;
2512 DBGINFO(("%s change_params\n", info->device_name));
2513
2514 cflag = info->port.tty->termios->c_cflag;
2515
2516 /* if B0 rate (hangup) specified then negate DTR and RTS */
2517 /* otherwise assert DTR and RTS */
2518 if (cflag & CBAUD)
2519 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2520 else
2521 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2522
2523 /* byte size and parity */
2524
2525 switch (cflag & CSIZE) {
2526 case CS5: info->params.data_bits = 5; break;
2527 case CS6: info->params.data_bits = 6; break;
2528 case CS7: info->params.data_bits = 7; break;
2529 case CS8: info->params.data_bits = 8; break;
2530 default: info->params.data_bits = 7; break;
2531 }
2532
2533 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2534
2535 if (cflag & PARENB)
2536 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2537 else
2538 info->params.parity = ASYNC_PARITY_NONE;
2539
2540 /* calculate number of jiffies to transmit a full
2541 * FIFO (32 bytes) at specified data rate
2542 */
2543 bits_per_char = info->params.data_bits +
2544 info->params.stop_bits + 1;
2545
2546 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2547
2548 if (info->params.data_rate) {
2549 info->timeout = (32*HZ*bits_per_char) /
2550 info->params.data_rate;
2551 }
2552 info->timeout += HZ/50; /* Add .02 seconds of slop */
2553
2554 if (cflag & CRTSCTS)
2555 info->port.flags |= ASYNC_CTS_FLOW;
2556 else
2557 info->port.flags &= ~ASYNC_CTS_FLOW;
2558
2559 if (cflag & CLOCAL)
2560 info->port.flags &= ~ASYNC_CHECK_CD;
2561 else
2562 info->port.flags |= ASYNC_CHECK_CD;
2563
2564 /* process tty input control flags */
2565
2566 info->read_status_mask = IRQ_RXOVER;
2567 if (I_INPCK(info->port.tty))
2568 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2569 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2570 info->read_status_mask |= MASK_BREAK;
2571 if (I_IGNPAR(info->port.tty))
2572 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2573 if (I_IGNBRK(info->port.tty)) {
2574 info->ignore_status_mask |= MASK_BREAK;
2575 /* If ignoring parity and break indicators, ignore
2576 * overruns too. (For real raw support).
2577 */
2578 if (I_IGNPAR(info->port.tty))
2579 info->ignore_status_mask |= MASK_OVERRUN;
2580 }
2581
2582 program_hw(info);
2583 }
2584
2585 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2586 {
2587 DBGINFO(("%s get_stats\n", info->device_name));
2588 if (!user_icount) {
2589 memset(&info->icount, 0, sizeof(info->icount));
2590 } else {
2591 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2592 return -EFAULT;
2593 }
2594 return 0;
2595 }
2596
2597 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2598 {
2599 DBGINFO(("%s get_params\n", info->device_name));
2600 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2601 return -EFAULT;
2602 return 0;
2603 }
2604
2605 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2606 {
2607 unsigned long flags;
2608 MGSL_PARAMS tmp_params;
2609
2610 DBGINFO(("%s set_params\n", info->device_name));
2611 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2612 return -EFAULT;
2613
2614 spin_lock_irqsave(&info->lock, flags);
2615 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2616 spin_unlock_irqrestore(&info->lock, flags);
2617
2618 change_params(info);
2619
2620 return 0;
2621 }
2622
2623 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2624 {
2625 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2626 if (put_user(info->idle_mode, idle_mode))
2627 return -EFAULT;
2628 return 0;
2629 }
2630
2631 static int set_txidle(struct slgt_info *info, int idle_mode)
2632 {
2633 unsigned long flags;
2634 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2635 spin_lock_irqsave(&info->lock,flags);
2636 info->idle_mode = idle_mode;
2637 if (info->params.mode != MGSL_MODE_ASYNC)
2638 tx_set_idle(info);
2639 spin_unlock_irqrestore(&info->lock,flags);
2640 return 0;
2641 }
2642
2643 static int tx_enable(struct slgt_info *info, int enable)
2644 {
2645 unsigned long flags;
2646 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2647 spin_lock_irqsave(&info->lock,flags);
2648 if (enable) {
2649 if (!info->tx_enabled)
2650 tx_start(info);
2651 } else {
2652 if (info->tx_enabled)
2653 tx_stop(info);
2654 }
2655 spin_unlock_irqrestore(&info->lock,flags);
2656 return 0;
2657 }
2658
2659 /*
2660 * abort transmit HDLC frame
2661 */
2662 static int tx_abort(struct slgt_info *info)
2663 {
2664 unsigned long flags;
2665 DBGINFO(("%s tx_abort\n", info->device_name));
2666 spin_lock_irqsave(&info->lock,flags);
2667 tdma_reset(info);
2668 spin_unlock_irqrestore(&info->lock,flags);
2669 return 0;
2670 }
2671
2672 static int rx_enable(struct slgt_info *info, int enable)
2673 {
2674 unsigned long flags;
2675 unsigned int rbuf_fill_level;
2676 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2677 spin_lock_irqsave(&info->lock,flags);
2678 /*
2679 * enable[31..16] = receive DMA buffer fill level
2680 * 0 = noop (leave fill level unchanged)
2681 * fill level must be multiple of 4 and <= buffer size
2682 */
2683 rbuf_fill_level = ((unsigned int)enable) >> 16;
2684 if (rbuf_fill_level) {
2685 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2686 spin_unlock_irqrestore(&info->lock, flags);
2687 return -EINVAL;
2688 }
2689 info->rbuf_fill_level = rbuf_fill_level;
2690 rx_stop(info); /* restart receiver to use new fill level */
2691 }
2692
2693 /*
2694 * enable[1..0] = receiver enable command
2695 * 0 = disable
2696 * 1 = enable
2697 * 2 = enable or force hunt mode if already enabled
2698 */
2699 enable &= 3;
2700 if (enable) {
2701 if (!info->rx_enabled)
2702 rx_start(info);
2703 else if (enable == 2) {
2704 /* force hunt mode (write 1 to RCR[3]) */
2705 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2706 }
2707 } else {
2708 if (info->rx_enabled)
2709 rx_stop(info);
2710 }
2711 spin_unlock_irqrestore(&info->lock,flags);
2712 return 0;
2713 }
2714
2715 /*
2716 * wait for specified event to occur
2717 */
2718 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2719 {
2720 unsigned long flags;
2721 int s;
2722 int rc=0;
2723 struct mgsl_icount cprev, cnow;
2724 int events;
2725 int mask;
2726 struct _input_signal_events oldsigs, newsigs;
2727 DECLARE_WAITQUEUE(wait, current);
2728
2729 if (get_user(mask, mask_ptr))
2730 return -EFAULT;
2731
2732 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2733
2734 spin_lock_irqsave(&info->lock,flags);
2735
2736 /* return immediately if state matches requested events */
2737 get_signals(info);
2738 s = info->signals;
2739
2740 events = mask &
2741 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2742 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2743 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2744 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2745 if (events) {
2746 spin_unlock_irqrestore(&info->lock,flags);
2747 goto exit;
2748 }
2749
2750 /* save current irq counts */
2751 cprev = info->icount;
2752 oldsigs = info->input_signal_events;
2753
2754 /* enable hunt and idle irqs if needed */
2755 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2756 unsigned short val = rd_reg16(info, SCR);
2757 if (!(val & IRQ_RXIDLE))
2758 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2759 }
2760
2761 set_current_state(TASK_INTERRUPTIBLE);
2762 add_wait_queue(&info->event_wait_q, &wait);
2763
2764 spin_unlock_irqrestore(&info->lock,flags);
2765
2766 for(;;) {
2767 schedule();
2768 if (signal_pending(current)) {
2769 rc = -ERESTARTSYS;
2770 break;
2771 }
2772
2773 /* get current irq counts */
2774 spin_lock_irqsave(&info->lock,flags);
2775 cnow = info->icount;
2776 newsigs = info->input_signal_events;
2777 set_current_state(TASK_INTERRUPTIBLE);
2778 spin_unlock_irqrestore(&info->lock,flags);
2779
2780 /* if no change, wait aborted for some reason */
2781 if (newsigs.dsr_up == oldsigs.dsr_up &&
2782 newsigs.dsr_down == oldsigs.dsr_down &&
2783 newsigs.dcd_up == oldsigs.dcd_up &&
2784 newsigs.dcd_down == oldsigs.dcd_down &&
2785 newsigs.cts_up == oldsigs.cts_up &&
2786 newsigs.cts_down == oldsigs.cts_down &&
2787 newsigs.ri_up == oldsigs.ri_up &&
2788 newsigs.ri_down == oldsigs.ri_down &&
2789 cnow.exithunt == cprev.exithunt &&
2790 cnow.rxidle == cprev.rxidle) {
2791 rc = -EIO;
2792 break;
2793 }
2794
2795 events = mask &
2796 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2797 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2798 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2799 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2800 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2801 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2802 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2803 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2804 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2805 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2806 if (events)
2807 break;
2808
2809 cprev = cnow;
2810 oldsigs = newsigs;
2811 }
2812
2813 remove_wait_queue(&info->event_wait_q, &wait);
2814 set_current_state(TASK_RUNNING);
2815
2816
2817 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2818 spin_lock_irqsave(&info->lock,flags);
2819 if (!waitqueue_active(&info->event_wait_q)) {
2820 /* disable enable exit hunt mode/idle rcvd IRQs */
2821 wr_reg16(info, SCR,
2822 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2823 }
2824 spin_unlock_irqrestore(&info->lock,flags);
2825 }
2826 exit:
2827 if (rc == 0)
2828 rc = put_user(events, mask_ptr);
2829 return rc;
2830 }
2831
2832 static int get_interface(struct slgt_info *info, int __user *if_mode)
2833 {
2834 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2835 if (put_user(info->if_mode, if_mode))
2836 return -EFAULT;
2837 return 0;
2838 }
2839
2840 static int set_interface(struct slgt_info *info, int if_mode)
2841 {
2842 unsigned long flags;
2843 unsigned short val;
2844
2845 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2846 spin_lock_irqsave(&info->lock,flags);
2847 info->if_mode = if_mode;
2848
2849 msc_set_vcr(info);
2850
2851 /* TCR (tx control) 07 1=RTS driver control */
2852 val = rd_reg16(info, TCR);
2853 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2854 val |= BIT7;
2855 else
2856 val &= ~BIT7;
2857 wr_reg16(info, TCR, val);
2858
2859 spin_unlock_irqrestore(&info->lock,flags);
2860 return 0;
2861 }
2862
2863 /*
2864 * set general purpose IO pin state and direction
2865 *
2866 * user_gpio fields:
2867 * state each bit indicates a pin state
2868 * smask set bit indicates pin state to set
2869 * dir each bit indicates a pin direction (0=input, 1=output)
2870 * dmask set bit indicates pin direction to set
2871 */
2872 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2873 {
2874 unsigned long flags;
2875 struct gpio_desc gpio;
2876 __u32 data;
2877
2878 if (!info->gpio_present)
2879 return -EINVAL;
2880 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2881 return -EFAULT;
2882 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2883 info->device_name, gpio.state, gpio.smask,
2884 gpio.dir, gpio.dmask));
2885
2886 spin_lock_irqsave(&info->lock,flags);
2887 if (gpio.dmask) {
2888 data = rd_reg32(info, IODR);
2889 data |= gpio.dmask & gpio.dir;
2890 data &= ~(gpio.dmask & ~gpio.dir);
2891 wr_reg32(info, IODR, data);
2892 }
2893 if (gpio.smask) {
2894 data = rd_reg32(info, IOVR);
2895 data |= gpio.smask & gpio.state;
2896 data &= ~(gpio.smask & ~gpio.state);
2897 wr_reg32(info, IOVR, data);
2898 }
2899 spin_unlock_irqrestore(&info->lock,flags);
2900
2901 return 0;
2902 }
2903
2904 /*
2905 * get general purpose IO pin state and direction
2906 */
2907 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2908 {
2909 struct gpio_desc gpio;
2910 if (!info->gpio_present)
2911 return -EINVAL;
2912 gpio.state = rd_reg32(info, IOVR);
2913 gpio.smask = 0xffffffff;
2914 gpio.dir = rd_reg32(info, IODR);
2915 gpio.dmask = 0xffffffff;
2916 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2917 return -EFAULT;
2918 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2919 info->device_name, gpio.state, gpio.dir));
2920 return 0;
2921 }
2922
2923 /*
2924 * conditional wait facility
2925 */
2926 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2927 {
2928 init_waitqueue_head(&w->q);
2929 init_waitqueue_entry(&w->wait, current);
2930 w->data = data;
2931 }
2932
2933 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2934 {
2935 set_current_state(TASK_INTERRUPTIBLE);
2936 add_wait_queue(&w->q, &w->wait);
2937 w->next = *head;
2938 *head = w;
2939 }
2940
2941 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2942 {
2943 struct cond_wait *w, *prev;
2944 remove_wait_queue(&cw->q, &cw->wait);
2945 set_current_state(TASK_RUNNING);
2946 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2947 if (w == cw) {
2948 if (prev != NULL)
2949 prev->next = w->next;
2950 else
2951 *head = w->next;
2952 break;
2953 }
2954 }
2955 }
2956
2957 static void flush_cond_wait(struct cond_wait **head)
2958 {
2959 while (*head != NULL) {
2960 wake_up_interruptible(&(*head)->q);
2961 *head = (*head)->next;
2962 }
2963 }
2964
2965 /*
2966 * wait for general purpose I/O pin(s) to enter specified state
2967 *
2968 * user_gpio fields:
2969 * state - bit indicates target pin state
2970 * smask - set bit indicates watched pin
2971 *
2972 * The wait ends when at least one watched pin enters the specified
2973 * state. When 0 (no error) is returned, user_gpio->state is set to the
2974 * state of all GPIO pins when the wait ends.
2975 *
2976 * Note: Each pin may be a dedicated input, dedicated output, or
2977 * configurable input/output. The number and configuration of pins
2978 * varies with the specific adapter model. Only input pins (dedicated
2979 * or configured) can be monitored with this function.
2980 */
2981 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2982 {
2983 unsigned long flags;
2984 int rc = 0;
2985 struct gpio_desc gpio;
2986 struct cond_wait wait;
2987 u32 state;
2988
2989 if (!info->gpio_present)
2990 return -EINVAL;
2991 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2992 return -EFAULT;
2993 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2994 info->device_name, gpio.state, gpio.smask));
2995 /* ignore output pins identified by set IODR bit */
2996 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2997 return -EINVAL;
2998 init_cond_wait(&wait, gpio.smask);
2999
3000 spin_lock_irqsave(&info->lock, flags);
3001 /* enable interrupts for watched pins */
3002 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3003 /* get current pin states */
3004 state = rd_reg32(info, IOVR);
3005
3006 if (gpio.smask & ~(state ^ gpio.state)) {
3007 /* already in target state */
3008 gpio.state = state;
3009 } else {
3010 /* wait for target state */
3011 add_cond_wait(&info->gpio_wait_q, &wait);
3012 spin_unlock_irqrestore(&info->lock, flags);
3013 schedule();
3014 if (signal_pending(current))
3015 rc = -ERESTARTSYS;
3016 else
3017 gpio.state = wait.data;
3018 spin_lock_irqsave(&info->lock, flags);
3019 remove_cond_wait(&info->gpio_wait_q, &wait);
3020 }
3021
3022 /* disable all GPIO interrupts if no waiting processes */
3023 if (info->gpio_wait_q == NULL)
3024 wr_reg32(info, IOER, 0);
3025 spin_unlock_irqrestore(&info->lock,flags);
3026
3027 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3028 rc = -EFAULT;
3029 return rc;
3030 }
3031
3032 static int modem_input_wait(struct slgt_info *info,int arg)
3033 {
3034 unsigned long flags;
3035 int rc;
3036 struct mgsl_icount cprev, cnow;
3037 DECLARE_WAITQUEUE(wait, current);
3038
3039 /* save current irq counts */
3040 spin_lock_irqsave(&info->lock,flags);
3041 cprev = info->icount;
3042 add_wait_queue(&info->status_event_wait_q, &wait);
3043 set_current_state(TASK_INTERRUPTIBLE);
3044 spin_unlock_irqrestore(&info->lock,flags);
3045
3046 for(;;) {
3047 schedule();
3048 if (signal_pending(current)) {
3049 rc = -ERESTARTSYS;
3050 break;
3051 }
3052
3053 /* get new irq counts */
3054 spin_lock_irqsave(&info->lock,flags);
3055 cnow = info->icount;
3056 set_current_state(TASK_INTERRUPTIBLE);
3057 spin_unlock_irqrestore(&info->lock,flags);
3058
3059 /* if no change, wait aborted for some reason */
3060 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3061 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3062 rc = -EIO;
3063 break;
3064 }
3065
3066 /* check for change in caller specified modem input */
3067 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3068 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3069 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3070 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3071 rc = 0;
3072 break;
3073 }
3074
3075 cprev = cnow;
3076 }
3077 remove_wait_queue(&info->status_event_wait_q, &wait);
3078 set_current_state(TASK_RUNNING);
3079 return rc;
3080 }
3081
3082 /*
3083 * return state of serial control and status signals
3084 */
3085 static int tiocmget(struct tty_struct *tty, struct file *file)
3086 {
3087 struct slgt_info *info = tty->driver_data;
3088 unsigned int result;
3089 unsigned long flags;
3090
3091 spin_lock_irqsave(&info->lock,flags);
3092 get_signals(info);
3093 spin_unlock_irqrestore(&info->lock,flags);
3094
3095 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3096 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3097 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3098 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3099 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3100 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3101
3102 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3103 return result;
3104 }
3105
3106 /*
3107 * set modem control signals (DTR/RTS)
3108 *
3109 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3110 * TIOCMSET = set/clear signal values
3111 * value bit mask for command
3112 */
3113 static int tiocmset(struct tty_struct *tty, struct file *file,
3114 unsigned int set, unsigned int clear)
3115 {
3116 struct slgt_info *info = tty->driver_data;
3117 unsigned long flags;
3118
3119 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3120
3121 if (set & TIOCM_RTS)
3122 info->signals |= SerialSignal_RTS;
3123 if (set & TIOCM_DTR)
3124 info->signals |= SerialSignal_DTR;
3125 if (clear & TIOCM_RTS)
3126 info->signals &= ~SerialSignal_RTS;
3127 if (clear & TIOCM_DTR)
3128 info->signals &= ~SerialSignal_DTR;
3129
3130 spin_lock_irqsave(&info->lock,flags);
3131 set_signals(info);
3132 spin_unlock_irqrestore(&info->lock,flags);
3133 return 0;
3134 }
3135
3136 /*
3137 * block current process until the device is ready to open
3138 */
3139 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3140 struct slgt_info *info)
3141 {
3142 DECLARE_WAITQUEUE(wait, current);
3143 int retval;
3144 bool do_clocal = false;
3145 bool extra_count = false;
3146 unsigned long flags;
3147
3148 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3149
3150 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3151 /* nonblock mode is set or port is not enabled */
3152 info->port.flags |= ASYNC_NORMAL_ACTIVE;
3153 return 0;
3154 }
3155
3156 if (tty->termios->c_cflag & CLOCAL)
3157 do_clocal = true;
3158
3159 /* Wait for carrier detect and the line to become
3160 * free (i.e., not in use by the callout). While we are in
3161 * this loop, info->port.count is dropped by one, so that
3162 * close() knows when to free things. We restore it upon
3163 * exit, either normal or abnormal.
3164 */
3165
3166 retval = 0;
3167 add_wait_queue(&info->port.open_wait, &wait);
3168
3169 spin_lock_irqsave(&info->lock, flags);
3170 if (!tty_hung_up_p(filp)) {
3171 extra_count = true;
3172 info->port.count--;
3173 }
3174 spin_unlock_irqrestore(&info->lock, flags);
3175 info->port.blocked_open++;
3176
3177 while (1) {
3178 if ((tty->termios->c_cflag & CBAUD)) {
3179 spin_lock_irqsave(&info->lock,flags);
3180 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3181 set_signals(info);
3182 spin_unlock_irqrestore(&info->lock,flags);
3183 }
3184
3185 set_current_state(TASK_INTERRUPTIBLE);
3186
3187 if (tty_hung_up_p(filp) || !(info->port.flags & ASYNC_INITIALIZED)){
3188 retval = (info->port.flags & ASYNC_HUP_NOTIFY) ?
3189 -EAGAIN : -ERESTARTSYS;
3190 break;
3191 }
3192
3193 spin_lock_irqsave(&info->lock,flags);
3194 get_signals(info);
3195 spin_unlock_irqrestore(&info->lock,flags);
3196
3197 if (!(info->port.flags & ASYNC_CLOSING) &&
3198 (do_clocal || (info->signals & SerialSignal_DCD)) ) {
3199 break;
3200 }
3201
3202 if (signal_pending(current)) {
3203 retval = -ERESTARTSYS;
3204 break;
3205 }
3206
3207 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3208 schedule();
3209 }
3210
3211 set_current_state(TASK_RUNNING);
3212 remove_wait_queue(&info->port.open_wait, &wait);
3213
3214 if (extra_count)
3215 info->port.count++;
3216 info->port.blocked_open--;
3217
3218 if (!retval)
3219 info->port.flags |= ASYNC_NORMAL_ACTIVE;
3220
3221 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3222 return retval;
3223 }
3224
3225 static int alloc_tmp_rbuf(struct slgt_info *info)
3226 {
3227 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3228 if (info->tmp_rbuf == NULL)
3229 return -ENOMEM;
3230 return 0;
3231 }
3232
3233 static void free_tmp_rbuf(struct slgt_info *info)
3234 {
3235 kfree(info->tmp_rbuf);
3236 info->tmp_rbuf = NULL;
3237 }
3238
3239 /*
3240 * allocate DMA descriptor lists.
3241 */
3242 static int alloc_desc(struct slgt_info *info)
3243 {
3244 unsigned int i;
3245 unsigned int pbufs;
3246
3247 /* allocate memory to hold descriptor lists */
3248 info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3249 if (info->bufs == NULL)
3250 return -ENOMEM;
3251
3252 memset(info->bufs, 0, DESC_LIST_SIZE);
3253
3254 info->rbufs = (struct slgt_desc*)info->bufs;
3255 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3256
3257 pbufs = (unsigned int)info->bufs_dma_addr;
3258
3259 /*
3260 * Build circular lists of descriptors
3261 */
3262
3263 for (i=0; i < info->rbuf_count; i++) {
3264 /* physical address of this descriptor */
3265 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3266
3267 /* physical address of next descriptor */
3268 if (i == info->rbuf_count - 1)
3269 info->rbufs[i].next = cpu_to_le32(pbufs);
3270 else
3271 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3272 set_desc_count(info->rbufs[i], DMABUFSIZE);
3273 }
3274
3275 for (i=0; i < info->tbuf_count; i++) {
3276 /* physical address of this descriptor */
3277 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3278
3279 /* physical address of next descriptor */
3280 if (i == info->tbuf_count - 1)
3281 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3282 else
3283 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3284 }
3285
3286 return 0;
3287 }
3288
3289 static void free_desc(struct slgt_info *info)
3290 {
3291 if (info->bufs != NULL) {
3292 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3293 info->bufs = NULL;
3294 info->rbufs = NULL;
3295 info->tbufs = NULL;
3296 }
3297 }
3298
3299 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3300 {
3301 int i;
3302 for (i=0; i < count; i++) {
3303 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3304 return -ENOMEM;
3305 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3306 }
3307 return 0;
3308 }
3309
3310 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3311 {
3312 int i;
3313 for (i=0; i < count; i++) {
3314 if (bufs[i].buf == NULL)
3315 continue;
3316 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3317 bufs[i].buf = NULL;
3318 }
3319 }
3320
3321 static int alloc_dma_bufs(struct slgt_info *info)
3322 {
3323 info->rbuf_count = 32;
3324 info->tbuf_count = 32;
3325
3326 if (alloc_desc(info) < 0 ||
3327 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3328 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3329 alloc_tmp_rbuf(info) < 0) {
3330 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3331 return -ENOMEM;
3332 }
3333 reset_rbufs(info);
3334 return 0;
3335 }
3336
3337 static void free_dma_bufs(struct slgt_info *info)
3338 {
3339 if (info->bufs) {
3340 free_bufs(info, info->rbufs, info->rbuf_count);
3341 free_bufs(info, info->tbufs, info->tbuf_count);
3342 free_desc(info);
3343 }
3344 free_tmp_rbuf(info);
3345 }
3346
3347 static int claim_resources(struct slgt_info *info)
3348 {
3349 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3350 DBGERR(("%s reg addr conflict, addr=%08X\n",
3351 info->device_name, info->phys_reg_addr));
3352 info->init_error = DiagStatus_AddressConflict;
3353 goto errout;
3354 }
3355 else
3356 info->reg_addr_requested = true;
3357
3358 info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3359 if (!info->reg_addr) {
3360 DBGERR(("%s cant map device registers, addr=%08X\n",
3361 info->device_name, info->phys_reg_addr));
3362 info->init_error = DiagStatus_CantAssignPciResources;
3363 goto errout;
3364 }
3365 return 0;
3366
3367 errout:
3368 release_resources(info);
3369 return -ENODEV;
3370 }
3371
3372 static void release_resources(struct slgt_info *info)
3373 {
3374 if (info->irq_requested) {
3375 free_irq(info->irq_level, info);
3376 info->irq_requested = false;
3377 }
3378
3379 if (info->reg_addr_requested) {
3380 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3381 info->reg_addr_requested = false;
3382 }
3383
3384 if (info->reg_addr) {
3385 iounmap(info->reg_addr);
3386 info->reg_addr = NULL;
3387 }
3388 }
3389
3390 /* Add the specified device instance data structure to the
3391 * global linked list of devices and increment the device count.
3392 */
3393 static void add_device(struct slgt_info *info)
3394 {
3395 char *devstr;
3396
3397 info->next_device = NULL;
3398 info->line = slgt_device_count;
3399 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3400
3401 if (info->line < MAX_DEVICES) {
3402 if (maxframe[info->line])
3403 info->max_frame_size = maxframe[info->line];
3404 }
3405
3406 slgt_device_count++;
3407
3408 if (!slgt_device_list)
3409 slgt_device_list = info;
3410 else {
3411 struct slgt_info *current_dev = slgt_device_list;
3412 while(current_dev->next_device)
3413 current_dev = current_dev->next_device;
3414 current_dev->next_device = info;
3415 }
3416
3417 if (info->max_frame_size < 4096)
3418 info->max_frame_size = 4096;
3419 else if (info->max_frame_size > 65535)
3420 info->max_frame_size = 65535;
3421
3422 switch(info->pdev->device) {
3423 case SYNCLINK_GT_DEVICE_ID:
3424 devstr = "GT";
3425 break;
3426 case SYNCLINK_GT2_DEVICE_ID:
3427 devstr = "GT2";
3428 break;
3429 case SYNCLINK_GT4_DEVICE_ID:
3430 devstr = "GT4";
3431 break;
3432 case SYNCLINK_AC_DEVICE_ID:
3433 devstr = "AC";
3434 info->params.mode = MGSL_MODE_ASYNC;
3435 break;
3436 default:
3437 devstr = "(unknown model)";
3438 }
3439 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3440 devstr, info->device_name, info->phys_reg_addr,
3441 info->irq_level, info->max_frame_size);
3442
3443 #if SYNCLINK_GENERIC_HDLC
3444 hdlcdev_init(info);
3445 #endif
3446 }
3447
3448 /*
3449 * allocate device instance structure, return NULL on failure
3450 */
3451 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3452 {
3453 struct slgt_info *info;
3454
3455 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3456
3457 if (!info) {
3458 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3459 driver_name, adapter_num, port_num));
3460 } else {
3461 tty_port_init(&info->port);
3462 info->magic = MGSL_MAGIC;
3463 INIT_WORK(&info->task, bh_handler);
3464 info->max_frame_size = 4096;
3465 info->rbuf_fill_level = DMABUFSIZE;
3466 info->port.close_delay = 5*HZ/10;
3467 info->port.closing_wait = 30*HZ;
3468 init_waitqueue_head(&info->status_event_wait_q);
3469 init_waitqueue_head(&info->event_wait_q);
3470 spin_lock_init(&info->netlock);
3471 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3472 info->idle_mode = HDLC_TXIDLE_FLAGS;
3473 info->adapter_num = adapter_num;
3474 info->port_num = port_num;
3475
3476 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3477 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3478
3479 /* Copy configuration info to device instance data */
3480 info->pdev = pdev;
3481 info->irq_level = pdev->irq;
3482 info->phys_reg_addr = pci_resource_start(pdev,0);
3483
3484 info->bus_type = MGSL_BUS_TYPE_PCI;
3485 info->irq_flags = IRQF_SHARED;
3486
3487 info->init_error = -1; /* assume error, set to 0 on successful init */
3488 }
3489
3490 return info;
3491 }
3492
3493 static void device_init(int adapter_num, struct pci_dev *pdev)
3494 {
3495 struct slgt_info *port_array[SLGT_MAX_PORTS];
3496 int i;
3497 int port_count = 1;
3498
3499 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3500 port_count = 2;
3501 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3502 port_count = 4;
3503
3504 /* allocate device instances for all ports */
3505 for (i=0; i < port_count; ++i) {
3506 port_array[i] = alloc_dev(adapter_num, i, pdev);
3507 if (port_array[i] == NULL) {
3508 for (--i; i >= 0; --i)
3509 kfree(port_array[i]);
3510 return;
3511 }
3512 }
3513
3514 /* give copy of port_array to all ports and add to device list */
3515 for (i=0; i < port_count; ++i) {
3516 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3517 add_device(port_array[i]);
3518 port_array[i]->port_count = port_count;
3519 spin_lock_init(&port_array[i]->lock);
3520 }
3521
3522 /* Allocate and claim adapter resources */
3523 if (!claim_resources(port_array[0])) {
3524
3525 alloc_dma_bufs(port_array[0]);
3526
3527 /* copy resource information from first port to others */
3528 for (i = 1; i < port_count; ++i) {
3529 port_array[i]->lock = port_array[0]->lock;
3530 port_array[i]->irq_level = port_array[0]->irq_level;
3531 port_array[i]->reg_addr = port_array[0]->reg_addr;
3532 alloc_dma_bufs(port_array[i]);
3533 }
3534
3535 if (request_irq(port_array[0]->irq_level,
3536 slgt_interrupt,
3537 port_array[0]->irq_flags,
3538 port_array[0]->device_name,
3539 port_array[0]) < 0) {
3540 DBGERR(("%s request_irq failed IRQ=%d\n",
3541 port_array[0]->device_name,
3542 port_array[0]->irq_level));
3543 } else {
3544 port_array[0]->irq_requested = true;
3545 adapter_test(port_array[0]);
3546 for (i=1 ; i < port_count ; i++) {
3547 port_array[i]->init_error = port_array[0]->init_error;
3548 port_array[i]->gpio_present = port_array[0]->gpio_present;
3549 }
3550 }
3551 }
3552
3553 for (i=0; i < port_count; ++i)
3554 tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev));
3555 }
3556
3557 static int __devinit init_one(struct pci_dev *dev,
3558 const struct pci_device_id *ent)
3559 {
3560 if (pci_enable_device(dev)) {
3561 printk("error enabling pci device %p\n", dev);
3562 return -EIO;
3563 }
3564 pci_set_master(dev);
3565 device_init(slgt_device_count, dev);
3566 return 0;
3567 }
3568
3569 static void __devexit remove_one(struct pci_dev *dev)
3570 {
3571 }
3572
3573 static const struct tty_operations ops = {
3574 .open = open,
3575 .close = close,
3576 .write = write,
3577 .put_char = put_char,
3578 .flush_chars = flush_chars,
3579 .write_room = write_room,
3580 .chars_in_buffer = chars_in_buffer,
3581 .flush_buffer = flush_buffer,
3582 .ioctl = ioctl,
3583 .compat_ioctl = slgt_compat_ioctl,
3584 .throttle = throttle,
3585 .unthrottle = unthrottle,
3586 .send_xchar = send_xchar,
3587 .break_ctl = set_break,
3588 .wait_until_sent = wait_until_sent,
3589 .read_proc = read_proc,
3590 .set_termios = set_termios,
3591 .stop = tx_hold,
3592 .start = tx_release,
3593 .hangup = hangup,
3594 .tiocmget = tiocmget,
3595 .tiocmset = tiocmset,
3596 };
3597
3598 static void slgt_cleanup(void)
3599 {
3600 int rc;
3601 struct slgt_info *info;
3602 struct slgt_info *tmp;
3603
3604 printk("unload %s %s\n", driver_name, driver_version);
3605
3606 if (serial_driver) {
3607 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3608 tty_unregister_device(serial_driver, info->line);
3609 if ((rc = tty_unregister_driver(serial_driver)))
3610 DBGERR(("tty_unregister_driver error=%d\n", rc));
3611 put_tty_driver(serial_driver);
3612 }
3613
3614 /* reset devices */
3615 info = slgt_device_list;
3616 while(info) {
3617 reset_port(info);
3618 info = info->next_device;
3619 }
3620
3621 /* release devices */
3622 info = slgt_device_list;
3623 while(info) {
3624 #if SYNCLINK_GENERIC_HDLC
3625 hdlcdev_exit(info);
3626 #endif
3627 free_dma_bufs(info);
3628 free_tmp_rbuf(info);
3629 if (info->port_num == 0)
3630 release_resources(info);
3631 tmp = info;
3632 info = info->next_device;
3633 kfree(tmp);
3634 }
3635
3636 if (pci_registered)
3637 pci_unregister_driver(&pci_driver);
3638 }
3639
3640 /*
3641 * Driver initialization entry point.
3642 */
3643 static int __init slgt_init(void)
3644 {
3645 int rc;
3646
3647 printk("%s %s\n", driver_name, driver_version);
3648
3649 serial_driver = alloc_tty_driver(MAX_DEVICES);
3650 if (!serial_driver) {
3651 printk("%s can't allocate tty driver\n", driver_name);
3652 return -ENOMEM;
3653 }
3654
3655 /* Initialize the tty_driver structure */
3656
3657 serial_driver->owner = THIS_MODULE;
3658 serial_driver->driver_name = tty_driver_name;
3659 serial_driver->name = tty_dev_prefix;
3660 serial_driver->major = ttymajor;
3661 serial_driver->minor_start = 64;
3662 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3663 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3664 serial_driver->init_termios = tty_std_termios;
3665 serial_driver->init_termios.c_cflag =
3666 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3667 serial_driver->init_termios.c_ispeed = 9600;
3668 serial_driver->init_termios.c_ospeed = 9600;
3669 serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3670 tty_set_operations(serial_driver, &ops);
3671 if ((rc = tty_register_driver(serial_driver)) < 0) {
3672 DBGERR(("%s can't register serial driver\n", driver_name));
3673 put_tty_driver(serial_driver);
3674 serial_driver = NULL;
3675 goto error;
3676 }
3677
3678 printk("%s %s, tty major#%d\n",
3679 driver_name, driver_version,
3680 serial_driver->major);
3681
3682 slgt_device_count = 0;
3683 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3684 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3685 goto error;
3686 }
3687 pci_registered = true;
3688
3689 if (!slgt_device_list)
3690 printk("%s no devices found\n",driver_name);
3691
3692 return 0;
3693
3694 error:
3695 slgt_cleanup();
3696 return rc;
3697 }
3698
3699 static void __exit slgt_exit(void)
3700 {
3701 slgt_cleanup();
3702 }
3703
3704 module_init(slgt_init);
3705 module_exit(slgt_exit);
3706
3707 /*
3708 * register access routines
3709 */
3710
3711 #define CALC_REGADDR() \
3712 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3713 if (addr >= 0x80) \
3714 reg_addr += (info->port_num) * 32;
3715
3716 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3717 {
3718 CALC_REGADDR();
3719 return readb((void __iomem *)reg_addr);
3720 }
3721
3722 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3723 {
3724 CALC_REGADDR();
3725 writeb(value, (void __iomem *)reg_addr);
3726 }
3727
3728 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3729 {
3730 CALC_REGADDR();
3731 return readw((void __iomem *)reg_addr);
3732 }
3733
3734 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3735 {
3736 CALC_REGADDR();
3737 writew(value, (void __iomem *)reg_addr);
3738 }
3739
3740 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3741 {
3742 CALC_REGADDR();
3743 return readl((void __iomem *)reg_addr);
3744 }
3745
3746 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3747 {
3748 CALC_REGADDR();
3749 writel(value, (void __iomem *)reg_addr);
3750 }
3751
3752 static void rdma_reset(struct slgt_info *info)
3753 {
3754 unsigned int i;
3755
3756 /* set reset bit */
3757 wr_reg32(info, RDCSR, BIT1);
3758
3759 /* wait for enable bit cleared */
3760 for(i=0 ; i < 1000 ; i++)
3761 if (!(rd_reg32(info, RDCSR) & BIT0))
3762 break;
3763 }
3764
3765 static void tdma_reset(struct slgt_info *info)
3766 {
3767 unsigned int i;
3768
3769 /* set reset bit */
3770 wr_reg32(info, TDCSR, BIT1);
3771
3772 /* wait for enable bit cleared */
3773 for(i=0 ; i < 1000 ; i++)
3774 if (!(rd_reg32(info, TDCSR) & BIT0))
3775 break;
3776 }
3777
3778 /*
3779 * enable internal loopback
3780 * TxCLK and RxCLK are generated from BRG
3781 * and TxD is looped back to RxD internally.
3782 */
3783 static void enable_loopback(struct slgt_info *info)
3784 {
3785 /* SCR (serial control) BIT2=looopback enable */
3786 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3787
3788 if (info->params.mode != MGSL_MODE_ASYNC) {
3789 /* CCR (clock control)
3790 * 07..05 tx clock source (010 = BRG)
3791 * 04..02 rx clock source (010 = BRG)
3792 * 01 auxclk enable (0 = disable)
3793 * 00 BRG enable (1 = enable)
3794 *
3795 * 0100 1001
3796 */
3797 wr_reg8(info, CCR, 0x49);
3798
3799 /* set speed if available, otherwise use default */
3800 if (info->params.clock_speed)
3801 set_rate(info, info->params.clock_speed);
3802 else
3803 set_rate(info, 3686400);
3804 }
3805 }
3806
3807 /*
3808 * set baud rate generator to specified rate
3809 */
3810 static void set_rate(struct slgt_info *info, u32 rate)
3811 {
3812 unsigned int div;
3813 static unsigned int osc = 14745600;
3814
3815 /* div = osc/rate - 1
3816 *
3817 * Round div up if osc/rate is not integer to
3818 * force to next slowest rate.
3819 */
3820
3821 if (rate) {
3822 div = osc/rate;
3823 if (!(osc % rate) && div)
3824 div--;
3825 wr_reg16(info, BDR, (unsigned short)div);
3826 }
3827 }
3828
3829 static void rx_stop(struct slgt_info *info)
3830 {
3831 unsigned short val;
3832
3833 /* disable and reset receiver */
3834 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3835 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3836 wr_reg16(info, RCR, val); /* clear reset bit */
3837
3838 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3839
3840 /* clear pending rx interrupts */
3841 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3842
3843 rdma_reset(info);
3844
3845 info->rx_enabled = false;
3846 info->rx_restart = false;
3847 }
3848
3849 static void rx_start(struct slgt_info *info)
3850 {
3851 unsigned short val;
3852
3853 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3854
3855 /* clear pending rx overrun IRQ */
3856 wr_reg16(info, SSR, IRQ_RXOVER);
3857
3858 /* reset and disable receiver */
3859 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3860 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3861 wr_reg16(info, RCR, val); /* clear reset bit */
3862
3863 rdma_reset(info);
3864 reset_rbufs(info);
3865
3866 /* set 1st descriptor address */
3867 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3868
3869 if (info->params.mode != MGSL_MODE_ASYNC) {
3870 /* enable rx DMA and DMA interrupt */
3871 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3872 } else {
3873 /* enable saving of rx status, rx DMA and DMA interrupt */
3874 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3875 }
3876
3877 slgt_irq_on(info, IRQ_RXOVER);
3878
3879 /* enable receiver */
3880 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3881
3882 info->rx_restart = false;
3883 info->rx_enabled = true;
3884 }
3885
3886 static void tx_start(struct slgt_info *info)
3887 {
3888 if (!info->tx_enabled) {
3889 wr_reg16(info, TCR,
3890 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3891 info->tx_enabled = true;
3892 }
3893
3894 if (info->tx_count) {
3895 info->drop_rts_on_tx_done = false;
3896
3897 if (info->params.mode != MGSL_MODE_ASYNC) {
3898 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3899 get_signals(info);
3900 if (!(info->signals & SerialSignal_RTS)) {
3901 info->signals |= SerialSignal_RTS;
3902 set_signals(info);
3903 info->drop_rts_on_tx_done = true;
3904 }
3905 }
3906
3907 slgt_irq_off(info, IRQ_TXDATA);
3908 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3909 /* clear tx idle and underrun status bits */
3910 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3911 if (info->params.mode == MGSL_MODE_HDLC)
3912 mod_timer(&info->tx_timer, jiffies +
3913 msecs_to_jiffies(5000));
3914 } else {
3915 slgt_irq_off(info, IRQ_TXDATA);
3916 slgt_irq_on(info, IRQ_TXIDLE);
3917 /* clear tx idle status bit */
3918 wr_reg16(info, SSR, IRQ_TXIDLE);
3919 }
3920 tdma_start(info);
3921 info->tx_active = true;
3922 }
3923 }
3924
3925 /*
3926 * start transmit DMA if inactive and there are unsent buffers
3927 */
3928 static void tdma_start(struct slgt_info *info)
3929 {
3930 unsigned int i;
3931
3932 if (rd_reg32(info, TDCSR) & BIT0)
3933 return;
3934
3935 /* transmit DMA inactive, check for unsent buffers */
3936 i = info->tbuf_start;
3937 while (!desc_count(info->tbufs[i])) {
3938 if (++i == info->tbuf_count)
3939 i = 0;
3940 if (i == info->tbuf_current)
3941 return;
3942 }
3943 info->tbuf_start = i;
3944
3945 /* there are unsent buffers, start transmit DMA */
3946
3947 /* reset needed if previous error condition */
3948 tdma_reset(info);
3949
3950 /* set 1st descriptor address */
3951 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3952 wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3953 }
3954
3955 static void tx_stop(struct slgt_info *info)
3956 {
3957 unsigned short val;
3958
3959 del_timer(&info->tx_timer);
3960
3961 tdma_reset(info);
3962
3963 /* reset and disable transmitter */
3964 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
3965 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3966
3967 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3968
3969 /* clear tx idle and underrun status bit */
3970 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3971
3972 reset_tbufs(info);
3973
3974 info->tx_enabled = false;
3975 info->tx_active = false;
3976 }
3977
3978 static void reset_port(struct slgt_info *info)
3979 {
3980 if (!info->reg_addr)
3981 return;
3982
3983 tx_stop(info);
3984 rx_stop(info);
3985
3986 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
3987 set_signals(info);
3988
3989 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3990 }
3991
3992 static void reset_adapter(struct slgt_info *info)
3993 {
3994 int i;
3995 for (i=0; i < info->port_count; ++i) {
3996 if (info->port_array[i])
3997 reset_port(info->port_array[i]);
3998 }
3999 }
4000
4001 static void async_mode(struct slgt_info *info)
4002 {
4003 unsigned short val;
4004
4005 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4006 tx_stop(info);
4007 rx_stop(info);
4008
4009 /* TCR (tx control)
4010 *
4011 * 15..13 mode, 010=async
4012 * 12..10 encoding, 000=NRZ
4013 * 09 parity enable
4014 * 08 1=odd parity, 0=even parity
4015 * 07 1=RTS driver control
4016 * 06 1=break enable
4017 * 05..04 character length
4018 * 00=5 bits
4019 * 01=6 bits
4020 * 10=7 bits
4021 * 11=8 bits
4022 * 03 0=1 stop bit, 1=2 stop bits
4023 * 02 reset
4024 * 01 enable
4025 * 00 auto-CTS enable
4026 */
4027 val = 0x4000;
4028
4029 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4030 val |= BIT7;
4031
4032 if (info->params.parity != ASYNC_PARITY_NONE) {
4033 val |= BIT9;
4034 if (info->params.parity == ASYNC_PARITY_ODD)
4035 val |= BIT8;
4036 }
4037
4038 switch (info->params.data_bits)
4039 {
4040 case 6: val |= BIT4; break;
4041 case 7: val |= BIT5; break;
4042 case 8: val |= BIT5 + BIT4; break;
4043 }
4044
4045 if (info->params.stop_bits != 1)
4046 val |= BIT3;
4047
4048 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4049 val |= BIT0;
4050
4051 wr_reg16(info, TCR, val);
4052
4053 /* RCR (rx control)
4054 *
4055 * 15..13 mode, 010=async
4056 * 12..10 encoding, 000=NRZ
4057 * 09 parity enable
4058 * 08 1=odd parity, 0=even parity
4059 * 07..06 reserved, must be 0
4060 * 05..04 character length
4061 * 00=5 bits
4062 * 01=6 bits
4063 * 10=7 bits
4064 * 11=8 bits
4065 * 03 reserved, must be zero
4066 * 02 reset
4067 * 01 enable
4068 * 00 auto-DCD enable
4069 */
4070 val = 0x4000;
4071
4072 if (info->params.parity != ASYNC_PARITY_NONE) {
4073 val |= BIT9;
4074 if (info->params.parity == ASYNC_PARITY_ODD)
4075 val |= BIT8;
4076 }
4077
4078 switch (info->params.data_bits)
4079 {
4080 case 6: val |= BIT4; break;
4081 case 7: val |= BIT5; break;
4082 case 8: val |= BIT5 + BIT4; break;
4083 }
4084
4085 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4086 val |= BIT0;
4087
4088 wr_reg16(info, RCR, val);
4089
4090 /* CCR (clock control)
4091 *
4092 * 07..05 011 = tx clock source is BRG/16
4093 * 04..02 010 = rx clock source is BRG
4094 * 01 0 = auxclk disabled
4095 * 00 1 = BRG enabled
4096 *
4097 * 0110 1001
4098 */
4099 wr_reg8(info, CCR, 0x69);
4100
4101 msc_set_vcr(info);
4102
4103 /* SCR (serial control)
4104 *
4105 * 15 1=tx req on FIFO half empty
4106 * 14 1=rx req on FIFO half full
4107 * 13 tx data IRQ enable
4108 * 12 tx idle IRQ enable
4109 * 11 rx break on IRQ enable
4110 * 10 rx data IRQ enable
4111 * 09 rx break off IRQ enable
4112 * 08 overrun IRQ enable
4113 * 07 DSR IRQ enable
4114 * 06 CTS IRQ enable
4115 * 05 DCD IRQ enable
4116 * 04 RI IRQ enable
4117 * 03 reserved, must be zero
4118 * 02 1=txd->rxd internal loopback enable
4119 * 01 reserved, must be zero
4120 * 00 1=master IRQ enable
4121 */
4122 val = BIT15 + BIT14 + BIT0;
4123 wr_reg16(info, SCR, val);
4124
4125 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4126
4127 set_rate(info, info->params.data_rate * 16);
4128
4129 if (info->params.loopback)
4130 enable_loopback(info);
4131 }
4132
4133 static void sync_mode(struct slgt_info *info)
4134 {
4135 unsigned short val;
4136
4137 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4138 tx_stop(info);
4139 rx_stop(info);
4140
4141 /* TCR (tx control)
4142 *
4143 * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4144 * 12..10 encoding
4145 * 09 CRC enable
4146 * 08 CRC32
4147 * 07 1=RTS driver control
4148 * 06 preamble enable
4149 * 05..04 preamble length
4150 * 03 share open/close flag
4151 * 02 reset
4152 * 01 enable
4153 * 00 auto-CTS enable
4154 */
4155 val = BIT2;
4156
4157 switch(info->params.mode) {
4158 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4159 case MGSL_MODE_BISYNC: val |= BIT15; break;
4160 case MGSL_MODE_RAW: val |= BIT13; break;
4161 }
4162 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4163 val |= BIT7;
4164
4165 switch(info->params.encoding)
4166 {
4167 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4168 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4169 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4170 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4171 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4172 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4173 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4174 }
4175
4176 switch (info->params.crc_type & HDLC_CRC_MASK)
4177 {
4178 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4179 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4180 }
4181
4182 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4183 val |= BIT6;
4184
4185 switch (info->params.preamble_length)
4186 {
4187 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4188 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4189 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4190 }
4191
4192 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4193 val |= BIT0;
4194
4195 wr_reg16(info, TCR, val);
4196
4197 /* TPR (transmit preamble) */
4198
4199 switch (info->params.preamble)
4200 {
4201 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4202 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4203 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4204 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4205 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4206 default: val = 0x7e; break;
4207 }
4208 wr_reg8(info, TPR, (unsigned char)val);
4209
4210 /* RCR (rx control)
4211 *
4212 * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4213 * 12..10 encoding
4214 * 09 CRC enable
4215 * 08 CRC32
4216 * 07..03 reserved, must be 0
4217 * 02 reset
4218 * 01 enable
4219 * 00 auto-DCD enable
4220 */
4221 val = 0;
4222
4223 switch(info->params.mode) {
4224 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4225 case MGSL_MODE_BISYNC: val |= BIT15; break;
4226 case MGSL_MODE_RAW: val |= BIT13; break;
4227 }
4228
4229 switch(info->params.encoding)
4230 {
4231 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4232 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4233 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4234 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4235 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4236 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4237 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4238 }
4239
4240 switch (info->params.crc_type & HDLC_CRC_MASK)
4241 {
4242 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4243 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4244 }
4245
4246 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4247 val |= BIT0;
4248
4249 wr_reg16(info, RCR, val);
4250
4251 /* CCR (clock control)
4252 *
4253 * 07..05 tx clock source
4254 * 04..02 rx clock source
4255 * 01 auxclk enable
4256 * 00 BRG enable
4257 */
4258 val = 0;
4259
4260 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4261 {
4262 // when RxC source is DPLL, BRG generates 16X DPLL
4263 // reference clock, so take TxC from BRG/16 to get
4264 // transmit clock at actual data rate
4265 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4266 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4267 else
4268 val |= BIT6; /* 010, txclk = BRG */
4269 }
4270 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4271 val |= BIT7; /* 100, txclk = DPLL Input */
4272 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4273 val |= BIT5; /* 001, txclk = RXC Input */
4274
4275 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4276 val |= BIT3; /* 010, rxclk = BRG */
4277 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4278 val |= BIT4; /* 100, rxclk = DPLL */
4279 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4280 val |= BIT2; /* 001, rxclk = TXC Input */
4281
4282 if (info->params.clock_speed)
4283 val |= BIT1 + BIT0;
4284
4285 wr_reg8(info, CCR, (unsigned char)val);
4286
4287 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4288 {
4289 // program DPLL mode
4290 switch(info->params.encoding)
4291 {
4292 case HDLC_ENCODING_BIPHASE_MARK:
4293 case HDLC_ENCODING_BIPHASE_SPACE:
4294 val = BIT7; break;
4295 case HDLC_ENCODING_BIPHASE_LEVEL:
4296 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4297 val = BIT7 + BIT6; break;
4298 default: val = BIT6; // NRZ encodings
4299 }
4300 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4301
4302 // DPLL requires a 16X reference clock from BRG
4303 set_rate(info, info->params.clock_speed * 16);
4304 }
4305 else
4306 set_rate(info, info->params.clock_speed);
4307
4308 tx_set_idle(info);
4309
4310 msc_set_vcr(info);
4311
4312 /* SCR (serial control)
4313 *
4314 * 15 1=tx req on FIFO half empty
4315 * 14 1=rx req on FIFO half full
4316 * 13 tx data IRQ enable
4317 * 12 tx idle IRQ enable
4318 * 11 underrun IRQ enable
4319 * 10 rx data IRQ enable
4320 * 09 rx idle IRQ enable
4321 * 08 overrun IRQ enable
4322 * 07 DSR IRQ enable
4323 * 06 CTS IRQ enable
4324 * 05 DCD IRQ enable
4325 * 04 RI IRQ enable
4326 * 03 reserved, must be zero
4327 * 02 1=txd->rxd internal loopback enable
4328 * 01 reserved, must be zero
4329 * 00 1=master IRQ enable
4330 */
4331 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4332
4333 if (info->params.loopback)
4334 enable_loopback(info);
4335 }
4336
4337 /*
4338 * set transmit idle mode
4339 */
4340 static void tx_set_idle(struct slgt_info *info)
4341 {
4342 unsigned char val;
4343 unsigned short tcr;
4344
4345 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4346 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4347 */
4348 tcr = rd_reg16(info, TCR);
4349 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4350 /* disable preamble, set idle size to 16 bits */
4351 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4352 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4353 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4354 } else if (!(tcr & BIT6)) {
4355 /* preamble is disabled, set idle size to 8 bits */
4356 tcr &= ~(BIT5 + BIT4);
4357 }
4358 wr_reg16(info, TCR, tcr);
4359
4360 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4361 /* LSB of custom tx idle specified in tx idle register */
4362 val = (unsigned char)(info->idle_mode & 0xff);
4363 } else {
4364 /* standard 8 bit idle patterns */
4365 switch(info->idle_mode)
4366 {
4367 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4368 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4369 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4370 case HDLC_TXIDLE_ZEROS:
4371 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4372 default: val = 0xff;
4373 }
4374 }
4375
4376 wr_reg8(info, TIR, val);
4377 }
4378
4379 /*
4380 * get state of V24 status (input) signals
4381 */
4382 static void get_signals(struct slgt_info *info)
4383 {
4384 unsigned short status = rd_reg16(info, SSR);
4385
4386 /* clear all serial signals except DTR and RTS */
4387 info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4388
4389 if (status & BIT3)
4390 info->signals |= SerialSignal_DSR;
4391 if (status & BIT2)
4392 info->signals |= SerialSignal_CTS;
4393 if (status & BIT1)
4394 info->signals |= SerialSignal_DCD;
4395 if (status & BIT0)
4396 info->signals |= SerialSignal_RI;
4397 }
4398
4399 /*
4400 * set V.24 Control Register based on current configuration
4401 */
4402 static void msc_set_vcr(struct slgt_info *info)
4403 {
4404 unsigned char val = 0;
4405
4406 /* VCR (V.24 control)
4407 *
4408 * 07..04 serial IF select
4409 * 03 DTR
4410 * 02 RTS
4411 * 01 LL
4412 * 00 RL
4413 */
4414
4415 switch(info->if_mode & MGSL_INTERFACE_MASK)
4416 {
4417 case MGSL_INTERFACE_RS232:
4418 val |= BIT5; /* 0010 */
4419 break;
4420 case MGSL_INTERFACE_V35:
4421 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4422 break;
4423 case MGSL_INTERFACE_RS422:
4424 val |= BIT6; /* 0100 */
4425 break;
4426 }
4427
4428 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4429 val |= BIT4;
4430 if (info->signals & SerialSignal_DTR)
4431 val |= BIT3;
4432 if (info->signals & SerialSignal_RTS)
4433 val |= BIT2;
4434 if (info->if_mode & MGSL_INTERFACE_LL)
4435 val |= BIT1;
4436 if (info->if_mode & MGSL_INTERFACE_RL)
4437 val |= BIT0;
4438 wr_reg8(info, VCR, val);
4439 }
4440
4441 /*
4442 * set state of V24 control (output) signals
4443 */
4444 static void set_signals(struct slgt_info *info)
4445 {
4446 unsigned char val = rd_reg8(info, VCR);
4447 if (info->signals & SerialSignal_DTR)
4448 val |= BIT3;
4449 else
4450 val &= ~BIT3;
4451 if (info->signals & SerialSignal_RTS)
4452 val |= BIT2;
4453 else
4454 val &= ~BIT2;
4455 wr_reg8(info, VCR, val);
4456 }
4457
4458 /*
4459 * free range of receive DMA buffers (i to last)
4460 */
4461 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4462 {
4463 int done = 0;
4464
4465 while(!done) {
4466 /* reset current buffer for reuse */
4467 info->rbufs[i].status = 0;
4468 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4469 if (i == last)
4470 done = 1;
4471 if (++i == info->rbuf_count)
4472 i = 0;
4473 }
4474 info->rbuf_current = i;
4475 }
4476
4477 /*
4478 * mark all receive DMA buffers as free
4479 */
4480 static void reset_rbufs(struct slgt_info *info)
4481 {
4482 free_rbufs(info, 0, info->rbuf_count - 1);
4483 }
4484
4485 /*
4486 * pass receive HDLC frame to upper layer
4487 *
4488 * return true if frame available, otherwise false
4489 */
4490 static bool rx_get_frame(struct slgt_info *info)
4491 {
4492 unsigned int start, end;
4493 unsigned short status;
4494 unsigned int framesize = 0;
4495 unsigned long flags;
4496 struct tty_struct *tty = info->port.tty;
4497 unsigned char addr_field = 0xff;
4498 unsigned int crc_size = 0;
4499
4500 switch (info->params.crc_type & HDLC_CRC_MASK) {
4501 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4502 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4503 }
4504
4505 check_again:
4506
4507 framesize = 0;
4508 addr_field = 0xff;
4509 start = end = info->rbuf_current;
4510
4511 for (;;) {
4512 if (!desc_complete(info->rbufs[end]))
4513 goto cleanup;
4514
4515 if (framesize == 0 && info->params.addr_filter != 0xff)
4516 addr_field = info->rbufs[end].buf[0];
4517
4518 framesize += desc_count(info->rbufs[end]);
4519
4520 if (desc_eof(info->rbufs[end]))
4521 break;
4522
4523 if (++end == info->rbuf_count)
4524 end = 0;
4525
4526 if (end == info->rbuf_current) {
4527 if (info->rx_enabled){
4528 spin_lock_irqsave(&info->lock,flags);
4529 rx_start(info);
4530 spin_unlock_irqrestore(&info->lock,flags);
4531 }
4532 goto cleanup;
4533 }
4534 }
4535
4536 /* status
4537 *
4538 * 15 buffer complete
4539 * 14..06 reserved
4540 * 05..04 residue
4541 * 02 eof (end of frame)
4542 * 01 CRC error
4543 * 00 abort
4544 */
4545 status = desc_status(info->rbufs[end]);
4546
4547 /* ignore CRC bit if not using CRC (bit is undefined) */
4548 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4549 status &= ~BIT1;
4550
4551 if (framesize == 0 ||
4552 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4553 free_rbufs(info, start, end);
4554 goto check_again;
4555 }
4556
4557 if (framesize < (2 + crc_size) || status & BIT0) {
4558 info->icount.rxshort++;
4559 framesize = 0;
4560 } else if (status & BIT1) {
4561 info->icount.rxcrc++;
4562 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4563 framesize = 0;
4564 }
4565
4566 #if SYNCLINK_GENERIC_HDLC
4567 if (framesize == 0) {
4568 info->netdev->stats.rx_errors++;
4569 info->netdev->stats.rx_frame_errors++;
4570 }
4571 #endif
4572
4573 DBGBH(("%s rx frame status=%04X size=%d\n",
4574 info->device_name, status, framesize));
4575 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4576
4577 if (framesize) {
4578 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4579 framesize -= crc_size;
4580 crc_size = 0;
4581 }
4582
4583 if (framesize > info->max_frame_size + crc_size)
4584 info->icount.rxlong++;
4585 else {
4586 /* copy dma buffer(s) to contiguous temp buffer */
4587 int copy_count = framesize;
4588 int i = start;
4589 unsigned char *p = info->tmp_rbuf;
4590 info->tmp_rbuf_count = framesize;
4591
4592 info->icount.rxok++;
4593
4594 while(copy_count) {
4595 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4596 memcpy(p, info->rbufs[i].buf, partial_count);
4597 p += partial_count;
4598 copy_count -= partial_count;
4599 if (++i == info->rbuf_count)
4600 i = 0;
4601 }
4602
4603 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4604 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4605 framesize++;
4606 }
4607
4608 #if SYNCLINK_GENERIC_HDLC
4609 if (info->netcount)
4610 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4611 else
4612 #endif
4613 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4614 }
4615 }
4616 free_rbufs(info, start, end);
4617 return true;
4618
4619 cleanup:
4620 return false;
4621 }
4622
4623 /*
4624 * pass receive buffer (RAW synchronous mode) to tty layer
4625 * return true if buffer available, otherwise false
4626 */
4627 static bool rx_get_buf(struct slgt_info *info)
4628 {
4629 unsigned int i = info->rbuf_current;
4630 unsigned int count;
4631
4632 if (!desc_complete(info->rbufs[i]))
4633 return false;
4634 count = desc_count(info->rbufs[i]);
4635 switch(info->params.mode) {
4636 case MGSL_MODE_MONOSYNC:
4637 case MGSL_MODE_BISYNC:
4638 /* ignore residue in byte synchronous modes */
4639 if (desc_residue(info->rbufs[i]))
4640 count--;
4641 break;
4642 }
4643 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4644 DBGINFO(("rx_get_buf size=%d\n", count));
4645 if (count)
4646 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4647 info->flag_buf, count);
4648 free_rbufs(info, i, i);
4649 return true;
4650 }
4651
4652 static void reset_tbufs(struct slgt_info *info)
4653 {
4654 unsigned int i;
4655 info->tbuf_current = 0;
4656 for (i=0 ; i < info->tbuf_count ; i++) {
4657 info->tbufs[i].status = 0;
4658 info->tbufs[i].count = 0;
4659 }
4660 }
4661
4662 /*
4663 * return number of free transmit DMA buffers
4664 */
4665 static unsigned int free_tbuf_count(struct slgt_info *info)
4666 {
4667 unsigned int count = 0;
4668 unsigned int i = info->tbuf_current;
4669
4670 do
4671 {
4672 if (desc_count(info->tbufs[i]))
4673 break; /* buffer in use */
4674 ++count;
4675 if (++i == info->tbuf_count)
4676 i=0;
4677 } while (i != info->tbuf_current);
4678
4679 /* if tx DMA active, last zero count buffer is in use */
4680 if (count && (rd_reg32(info, TDCSR) & BIT0))
4681 --count;
4682
4683 return count;
4684 }
4685
4686 /*
4687 * return number of bytes in unsent transmit DMA buffers
4688 * and the serial controller tx FIFO
4689 */
4690 static unsigned int tbuf_bytes(struct slgt_info *info)
4691 {
4692 unsigned int total_count = 0;
4693 unsigned int i = info->tbuf_current;
4694 unsigned int reg_value;
4695 unsigned int count;
4696 unsigned int active_buf_count = 0;
4697
4698 /*
4699 * Add descriptor counts for all tx DMA buffers.
4700 * If count is zero (cleared by DMA controller after read),
4701 * the buffer is complete or is actively being read from.
4702 *
4703 * Record buf_count of last buffer with zero count starting
4704 * from current ring position. buf_count is mirror
4705 * copy of count and is not cleared by serial controller.
4706 * If DMA controller is active, that buffer is actively
4707 * being read so add to total.
4708 */
4709 do {
4710 count = desc_count(info->tbufs[i]);
4711 if (count)
4712 total_count += count;
4713 else if (!total_count)
4714 active_buf_count = info->tbufs[i].buf_count;
4715 if (++i == info->tbuf_count)
4716 i = 0;
4717 } while (i != info->tbuf_current);
4718
4719 /* read tx DMA status register */
4720 reg_value = rd_reg32(info, TDCSR);
4721
4722 /* if tx DMA active, last zero count buffer is in use */
4723 if (reg_value & BIT0)
4724 total_count += active_buf_count;
4725
4726 /* add tx FIFO count = reg_value[15..8] */
4727 total_count += (reg_value >> 8) & 0xff;
4728
4729 /* if transmitter active add one byte for shift register */
4730 if (info->tx_active)
4731 total_count++;
4732
4733 return total_count;
4734 }
4735
4736 /*
4737 * load transmit DMA buffer(s) with data
4738 */
4739 static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4740 {
4741 unsigned short count;
4742 unsigned int i;
4743 struct slgt_desc *d;
4744
4745 if (size == 0)
4746 return;
4747
4748 DBGDATA(info, buf, size, "tx");
4749
4750 info->tbuf_start = i = info->tbuf_current;
4751
4752 while (size) {
4753 d = &info->tbufs[i];
4754 if (++i == info->tbuf_count)
4755 i = 0;
4756
4757 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4758 memcpy(d->buf, buf, count);
4759
4760 size -= count;
4761 buf += count;
4762
4763 /*
4764 * set EOF bit for last buffer of HDLC frame or
4765 * for every buffer in raw mode
4766 */
4767 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4768 info->params.mode == MGSL_MODE_RAW)
4769 set_desc_eof(*d, 1);
4770 else
4771 set_desc_eof(*d, 0);
4772
4773 set_desc_count(*d, count);
4774 d->buf_count = count;
4775 }
4776
4777 info->tbuf_current = i;
4778 }
4779
4780 static int register_test(struct slgt_info *info)
4781 {
4782 static unsigned short patterns[] =
4783 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4784 static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4785 unsigned int i;
4786 int rc = 0;
4787
4788 for (i=0 ; i < count ; i++) {
4789 wr_reg16(info, TIR, patterns[i]);
4790 wr_reg16(info, BDR, patterns[(i+1)%count]);
4791 if ((rd_reg16(info, TIR) != patterns[i]) ||
4792 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4793 rc = -ENODEV;
4794 break;
4795 }
4796 }
4797 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4798 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4799 return rc;
4800 }
4801
4802 static int irq_test(struct slgt_info *info)
4803 {
4804 unsigned long timeout;
4805 unsigned long flags;
4806 struct tty_struct *oldtty = info->port.tty;
4807 u32 speed = info->params.data_rate;
4808
4809 info->params.data_rate = 921600;
4810 info->port.tty = NULL;
4811
4812 spin_lock_irqsave(&info->lock, flags);
4813 async_mode(info);
4814 slgt_irq_on(info, IRQ_TXIDLE);
4815
4816 /* enable transmitter */
4817 wr_reg16(info, TCR,
4818 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4819
4820 /* write one byte and wait for tx idle */
4821 wr_reg16(info, TDR, 0);
4822
4823 /* assume failure */
4824 info->init_error = DiagStatus_IrqFailure;
4825 info->irq_occurred = false;
4826
4827 spin_unlock_irqrestore(&info->lock, flags);
4828
4829 timeout=100;
4830 while(timeout-- && !info->irq_occurred)
4831 msleep_interruptible(10);
4832
4833 spin_lock_irqsave(&info->lock,flags);
4834 reset_port(info);
4835 spin_unlock_irqrestore(&info->lock,flags);
4836
4837 info->params.data_rate = speed;
4838 info->port.tty = oldtty;
4839
4840 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4841 return info->irq_occurred ? 0 : -ENODEV;
4842 }
4843
4844 static int loopback_test_rx(struct slgt_info *info)
4845 {
4846 unsigned char *src, *dest;
4847 int count;
4848
4849 if (desc_complete(info->rbufs[0])) {
4850 count = desc_count(info->rbufs[0]);
4851 src = info->rbufs[0].buf;
4852 dest = info->tmp_rbuf;
4853
4854 for( ; count ; count-=2, src+=2) {
4855 /* src=data byte (src+1)=status byte */
4856 if (!(*(src+1) & (BIT9 + BIT8))) {
4857 *dest = *src;
4858 dest++;
4859 info->tmp_rbuf_count++;
4860 }
4861 }
4862 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4863 return 1;
4864 }
4865 return 0;
4866 }
4867
4868 static int loopback_test(struct slgt_info *info)
4869 {
4870 #define TESTFRAMESIZE 20
4871
4872 unsigned long timeout;
4873 u16 count = TESTFRAMESIZE;
4874 unsigned char buf[TESTFRAMESIZE];
4875 int rc = -ENODEV;
4876 unsigned long flags;
4877
4878 struct tty_struct *oldtty = info->port.tty;
4879 MGSL_PARAMS params;
4880
4881 memcpy(&params, &info->params, sizeof(params));
4882
4883 info->params.mode = MGSL_MODE_ASYNC;
4884 info->params.data_rate = 921600;
4885 info->params.loopback = 1;
4886 info->port.tty = NULL;
4887
4888 /* build and send transmit frame */
4889 for (count = 0; count < TESTFRAMESIZE; ++count)
4890 buf[count] = (unsigned char)count;
4891
4892 info->tmp_rbuf_count = 0;
4893 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4894
4895 /* program hardware for HDLC and enabled receiver */
4896 spin_lock_irqsave(&info->lock,flags);
4897 async_mode(info);
4898 rx_start(info);
4899 info->tx_count = count;
4900 tx_load(info, buf, count);
4901 tx_start(info);
4902 spin_unlock_irqrestore(&info->lock, flags);
4903
4904 /* wait for receive complete */
4905 for (timeout = 100; timeout; --timeout) {
4906 msleep_interruptible(10);
4907 if (loopback_test_rx(info)) {
4908 rc = 0;
4909 break;
4910 }
4911 }
4912
4913 /* verify received frame length and contents */
4914 if (!rc && (info->tmp_rbuf_count != count ||
4915 memcmp(buf, info->tmp_rbuf, count))) {
4916 rc = -ENODEV;
4917 }
4918
4919 spin_lock_irqsave(&info->lock,flags);
4920 reset_adapter(info);
4921 spin_unlock_irqrestore(&info->lock,flags);
4922
4923 memcpy(&info->params, &params, sizeof(info->params));
4924 info->port.tty = oldtty;
4925
4926 info->init_error = rc ? DiagStatus_DmaFailure : 0;
4927 return rc;
4928 }
4929
4930 static int adapter_test(struct slgt_info *info)
4931 {
4932 DBGINFO(("testing %s\n", info->device_name));
4933 if (register_test(info) < 0) {
4934 printk("register test failure %s addr=%08X\n",
4935 info->device_name, info->phys_reg_addr);
4936 } else if (irq_test(info) < 0) {
4937 printk("IRQ test failure %s IRQ=%d\n",
4938 info->device_name, info->irq_level);
4939 } else if (loopback_test(info) < 0) {
4940 printk("loopback test failure %s\n", info->device_name);
4941 }
4942 return info->init_error;
4943 }
4944
4945 /*
4946 * transmit timeout handler
4947 */
4948 static void tx_timeout(unsigned long context)
4949 {
4950 struct slgt_info *info = (struct slgt_info*)context;
4951 unsigned long flags;
4952
4953 DBGINFO(("%s tx_timeout\n", info->device_name));
4954 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
4955 info->icount.txtimeout++;
4956 }
4957 spin_lock_irqsave(&info->lock,flags);
4958 info->tx_active = false;
4959 info->tx_count = 0;
4960 spin_unlock_irqrestore(&info->lock,flags);
4961
4962 #if SYNCLINK_GENERIC_HDLC
4963 if (info->netcount)
4964 hdlcdev_tx_done(info);
4965 else
4966 #endif
4967 bh_transmit(info);
4968 }
4969
4970 /*
4971 * receive buffer polling timer
4972 */
4973 static void rx_timeout(unsigned long context)
4974 {
4975 struct slgt_info *info = (struct slgt_info*)context;
4976 unsigned long flags;
4977
4978 DBGINFO(("%s rx_timeout\n", info->device_name));
4979 spin_lock_irqsave(&info->lock, flags);
4980 info->pending_bh |= BH_RECEIVE;
4981 spin_unlock_irqrestore(&info->lock, flags);
4982 bh_handler(&info->task);
4983 }
4984
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