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x86, apic: refactor ->cpu_mask_to_apicid*()
[linux-2.6/mini2440.git] / arch / x86 / kernel / genx2apic_uv_x.c
blobf957878c21e94272058dd2fe043176031dbfd1d7
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV APIC functions (note: not an Intel compatible APIC)
7 *
8 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/threads.h>
13 #include <linux/cpu.h>
14 #include <linux/cpumask.h>
15 #include <linux/string.h>
16 #include <linux/ctype.h>
17 #include <linux/init.h>
18 #include <linux/sched.h>
19 #include <linux/module.h>
20 #include <linux/hardirq.h>
21 #include <linux/timer.h>
22 #include <linux/proc_fs.h>
23 #include <asm/current.h>
24 #include <asm/smp.h>
25 #include <asm/ipi.h>
26 #include <asm/genapic.h>
27 #include <asm/pgtable.h>
28 #include <asm/uv/uv.h>
29 #include <asm/uv/uv_mmrs.h>
30 #include <asm/uv/uv_hub.h>
31 #include <asm/uv/bios.h>
32
33 DEFINE_PER_CPU(int, x2apic_extra_bits);
34
35 static enum uv_system_type uv_system_type;
36
37 static int uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
38 {
39 if (!strcmp(oem_id, "SGI")) {
40 if (!strcmp(oem_table_id, "UVL"))
41 uv_system_type = UV_LEGACY_APIC;
42 else if (!strcmp(oem_table_id, "UVX"))
43 uv_system_type = UV_X2APIC;
44 else if (!strcmp(oem_table_id, "UVH")) {
45 uv_system_type = UV_NON_UNIQUE_APIC;
46 return 1;
47 }
48 }
49 return 0;
50 }
51
52 enum uv_system_type get_uv_system_type(void)
53 {
54 return uv_system_type;
55 }
56
57 int is_uv_system(void)
58 {
59 return uv_system_type != UV_NONE;
60 }
61 EXPORT_SYMBOL_GPL(is_uv_system);
62
63 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
64 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
65
66 struct uv_blade_info *uv_blade_info;
67 EXPORT_SYMBOL_GPL(uv_blade_info);
68
69 short *uv_node_to_blade;
70 EXPORT_SYMBOL_GPL(uv_node_to_blade);
71
72 short *uv_cpu_to_blade;
73 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
74
75 short uv_possible_blades;
76 EXPORT_SYMBOL_GPL(uv_possible_blades);
77
78 unsigned long sn_rtc_cycles_per_second;
79 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
80
81 /* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */
82
83 static const struct cpumask *uv_target_cpus(void)
84 {
85 return cpumask_of(0);
86 }
87
88 static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask)
89 {
90 cpumask_clear(retmask);
91 cpumask_set_cpu(cpu, retmask);
92 }
93
94 int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
95 {
96 unsigned long val;
97 int pnode;
98
99 pnode = uv_apicid_to_pnode(phys_apicid);
100 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
101 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
102 (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
103 APIC_DM_INIT;
104 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
105 mdelay(10);
106
107 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
108 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
109 (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
110 APIC_DM_STARTUP;
111 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
112 return 0;
113 }
114
115 static void uv_send_IPI_one(int cpu, int vector)
116 {
117 unsigned long val, apicid, lapicid;
118 int pnode;
119
120 apicid = per_cpu(x86_cpu_to_apicid, cpu);
121 lapicid = apicid & 0x3f; /* ZZZ macro needed */
122 pnode = uv_apicid_to_pnode(apicid);
123 val =
124 (1UL << UVH_IPI_INT_SEND_SHFT) | (lapicid <<
125 UVH_IPI_INT_APIC_ID_SHFT) |
126 (vector << UVH_IPI_INT_VECTOR_SHFT);
127 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
128 }
129
130 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
131 {
132 unsigned int cpu;
133
134 for_each_cpu(cpu, mask)
135 uv_send_IPI_one(cpu, vector);
136 }
137
138 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
139 {
140 unsigned int cpu;
141 unsigned int this_cpu = smp_processor_id();
142
143 for_each_cpu(cpu, mask)
144 if (cpu != this_cpu)
145 uv_send_IPI_one(cpu, vector);
146 }
147
148 static void uv_send_IPI_allbutself(int vector)
149 {
150 unsigned int cpu;
151 unsigned int this_cpu = smp_processor_id();
152
153 for_each_online_cpu(cpu)
154 if (cpu != this_cpu)
155 uv_send_IPI_one(cpu, vector);
156 }
157
158 static void uv_send_IPI_all(int vector)
159 {
160 uv_send_IPI_mask(cpu_online_mask, vector);
161 }
162
163 static int uv_apic_id_registered(void)
164 {
165 return 1;
166 }
167
168 static void uv_init_apic_ldr(void)
169 {
170 }
171
172 static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask)
173 {
174 /*
175 * We're using fixed IRQ delivery, can only return one phys APIC ID.
176 * May as well be the first.
177 */
178 int cpu = cpumask_first(cpumask);
179
180 if ((unsigned)cpu < nr_cpu_ids)
181 return per_cpu(x86_cpu_to_apicid, cpu);
182 else
183 return BAD_APICID;
184 }
185
186 static unsigned int
187 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
188 const struct cpumask *andmask)
189 {
190 int cpu;
191
192 /*
193 * We're using fixed IRQ delivery, can only return one phys APIC ID.
194 * May as well be the first.
195 */
196 for_each_cpu_and(cpu, cpumask, andmask) {
197 if (cpumask_test_cpu(cpu, cpu_online_mask))
198 break;
199 }
200 if (cpu < nr_cpu_ids)
201 return per_cpu(x86_cpu_to_apicid, cpu);
202
203 return BAD_APICID;
204 }
205
206 static unsigned int x2apic_get_apic_id(unsigned long x)
207 {
208 unsigned int id;
209
210 WARN_ON(preemptible() && num_online_cpus() > 1);
211 id = x | __get_cpu_var(x2apic_extra_bits);
212
213 return id;
214 }
215
216 static unsigned long set_apic_id(unsigned int id)
217 {
218 unsigned long x;
219
220 /* maskout x2apic_extra_bits ? */
221 x = id;
222 return x;
223 }
224
225 static unsigned int uv_read_apic_id(void)
226 {
227
228 return x2apic_get_apic_id(apic_read(APIC_ID));
229 }
230
231 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
232 {
233 return uv_read_apic_id() >> index_msb;
234 }
235
236 static void uv_send_IPI_self(int vector)
237 {
238 apic_write(APIC_SELF_IPI, vector);
239 }
240
241 struct genapic apic_x2apic_uv_x = {
242
243 .name = "UV large system",
244 .probe = NULL,
245 .acpi_madt_oem_check = uv_acpi_madt_oem_check,
246 .apic_id_registered = uv_apic_id_registered,
247
248 .irq_delivery_mode = dest_Fixed,
249 .irq_dest_mode = 1, /* logical */
250
251 .target_cpus = uv_target_cpus,
252 .disable_esr = 0,
253 .dest_logical = APIC_DEST_LOGICAL,
254 .check_apicid_used = NULL,
255 .check_apicid_present = NULL,
256
257 .vector_allocation_domain = uv_vector_allocation_domain,
258 .init_apic_ldr = uv_init_apic_ldr,
259
260 .ioapic_phys_id_map = NULL,
261 .setup_apic_routing = NULL,
262 .multi_timer_check = NULL,
263 .apicid_to_node = NULL,
264 .cpu_to_logical_apicid = NULL,
265 .cpu_present_to_apicid = default_cpu_present_to_apicid,
266 .apicid_to_cpu_present = NULL,
267 .setup_portio_remap = NULL,
268 .check_phys_apicid_present = default_check_phys_apicid_present,
269 .enable_apic_mode = NULL,
270 .phys_pkg_id = uv_phys_pkg_id,
271 .mps_oem_check = NULL,
272
273 .get_apic_id = x2apic_get_apic_id,
274 .set_apic_id = set_apic_id,
275 .apic_id_mask = 0xFFFFFFFFu,
276
277 .cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
278 .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and,
279
280 .send_IPI_mask = uv_send_IPI_mask,
281 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself,
282 .send_IPI_allbutself = uv_send_IPI_allbutself,
283 .send_IPI_all = uv_send_IPI_all,
284 .send_IPI_self = uv_send_IPI_self,
285
286 .wakeup_cpu = NULL,
287 .trampoline_phys_low = 0,
288 .trampoline_phys_high = 0,
289 .wait_for_init_deassert = NULL,
290 .smp_callin_clear_local_apic = NULL,
291 .store_NMI_vector = NULL,
292 .restore_NMI_vector = NULL,
293 .inquire_remote_apic = NULL,
294 };
295
296 static __cpuinit void set_x2apic_extra_bits(int pnode)
297 {
298 __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
299 }
300
301 /*
302 * Called on boot cpu.
303 */
304 static __init int boot_pnode_to_blade(int pnode)
305 {
306 int blade;
307
308 for (blade = 0; blade < uv_num_possible_blades(); blade++)
309 if (pnode == uv_blade_info[blade].pnode)
310 return blade;
311 BUG();
312 }
313
314 struct redir_addr {
315 unsigned long redirect;
316 unsigned long alias;
317 };
318
319 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
320
321 static __initdata struct redir_addr redir_addrs[] = {
322 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
323 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
324 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
325 };
326
327 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
328 {
329 union uvh_si_alias0_overlay_config_u alias;
330 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
331 int i;
332
333 for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
334 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
335 if (alias.s.base == 0) {
336 *size = (1UL << alias.s.m_alias);
337 redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
338 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
339 return;
340 }
341 }
342 BUG();
343 }
344
345 static __init void map_low_mmrs(void)
346 {
347 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
348 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
349 }
350
351 enum map_type {map_wb, map_uc};
352
353 static __init void map_high(char *id, unsigned long base, int shift,
354 int max_pnode, enum map_type map_type)
355 {
356 unsigned long bytes, paddr;
357
358 paddr = base << shift;
359 bytes = (1UL << shift) * (max_pnode + 1);
360 printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
361 paddr + bytes);
362 if (map_type == map_uc)
363 init_extra_mapping_uc(paddr, bytes);
364 else
365 init_extra_mapping_wb(paddr, bytes);
366
367 }
368 static __init void map_gru_high(int max_pnode)
369 {
370 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
371 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
372
373 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
374 if (gru.s.enable)
375 map_high("GRU", gru.s.base, shift, max_pnode, map_wb);
376 }
377
378 static __init void map_config_high(int max_pnode)
379 {
380 union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
381 int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;
382
383 cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
384 if (cfg.s.enable)
385 map_high("CONFIG", cfg.s.base, shift, max_pnode, map_uc);
386 }
387
388 static __init void map_mmr_high(int max_pnode)
389 {
390 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
391 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
392
393 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
394 if (mmr.s.enable)
395 map_high("MMR", mmr.s.base, shift, max_pnode, map_uc);
396 }
397
398 static __init void map_mmioh_high(int max_pnode)
399 {
400 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
401 int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
402
403 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
404 if (mmioh.s.enable)
405 map_high("MMIOH", mmioh.s.base, shift, max_pnode, map_uc);
406 }
407
408 static __init void uv_rtc_init(void)
409 {
410 long status;
411 u64 ticks_per_sec;
412
413 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
414 &ticks_per_sec);
415 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
416 printk(KERN_WARNING
417 "unable to determine platform RTC clock frequency, "
418 "guessing.\n");
419 /* BIOS gives wrong value for clock freq. so guess */
420 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
421 } else
422 sn_rtc_cycles_per_second = ticks_per_sec;
423 }
424
425 /*
426 * percpu heartbeat timer
427 */
428 static void uv_heartbeat(unsigned long ignored)
429 {
430 struct timer_list *timer = &uv_hub_info->scir.timer;
431 unsigned char bits = uv_hub_info->scir.state;
432
433 /* flip heartbeat bit */
434 bits ^= SCIR_CPU_HEARTBEAT;
435
436 /* is this cpu idle? */
437 if (idle_cpu(raw_smp_processor_id()))
438 bits &= ~SCIR_CPU_ACTIVITY;
439 else
440 bits |= SCIR_CPU_ACTIVITY;
441
442 /* update system controller interface reg */
443 uv_set_scir_bits(bits);
444
445 /* enable next timer period */
446 mod_timer(timer, jiffies + SCIR_CPU_HB_INTERVAL);
447 }
448
449 static void __cpuinit uv_heartbeat_enable(int cpu)
450 {
451 if (!uv_cpu_hub_info(cpu)->scir.enabled) {
452 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
453
454 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
455 setup_timer(timer, uv_heartbeat, cpu);
456 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
457 add_timer_on(timer, cpu);
458 uv_cpu_hub_info(cpu)->scir.enabled = 1;
459 }
460
461 /* check boot cpu */
462 if (!uv_cpu_hub_info(0)->scir.enabled)
463 uv_heartbeat_enable(0);
464 }
465
466 #ifdef CONFIG_HOTPLUG_CPU
467 static void __cpuinit uv_heartbeat_disable(int cpu)
468 {
469 if (uv_cpu_hub_info(cpu)->scir.enabled) {
470 uv_cpu_hub_info(cpu)->scir.enabled = 0;
471 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
472 }
473 uv_set_cpu_scir_bits(cpu, 0xff);
474 }
475
476 /*
477 * cpu hotplug notifier
478 */
479 static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self,
480 unsigned long action, void *hcpu)
481 {
482 long cpu = (long)hcpu;
483
484 switch (action) {
485 case CPU_ONLINE:
486 uv_heartbeat_enable(cpu);
487 break;
488 case CPU_DOWN_PREPARE:
489 uv_heartbeat_disable(cpu);
490 break;
491 default:
492 break;
493 }
494 return NOTIFY_OK;
495 }
496
497 static __init void uv_scir_register_cpu_notifier(void)
498 {
499 hotcpu_notifier(uv_scir_cpu_notify, 0);
500 }
501
502 #else /* !CONFIG_HOTPLUG_CPU */
503
504 static __init void uv_scir_register_cpu_notifier(void)
505 {
506 }
507
508 static __init int uv_init_heartbeat(void)
509 {
510 int cpu;
511
512 if (is_uv_system())
513 for_each_online_cpu(cpu)
514 uv_heartbeat_enable(cpu);
515 return 0;
516 }
517
518 late_initcall(uv_init_heartbeat);
519
520 #endif /* !CONFIG_HOTPLUG_CPU */
521
522 /*
523 * Called on each cpu to initialize the per_cpu UV data area.
524 * ZZZ hotplug not supported yet
525 */
526 void __cpuinit uv_cpu_init(void)
527 {
528 /* CPU 0 initilization will be done via uv_system_init. */
529 if (!uv_blade_info)
530 return;
531
532 uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
533
534 if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
535 set_x2apic_extra_bits(uv_hub_info->pnode);
536 }
537
538
539 void __init uv_system_init(void)
540 {
541 union uvh_si_addr_map_config_u m_n_config;
542 union uvh_node_id_u node_id;
543 unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
544 int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
545 int max_pnode = 0;
546 unsigned long mmr_base, present;
547
548 map_low_mmrs();
549
550 m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
551 m_val = m_n_config.s.m_skt;
552 n_val = m_n_config.s.n_skt;
553 mmr_base =
554 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
555 ~UV_MMR_ENABLE;
556 printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
557
558 for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
559 uv_possible_blades +=
560 hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
561 printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
562
563 bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
564 uv_blade_info = kmalloc(bytes, GFP_KERNEL);
565
566 get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
567
568 bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
569 uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
570 memset(uv_node_to_blade, 255, bytes);
571
572 bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
573 uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
574 memset(uv_cpu_to_blade, 255, bytes);
575
576 blade = 0;
577 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
578 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
579 for (j = 0; j < 64; j++) {
580 if (!test_bit(j, &present))
581 continue;
582 uv_blade_info[blade].pnode = (i * 64 + j);
583 uv_blade_info[blade].nr_possible_cpus = 0;
584 uv_blade_info[blade].nr_online_cpus = 0;
585 blade++;
586 }
587 }
588
589 node_id.v = uv_read_local_mmr(UVH_NODE_ID);
590 gnode_upper = (((unsigned long)node_id.s.node_id) &
591 ~((1 << n_val) - 1)) << m_val;
592
593 uv_bios_init();
594 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id,
595 &sn_coherency_id, &sn_region_size);
596 uv_rtc_init();
597
598 for_each_present_cpu(cpu) {
599 nid = cpu_to_node(cpu);
600 pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
601 blade = boot_pnode_to_blade(pnode);
602 lcpu = uv_blade_info[blade].nr_possible_cpus;
603 uv_blade_info[blade].nr_possible_cpus++;
604
605 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
606 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
607 uv_cpu_hub_info(cpu)->m_val = m_val;
608 uv_cpu_hub_info(cpu)->n_val = m_val;
609 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
610 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
611 uv_cpu_hub_info(cpu)->pnode = pnode;
612 uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
613 uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
614 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
615 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
616 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
617 uv_cpu_hub_info(cpu)->scir.offset = SCIR_LOCAL_MMR_BASE + lcpu;
618 uv_node_to_blade[nid] = blade;
619 uv_cpu_to_blade[cpu] = blade;
620 max_pnode = max(pnode, max_pnode);
621
622 printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
623 "lcpu %d, blade %d\n",
624 cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
625 lcpu, blade);
626 }
627
628 map_gru_high(max_pnode);
629 map_mmr_high(max_pnode);
630 map_config_high(max_pnode);
631 map_mmioh_high(max_pnode);
632
633 uv_cpu_init();
634 uv_scir_register_cpu_notifier();
635 proc_mkdir("sgi_uv", NULL);
636 }
Support for the Chinese Samsung S3C2440 based development boards