arch/x86/include/asm/numaq/apic.h

   1 #ifndef __ASM_NUMAQ_APIC_H
   2 #define __ASM_NUMAQ_APIC_H
   3
   4 #include <asm/io.h>
   5 #include <linux/mmzone.h>
   6 #include <linux/nodemask.h>
   7
   8 #define APIC_DFR_VALUE  (APIC_DFR_CLUSTER)
   9
  10 static inline const cpumask_t *numaq_target_cpus(void)
  11 {
  12         return &CPU_MASK_ALL;
  13 }
  14
  15 static inline unsigned long
  16 numaq_check_apicid_used(physid_mask_t bitmap, int apicid)
  17 {
  18         return physid_isset(apicid, bitmap);
  19 }
  20 static inline unsigned long numaq_check_apicid_present(int bit)
  21 {
  22         return physid_isset(bit, phys_cpu_present_map);
  23 }
  24 #define apicid_cluster(apicid) (apicid & 0xF0)
  25
  26 static inline int numaq_apic_id_registered(void)
  27 {
  28         return 1;
  29 }
  30
  31 static inline void numaq_init_apic_ldr(void)
  32 {
  33         /* Already done in NUMA-Q firmware */
  34 }
  35
  36 static inline void numaq_setup_apic_routing(void)
  37 {
  38         printk("Enabling APIC mode:  %s.  Using %d I/O APICs\n",
  39                 "NUMA-Q", nr_ioapics);
  40 }
  41
  42 /*
  43  * Skip adding the timer int on secondary nodes, which causes
  44  * a small but painful rift in the time-space continuum.
  45  */
  46 static inline int numaq_multi_timer_check(int apic, int irq)
  47 {
  48         return apic != 0 && irq == 0;
  49 }
  50
  51 static inline physid_mask_t numaq_ioapic_phys_id_map(physid_mask_t phys_map)
  52 {
  53         /* We don't have a good way to do this yet - hack */
  54         return physids_promote(0xFUL);
  55 }
  56
  57 /* Mapping from cpu number to logical apicid */
  58 extern u8 cpu_2_logical_apicid[];
  59
  60 static inline int numaq_cpu_to_logical_apicid(int cpu)
  61 {
  62         if (cpu >= nr_cpu_ids)
  63                 return BAD_APICID;
  64         return (int)cpu_2_logical_apicid[cpu];
  65 }
  66
  67 /*
  68  * Supporting over 60 cpus on NUMA-Q requires a locality-dependent
  69  * cpu to APIC ID relation to properly interact with the intelligent
  70  * mode of the cluster controller.
  71  */
  72 static inline int numaq_cpu_present_to_apicid(int mps_cpu)
  73 {
  74         if (mps_cpu < 60)
  75                 return ((mps_cpu >> 2) << 4) | (1 << (mps_cpu & 0x3));
  76         else
  77                 return BAD_APICID;
  78 }
  79
  80 static inline int numaq_apicid_to_node(int logical_apicid)
  81 {
  82         return logical_apicid >> 4;
  83 }
  84
  85 static inline physid_mask_t numaq_apicid_to_cpu_present(int logical_apicid)
  86 {
  87         int node = numaq_apicid_to_node(logical_apicid);
  88         int cpu = __ffs(logical_apicid & 0xf);
  89
  90         return physid_mask_of_physid(cpu + 4*node);
  91 }
  92
  93 extern void *xquad_portio;
  94
  95 static inline int numaq_check_phys_apicid_present(int boot_cpu_physical_apicid)
  96 {
  97         return 1;
  98 }
  99
 100 /*
 101  * We use physical apicids here, not logical, so just return the default
 102  * physical broadcast to stop people from breaking us
 103  */
 104 static inline unsigned int numaq_cpu_mask_to_apicid(const cpumask_t *cpumask)
 105 {
 106         return 0x0F;
 107 }
 108
 109 static inline unsigned int
 110 numaq_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
 111                              const struct cpumask *andmask)
 112 {
 113         return 0x0F;
 114 }
 115
 116 /* No NUMA-Q box has a HT CPU, but it can't hurt to use the default code. */
 117 static inline int numaq_phys_pkg_id(int cpuid_apic, int index_msb)
 118 {
 119         return cpuid_apic >> index_msb;
 120 }
 121
 122 #endif /* __ASM_NUMAQ_APIC_H */