drivers/net/bnx2x_fw_defs.h

   1 /* bnx2x_fw_defs.h: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2008 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  */
   9
  10
  11 #define CSTORM_ASSERT_LIST_INDEX_OFFSET \
  12         (IS_E1H_OFFSET ? 0x7000 : 0x1000)
  13 #define CSTORM_ASSERT_LIST_OFFSET(idx) \
  14         (IS_E1H_OFFSET ? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
  15 #define CSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
  16         (IS_E1H_OFFSET ? (0x8522 + ((function>>1) * 0x40) + \
  17         ((function&1) * 0x100) + (index * 0x4)) : (0x1922 + (function * \
  18         0x40) + (index * 0x4)))
  19 #define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
  20         (IS_E1H_OFFSET ? (0x8500 + ((function>>1) * 0x40) + \
  21         ((function&1) * 0x100)) : (0x1900 + (function * 0x40)))
  22 #define CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
  23         (IS_E1H_OFFSET ? (0x8508 + ((function>>1) * 0x40) + \
  24         ((function&1) * 0x100)) : (0x1908 + (function * 0x40)))
  25 #define CSTORM_FUNCTION_MODE_OFFSET \
  26         (IS_E1H_OFFSET ? 0x11e8 : 0xffffffff)
  27 #define CSTORM_HC_BTR_OFFSET(port) \
  28         (IS_E1H_OFFSET ? (0x8704 + (port * 0xf0)) : (0x1984 + (port * 0xc0)))
  29 #define CSTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
  30         (IS_E1H_OFFSET ? (0x801a + (port * 0x280) + (cpu_id * 0x28) + \
  31         (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
  32         (index * 0x4)))
  33 #define CSTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
  34         (IS_E1H_OFFSET ? (0x8018 + (port * 0x280) + (cpu_id * 0x28) + \
  35         (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \
  36         (index * 0x4)))
  37 #define CSTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
  38         (IS_E1H_OFFSET ? (0x8000 + (port * 0x280) + (cpu_id * 0x28)) : \
  39         (0x1400 + (port * 0x280) + (cpu_id * 0x28)))
  40 #define CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
  41         (IS_E1H_OFFSET ? (0x8008 + (port * 0x280) + (cpu_id * 0x28)) : \
  42         (0x1408 + (port * 0x280) + (cpu_id * 0x28)))
  43 #define CSTORM_STATS_FLAGS_OFFSET(function) \
  44         (IS_E1H_OFFSET ? (0x1108 + (function * 0x8)) : (0x5108 + \
  45         (function * 0x8)))
  46 #define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(function) \
  47         (IS_E1H_OFFSET ? (0x31c0 + (function * 0x20)) : 0xffffffff)
  48 #define TSTORM_ASSERT_LIST_INDEX_OFFSET \
  49         (IS_E1H_OFFSET ? 0xa000 : 0x1000)
  50 #define TSTORM_ASSERT_LIST_OFFSET(idx) \
  51         (IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
  52 #define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \
  53         (IS_E1H_OFFSET ? (0x3350 + (port * 0x190) + (client_id * 0x10)) \
  54         : (0x9c0 + (port * 0x130) + (client_id * 0x10)))
  55 #define TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET \
  56         (IS_E1H_OFFSET ? 0x1ad8 : 0xffffffff)
  57 #define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
  58         (IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \
  59         ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
  60         0x28) + (index * 0x4)))
  61 #define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
  62         (IS_E1H_OFFSET ? (0xb000 + ((function>>1) * 0x28) + \
  63         ((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))
  64 #define TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
  65         (IS_E1H_OFFSET ? (0xb008 + ((function>>1) * 0x28) + \
  66         ((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
  67 #define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
  68         (IS_E1H_OFFSET ? (0x2b80 + (function * 0x8)) : (0x4b68 + \
  69         (function * 0x8)))
  70 #define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function) \
  71         (IS_E1H_OFFSET ? (0x3000 + (function * 0x38)) : (0x1500 + \
  72         (function * 0x38)))
  73 #define TSTORM_FUNCTION_MODE_OFFSET \
  74         (IS_E1H_OFFSET ? 0x1ad0 : 0xffffffff)
  75 #define TSTORM_HC_BTR_OFFSET(port) \
  76         (IS_E1H_OFFSET ? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
  77 #define TSTORM_INDIRECTION_TABLE_OFFSET(function) \
  78         (IS_E1H_OFFSET ? (0x12c8 + (function * 0x80)) : (0x22c8 + \
  79         (function * 0x80)))
  80 #define TSTORM_INDIRECTION_TABLE_SIZE 0x80
  81 #define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \
  82         (IS_E1H_OFFSET ? (0x3008 + (function * 0x38)) : (0x1508 + \
  83         (function * 0x38)))
  84 #define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
  85         (IS_E1H_OFFSET ? (0x2010 + (port * 0x5b0) + (stats_counter_id * \
  86         0x50)) : (0x4080 + (port * 0x5b0) + (stats_counter_id * 0x50)))
  87 #define TSTORM_STATS_FLAGS_OFFSET(function) \
  88         (IS_E1H_OFFSET ? (0x2c00 + (function * 0x8)) : (0x4b88 + \
  89         (function * 0x8)))
  90 #define TSTORM_TPA_EXIST_OFFSET (IS_E1H_OFFSET ? 0x3680 : 0x1c20)
  91 #define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa040 : 0x2c10)
  92 #define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2440 : 0x1200)
  93 #define USTORM_ASSERT_LIST_INDEX_OFFSET \
  94         (IS_E1H_OFFSET ? 0x8960 : 0x1000)
  95 #define USTORM_ASSERT_LIST_OFFSET(idx) \
  96         (IS_E1H_OFFSET ? (0x8980 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
  97 #define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \
  98         (IS_E1H_OFFSET ? (0x8018 + (port * 0x4b0) + (clientId * 0x30)) : \
  99         (0x5330 + (port * 0x260) + (clientId * 0x20)))
 100 #define USTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
 101         (IS_E1H_OFFSET ? (0x9522 + ((function>>1) * 0x40) + \
 102         ((function&1) * 0x100) + (index * 0x4)) : (0x1922 + (function * \
 103         0x40) + (index * 0x4)))
 104 #define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
 105         (IS_E1H_OFFSET ? (0x9500 + ((function>>1) * 0x40) + \
 106         ((function&1) * 0x100)) : (0x1900 + (function * 0x40)))
 107 #define USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
 108         (IS_E1H_OFFSET ? (0x9508 + ((function>>1) * 0x40) + \
 109         ((function&1) * 0x100)) : (0x1908 + (function * 0x40)))
 110 #define USTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
 111         (IS_E1H_OFFSET ? (0x2a50 + (function * 0x8)) : (0x1d98 + \
 112         (function * 0x8)))
 113 #define USTORM_FUNCTION_MODE_OFFSET \
 114         (IS_E1H_OFFSET ? 0x2448 : 0xffffffff)
 115 #define USTORM_HC_BTR_OFFSET(port) \
 116         (IS_E1H_OFFSET ? (0x9704 + (port * 0xf0)) : (0x1984 + (port * 0xc0)))
 117 #define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \
 118         (IS_E1H_OFFSET ? (0x8010 + (port * 0x4b0) + (clientId * 0x30)) : \
 119         (0x5328 + (port * 0x260) + (clientId * 0x20)))
 120 #define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \
 121         (IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x5308 + \
 122         (function * 0x8)))
 123 #define USTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
 124         (IS_E1H_OFFSET ? (0x2450 + (port * 0x2d0) + (stats_counter_id * \
 125         0x28)) : (0x4740 + (port * 0x2d0) + (stats_counter_id * 0x28)))
 126 #define USTORM_RX_PRODS_OFFSET(port, client_id) \
 127         (IS_E1H_OFFSET ? (0x8000 + (port * 0x4b0) + (client_id * 0x30)) \
 128         : (0x5318 + (port * 0x260) + (client_id * 0x20)))
 129 #define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
 130         (IS_E1H_OFFSET ? (0x901a + (port * 0x280) + (cpu_id * 0x28) + \
 131         (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
 132         (index * 0x4)))
 133 #define USTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
 134         (IS_E1H_OFFSET ? (0x9018 + (port * 0x280) + (cpu_id * 0x28) + \
 135         (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \
 136         (index * 0x4)))
 137 #define USTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
 138         (IS_E1H_OFFSET ? (0x9000 + (port * 0x280) + (cpu_id * 0x28)) : \
 139         (0x1400 + (port * 0x280) + (cpu_id * 0x28)))
 140 #define USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
 141         (IS_E1H_OFFSET ? (0x9008 + (port * 0x280) + (cpu_id * 0x28)) : \
 142         (0x1408 + (port * 0x280) + (cpu_id * 0x28)))
 143 #define USTORM_STATS_FLAGS_OFFSET(function) \
 144         (IS_E1H_OFFSET ? (0x29f0 + (function * 0x8)) : (0x1d80 + \
 145         (function * 0x8)))
 146 #define XSTORM_ASSERT_LIST_INDEX_OFFSET \
 147         (IS_E1H_OFFSET ? 0x9000 : 0x1000)
 148 #define XSTORM_ASSERT_LIST_OFFSET(idx) \
 149         (IS_E1H_OFFSET ? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
 150 #define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \
 151         (IS_E1H_OFFSET ? (0x24a8 + (port * 0x50)) : (0x3ba0 + (port * 0x50)))
 152 #define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
 153         (IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \
 154         ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
 155         0x28) + (index * 0x4)))
 156 #define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
 157         (IS_E1H_OFFSET ? (0xa000 + ((function>>1) * 0x28) + \
 158         ((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))
 159 #define XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
 160         (IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \
 161         ((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
 162 #define XSTORM_E1HOV_OFFSET(function) \
 163         (IS_E1H_OFFSET ? (0x2c10 + (function * 0x2)) : 0xffffffff)
 164 #define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
 165         (IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3b70 + \
 166         (function * 0x8)))
 167 #define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \
 168         (IS_E1H_OFFSET ? (0x2588 + (function * 0x90)) : (0x3c80 + \
 169         (function * 0x90)))
 170 #define XSTORM_FUNCTION_MODE_OFFSET \
 171         (IS_E1H_OFFSET ? 0x2c20 : 0xffffffff)
 172 #define XSTORM_HC_BTR_OFFSET(port) \
 173         (IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
 174 #define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
 175         (IS_E1H_OFFSET ? (0xc000 + (port * 0x3f0) + (stats_counter_id * \
 176         0x38)) : (0x3378 + (port * 0x3f0) + (stats_counter_id * 0x38)))
 177 #define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \
 178         (IS_E1H_OFFSET ? (0x2548 + (function * 0x90)) : (0x3c40 + \
 179         (function * 0x90)))
 180 #define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \
 181         (IS_E1H_OFFSET ? (0x2000 + (function * 0x10)) : (0x3328 + \
 182         (function * 0x10)))
 183 #define XSTORM_SPQ_PROD_OFFSET(function) \
 184         (IS_E1H_OFFSET ? (0x2008 + (function * 0x10)) : (0x3330 + \
 185         (function * 0x10)))
 186 #define XSTORM_STATS_FLAGS_OFFSET(function) \
 187         (IS_E1H_OFFSET ? (0x23d8 + (function * 0x8)) : (0x3b60 + \
 188         (function * 0x8)))
 189 #define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
 190
 191 /**
 192 * This file defines HSI constatnts for the ETH flow
 193 */
 194 #ifdef _EVEREST_MICROCODE
 195 #include "microcode_constants.h"
 196 #include "eth_rx_bd.h"
 197 #include "eth_tx_bd.h"
 198 #include "eth_rx_cqe.h"
 199 #include "eth_rx_sge.h"
 200 #include "eth_rx_cqe_next_page.h"
 201 #endif
 202
 203 /* RSS hash types */
 204 #define DEFAULT_HASH_TYPE 0
 205 #define IPV4_HASH_TYPE 1
 206 #define TCP_IPV4_HASH_TYPE 2
 207 #define IPV6_HASH_TYPE 3
 208 #define TCP_IPV6_HASH_TYPE 4
 209
 210 /* Ethernet Ring parmaters */
 211 #define X_ETH_LOCAL_RING_SIZE 13
 212 #define FIRST_BD_IN_PKT 0
 213 #define PARSE_BD_INDEX 1
 214 #define NUM_OF_ETH_BDS_IN_PAGE \
 215         ((PAGE_SIZE) / (STRUCT_SIZE(eth_tx_bd)/8))
 216
 217
 218 /* Rx ring params */
 219 #define U_ETH_LOCAL_BD_RING_SIZE (16)
 220 #define U_ETH_LOCAL_SGE_RING_SIZE (12)
 221 #define U_ETH_SGL_SIZE (8)
 222
 223
 224 #define U_ETH_BDS_PER_PAGE_MASK \
 225         ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))-1)
 226 #define U_ETH_CQE_PER_PAGE_MASK \
 227         ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))-1)
 228 #define U_ETH_SGES_PER_PAGE_MASK \
 229         ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))-1)
 230
 231 #define U_ETH_SGES_PER_PAGE_INVERSE_MASK \
 232         (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
 233
 234
 235 #define TU_ETH_CQES_PER_PAGE \
 236         (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe_next_page)/8))
 237 #define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))
 238 #define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
 239
 240 #define U_ETH_UNDEFINED_Q 0xFF
 241
 242 /* values of command IDs in the ramrod message */
 243 #define RAMROD_CMD_ID_ETH_PORT_SETUP (80)
 244 #define RAMROD_CMD_ID_ETH_CLIENT_SETUP (85)
 245 #define RAMROD_CMD_ID_ETH_STAT_QUERY (90)
 246 #define RAMROD_CMD_ID_ETH_UPDATE (100)
 247 #define RAMROD_CMD_ID_ETH_HALT (105)
 248 #define RAMROD_CMD_ID_ETH_SET_MAC (110)
 249 #define RAMROD_CMD_ID_ETH_CFC_DEL (115)
 250 #define RAMROD_CMD_ID_ETH_PORT_DEL (120)
 251 #define RAMROD_CMD_ID_ETH_FORWARD_SETUP (125)
 252
 253
 254 /* command values for set mac command */
 255 #define T_ETH_MAC_COMMAND_SET 0
 256 #define T_ETH_MAC_COMMAND_INVALIDATE 1
 257
 258 #define T_ETH_INDIRECTION_TABLE_SIZE 128
 259
 260 /*The CRC32 seed, that is used for the hash(reduction) multicast address */
 261 #define T_ETH_CRC32_HASH_SEED 0x00000000
 262
 263 /* Maximal L2 clients supported */
 264 #define ETH_MAX_RX_CLIENTS_E1 19
 265 #define ETH_MAX_RX_CLIENTS_E1H 25
 266
 267 /* Maximal aggregation queues supported */
 268 #define ETH_MAX_AGGREGATION_QUEUES_E1 (32)
 269 #define ETH_MAX_AGGREGATION_QUEUES_E1H (64)
 270
 271 /* ETH RSS modes */
 272 #define ETH_RSS_MODE_DISABLED 0
 273 #define ETH_RSS_MODE_REGULAR 1
 274
 275
 276 /**
 277 * This file defines HSI constatnts common to all microcode flows
 278 */
 279
 280 /* Connection types */
 281 #define ETH_CONNECTION_TYPE 0
 282 #define TOE_CONNECTION_TYPE 1
 283 #define RDMA_CONNECTION_TYPE 2
 284 #define ISCSI_CONNECTION_TYPE 3
 285 #define FCOE_CONNECTION_TYPE 4
 286 #define RESERVED_CONNECTION_TYPE_0 5
 287 #define RESERVED_CONNECTION_TYPE_1 6
 288 #define RESERVED_CONNECTION_TYPE_2 7
 289
 290
 291 #define PROTOCOL_STATE_BIT_OFFSET 6
 292
 293 #define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
 294 #define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
 295 #define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
 296
 297 /* microcode fixed page page size 4K (chains and ring segments) */
 298 #define MC_PAGE_SIZE (4096)
 299
 300
 301 /* Host coalescing constants */
 302
 303 /* index numbers */
 304 #define HC_USTORM_DEF_SB_NUM_INDICES 8
 305 #define HC_CSTORM_DEF_SB_NUM_INDICES 8
 306 #define HC_XSTORM_DEF_SB_NUM_INDICES 4
 307 #define HC_TSTORM_DEF_SB_NUM_INDICES 4
 308 #define HC_USTORM_SB_NUM_INDICES 4
 309 #define HC_CSTORM_SB_NUM_INDICES 4
 310
 311 /* index values - which counterto update */
 312
 313 #define HC_INDEX_U_TOE_RX_CQ_CONS 0
 314 #define HC_INDEX_U_ETH_RX_CQ_CONS 1
 315 #define HC_INDEX_U_ETH_RX_BD_CONS 2
 316 #define HC_INDEX_U_FCOE_EQ_CONS 3
 317
 318 #define HC_INDEX_C_TOE_TX_CQ_CONS 0
 319 #define HC_INDEX_C_ETH_TX_CQ_CONS 1
 320 #define HC_INDEX_C_ISCSI_EQ_CONS 2
 321
 322 #define HC_INDEX_DEF_X_SPQ_CONS 0
 323
 324 #define HC_INDEX_DEF_C_RDMA_EQ_CONS 0
 325 #define HC_INDEX_DEF_C_RDMA_NAL_PROD 1
 326 #define HC_INDEX_DEF_C_ETH_FW_TX_CQ_CONS 2
 327 #define HC_INDEX_DEF_C_ETH_SLOW_PATH 3
 328 #define HC_INDEX_DEF_C_ETH_RDMA_CQ_CONS 4
 329 #define HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS 5
 330
 331 #define HC_INDEX_DEF_U_ETH_RDMA_RX_CQ_CONS 0
 332 #define HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS 1
 333 #define HC_INDEX_DEF_U_ETH_RDMA_RX_BD_CONS 2
 334 #define HC_INDEX_DEF_U_ETH_ISCSI_RX_BD_CONS 3
 335
 336
 337 /* used by the driver to get the SB offset */
 338 #define USTORM_ID 0
 339 #define CSTORM_ID 1
 340 #define XSTORM_ID 2
 341 #define TSTORM_ID 3
 342 #define ATTENTION_ID 4
 343
 344 /* max number of slow path commands per port */
 345 #define MAX_RAMRODS_PER_PORT (8)
 346
 347 /* values for RX ETH CQE type field */
 348 #define RX_ETH_CQE_TYPE_ETH_FASTPATH (0)
 349 #define RX_ETH_CQE_TYPE_ETH_RAMROD (1)
 350
 351
 352 /**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
 353 #define EMULATION_FREQUENCY_FACTOR (1600)
 354 #define FPGA_FREQUENCY_FACTOR (100)
 355
 356 #define TIMERS_TICK_SIZE_CHIP (1e-3)
 357 #define TIMERS_TICK_SIZE_EMUL \
 358  ((TIMERS_TICK_SIZE_CHIP)/((EMULATION_FREQUENCY_FACTOR)))
 359 #define TIMERS_TICK_SIZE_FPGA \
 360  ((TIMERS_TICK_SIZE_CHIP)/((FPGA_FREQUENCY_FACTOR)))
 361
 362 #define TSEMI_CLK1_RESUL_CHIP (1e-3)
 363 #define TSEMI_CLK1_RESUL_EMUL \
 364  ((TSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
 365 #define TSEMI_CLK1_RESUL_FPGA \
 366  ((TSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
 367
 368 #define USEMI_CLK1_RESUL_CHIP \
 369  (TIMERS_TICK_SIZE_CHIP)
 370 #define USEMI_CLK1_RESUL_EMUL \
 371  (TIMERS_TICK_SIZE_EMUL)
 372 #define USEMI_CLK1_RESUL_FPGA \
 373  (TIMERS_TICK_SIZE_FPGA)
 374
 375 #define XSEMI_CLK1_RESUL_CHIP (1e-3)
 376 #define XSEMI_CLK1_RESUL_EMUL \
 377  ((XSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
 378 #define XSEMI_CLK1_RESUL_FPGA \
 379  ((XSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
 380
 381 #define XSEMI_CLK2_RESUL_CHIP (1e-6)
 382 #define XSEMI_CLK2_RESUL_EMUL \
 383  ((XSEMI_CLK2_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
 384 #define XSEMI_CLK2_RESUL_FPGA \
 385  ((XSEMI_CLK2_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
 386
 387 #define SDM_TIMER_TICK_RESUL_CHIP (4*(1e-6))
 388 #define SDM_TIMER_TICK_RESUL_EMUL \
 389  ((SDM_TIMER_TICK_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
 390 #define SDM_TIMER_TICK_RESUL_FPGA \
 391  ((SDM_TIMER_TICK_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
 392
 393
 394 /**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
 395 #define XSTORM_IP_ID_ROLL_HALF 0x8000
 396 #define XSTORM_IP_ID_ROLL_ALL 0
 397
 398 #define FW_LOG_LIST_SIZE (50)
 399
 400 #define NUM_OF_PROTOCOLS 4
 401 #define NUM_OF_SAFC_BITS 16
 402 #define MAX_COS_NUMBER 4
 403 #define MAX_T_STAT_COUNTER_ID 18
 404 #define MAX_X_STAT_COUNTER_ID 18
 405 #define MAX_U_STAT_COUNTER_ID 18
 406
 407
 408 #define UNKNOWN_ADDRESS 0
 409 #define UNICAST_ADDRESS 1
 410 #define MULTICAST_ADDRESS 2
 411 #define BROADCAST_ADDRESS 3
 412
 413 #define SINGLE_FUNCTION 0
 414 #define MULTI_FUNCTION 1
 415
 416 #define IP_V4 0
 417 #define IP_V6 1
 418