include/drm/i915_drm.h

   1 /*
   2  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  20  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #ifndef _I915_DRM_H_
  28 #define _I915_DRM_H_
  29
  30 /* Please note that modifications to all structs defined here are
  31  * subject to backwards-compatibility constraints.
  32  */
  33
  34 #include "drm.h"
  35
  36 /* Each region is a minimum of 16k, and there are at most 255 of them.
  37  */
  38 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
  39                                  * of chars for next/prev indices */
  40 #define I915_LOG_MIN_TEX_REGION_SIZE 14
  41
  42 typedef struct _drm_i915_init {
  43         enum {
  44                 I915_INIT_DMA = 0x01,
  45                 I915_CLEANUP_DMA = 0x02,
  46                 I915_RESUME_DMA = 0x03
  47         } func;
  48         unsigned int mmio_offset;
  49         int sarea_priv_offset;
  50         unsigned int ring_start;
  51         unsigned int ring_end;
  52         unsigned int ring_size;
  53         unsigned int front_offset;
  54         unsigned int back_offset;
  55         unsigned int depth_offset;
  56         unsigned int w;
  57         unsigned int h;
  58         unsigned int pitch;
  59         unsigned int pitch_bits;
  60         unsigned int back_pitch;
  61         unsigned int depth_pitch;
  62         unsigned int cpp;
  63         unsigned int chipset;
  64 } drm_i915_init_t;
  65
  66 typedef struct _drm_i915_sarea {
  67         struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
  68         int last_upload;        /* last time texture was uploaded */
  69         int last_enqueue;       /* last time a buffer was enqueued */
  70         int last_dispatch;      /* age of the most recently dispatched buffer */
  71         int ctxOwner;           /* last context to upload state */
  72         int texAge;
  73         int pf_enabled;         /* is pageflipping allowed? */
  74         int pf_active;
  75         int pf_current_page;    /* which buffer is being displayed? */
  76         int perf_boxes;         /* performance boxes to be displayed */
  77         int width, height;      /* screen size in pixels */
  78
  79         drm_handle_t front_handle;
  80         int front_offset;
  81         int front_size;
  82
  83         drm_handle_t back_handle;
  84         int back_offset;
  85         int back_size;
  86
  87         drm_handle_t depth_handle;
  88         int depth_offset;
  89         int depth_size;
  90
  91         drm_handle_t tex_handle;
  92         int tex_offset;
  93         int tex_size;
  94         int log_tex_granularity;
  95         int pitch;
  96         int rotation;           /* 0, 90, 180 or 270 */
  97         int rotated_offset;
  98         int rotated_size;
  99         int rotated_pitch;
 100         int virtualX, virtualY;
 101
 102         unsigned int front_tiled;
 103         unsigned int back_tiled;
 104         unsigned int depth_tiled;
 105         unsigned int rotated_tiled;
 106         unsigned int rotated2_tiled;
 107
 108         int pipeA_x;
 109         int pipeA_y;
 110         int pipeA_w;
 111         int pipeA_h;
 112         int pipeB_x;
 113         int pipeB_y;
 114         int pipeB_w;
 115         int pipeB_h;
 116 } drm_i915_sarea_t;
 117
 118 /* Flags for perf_boxes
 119  */
 120 #define I915_BOX_RING_EMPTY    0x1
 121 #define I915_BOX_FLIP          0x2
 122 #define I915_BOX_WAIT          0x4
 123 #define I915_BOX_TEXTURE_LOAD  0x8
 124 #define I915_BOX_LOST_CONTEXT  0x10
 125
 126 /* I915 specific ioctls
 127  * The device specific ioctl range is 0x40 to 0x79.
 128  */
 129 #define DRM_I915_INIT           0x00
 130 #define DRM_I915_FLUSH          0x01
 131 #define DRM_I915_FLIP           0x02
 132 #define DRM_I915_BATCHBUFFER    0x03
 133 #define DRM_I915_IRQ_EMIT       0x04
 134 #define DRM_I915_IRQ_WAIT       0x05
 135 #define DRM_I915_GETPARAM       0x06
 136 #define DRM_I915_SETPARAM       0x07
 137 #define DRM_I915_ALLOC          0x08
 138 #define DRM_I915_FREE           0x09
 139 #define DRM_I915_INIT_HEAP      0x0a
 140 #define DRM_I915_CMDBUFFER      0x0b
 141 #define DRM_I915_DESTROY_HEAP   0x0c
 142 #define DRM_I915_SET_VBLANK_PIPE        0x0d
 143 #define DRM_I915_GET_VBLANK_PIPE        0x0e
 144 #define DRM_I915_VBLANK_SWAP    0x0f
 145 #define DRM_I915_HWS_ADDR       0x11
 146 #define DRM_I915_GEM_INIT       0x13
 147 #define DRM_I915_GEM_EXECBUFFER 0x14
 148 #define DRM_I915_GEM_PIN        0x15
 149 #define DRM_I915_GEM_UNPIN      0x16
 150 #define DRM_I915_GEM_BUSY       0x17
 151 #define DRM_I915_GEM_THROTTLE   0x18
 152 #define DRM_I915_GEM_ENTERVT    0x19
 153 #define DRM_I915_GEM_LEAVEVT    0x1a
 154 #define DRM_I915_GEM_CREATE     0x1b
 155 #define DRM_I915_GEM_PREAD      0x1c
 156 #define DRM_I915_GEM_PWRITE     0x1d
 157 #define DRM_I915_GEM_MMAP       0x1e
 158 #define DRM_I915_GEM_SET_DOMAIN 0x1f
 159 #define DRM_I915_GEM_SW_FINISH  0x20
 160 #define DRM_I915_GEM_SET_TILING 0x21
 161 #define DRM_I915_GEM_GET_TILING 0x22
 162 #define DRM_I915_GEM_GET_APERTURE 0x23
 163 #define DRM_I915_GEM_MMAP_GTT   0x24
 164
 165 #define DRM_IOCTL_I915_INIT             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 166 #define DRM_IOCTL_I915_FLUSH            DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
 167 #define DRM_IOCTL_I915_FLIP             DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
 168 #define DRM_IOCTL_I915_BATCHBUFFER      DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
 169 #define DRM_IOCTL_I915_IRQ_EMIT         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
 170 #define DRM_IOCTL_I915_IRQ_WAIT         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
 171 #define DRM_IOCTL_I915_GETPARAM         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
 172 #define DRM_IOCTL_I915_SETPARAM         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
 173 #define DRM_IOCTL_I915_ALLOC            DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
 174 #define DRM_IOCTL_I915_FREE             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
 175 #define DRM_IOCTL_I915_INIT_HEAP        DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
 176 #define DRM_IOCTL_I915_CMDBUFFER        DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
 177 #define DRM_IOCTL_I915_DESTROY_HEAP     DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
 178 #define DRM_IOCTL_I915_SET_VBLANK_PIPE  DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
 179 #define DRM_IOCTL_I915_GET_VBLANK_PIPE  DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
 180 #define DRM_IOCTL_I915_VBLANK_SWAP      DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
 181 #define DRM_IOCTL_I915_GEM_PIN          DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
 182 #define DRM_IOCTL_I915_GEM_UNPIN        DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
 183 #define DRM_IOCTL_I915_GEM_BUSY         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
 184 #define DRM_IOCTL_I915_GEM_THROTTLE     DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
 185 #define DRM_IOCTL_I915_GEM_ENTERVT      DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
 186 #define DRM_IOCTL_I915_GEM_LEAVEVT      DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
 187 #define DRM_IOCTL_I915_GEM_CREATE       DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
 188 #define DRM_IOCTL_I915_GEM_PREAD        DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
 189 #define DRM_IOCTL_I915_GEM_PWRITE       DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
 190 #define DRM_IOCTL_I915_GEM_MMAP         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
 191 #define DRM_IOCTL_I915_GEM_MMAP_GTT     DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
 192 #define DRM_IOCTL_I915_GEM_SET_DOMAIN   DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
 193 #define DRM_IOCTL_I915_GEM_SW_FINISH    DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
 194 #define DRM_IOCTL_I915_GEM_SET_TILING   DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
 195 #define DRM_IOCTL_I915_GEM_GET_TILING   DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
 196 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR  (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
 197
 198 /* Allow drivers to submit batchbuffers directly to hardware, relying
 199  * on the security mechanisms provided by hardware.
 200  */
 201 typedef struct _drm_i915_batchbuffer {
 202         int start;              /* agp offset */
 203         int used;               /* nr bytes in use */
 204         int DR1;                /* hw flags for GFX_OP_DRAWRECT_INFO */
 205         int DR4;                /* window origin for GFX_OP_DRAWRECT_INFO */
 206         int num_cliprects;      /* mulitpass with multiple cliprects? */
 207         struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
 208 } drm_i915_batchbuffer_t;
 209
 210 /* As above, but pass a pointer to userspace buffer which can be
 211  * validated by the kernel prior to sending to hardware.
 212  */
 213 typedef struct _drm_i915_cmdbuffer {
 214         char __user *buf;       /* pointer to userspace command buffer */
 215         int sz;                 /* nr bytes in buf */
 216         int DR1;                /* hw flags for GFX_OP_DRAWRECT_INFO */
 217         int DR4;                /* window origin for GFX_OP_DRAWRECT_INFO */
 218         int num_cliprects;      /* mulitpass with multiple cliprects? */
 219         struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
 220 } drm_i915_cmdbuffer_t;
 221
 222 /* Userspace can request & wait on irq's:
 223  */
 224 typedef struct drm_i915_irq_emit {
 225         int __user *irq_seq;
 226 } drm_i915_irq_emit_t;
 227
 228 typedef struct drm_i915_irq_wait {
 229         int irq_seq;
 230 } drm_i915_irq_wait_t;
 231
 232 /* Ioctl to query kernel params:
 233  */
 234 #define I915_PARAM_IRQ_ACTIVE            1
 235 #define I915_PARAM_ALLOW_BATCHBUFFER     2
 236 #define I915_PARAM_LAST_DISPATCH         3
 237 #define I915_PARAM_CHIPSET_ID            4
 238 #define I915_PARAM_HAS_GEM               5
 239
 240 typedef struct drm_i915_getparam {
 241         int param;
 242         int __user *value;
 243 } drm_i915_getparam_t;
 244
 245 /* Ioctl to set kernel params:
 246  */
 247 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START            1
 248 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY             2
 249 #define I915_SETPARAM_ALLOW_BATCHBUFFER                   3
 250
 251 typedef struct drm_i915_setparam {
 252         int param;
 253         int value;
 254 } drm_i915_setparam_t;
 255
 256 /* A memory manager for regions of shared memory:
 257  */
 258 #define I915_MEM_REGION_AGP 1
 259
 260 typedef struct drm_i915_mem_alloc {
 261         int region;
 262         int alignment;
 263         int size;
 264         int __user *region_offset;      /* offset from start of fb or agp */
 265 } drm_i915_mem_alloc_t;
 266
 267 typedef struct drm_i915_mem_free {
 268         int region;
 269         int region_offset;
 270 } drm_i915_mem_free_t;
 271
 272 typedef struct drm_i915_mem_init_heap {
 273         int region;
 274         int size;
 275         int start;
 276 } drm_i915_mem_init_heap_t;
 277
 278 /* Allow memory manager to be torn down and re-initialized (eg on
 279  * rotate):
 280  */
 281 typedef struct drm_i915_mem_destroy_heap {
 282         int region;
 283 } drm_i915_mem_destroy_heap_t;
 284
 285 /* Allow X server to configure which pipes to monitor for vblank signals
 286  */
 287 #define DRM_I915_VBLANK_PIPE_A  1
 288 #define DRM_I915_VBLANK_PIPE_B  2
 289
 290 typedef struct drm_i915_vblank_pipe {
 291         int pipe;
 292 } drm_i915_vblank_pipe_t;
 293
 294 /* Schedule buffer swap at given vertical blank:
 295  */
 296 typedef struct drm_i915_vblank_swap {
 297         drm_drawable_t drawable;
 298         enum drm_vblank_seq_type seqtype;
 299         unsigned int sequence;
 300 } drm_i915_vblank_swap_t;
 301
 302 typedef struct drm_i915_hws_addr {
 303         uint64_t addr;
 304 } drm_i915_hws_addr_t;
 305
 306 struct drm_i915_gem_init {
 307         /**
 308          * Beginning offset in the GTT to be managed by the DRM memory
 309          * manager.
 310          */
 311         uint64_t gtt_start;
 312         /**
 313          * Ending offset in the GTT to be managed by the DRM memory
 314          * manager.
 315          */
 316         uint64_t gtt_end;
 317 };
 318
 319 struct drm_i915_gem_create {
 320         /**
 321          * Requested size for the object.
 322          *
 323          * The (page-aligned) allocated size for the object will be returned.
 324          */
 325         uint64_t size;
 326         /**
 327          * Returned handle for the object.
 328          *
 329          * Object handles are nonzero.
 330          */
 331         uint32_t handle;
 332         uint32_t pad;
 333 };
 334
 335 struct drm_i915_gem_pread {
 336         /** Handle for the object being read. */
 337         uint32_t handle;
 338         uint32_t pad;
 339         /** Offset into the object to read from */
 340         uint64_t offset;
 341         /** Length of data to read */
 342         uint64_t size;
 343         /**
 344          * Pointer to write the data into.
 345          *
 346          * This is a fixed-size type for 32/64 compatibility.
 347          */
 348         uint64_t data_ptr;
 349 };
 350
 351 struct drm_i915_gem_pwrite {
 352         /** Handle for the object being written to. */
 353         uint32_t handle;
 354         uint32_t pad;
 355         /** Offset into the object to write to */
 356         uint64_t offset;
 357         /** Length of data to write */
 358         uint64_t size;
 359         /**
 360          * Pointer to read the data from.
 361          *
 362          * This is a fixed-size type for 32/64 compatibility.
 363          */
 364         uint64_t data_ptr;
 365 };
 366
 367 struct drm_i915_gem_mmap {
 368         /** Handle for the object being mapped. */
 369         uint32_t handle;
 370         uint32_t pad;
 371         /** Offset in the object to map. */
 372         uint64_t offset;
 373         /**
 374          * Length of data to map.
 375          *
 376          * The value will be page-aligned.
 377          */
 378         uint64_t size;
 379         /**
 380          * Returned pointer the data was mapped at.
 381          *
 382          * This is a fixed-size type for 32/64 compatibility.
 383          */
 384         uint64_t addr_ptr;
 385 };
 386
 387 struct drm_i915_gem_mmap_gtt {
 388         /** Handle for the object being mapped. */
 389         uint32_t handle;
 390         uint32_t pad;
 391         /**
 392          * Fake offset to use for subsequent mmap call
 393          *
 394          * This is a fixed-size type for 32/64 compatibility.
 395          */
 396         uint64_t offset;
 397 };
 398
 399 struct drm_i915_gem_set_domain {
 400         /** Handle for the object */
 401         uint32_t handle;
 402
 403         /** New read domains */
 404         uint32_t read_domains;
 405
 406         /** New write domain */
 407         uint32_t write_domain;
 408 };
 409
 410 struct drm_i915_gem_sw_finish {
 411         /** Handle for the object */
 412         uint32_t handle;
 413 };
 414
 415 struct drm_i915_gem_relocation_entry {
 416         /**
 417          * Handle of the buffer being pointed to by this relocation entry.
 418          *
 419          * It's appealing to make this be an index into the mm_validate_entry
 420          * list to refer to the buffer, but this allows the driver to create
 421          * a relocation list for state buffers and not re-write it per
 422          * exec using the buffer.
 423          */
 424         uint32_t target_handle;
 425
 426         /**
 427          * Value to be added to the offset of the target buffer to make up
 428          * the relocation entry.
 429          */
 430         uint32_t delta;
 431
 432         /** Offset in the buffer the relocation entry will be written into */
 433         uint64_t offset;
 434
 435         /**
 436          * Offset value of the target buffer that the relocation entry was last
 437          * written as.
 438          *
 439          * If the buffer has the same offset as last time, we can skip syncing
 440          * and writing the relocation.  This value is written back out by
 441          * the execbuffer ioctl when the relocation is written.
 442          */
 443         uint64_t presumed_offset;
 444
 445         /**
 446          * Target memory domains read by this operation.
 447          */
 448         uint32_t read_domains;
 449
 450         /**
 451          * Target memory domains written by this operation.
 452          *
 453          * Note that only one domain may be written by the whole
 454          * execbuffer operation, so that where there are conflicts,
 455          * the application will get -EINVAL back.
 456          */
 457         uint32_t write_domain;
 458 };
 459
 460 /** @{
 461  * Intel memory domains
 462  *
 463  * Most of these just align with the various caches in
 464  * the system and are used to flush and invalidate as
 465  * objects end up cached in different domains.
 466  */
 467 /** CPU cache */
 468 #define I915_GEM_DOMAIN_CPU             0x00000001
 469 /** Render cache, used by 2D and 3D drawing */
 470 #define I915_GEM_DOMAIN_RENDER          0x00000002
 471 /** Sampler cache, used by texture engine */
 472 #define I915_GEM_DOMAIN_SAMPLER         0x00000004
 473 /** Command queue, used to load batch buffers */
 474 #define I915_GEM_DOMAIN_COMMAND         0x00000008
 475 /** Instruction cache, used by shader programs */
 476 #define I915_GEM_DOMAIN_INSTRUCTION     0x00000010
 477 /** Vertex address cache */
 478 #define I915_GEM_DOMAIN_VERTEX          0x00000020
 479 /** GTT domain - aperture and scanout */
 480 #define I915_GEM_DOMAIN_GTT             0x00000040
 481 /** @} */
 482
 483 struct drm_i915_gem_exec_object {
 484         /**
 485          * User's handle for a buffer to be bound into the GTT for this
 486          * operation.
 487          */
 488         uint32_t handle;
 489
 490         /** Number of relocations to be performed on this buffer */
 491         uint32_t relocation_count;
 492         /**
 493          * Pointer to array of struct drm_i915_gem_relocation_entry containing
 494          * the relocations to be performed in this buffer.
 495          */
 496         uint64_t relocs_ptr;
 497
 498         /** Required alignment in graphics aperture */
 499         uint64_t alignment;
 500
 501         /**
 502          * Returned value of the updated offset of the object, for future
 503          * presumed_offset writes.
 504          */
 505         uint64_t offset;
 506 };
 507
 508 struct drm_i915_gem_execbuffer {
 509         /**
 510          * List of buffers to be validated with their relocations to be
 511          * performend on them.
 512          *
 513          * This is a pointer to an array of struct drm_i915_gem_validate_entry.
 514          *
 515          * These buffers must be listed in an order such that all relocations
 516          * a buffer is performing refer to buffers that have already appeared
 517          * in the validate list.
 518          */
 519         uint64_t buffers_ptr;
 520         uint32_t buffer_count;
 521
 522         /** Offset in the batchbuffer to start execution from. */
 523         uint32_t batch_start_offset;
 524         /** Bytes used in batchbuffer from batch_start_offset */
 525         uint32_t batch_len;
 526         uint32_t DR1;
 527         uint32_t DR4;
 528         uint32_t num_cliprects;
 529         /** This is a struct drm_clip_rect *cliprects */
 530         uint64_t cliprects_ptr;
 531 };
 532
 533 struct drm_i915_gem_pin {
 534         /** Handle of the buffer to be pinned. */
 535         uint32_t handle;
 536         uint32_t pad;
 537
 538         /** alignment required within the aperture */
 539         uint64_t alignment;
 540
 541         /** Returned GTT offset of the buffer. */
 542         uint64_t offset;
 543 };
 544
 545 struct drm_i915_gem_unpin {
 546         /** Handle of the buffer to be unpinned. */
 547         uint32_t handle;
 548         uint32_t pad;
 549 };
 550
 551 struct drm_i915_gem_busy {
 552         /** Handle of the buffer to check for busy */
 553         uint32_t handle;
 554
 555         /** Return busy status (1 if busy, 0 if idle) */
 556         uint32_t busy;
 557 };
 558
 559 #define I915_TILING_NONE        0
 560 #define I915_TILING_X           1
 561 #define I915_TILING_Y           2
 562
 563 #define I915_BIT_6_SWIZZLE_NONE         0
 564 #define I915_BIT_6_SWIZZLE_9            1
 565 #define I915_BIT_6_SWIZZLE_9_10         2
 566 #define I915_BIT_6_SWIZZLE_9_11         3
 567 #define I915_BIT_6_SWIZZLE_9_10_11      4
 568 /* Not seen by userland */
 569 #define I915_BIT_6_SWIZZLE_UNKNOWN      5
 570
 571 struct drm_i915_gem_set_tiling {
 572         /** Handle of the buffer to have its tiling state updated */
 573         uint32_t handle;
 574
 575         /**
 576          * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
 577          * I915_TILING_Y).
 578          *
 579          * This value is to be set on request, and will be updated by the
 580          * kernel on successful return with the actual chosen tiling layout.
 581          *
 582          * The tiling mode may be demoted to I915_TILING_NONE when the system
 583          * has bit 6 swizzling that can't be managed correctly by GEM.
 584          *
 585          * Buffer contents become undefined when changing tiling_mode.
 586          */
 587         uint32_t tiling_mode;
 588
 589         /**
 590          * Stride in bytes for the object when in I915_TILING_X or
 591          * I915_TILING_Y.
 592          */
 593         uint32_t stride;
 594
 595         /**
 596          * Returned address bit 6 swizzling required for CPU access through
 597          * mmap mapping.
 598          */
 599         uint32_t swizzle_mode;
 600 };
 601
 602 struct drm_i915_gem_get_tiling {
 603         /** Handle of the buffer to get tiling state for. */
 604         uint32_t handle;
 605
 606         /**
 607          * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
 608          * I915_TILING_Y).
 609          */
 610         uint32_t tiling_mode;
 611
 612         /**
 613          * Returned address bit 6 swizzling required for CPU access through
 614          * mmap mapping.
 615          */
 616         uint32_t swizzle_mode;
 617 };
 618
 619 struct drm_i915_gem_get_aperture {
 620         /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
 621         uint64_t aper_size;
 622
 623         /**
 624          * Available space in the aperture used by i915_gem_execbuffer, in
 625          * bytes
 626          */
 627         uint64_t aper_available_size;
 628 };
 629
 630 #endif                          /* _I915_DRM_H_ */