1 #include <linux/errno.h>
2 #include <linux/kernel.h>
5 #include <linux/prctl.h>
6 #include <linux/slab.h>
7 #include <linux/sched.h>
8 #include <linux/module.h>
10 #include <linux/clockchips.h>
11 #include <linux/random.h>
12 #include <trace/events/power.h>
13 #include <asm/system.h>
15 #include <asm/syscalls.h>
17 #include <asm/uaccess.h>
21 unsigned long idle_halt
;
22 EXPORT_SYMBOL(idle_halt
);
23 unsigned long idle_nomwait
;
24 EXPORT_SYMBOL(idle_nomwait
);
26 struct kmem_cache
*task_xstate_cachep
;
28 int arch_dup_task_struct(struct task_struct
*dst
, struct task_struct
*src
)
31 if (src
->thread
.xstate
) {
32 dst
->thread
.xstate
= kmem_cache_alloc(task_xstate_cachep
,
34 if (!dst
->thread
.xstate
)
36 WARN_ON((unsigned long)dst
->thread
.xstate
& 15);
37 memcpy(dst
->thread
.xstate
, src
->thread
.xstate
, xstate_size
);
42 void free_thread_xstate(struct task_struct
*tsk
)
44 if (tsk
->thread
.xstate
) {
45 kmem_cache_free(task_xstate_cachep
, tsk
->thread
.xstate
);
46 tsk
->thread
.xstate
= NULL
;
49 WARN(tsk
->thread
.ds_ctx
, "leaking DS context\n");
52 void free_thread_info(struct thread_info
*ti
)
54 free_thread_xstate(ti
->task
);
55 free_pages((unsigned long)ti
, get_order(THREAD_SIZE
));
58 void arch_task_cache_init(void)
61 kmem_cache_create("task_xstate", xstate_size
,
62 __alignof__(union thread_xstate
),
63 SLAB_PANIC
| SLAB_NOTRACK
, NULL
);
67 * Free current thread data structures etc..
69 void exit_thread(void)
71 struct task_struct
*me
= current
;
72 struct thread_struct
*t
= &me
->thread
;
73 unsigned long *bp
= t
->io_bitmap_ptr
;
76 struct tss_struct
*tss
= &per_cpu(init_tss
, get_cpu());
78 t
->io_bitmap_ptr
= NULL
;
79 clear_thread_flag(TIF_IO_BITMAP
);
81 * Careful, clear this in the TSS too:
83 memset(tss
->io_bitmap
, 0xff, t
->io_bitmap_max
);
90 void flush_thread(void)
92 struct task_struct
*tsk
= current
;
94 clear_tsk_thread_flag(tsk
, TIF_DEBUG
);
96 tsk
->thread
.debugreg0
= 0;
97 tsk
->thread
.debugreg1
= 0;
98 tsk
->thread
.debugreg2
= 0;
99 tsk
->thread
.debugreg3
= 0;
100 tsk
->thread
.debugreg6
= 0;
101 tsk
->thread
.debugreg7
= 0;
102 memset(tsk
->thread
.tls_array
, 0, sizeof(tsk
->thread
.tls_array
));
104 * Forget coprocessor state..
106 tsk
->fpu_counter
= 0;
111 static void hard_disable_TSC(void)
113 write_cr4(read_cr4() | X86_CR4_TSD
);
116 void disable_TSC(void)
119 if (!test_and_set_thread_flag(TIF_NOTSC
))
121 * Must flip the CPU state synchronously with
122 * TIF_NOTSC in the current running context.
128 static void hard_enable_TSC(void)
130 write_cr4(read_cr4() & ~X86_CR4_TSD
);
133 static void enable_TSC(void)
136 if (test_and_clear_thread_flag(TIF_NOTSC
))
138 * Must flip the CPU state synchronously with
139 * TIF_NOTSC in the current running context.
145 int get_tsc_mode(unsigned long adr
)
149 if (test_thread_flag(TIF_NOTSC
))
150 val
= PR_TSC_SIGSEGV
;
154 return put_user(val
, (unsigned int __user
*)adr
);
157 int set_tsc_mode(unsigned int val
)
159 if (val
== PR_TSC_SIGSEGV
)
161 else if (val
== PR_TSC_ENABLE
)
169 void __switch_to_xtra(struct task_struct
*prev_p
, struct task_struct
*next_p
,
170 struct tss_struct
*tss
)
172 struct thread_struct
*prev
, *next
;
174 prev
= &prev_p
->thread
;
175 next
= &next_p
->thread
;
177 if (test_tsk_thread_flag(next_p
, TIF_DS_AREA_MSR
) ||
178 test_tsk_thread_flag(prev_p
, TIF_DS_AREA_MSR
))
179 ds_switch_to(prev_p
, next_p
);
180 else if (next
->debugctlmsr
!= prev
->debugctlmsr
)
181 update_debugctlmsr(next
->debugctlmsr
);
183 if (test_tsk_thread_flag(next_p
, TIF_DEBUG
)) {
184 set_debugreg(next
->debugreg0
, 0);
185 set_debugreg(next
->debugreg1
, 1);
186 set_debugreg(next
->debugreg2
, 2);
187 set_debugreg(next
->debugreg3
, 3);
189 set_debugreg(next
->debugreg6
, 6);
190 set_debugreg(next
->debugreg7
, 7);
193 if (test_tsk_thread_flag(prev_p
, TIF_NOTSC
) ^
194 test_tsk_thread_flag(next_p
, TIF_NOTSC
)) {
195 /* prev and next are different */
196 if (test_tsk_thread_flag(next_p
, TIF_NOTSC
))
202 if (test_tsk_thread_flag(next_p
, TIF_IO_BITMAP
)) {
204 * Copy the relevant range of the IO bitmap.
205 * Normally this is 128 bytes or less:
207 memcpy(tss
->io_bitmap
, next
->io_bitmap_ptr
,
208 max(prev
->io_bitmap_max
, next
->io_bitmap_max
));
209 } else if (test_tsk_thread_flag(prev_p
, TIF_IO_BITMAP
)) {
211 * Clear any possible leftover bits:
213 memset(tss
->io_bitmap
, 0xff, prev
->io_bitmap_max
);
217 int sys_fork(struct pt_regs
*regs
)
219 return do_fork(SIGCHLD
, regs
->sp
, regs
, 0, NULL
, NULL
);
223 * This is trivial, and on the face of it looks like it
224 * could equally well be done in user mode.
226 * Not so, for quite unobvious reasons - register pressure.
227 * In user mode vfork() cannot have a stack frame, and if
228 * done by calling the "clone()" system call directly, you
229 * do not have enough call-clobbered registers to hold all
230 * the information you need.
232 int sys_vfork(struct pt_regs
*regs
)
234 return do_fork(CLONE_VFORK
| CLONE_VM
| SIGCHLD
, regs
->sp
, regs
, 0,
240 * Idle related variables and functions
242 unsigned long boot_option_idle_override
= 0;
243 EXPORT_SYMBOL(boot_option_idle_override
);
246 * Powermanagement idle function, if any..
248 void (*pm_idle
)(void);
249 EXPORT_SYMBOL(pm_idle
);
253 * This halt magic was a workaround for ancient floppy DMA
254 * wreckage. It should be safe to remove.
256 static int hlt_counter
;
257 void disable_hlt(void)
261 EXPORT_SYMBOL(disable_hlt
);
263 void enable_hlt(void)
267 EXPORT_SYMBOL(enable_hlt
);
269 static inline int hlt_use_halt(void)
271 return (!hlt_counter
&& boot_cpu_data
.hlt_works_ok
);
274 static inline int hlt_use_halt(void)
281 * We use this if we don't have any better
284 void default_idle(void)
286 if (hlt_use_halt()) {
287 trace_power_start(POWER_CSTATE
, 1);
288 current_thread_info()->status
&= ~TS_POLLING
;
290 * TS_POLLING-cleared state must be visible before we
296 safe_halt(); /* enables interrupts racelessly */
299 current_thread_info()->status
|= TS_POLLING
;
302 /* loop is done by the caller */
306 #ifdef CONFIG_APM_MODULE
307 EXPORT_SYMBOL(default_idle
);
310 void stop_this_cpu(void *dummy
)
316 set_cpu_online(smp_processor_id(), false);
317 disable_local_APIC();
320 if (hlt_works(smp_processor_id()))
325 static void do_nothing(void *unused
)
330 * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
331 * pm_idle and update to new pm_idle value. Required while changing pm_idle
332 * handler on SMP systems.
334 * Caller must have changed pm_idle to the new value before the call. Old
335 * pm_idle value will not be used by any CPU after the return of this function.
337 void cpu_idle_wait(void)
340 /* kick all the CPUs so that they exit out of pm_idle */
341 smp_call_function(do_nothing
, NULL
, 1);
343 EXPORT_SYMBOL_GPL(cpu_idle_wait
);
346 * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
347 * which can obviate IPI to trigger checking of need_resched.
348 * We execute MONITOR against need_resched and enter optimized wait state
349 * through MWAIT. Whenever someone changes need_resched, we would be woken
350 * up from MWAIT (without an IPI).
352 * New with Core Duo processors, MWAIT can take some hints based on CPU
355 void mwait_idle_with_hints(unsigned long ax
, unsigned long cx
)
357 trace_power_start(POWER_CSTATE
, (ax
>>4)+1);
358 if (!need_resched()) {
359 if (cpu_has(¤t_cpu_data
, X86_FEATURE_CLFLUSH_MONITOR
))
360 clflush((void *)¤t_thread_info()->flags
);
362 __monitor((void *)¤t_thread_info()->flags
, 0, 0);
369 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
370 static void mwait_idle(void)
372 if (!need_resched()) {
373 trace_power_start(POWER_CSTATE
, 1);
374 if (cpu_has(¤t_cpu_data
, X86_FEATURE_CLFLUSH_MONITOR
))
375 clflush((void *)¤t_thread_info()->flags
);
377 __monitor((void *)¤t_thread_info()->flags
, 0, 0);
388 * On SMP it's slightly faster (but much more power-consuming!)
389 * to poll the ->work.need_resched flag instead of waiting for the
390 * cross-CPU IPI to arrive. Use this option with caution.
392 static void poll_idle(void)
394 trace_power_start(POWER_CSTATE
, 0);
396 while (!need_resched())
402 * mwait selection logic:
404 * It depends on the CPU. For AMD CPUs that support MWAIT this is
405 * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
406 * then depend on a clock divisor and current Pstate of the core. If
407 * all cores of a processor are in halt state (C1) the processor can
408 * enter the C1E (C1 enhanced) state. If mwait is used this will never
411 * idle=mwait overrides this decision and forces the usage of mwait.
413 static int __cpuinitdata force_mwait
;
415 #define MWAIT_INFO 0x05
416 #define MWAIT_ECX_EXTENDED_INFO 0x01
417 #define MWAIT_EDX_C1 0xf0
419 static int __cpuinit
mwait_usable(const struct cpuinfo_x86
*c
)
421 u32 eax
, ebx
, ecx
, edx
;
426 if (c
->cpuid_level
< MWAIT_INFO
)
429 cpuid(MWAIT_INFO
, &eax
, &ebx
, &ecx
, &edx
);
430 /* Check, whether EDX has extended info about MWAIT */
431 if (!(ecx
& MWAIT_ECX_EXTENDED_INFO
))
435 * edx enumeratios MONITOR/MWAIT extensions. Check, whether
438 return (edx
& MWAIT_EDX_C1
);
442 * Check for AMD CPUs, which have potentially C1E support
444 static int __cpuinit
check_c1e_idle(const struct cpuinfo_x86
*c
)
446 if (c
->x86_vendor
!= X86_VENDOR_AMD
)
452 /* Family 0x0f models < rev F do not have C1E */
453 if (c
->x86
== 0x0f && c
->x86_model
< 0x40)
459 static cpumask_var_t c1e_mask
;
460 static int c1e_detected
;
462 void c1e_remove_cpu(int cpu
)
464 if (c1e_mask
!= NULL
)
465 cpumask_clear_cpu(cpu
, c1e_mask
);
469 * C1E aware idle routine. We check for C1E active in the interrupt
470 * pending message MSR. If we detect C1E, then we handle it the same
471 * way as C3 power states (local apic timer and TSC stop)
473 static void c1e_idle(void)
481 rdmsr(MSR_K8_INT_PENDING_MSG
, lo
, hi
);
482 if (lo
& K8_INTP_C1E_ACTIVE_MASK
) {
484 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC
))
485 mark_tsc_unstable("TSC halt in AMD C1E");
486 printk(KERN_INFO
"System has AMD C1E enabled\n");
487 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_AMDC1E
);
492 int cpu
= smp_processor_id();
494 if (!cpumask_test_cpu(cpu
, c1e_mask
)) {
495 cpumask_set_cpu(cpu
, c1e_mask
);
497 * Force broadcast so ACPI can not interfere.
499 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE
,
501 printk(KERN_INFO
"Switch to broadcast mode on CPU%d\n",
504 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER
, &cpu
);
509 * The switch back from broadcast mode needs to be
510 * called with interrupts disabled.
513 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT
, &cpu
);
519 void __cpuinit
select_idle_routine(const struct cpuinfo_x86
*c
)
522 if (pm_idle
== poll_idle
&& smp_num_siblings
> 1) {
523 printk(KERN_WARNING
"WARNING: polling idle and HT enabled,"
524 " performance may degrade.\n");
530 if (cpu_has(c
, X86_FEATURE_MWAIT
) && mwait_usable(c
)) {
532 * One CPU supports mwait => All CPUs supports mwait
534 printk(KERN_INFO
"using mwait in idle threads.\n");
535 pm_idle
= mwait_idle
;
536 } else if (check_c1e_idle(c
)) {
537 printk(KERN_INFO
"using C1E aware idle routine\n");
540 pm_idle
= default_idle
;
543 void __init
init_c1e_mask(void)
545 /* If we're using c1e_idle, we need to allocate c1e_mask. */
546 if (pm_idle
== c1e_idle
)
547 zalloc_cpumask_var(&c1e_mask
, GFP_KERNEL
);
550 static int __init
idle_setup(char *str
)
555 if (!strcmp(str
, "poll")) {
556 printk("using polling idle threads.\n");
558 } else if (!strcmp(str
, "mwait"))
560 else if (!strcmp(str
, "halt")) {
562 * When the boot option of idle=halt is added, halt is
563 * forced to be used for CPU idle. In such case CPU C2/C3
564 * won't be used again.
565 * To continue to load the CPU idle driver, don't touch
566 * the boot_option_idle_override.
568 pm_idle
= default_idle
;
571 } else if (!strcmp(str
, "nomwait")) {
573 * If the boot option of "idle=nomwait" is added,
574 * it means that mwait will be disabled for CPU C2/C3
575 * states. In such case it won't touch the variable
576 * of boot_option_idle_override.
583 boot_option_idle_override
= 1;
586 early_param("idle", idle_setup
);
588 unsigned long arch_align_stack(unsigned long sp
)
590 if (!(current
->personality
& ADDR_NO_RANDOMIZE
) && randomize_va_space
)
591 sp
-= get_random_int() % 8192;
595 unsigned long arch_randomize_brk(struct mm_struct
*mm
)
597 unsigned long range_end
= mm
->brk
+ 0x02000000;
598 return randomize_range(mm
->brk
, range_end
, 0) ? : mm
->brk
;