2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
4 * Copyright 2005 Tejun Heo
6 * Based on preview driver from Silicon Image.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/blkdev.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/device.h>
28 #include <scsi/scsi_host.h>
29 #include <scsi/scsi_cmnd.h>
30 #include <linux/libata.h>
33 #define DRV_NAME "sata_sil24"
34 #define DRV_VERSION "0.3"
37 * Port request block (PRB) 32 bytes
47 * Scatter gather entry (SGE) 16 bytes
58 struct sil24_port_multiplier
{
65 * Global controller registers (128 bytes @ BAR0)
68 HOST_SLOT_STAT
= 0x00, /* 32 bit slot stat * 4 */
72 HOST_BIST_CTRL
= 0x50,
73 HOST_BIST_PTRN
= 0x54,
74 HOST_BIST_STAT
= 0x58,
75 HOST_MEM_BIST_STAT
= 0x5c,
76 HOST_FLASH_CMD
= 0x70,
78 HOST_FLASH_DATA
= 0x74,
79 HOST_TRANSITION_DETECT
= 0x75,
80 HOST_GPIO_CTRL
= 0x76,
81 HOST_I2C_ADDR
= 0x78, /* 32 bit */
83 HOST_I2C_XFER_CNT
= 0x7e,
86 /* HOST_SLOT_STAT bits */
87 HOST_SSTAT_ATTN
= (1 << 31),
90 HOST_CTRL_M66EN
= (1 << 16), /* M66EN PCI bus signal */
91 HOST_CTRL_TRDY
= (1 << 17), /* latched PCI TRDY */
92 HOST_CTRL_STOP
= (1 << 18), /* latched PCI STOP */
93 HOST_CTRL_DEVSEL
= (1 << 19), /* latched PCI DEVSEL */
94 HOST_CTRL_REQ64
= (1 << 20), /* latched PCI REQ64 */
95 HOST_CTRL_GLOBAL_RST
= (1 << 31), /* global reset */
99 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
101 PORT_REGS_SIZE
= 0x2000,
103 PORT_LRAM
= 0x0000, /* 31 LRAM slots and PM regs */
104 PORT_LRAM_SLOT_SZ
= 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
106 PORT_PM
= 0x0f80, /* 8 bytes PM * 16 (128 bytes) */
108 PORT_CTRL_STAT
= 0x1000, /* write: ctrl-set, read: stat */
109 PORT_CTRL_CLR
= 0x1004, /* write: ctrl-clear */
110 PORT_IRQ_STAT
= 0x1008, /* high: status, low: interrupt */
111 PORT_IRQ_ENABLE_SET
= 0x1010, /* write: enable-set */
112 PORT_IRQ_ENABLE_CLR
= 0x1014, /* write: enable-clear */
113 PORT_ACTIVATE_UPPER_ADDR
= 0x101c,
114 PORT_EXEC_FIFO
= 0x1020, /* command execution fifo */
115 PORT_CMD_ERR
= 0x1024, /* command error number */
116 PORT_FIS_CFG
= 0x1028,
117 PORT_FIFO_THRES
= 0x102c,
119 PORT_DECODE_ERR_CNT
= 0x1040,
120 PORT_DECODE_ERR_THRESH
= 0x1042,
121 PORT_CRC_ERR_CNT
= 0x1044,
122 PORT_CRC_ERR_THRESH
= 0x1046,
123 PORT_HSHK_ERR_CNT
= 0x1048,
124 PORT_HSHK_ERR_THRESH
= 0x104a,
126 PORT_PHY_CFG
= 0x1050,
127 PORT_SLOT_STAT
= 0x1800,
128 PORT_CMD_ACTIVATE
= 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
129 PORT_EXEC_DIAG
= 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
130 PORT_PSD_DIAG
= 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
131 PORT_SCONTROL
= 0x1f00,
132 PORT_SSTATUS
= 0x1f04,
133 PORT_SERROR
= 0x1f08,
134 PORT_SACTIVE
= 0x1f0c,
136 /* PORT_CTRL_STAT bits */
137 PORT_CS_PORT_RST
= (1 << 0), /* port reset */
138 PORT_CS_DEV_RST
= (1 << 1), /* device reset */
139 PORT_CS_INIT
= (1 << 2), /* port initialize */
140 PORT_CS_IRQ_WOC
= (1 << 3), /* interrupt write one to clear */
141 PORT_CS_CDB16
= (1 << 5), /* 0=12b cdb, 1=16b cdb */
142 PORT_CS_RESUME
= (1 << 6), /* port resume */
143 PORT_CS_32BIT_ACTV
= (1 << 10), /* 32-bit activation */
144 PORT_CS_PM_EN
= (1 << 13), /* port multiplier enable */
145 PORT_CS_RDY
= (1 << 31), /* port ready to accept commands */
147 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
148 /* bits[11:0] are masked */
149 PORT_IRQ_COMPLETE
= (1 << 0), /* command(s) completed */
150 PORT_IRQ_ERROR
= (1 << 1), /* command execution error */
151 PORT_IRQ_PORTRDY_CHG
= (1 << 2), /* port ready change */
152 PORT_IRQ_PWR_CHG
= (1 << 3), /* power management change */
153 PORT_IRQ_PHYRDY_CHG
= (1 << 4), /* PHY ready change */
154 PORT_IRQ_COMWAKE
= (1 << 5), /* COMWAKE received */
155 PORT_IRQ_UNK_FIS
= (1 << 6), /* unknown FIS received */
156 PORT_IRQ_DEV_XCHG
= (1 << 7), /* device exchanged */
157 PORT_IRQ_8B10B
= (1 << 8), /* 8b/10b decode error threshold */
158 PORT_IRQ_CRC
= (1 << 9), /* CRC error threshold */
159 PORT_IRQ_HANDSHAKE
= (1 << 10), /* handshake error threshold */
160 PORT_IRQ_SDB_NOTIFY
= (1 << 11), /* SDB notify received */
162 DEF_PORT_IRQ
= PORT_IRQ_COMPLETE
| PORT_IRQ_ERROR
|
163 PORT_IRQ_PHYRDY_CHG
| PORT_IRQ_DEV_XCHG
|
166 /* bits[27:16] are unmasked (raw) */
167 PORT_IRQ_RAW_SHIFT
= 16,
168 PORT_IRQ_MASKED_MASK
= 0x7ff,
169 PORT_IRQ_RAW_MASK
= (0x7ff << PORT_IRQ_RAW_SHIFT
),
171 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
172 PORT_IRQ_STEER_SHIFT
= 30,
173 PORT_IRQ_STEER_MASK
= (3 << PORT_IRQ_STEER_SHIFT
),
175 /* PORT_CMD_ERR constants */
176 PORT_CERR_DEV
= 1, /* Error bit in D2H Register FIS */
177 PORT_CERR_SDB
= 2, /* Error bit in SDB FIS */
178 PORT_CERR_DATA
= 3, /* Error in data FIS not detected by dev */
179 PORT_CERR_SEND
= 4, /* Initial cmd FIS transmission failure */
180 PORT_CERR_INCONSISTENT
= 5, /* Protocol mismatch */
181 PORT_CERR_DIRECTION
= 6, /* Data direction mismatch */
182 PORT_CERR_UNDERRUN
= 7, /* Ran out of SGEs while writing */
183 PORT_CERR_OVERRUN
= 8, /* Ran out of SGEs while reading */
184 PORT_CERR_PKT_PROT
= 11, /* DIR invalid in 1st PIO setup of ATAPI */
185 PORT_CERR_SGT_BOUNDARY
= 16, /* PLD ecode 00 - SGT not on qword boundary */
186 PORT_CERR_SGT_TGTABRT
= 17, /* PLD ecode 01 - target abort */
187 PORT_CERR_SGT_MSTABRT
= 18, /* PLD ecode 10 - master abort */
188 PORT_CERR_SGT_PCIPERR
= 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
189 PORT_CERR_CMD_BOUNDARY
= 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
190 PORT_CERR_CMD_TGTABRT
= 25, /* ctrl[15:13] 010 - target abort */
191 PORT_CERR_CMD_MSTABRT
= 26, /* ctrl[15:13] 100 - master abort */
192 PORT_CERR_CMD_PCIPERR
= 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
193 PORT_CERR_XFR_UNDEF
= 32, /* PSD ecode 00 - undefined */
194 PORT_CERR_XFR_TGTABRT
= 33, /* PSD ecode 01 - target abort */
195 PORT_CERR_XFR_MSTABRT
= 34, /* PSD ecode 10 - master abort */
196 PORT_CERR_XFR_PCIPERR
= 35, /* PSD ecode 11 - PCI prity err during transfer */
197 PORT_CERR_SENDSERVICE
= 36, /* FIS received while sending service */
199 /* bits of PRB control field */
200 PRB_CTRL_PROTOCOL
= (1 << 0), /* override def. ATA protocol */
201 PRB_CTRL_PACKET_READ
= (1 << 4), /* PACKET cmd read */
202 PRB_CTRL_PACKET_WRITE
= (1 << 5), /* PACKET cmd write */
203 PRB_CTRL_NIEN
= (1 << 6), /* Mask completion irq */
204 PRB_CTRL_SRST
= (1 << 7), /* Soft reset request (ign BSY?) */
206 /* PRB protocol field */
207 PRB_PROT_PACKET
= (1 << 0),
208 PRB_PROT_TCQ
= (1 << 1),
209 PRB_PROT_NCQ
= (1 << 2),
210 PRB_PROT_READ
= (1 << 3),
211 PRB_PROT_WRITE
= (1 << 4),
212 PRB_PROT_TRANSPARENT
= (1 << 5),
217 SGE_TRM
= (1 << 31), /* Last SGE in chain */
218 SGE_LNK
= (1 << 30), /* linked list
219 Points to SGT, not SGE */
220 SGE_DRD
= (1 << 29), /* discard data read (/dev/null)
221 data address ignored */
231 SIL24_COMMON_FLAGS
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
232 ATA_FLAG_MMIO
| ATA_FLAG_PIO_DMA
|
233 ATA_FLAG_NCQ
| ATA_FLAG_SKIP_D2H_BSY
,
234 SIL24_FLAG_PCIX_IRQ_WOC
= (1 << 24), /* IRQ loss errata on PCI-X */
236 IRQ_STAT_4PORTS
= 0xf,
239 struct sil24_ata_block
{
240 struct sil24_prb prb
;
241 struct sil24_sge sge
[LIBATA_MAX_PRD
];
244 struct sil24_atapi_block
{
245 struct sil24_prb prb
;
247 struct sil24_sge sge
[LIBATA_MAX_PRD
- 1];
250 union sil24_cmd_block
{
251 struct sil24_ata_block ata
;
252 struct sil24_atapi_block atapi
;
255 static struct sil24_cerr_info
{
256 unsigned int err_mask
, action
;
258 } sil24_cerr_db
[] = {
259 [0] = { AC_ERR_DEV
, ATA_EH_REVALIDATE
,
261 [PORT_CERR_DEV
] = { AC_ERR_DEV
, ATA_EH_REVALIDATE
,
262 "device error via D2H FIS" },
263 [PORT_CERR_SDB
] = { AC_ERR_DEV
, ATA_EH_REVALIDATE
,
264 "device error via SDB FIS" },
265 [PORT_CERR_DATA
] = { AC_ERR_ATA_BUS
, ATA_EH_SOFTRESET
,
266 "error in data FIS" },
267 [PORT_CERR_SEND
] = { AC_ERR_ATA_BUS
, ATA_EH_SOFTRESET
,
268 "failed to transmit command FIS" },
269 [PORT_CERR_INCONSISTENT
] = { AC_ERR_HSM
, ATA_EH_SOFTRESET
,
270 "protocol mismatch" },
271 [PORT_CERR_DIRECTION
] = { AC_ERR_HSM
, ATA_EH_SOFTRESET
,
272 "data directon mismatch" },
273 [PORT_CERR_UNDERRUN
] = { AC_ERR_HSM
, ATA_EH_SOFTRESET
,
274 "ran out of SGEs while writing" },
275 [PORT_CERR_OVERRUN
] = { AC_ERR_HSM
, ATA_EH_SOFTRESET
,
276 "ran out of SGEs while reading" },
277 [PORT_CERR_PKT_PROT
] = { AC_ERR_HSM
, ATA_EH_SOFTRESET
,
278 "invalid data directon for ATAPI CDB" },
279 [PORT_CERR_SGT_BOUNDARY
] = { AC_ERR_SYSTEM
, ATA_EH_SOFTRESET
,
280 "SGT no on qword boundary" },
281 [PORT_CERR_SGT_TGTABRT
] = { AC_ERR_HOST_BUS
, ATA_EH_SOFTRESET
,
282 "PCI target abort while fetching SGT" },
283 [PORT_CERR_SGT_MSTABRT
] = { AC_ERR_HOST_BUS
, ATA_EH_SOFTRESET
,
284 "PCI master abort while fetching SGT" },
285 [PORT_CERR_SGT_PCIPERR
] = { AC_ERR_HOST_BUS
, ATA_EH_SOFTRESET
,
286 "PCI parity error while fetching SGT" },
287 [PORT_CERR_CMD_BOUNDARY
] = { AC_ERR_SYSTEM
, ATA_EH_SOFTRESET
,
288 "PRB not on qword boundary" },
289 [PORT_CERR_CMD_TGTABRT
] = { AC_ERR_HOST_BUS
, ATA_EH_SOFTRESET
,
290 "PCI target abort while fetching PRB" },
291 [PORT_CERR_CMD_MSTABRT
] = { AC_ERR_HOST_BUS
, ATA_EH_SOFTRESET
,
292 "PCI master abort while fetching PRB" },
293 [PORT_CERR_CMD_PCIPERR
] = { AC_ERR_HOST_BUS
, ATA_EH_SOFTRESET
,
294 "PCI parity error while fetching PRB" },
295 [PORT_CERR_XFR_UNDEF
] = { AC_ERR_HOST_BUS
, ATA_EH_SOFTRESET
,
296 "undefined error while transferring data" },
297 [PORT_CERR_XFR_TGTABRT
] = { AC_ERR_HOST_BUS
, ATA_EH_SOFTRESET
,
298 "PCI target abort while transferring data" },
299 [PORT_CERR_XFR_MSTABRT
] = { AC_ERR_HOST_BUS
, ATA_EH_SOFTRESET
,
300 "PCI master abort while transferring data" },
301 [PORT_CERR_XFR_PCIPERR
] = { AC_ERR_HOST_BUS
, ATA_EH_SOFTRESET
,
302 "PCI parity error while transferring data" },
303 [PORT_CERR_SENDSERVICE
] = { AC_ERR_HSM
, ATA_EH_SOFTRESET
,
304 "FIS received while sending service FIS" },
310 * The preview driver always returned 0 for status. We emulate it
311 * here from the previous interrupt.
313 struct sil24_port_priv
{
314 union sil24_cmd_block
*cmd_block
; /* 32 cmd blocks */
315 dma_addr_t cmd_block_dma
; /* DMA base addr for them */
316 struct ata_taskfile tf
; /* Cached taskfile registers */
319 /* ap->host_set->private_data */
320 struct sil24_host_priv
{
321 void __iomem
*host_base
; /* global controller control (128 bytes @BAR0) */
322 void __iomem
*port_base
; /* port registers (4 * 8192 bytes @BAR2) */
325 static void sil24_dev_config(struct ata_port
*ap
, struct ata_device
*dev
);
326 static u8
sil24_check_status(struct ata_port
*ap
);
327 static u32
sil24_scr_read(struct ata_port
*ap
, unsigned sc_reg
);
328 static void sil24_scr_write(struct ata_port
*ap
, unsigned sc_reg
, u32 val
);
329 static void sil24_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
);
330 static void sil24_qc_prep(struct ata_queued_cmd
*qc
);
331 static unsigned int sil24_qc_issue(struct ata_queued_cmd
*qc
);
332 static void sil24_irq_clear(struct ata_port
*ap
);
333 static irqreturn_t
sil24_interrupt(int irq
, void *dev_instance
, struct pt_regs
*regs
);
334 static void sil24_freeze(struct ata_port
*ap
);
335 static void sil24_thaw(struct ata_port
*ap
);
336 static void sil24_error_handler(struct ata_port
*ap
);
337 static void sil24_post_internal_cmd(struct ata_queued_cmd
*qc
);
338 static int sil24_port_start(struct ata_port
*ap
);
339 static void sil24_port_stop(struct ata_port
*ap
);
340 static void sil24_host_stop(struct ata_host_set
*host_set
);
341 static int sil24_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
342 static int sil24_pci_device_resume(struct pci_dev
*pdev
);
344 static const struct pci_device_id sil24_pci_tbl
[] = {
345 { 0x1095, 0x3124, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, BID_SIL3124
},
346 { 0x8086, 0x3124, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, BID_SIL3124
},
347 { 0x1095, 0x3132, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, BID_SIL3132
},
348 { 0x1095, 0x3131, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, BID_SIL3131
},
349 { 0x1095, 0x3531, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, BID_SIL3131
},
350 { } /* terminate list */
353 static struct pci_driver sil24_pci_driver
= {
355 .id_table
= sil24_pci_tbl
,
356 .probe
= sil24_init_one
,
357 .remove
= ata_pci_remove_one
, /* safe? */
358 .suspend
= ata_pci_device_suspend
,
359 .resume
= sil24_pci_device_resume
,
362 static struct scsi_host_template sil24_sht
= {
363 .module
= THIS_MODULE
,
365 .ioctl
= ata_scsi_ioctl
,
366 .queuecommand
= ata_scsi_queuecmd
,
367 .change_queue_depth
= ata_scsi_change_queue_depth
,
368 .can_queue
= SIL24_MAX_CMDS
,
369 .this_id
= ATA_SHT_THIS_ID
,
370 .sg_tablesize
= LIBATA_MAX_PRD
,
371 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
372 .emulated
= ATA_SHT_EMULATED
,
373 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
374 .proc_name
= DRV_NAME
,
375 .dma_boundary
= ATA_DMA_BOUNDARY
,
376 .slave_configure
= ata_scsi_slave_config
,
377 .slave_destroy
= ata_scsi_slave_destroy
,
378 .bios_param
= ata_std_bios_param
,
379 .suspend
= ata_scsi_device_suspend
,
380 .resume
= ata_scsi_device_resume
,
383 static const struct ata_port_operations sil24_ops
= {
384 .port_disable
= ata_port_disable
,
386 .dev_config
= sil24_dev_config
,
388 .check_status
= sil24_check_status
,
389 .check_altstatus
= sil24_check_status
,
390 .dev_select
= ata_noop_dev_select
,
392 .tf_read
= sil24_tf_read
,
394 .qc_prep
= sil24_qc_prep
,
395 .qc_issue
= sil24_qc_issue
,
397 .irq_handler
= sil24_interrupt
,
398 .irq_clear
= sil24_irq_clear
,
400 .scr_read
= sil24_scr_read
,
401 .scr_write
= sil24_scr_write
,
403 .freeze
= sil24_freeze
,
405 .error_handler
= sil24_error_handler
,
406 .post_internal_cmd
= sil24_post_internal_cmd
,
408 .port_start
= sil24_port_start
,
409 .port_stop
= sil24_port_stop
,
410 .host_stop
= sil24_host_stop
,
414 * Use bits 30-31 of host_flags to encode available port numbers.
415 * Current maxium is 4.
417 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
418 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
420 static struct ata_port_info sil24_port_info
[] = {
424 .host_flags
= SIL24_COMMON_FLAGS
| SIL24_NPORTS2FLAG(4) |
425 SIL24_FLAG_PCIX_IRQ_WOC
,
426 .pio_mask
= 0x1f, /* pio0-4 */
427 .mwdma_mask
= 0x07, /* mwdma0-2 */
428 .udma_mask
= 0x3f, /* udma0-5 */
429 .port_ops
= &sil24_ops
,
434 .host_flags
= SIL24_COMMON_FLAGS
| SIL24_NPORTS2FLAG(2),
435 .pio_mask
= 0x1f, /* pio0-4 */
436 .mwdma_mask
= 0x07, /* mwdma0-2 */
437 .udma_mask
= 0x3f, /* udma0-5 */
438 .port_ops
= &sil24_ops
,
440 /* sil_3131/sil_3531 */
443 .host_flags
= SIL24_COMMON_FLAGS
| SIL24_NPORTS2FLAG(1),
444 .pio_mask
= 0x1f, /* pio0-4 */
445 .mwdma_mask
= 0x07, /* mwdma0-2 */
446 .udma_mask
= 0x3f, /* udma0-5 */
447 .port_ops
= &sil24_ops
,
451 static int sil24_tag(int tag
)
453 if (unlikely(ata_tag_internal(tag
)))
458 static void sil24_dev_config(struct ata_port
*ap
, struct ata_device
*dev
)
460 void __iomem
*port
= (void __iomem
*)ap
->ioaddr
.cmd_addr
;
462 if (dev
->cdb_len
== 16)
463 writel(PORT_CS_CDB16
, port
+ PORT_CTRL_STAT
);
465 writel(PORT_CS_CDB16
, port
+ PORT_CTRL_CLR
);
468 static inline void sil24_update_tf(struct ata_port
*ap
)
470 struct sil24_port_priv
*pp
= ap
->private_data
;
471 void __iomem
*port
= (void __iomem
*)ap
->ioaddr
.cmd_addr
;
472 struct sil24_prb __iomem
*prb
= port
;
475 memcpy_fromio(fis
, prb
->fis
, 6 * 4);
476 ata_tf_from_fis(fis
, &pp
->tf
);
479 static u8
sil24_check_status(struct ata_port
*ap
)
481 struct sil24_port_priv
*pp
= ap
->private_data
;
482 return pp
->tf
.command
;
485 static int sil24_scr_map
[] = {
492 static u32
sil24_scr_read(struct ata_port
*ap
, unsigned sc_reg
)
494 void __iomem
*scr_addr
= (void __iomem
*)ap
->ioaddr
.scr_addr
;
495 if (sc_reg
< ARRAY_SIZE(sil24_scr_map
)) {
497 addr
= scr_addr
+ sil24_scr_map
[sc_reg
] * 4;
498 return readl(scr_addr
+ sil24_scr_map
[sc_reg
] * 4);
503 static void sil24_scr_write(struct ata_port
*ap
, unsigned sc_reg
, u32 val
)
505 void __iomem
*scr_addr
= (void __iomem
*)ap
->ioaddr
.scr_addr
;
506 if (sc_reg
< ARRAY_SIZE(sil24_scr_map
)) {
508 addr
= scr_addr
+ sil24_scr_map
[sc_reg
] * 4;
509 writel(val
, scr_addr
+ sil24_scr_map
[sc_reg
] * 4);
513 static void sil24_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
)
515 struct sil24_port_priv
*pp
= ap
->private_data
;
519 static int sil24_init_port(struct ata_port
*ap
)
521 void __iomem
*port
= (void __iomem
*)ap
->ioaddr
.cmd_addr
;
524 writel(PORT_CS_INIT
, port
+ PORT_CTRL_STAT
);
525 ata_wait_register(port
+ PORT_CTRL_STAT
,
526 PORT_CS_INIT
, PORT_CS_INIT
, 10, 100);
527 tmp
= ata_wait_register(port
+ PORT_CTRL_STAT
,
528 PORT_CS_RDY
, 0, 10, 100);
530 if ((tmp
& (PORT_CS_INIT
| PORT_CS_RDY
)) != PORT_CS_RDY
)
535 static int sil24_softreset(struct ata_port
*ap
, unsigned int *class)
537 void __iomem
*port
= (void __iomem
*)ap
->ioaddr
.cmd_addr
;
538 struct sil24_port_priv
*pp
= ap
->private_data
;
539 struct sil24_prb
*prb
= &pp
->cmd_block
[0].ata
.prb
;
540 dma_addr_t paddr
= pp
->cmd_block_dma
;
546 if (ata_port_offline(ap
)) {
547 DPRINTK("PHY reports no device\n");
548 *class = ATA_DEV_NONE
;
552 /* put the port into known state */
553 if (sil24_init_port(ap
)) {
554 reason
="port not ready";
559 prb
->ctrl
= cpu_to_le16(PRB_CTRL_SRST
);
560 prb
->fis
[1] = 0; /* no PM yet */
562 writel((u32
)paddr
, port
+ PORT_CMD_ACTIVATE
);
563 writel((u64
)paddr
>> 32, port
+ PORT_CMD_ACTIVATE
+ 4);
565 mask
= (PORT_IRQ_COMPLETE
| PORT_IRQ_ERROR
) << PORT_IRQ_RAW_SHIFT
;
566 irq_stat
= ata_wait_register(port
+ PORT_IRQ_STAT
, mask
, 0x0,
567 100, ATA_TMOUT_BOOT
/ HZ
* 1000);
569 writel(irq_stat
, port
+ PORT_IRQ_STAT
); /* clear IRQs */
570 irq_stat
>>= PORT_IRQ_RAW_SHIFT
;
572 if (!(irq_stat
& PORT_IRQ_COMPLETE
)) {
573 if (irq_stat
& PORT_IRQ_ERROR
)
574 reason
= "SRST command error";
581 *class = ata_dev_classify(&pp
->tf
);
583 if (*class == ATA_DEV_UNKNOWN
)
584 *class = ATA_DEV_NONE
;
587 DPRINTK("EXIT, class=%u\n", *class);
591 ata_port_printk(ap
, KERN_ERR
, "softreset failed (%s)\n", reason
);
595 static int sil24_hardreset(struct ata_port
*ap
, unsigned int *class)
597 void __iomem
*port
= (void __iomem
*)ap
->ioaddr
.cmd_addr
;
602 /* sil24 does the right thing(tm) without any protection */
606 if (ata_port_online(ap
))
609 writel(PORT_CS_DEV_RST
, port
+ PORT_CTRL_STAT
);
610 tmp
= ata_wait_register(port
+ PORT_CTRL_STAT
,
611 PORT_CS_DEV_RST
, PORT_CS_DEV_RST
, 10, tout_msec
);
613 /* SStatus oscillates between zero and valid status after
614 * DEV_RST, debounce it.
616 rc
= sata_phy_debounce(ap
, sata_deb_timing_long
);
618 reason
= "PHY debouncing failed";
622 if (tmp
& PORT_CS_DEV_RST
) {
623 if (ata_port_offline(ap
))
625 reason
= "link not ready";
629 /* Sil24 doesn't store signature FIS after hardreset, so we
630 * can't wait for BSY to clear. Some devices take a long time
631 * to get ready and those devices will choke if we don't wait
632 * for BSY clearance here. Tell libata to perform follow-up
638 ata_port_printk(ap
, KERN_ERR
, "hardreset failed (%s)\n", reason
);
642 static inline void sil24_fill_sg(struct ata_queued_cmd
*qc
,
643 struct sil24_sge
*sge
)
645 struct scatterlist
*sg
;
646 unsigned int idx
= 0;
648 ata_for_each_sg(sg
, qc
) {
649 sge
->addr
= cpu_to_le64(sg_dma_address(sg
));
650 sge
->cnt
= cpu_to_le32(sg_dma_len(sg
));
651 if (ata_sg_is_last(sg
, qc
))
652 sge
->flags
= cpu_to_le32(SGE_TRM
);
661 static void sil24_qc_prep(struct ata_queued_cmd
*qc
)
663 struct ata_port
*ap
= qc
->ap
;
664 struct sil24_port_priv
*pp
= ap
->private_data
;
665 union sil24_cmd_block
*cb
;
666 struct sil24_prb
*prb
;
667 struct sil24_sge
*sge
;
670 cb
= &pp
->cmd_block
[sil24_tag(qc
->tag
)];
672 switch (qc
->tf
.protocol
) {
676 case ATA_PROT_NODATA
:
682 case ATA_PROT_ATAPI_DMA
:
683 case ATA_PROT_ATAPI_NODATA
:
684 prb
= &cb
->atapi
.prb
;
686 memset(cb
->atapi
.cdb
, 0, 32);
687 memcpy(cb
->atapi
.cdb
, qc
->cdb
, qc
->dev
->cdb_len
);
689 if (qc
->tf
.protocol
!= ATA_PROT_ATAPI_NODATA
) {
690 if (qc
->tf
.flags
& ATA_TFLAG_WRITE
)
691 ctrl
= PRB_CTRL_PACKET_WRITE
;
693 ctrl
= PRB_CTRL_PACKET_READ
;
698 prb
= NULL
; /* shut up, gcc */
703 prb
->ctrl
= cpu_to_le16(ctrl
);
704 ata_tf_to_fis(&qc
->tf
, prb
->fis
, 0);
706 if (qc
->flags
& ATA_QCFLAG_DMAMAP
)
707 sil24_fill_sg(qc
, sge
);
710 static unsigned int sil24_qc_issue(struct ata_queued_cmd
*qc
)
712 struct ata_port
*ap
= qc
->ap
;
713 struct sil24_port_priv
*pp
= ap
->private_data
;
714 void __iomem
*port
= (void __iomem
*)ap
->ioaddr
.cmd_addr
;
715 unsigned int tag
= sil24_tag(qc
->tag
);
717 void __iomem
*activate
;
719 paddr
= pp
->cmd_block_dma
+ tag
* sizeof(*pp
->cmd_block
);
720 activate
= port
+ PORT_CMD_ACTIVATE
+ tag
* 8;
722 writel((u32
)paddr
, activate
);
723 writel((u64
)paddr
>> 32, activate
+ 4);
728 static void sil24_irq_clear(struct ata_port
*ap
)
733 static void sil24_freeze(struct ata_port
*ap
)
735 void __iomem
*port
= (void __iomem
*)ap
->ioaddr
.cmd_addr
;
737 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
738 * PORT_IRQ_ENABLE instead.
740 writel(0xffff, port
+ PORT_IRQ_ENABLE_CLR
);
743 static void sil24_thaw(struct ata_port
*ap
)
745 void __iomem
*port
= (void __iomem
*)ap
->ioaddr
.cmd_addr
;
749 tmp
= readl(port
+ PORT_IRQ_STAT
);
750 writel(tmp
, port
+ PORT_IRQ_STAT
);
752 /* turn IRQ back on */
753 writel(DEF_PORT_IRQ
, port
+ PORT_IRQ_ENABLE_SET
);
756 static void sil24_error_intr(struct ata_port
*ap
)
758 void __iomem
*port
= (void __iomem
*)ap
->ioaddr
.cmd_addr
;
759 struct ata_eh_info
*ehi
= &ap
->eh_info
;
763 /* on error, we need to clear IRQ explicitly */
764 irq_stat
= readl(port
+ PORT_IRQ_STAT
);
765 writel(irq_stat
, port
+ PORT_IRQ_STAT
);
767 /* first, analyze and record host port events */
768 ata_ehi_clear_desc(ehi
);
770 ata_ehi_push_desc(ehi
, "irq_stat 0x%08x", irq_stat
);
772 if (irq_stat
& (PORT_IRQ_PHYRDY_CHG
| PORT_IRQ_DEV_XCHG
)) {
773 ata_ehi_hotplugged(ehi
);
774 ata_ehi_push_desc(ehi
, ", %s",
775 irq_stat
& PORT_IRQ_PHYRDY_CHG
?
776 "PHY RDY changed" : "device exchanged");
780 if (irq_stat
& PORT_IRQ_UNK_FIS
) {
781 ehi
->err_mask
|= AC_ERR_HSM
;
782 ehi
->action
|= ATA_EH_SOFTRESET
;
783 ata_ehi_push_desc(ehi
, ", unknown FIS");
787 /* deal with command error */
788 if (irq_stat
& PORT_IRQ_ERROR
) {
789 struct sil24_cerr_info
*ci
= NULL
;
790 unsigned int err_mask
= 0, action
= 0;
791 struct ata_queued_cmd
*qc
;
794 /* analyze CMD_ERR */
795 cerr
= readl(port
+ PORT_CMD_ERR
);
796 if (cerr
< ARRAY_SIZE(sil24_cerr_db
))
797 ci
= &sil24_cerr_db
[cerr
];
799 if (ci
&& ci
->desc
) {
800 err_mask
|= ci
->err_mask
;
801 action
|= ci
->action
;
802 ata_ehi_push_desc(ehi
, ", %s", ci
->desc
);
804 err_mask
|= AC_ERR_OTHER
;
805 action
|= ATA_EH_SOFTRESET
;
806 ata_ehi_push_desc(ehi
, ", unknown command error %d",
810 /* record error info */
811 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
814 qc
->err_mask
|= err_mask
;
816 ehi
->err_mask
|= err_mask
;
818 ehi
->action
|= action
;
821 /* freeze or abort */
828 static void sil24_finish_qc(struct ata_queued_cmd
*qc
)
830 if (qc
->flags
& ATA_QCFLAG_RESULT_TF
)
831 sil24_update_tf(qc
->ap
);
834 static inline void sil24_host_intr(struct ata_port
*ap
)
836 void __iomem
*port
= (void __iomem
*)ap
->ioaddr
.cmd_addr
;
837 u32 slot_stat
, qc_active
;
840 slot_stat
= readl(port
+ PORT_SLOT_STAT
);
842 if (unlikely(slot_stat
& HOST_SSTAT_ATTN
)) {
843 sil24_error_intr(ap
);
847 if (ap
->flags
& SIL24_FLAG_PCIX_IRQ_WOC
)
848 writel(PORT_IRQ_COMPLETE
, port
+ PORT_IRQ_STAT
);
850 qc_active
= slot_stat
& ~HOST_SSTAT_ATTN
;
851 rc
= ata_qc_complete_multiple(ap
, qc_active
, sil24_finish_qc
);
855 struct ata_eh_info
*ehi
= &ap
->eh_info
;
856 ehi
->err_mask
|= AC_ERR_HSM
;
857 ehi
->action
|= ATA_EH_SOFTRESET
;
863 ata_port_printk(ap
, KERN_INFO
, "spurious interrupt "
864 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n",
865 slot_stat
, ap
->active_tag
, ap
->sactive
);
868 static irqreturn_t
sil24_interrupt(int irq
, void *dev_instance
, struct pt_regs
*regs
)
870 struct ata_host_set
*host_set
= dev_instance
;
871 struct sil24_host_priv
*hpriv
= host_set
->private_data
;
872 unsigned handled
= 0;
876 status
= readl(hpriv
->host_base
+ HOST_IRQ_STAT
);
878 if (status
== 0xffffffff) {
879 printk(KERN_ERR DRV_NAME
": IRQ status == 0xffffffff, "
880 "PCI fault or device removal?\n");
884 if (!(status
& IRQ_STAT_4PORTS
))
887 spin_lock(&host_set
->lock
);
889 for (i
= 0; i
< host_set
->n_ports
; i
++)
890 if (status
& (1 << i
)) {
891 struct ata_port
*ap
= host_set
->ports
[i
];
892 if (ap
&& !(ap
->flags
& ATA_FLAG_DISABLED
)) {
893 sil24_host_intr(host_set
->ports
[i
]);
896 printk(KERN_ERR DRV_NAME
897 ": interrupt from disabled port %d\n", i
);
900 spin_unlock(&host_set
->lock
);
902 return IRQ_RETVAL(handled
);
905 static void sil24_error_handler(struct ata_port
*ap
)
907 struct ata_eh_context
*ehc
= &ap
->eh_context
;
909 if (sil24_init_port(ap
)) {
910 ata_eh_freeze_port(ap
);
911 ehc
->i
.action
|= ATA_EH_HARDRESET
;
914 /* perform recovery */
915 ata_do_eh(ap
, ata_std_prereset
, sil24_softreset
, sil24_hardreset
,
919 static void sil24_post_internal_cmd(struct ata_queued_cmd
*qc
)
921 struct ata_port
*ap
= qc
->ap
;
923 if (qc
->flags
& ATA_QCFLAG_FAILED
)
924 qc
->err_mask
|= AC_ERR_OTHER
;
926 /* make DMA engine forget about the failed command */
931 static inline void sil24_cblk_free(struct sil24_port_priv
*pp
, struct device
*dev
)
933 const size_t cb_size
= sizeof(*pp
->cmd_block
) * SIL24_MAX_CMDS
;
935 dma_free_coherent(dev
, cb_size
, pp
->cmd_block
, pp
->cmd_block_dma
);
938 static int sil24_port_start(struct ata_port
*ap
)
940 struct device
*dev
= ap
->host_set
->dev
;
941 struct sil24_port_priv
*pp
;
942 union sil24_cmd_block
*cb
;
943 size_t cb_size
= sizeof(*cb
) * SIL24_MAX_CMDS
;
947 pp
= kzalloc(sizeof(*pp
), GFP_KERNEL
);
951 pp
->tf
.command
= ATA_DRDY
;
953 cb
= dma_alloc_coherent(dev
, cb_size
, &cb_dma
, GFP_KERNEL
);
956 memset(cb
, 0, cb_size
);
958 rc
= ata_pad_alloc(ap
, dev
);
963 pp
->cmd_block_dma
= cb_dma
;
965 ap
->private_data
= pp
;
970 sil24_cblk_free(pp
, dev
);
977 static void sil24_port_stop(struct ata_port
*ap
)
979 struct device
*dev
= ap
->host_set
->dev
;
980 struct sil24_port_priv
*pp
= ap
->private_data
;
982 sil24_cblk_free(pp
, dev
);
983 ata_pad_free(ap
, dev
);
987 static void sil24_host_stop(struct ata_host_set
*host_set
)
989 struct sil24_host_priv
*hpriv
= host_set
->private_data
;
990 struct pci_dev
*pdev
= to_pci_dev(host_set
->dev
);
992 pci_iounmap(pdev
, hpriv
->host_base
);
993 pci_iounmap(pdev
, hpriv
->port_base
);
997 static void sil24_init_controller(struct pci_dev
*pdev
, int n_ports
,
998 unsigned long host_flags
,
999 void __iomem
*host_base
,
1000 void __iomem
*port_base
)
1006 writel(0, host_base
+ HOST_FLASH_CMD
);
1008 /* clear global reset & mask interrupts during initialization */
1009 writel(0, host_base
+ HOST_CTRL
);
1012 for (i
= 0; i
< n_ports
; i
++) {
1013 void __iomem
*port
= port_base
+ i
* PORT_REGS_SIZE
;
1015 /* Initial PHY setting */
1016 writel(0x20c, port
+ PORT_PHY_CFG
);
1018 /* Clear port RST */
1019 tmp
= readl(port
+ PORT_CTRL_STAT
);
1020 if (tmp
& PORT_CS_PORT_RST
) {
1021 writel(PORT_CS_PORT_RST
, port
+ PORT_CTRL_CLR
);
1022 tmp
= ata_wait_register(port
+ PORT_CTRL_STAT
,
1024 PORT_CS_PORT_RST
, 10, 100);
1025 if (tmp
& PORT_CS_PORT_RST
)
1026 dev_printk(KERN_ERR
, &pdev
->dev
,
1027 "failed to clear port RST\n");
1030 /* Configure IRQ WoC */
1031 if (host_flags
& SIL24_FLAG_PCIX_IRQ_WOC
)
1032 writel(PORT_CS_IRQ_WOC
, port
+ PORT_CTRL_STAT
);
1034 writel(PORT_CS_IRQ_WOC
, port
+ PORT_CTRL_CLR
);
1036 /* Zero error counters. */
1037 writel(0x8000, port
+ PORT_DECODE_ERR_THRESH
);
1038 writel(0x8000, port
+ PORT_CRC_ERR_THRESH
);
1039 writel(0x8000, port
+ PORT_HSHK_ERR_THRESH
);
1040 writel(0x0000, port
+ PORT_DECODE_ERR_CNT
);
1041 writel(0x0000, port
+ PORT_CRC_ERR_CNT
);
1042 writel(0x0000, port
+ PORT_HSHK_ERR_CNT
);
1044 /* Always use 64bit activation */
1045 writel(PORT_CS_32BIT_ACTV
, port
+ PORT_CTRL_CLR
);
1047 /* Clear port multiplier enable and resume bits */
1048 writel(PORT_CS_PM_EN
| PORT_CS_RESUME
, port
+ PORT_CTRL_CLR
);
1051 /* Turn on interrupts */
1052 writel(IRQ_STAT_4PORTS
, host_base
+ HOST_CTRL
);
1055 static int sil24_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1057 static int printed_version
= 0;
1058 unsigned int board_id
= (unsigned int)ent
->driver_data
;
1059 struct ata_port_info
*pinfo
= &sil24_port_info
[board_id
];
1060 struct ata_probe_ent
*probe_ent
= NULL
;
1061 struct sil24_host_priv
*hpriv
= NULL
;
1062 void __iomem
*host_base
= NULL
;
1063 void __iomem
*port_base
= NULL
;
1067 if (!printed_version
++)
1068 dev_printk(KERN_DEBUG
, &pdev
->dev
, "version " DRV_VERSION
"\n");
1070 rc
= pci_enable_device(pdev
);
1074 rc
= pci_request_regions(pdev
, DRV_NAME
);
1079 /* map mmio registers */
1080 host_base
= pci_iomap(pdev
, 0, 0);
1083 port_base
= pci_iomap(pdev
, 2, 0);
1087 /* allocate & init probe_ent and hpriv */
1088 probe_ent
= kzalloc(sizeof(*probe_ent
), GFP_KERNEL
);
1092 hpriv
= kzalloc(sizeof(*hpriv
), GFP_KERNEL
);
1096 probe_ent
->dev
= pci_dev_to_dev(pdev
);
1097 INIT_LIST_HEAD(&probe_ent
->node
);
1099 probe_ent
->sht
= pinfo
->sht
;
1100 probe_ent
->host_flags
= pinfo
->host_flags
;
1101 probe_ent
->pio_mask
= pinfo
->pio_mask
;
1102 probe_ent
->mwdma_mask
= pinfo
->mwdma_mask
;
1103 probe_ent
->udma_mask
= pinfo
->udma_mask
;
1104 probe_ent
->port_ops
= pinfo
->port_ops
;
1105 probe_ent
->n_ports
= SIL24_FLAG2NPORTS(pinfo
->host_flags
);
1107 probe_ent
->irq
= pdev
->irq
;
1108 probe_ent
->irq_flags
= IRQF_SHARED
;
1109 probe_ent
->mmio_base
= port_base
;
1110 probe_ent
->private_data
= hpriv
;
1112 hpriv
->host_base
= host_base
;
1113 hpriv
->port_base
= port_base
;
1116 * Configure the device
1118 if (!pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
1119 rc
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
1121 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
1123 dev_printk(KERN_ERR
, &pdev
->dev
,
1124 "64-bit DMA enable failed\n");
1129 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
1131 dev_printk(KERN_ERR
, &pdev
->dev
,
1132 "32-bit DMA enable failed\n");
1135 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
1137 dev_printk(KERN_ERR
, &pdev
->dev
,
1138 "32-bit consistent DMA enable failed\n");
1143 /* Apply workaround for completion IRQ loss on PCI-X errata */
1144 if (probe_ent
->host_flags
& SIL24_FLAG_PCIX_IRQ_WOC
) {
1145 tmp
= readl(host_base
+ HOST_CTRL
);
1146 if (tmp
& (HOST_CTRL_TRDY
| HOST_CTRL_STOP
| HOST_CTRL_DEVSEL
))
1147 dev_printk(KERN_INFO
, &pdev
->dev
,
1148 "Applying completion IRQ loss on PCI-X "
1151 probe_ent
->host_flags
&= ~SIL24_FLAG_PCIX_IRQ_WOC
;
1154 for (i
= 0; i
< probe_ent
->n_ports
; i
++) {
1155 unsigned long portu
=
1156 (unsigned long)port_base
+ i
* PORT_REGS_SIZE
;
1158 probe_ent
->port
[i
].cmd_addr
= portu
;
1159 probe_ent
->port
[i
].scr_addr
= portu
+ PORT_SCONTROL
;
1161 ata_std_ports(&probe_ent
->port
[i
]);
1164 sil24_init_controller(pdev
, probe_ent
->n_ports
, probe_ent
->host_flags
,
1165 host_base
, port_base
);
1167 pci_set_master(pdev
);
1169 /* FIXME: check ata_device_add return value */
1170 ata_device_add(probe_ent
);
1177 pci_iounmap(pdev
, host_base
);
1179 pci_iounmap(pdev
, port_base
);
1182 pci_release_regions(pdev
);
1184 pci_disable_device(pdev
);
1188 static int sil24_pci_device_resume(struct pci_dev
*pdev
)
1190 struct ata_host_set
*host_set
= dev_get_drvdata(&pdev
->dev
);
1191 struct sil24_host_priv
*hpriv
= host_set
->private_data
;
1193 ata_pci_device_do_resume(pdev
);
1195 if (pdev
->dev
.power
.power_state
.event
== PM_EVENT_SUSPEND
)
1196 writel(HOST_CTRL_GLOBAL_RST
, hpriv
->host_base
+ HOST_CTRL
);
1198 sil24_init_controller(pdev
, host_set
->n_ports
,
1199 host_set
->ports
[0]->flags
,
1200 hpriv
->host_base
, hpriv
->port_base
);
1202 ata_host_set_resume(host_set
);
1207 static int __init
sil24_init(void)
1209 return pci_module_init(&sil24_pci_driver
);
1212 static void __exit
sil24_exit(void)
1214 pci_unregister_driver(&sil24_pci_driver
);
1217 MODULE_AUTHOR("Tejun Heo");
1218 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1219 MODULE_LICENSE("GPL");
1220 MODULE_DEVICE_TABLE(pci
, sil24_pci_tbl
);
1222 module_init(sil24_init
);
1223 module_exit(sil24_exit
);