2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey. It's neither supported nor endorsed
7 * by NVIDIA Corp. Use at your own risk.
9 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
10 * trademarks of NVIDIA Corporation in the United States and other
13 * Copyright (C) 2003,4 Manfred Spraul
14 * Copyright (C) 2004 Andrew de Quincey (wol support)
15 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
16 * IRQ rate fixes, bigendian fixes, cleanups, verification)
17 * Copyright (c) 2004 NVIDIA Corporation
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34 * 0.01: 05 Oct 2003: First release that compiles without warnings.
35 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
36 * Check all PCI BARs for the register window.
37 * udelay added to mii_rw.
38 * 0.03: 06 Oct 2003: Initialize dev->irq.
39 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
40 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
41 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
43 * 0.07: 14 Oct 2003: Further irq mask updates.
44 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
45 * added into irq handler, NULL check for drain_ring.
46 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
47 * requested interrupt sources.
48 * 0.10: 20 Oct 2003: First cleanup for release.
49 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
50 * MAC Address init fix, set_multicast cleanup.
51 * 0.12: 23 Oct 2003: Cleanups for release.
52 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
53 * Set link speed correctly. start rx before starting
54 * tx (nv_start_rx sets the link speed).
55 * 0.14: 25 Oct 2003: Nic dependant irq mask.
56 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
58 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
59 * increased to 1628 bytes.
60 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
62 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
63 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
64 * addresses, really stop rx if already running
65 * in nv_start_rx, clean up a bit.
66 * 0.20: 07 Dec 2003: alloc fixes
67 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
68 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
70 * 0.23: 26 Jan 2004: various small cleanups
71 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
72 * 0.25: 09 Mar 2004: wol support
73 * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
74 * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
75 * added CK804/MCP04 device IDs, code fixes
76 * for registers, link status and other minor fixes.
77 * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
78 * 0.29: 31 Aug 2004: Add backup timer for link change notification.
79 * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
80 * into nv_close, otherwise reenabling for wol can
81 * cause DMA to kfree'd memory.
82 * 0.31: 14 Nov 2004: ethtool support for getting/setting link
84 * 0.32: 16 Apr 2005: RX_ERROR4 handling added.
85 * 0.33: 16 May 2005: Support for MCP51 added.
86 * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
87 * 0.35: 26 Jun 2005: Support for MCP55 added.
88 * 0.36: 28 Jun 2005: Add jumbo frame support.
89 * 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
92 * We suspect that on some hardware no TX done interrupts are generated.
93 * This means recovery from netif_stop_queue only happens if the hw timer
94 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
95 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
96 * If your hardware reliably generates tx done interrupts, then you can remove
97 * DEV_NEED_TIMERIRQ from the driver_data flags.
98 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
99 * superfluous timer interrupts from the nic.
101 #define FORCEDETH_VERSION "0.37"
102 #define DRV_NAME "forcedeth"
104 #include <linux/module.h>
105 #include <linux/types.h>
106 #include <linux/pci.h>
107 #include <linux/interrupt.h>
108 #include <linux/netdevice.h>
109 #include <linux/etherdevice.h>
110 #include <linux/delay.h>
111 #include <linux/spinlock.h>
112 #include <linux/ethtool.h>
113 #include <linux/timer.h>
114 #include <linux/skbuff.h>
115 #include <linux/mii.h>
116 #include <linux/random.h>
117 #include <linux/init.h>
118 #include <linux/if_vlan.h>
122 #include <asm/uaccess.h>
123 #include <asm/system.h>
126 #define dprintk printk
128 #define dprintk(x...) do { } while (0)
136 #define DEV_NEED_LASTPACKET1 0x0001 /* set LASTPACKET1 in tx flags */
137 #define DEV_IRQMASK_1 0x0002 /* use NVREG_IRQMASK_WANTED_1 for irq mask */
138 #define DEV_IRQMASK_2 0x0004 /* use NVREG_IRQMASK_WANTED_2 for irq mask */
139 #define DEV_NEED_TIMERIRQ 0x0008 /* set the timer irq flag in the irq mask */
140 #define DEV_NEED_LINKTIMER 0x0010 /* poll link settings. Relies on the timer irq */
141 #define DEV_HAS_LARGEDESC 0x0020 /* device supports jumbo frames and needs packet format 2 */
144 NvRegIrqStatus
= 0x000,
145 #define NVREG_IRQSTAT_MIIEVENT 0x040
146 #define NVREG_IRQSTAT_MASK 0x1ff
147 NvRegIrqMask
= 0x004,
148 #define NVREG_IRQ_RX_ERROR 0x0001
149 #define NVREG_IRQ_RX 0x0002
150 #define NVREG_IRQ_RX_NOBUF 0x0004
151 #define NVREG_IRQ_TX_ERR 0x0008
152 #define NVREG_IRQ_TX2 0x0010
153 #define NVREG_IRQ_TIMER 0x0020
154 #define NVREG_IRQ_LINK 0x0040
155 #define NVREG_IRQ_TX1 0x0100
156 #define NVREG_IRQMASK_WANTED_1 0x005f
157 #define NVREG_IRQMASK_WANTED_2 0x0147
158 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR|NVREG_IRQ_TX2|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX1))
160 NvRegUnknownSetupReg6
= 0x008,
161 #define NVREG_UNKSETUP6_VAL 3
164 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
165 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
167 NvRegPollingInterval
= 0x00c,
168 #define NVREG_POLL_DEFAULT 970
170 #define NVREG_MISC1_HD 0x02
171 #define NVREG_MISC1_FORCE 0x3b0f3c
173 NvRegTransmitterControl
= 0x084,
174 #define NVREG_XMITCTL_START 0x01
175 NvRegTransmitterStatus
= 0x088,
176 #define NVREG_XMITSTAT_BUSY 0x01
178 NvRegPacketFilterFlags
= 0x8c,
179 #define NVREG_PFF_ALWAYS 0x7F0008
180 #define NVREG_PFF_PROMISC 0x80
181 #define NVREG_PFF_MYADDR 0x20
183 NvRegOffloadConfig
= 0x90,
184 #define NVREG_OFFLOAD_HOMEPHY 0x601
185 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
186 NvRegReceiverControl
= 0x094,
187 #define NVREG_RCVCTL_START 0x01
188 NvRegReceiverStatus
= 0x98,
189 #define NVREG_RCVSTAT_BUSY 0x01
191 NvRegRandomSeed
= 0x9c,
192 #define NVREG_RNDSEED_MASK 0x00ff
193 #define NVREG_RNDSEED_FORCE 0x7f00
194 #define NVREG_RNDSEED_FORCE2 0x2d00
195 #define NVREG_RNDSEED_FORCE3 0x7400
197 NvRegUnknownSetupReg1
= 0xA0,
198 #define NVREG_UNKSETUP1_VAL 0x16070f
199 NvRegUnknownSetupReg2
= 0xA4,
200 #define NVREG_UNKSETUP2_VAL 0x16
201 NvRegMacAddrA
= 0xA8,
202 NvRegMacAddrB
= 0xAC,
203 NvRegMulticastAddrA
= 0xB0,
204 #define NVREG_MCASTADDRA_FORCE 0x01
205 NvRegMulticastAddrB
= 0xB4,
206 NvRegMulticastMaskA
= 0xB8,
207 NvRegMulticastMaskB
= 0xBC,
209 NvRegPhyInterface
= 0xC0,
210 #define PHY_RGMII 0x10000000
212 NvRegTxRingPhysAddr
= 0x100,
213 NvRegRxRingPhysAddr
= 0x104,
214 NvRegRingSizes
= 0x108,
215 #define NVREG_RINGSZ_TXSHIFT 0
216 #define NVREG_RINGSZ_RXSHIFT 16
217 NvRegUnknownTransmitterReg
= 0x10c,
218 NvRegLinkSpeed
= 0x110,
219 #define NVREG_LINKSPEED_FORCE 0x10000
220 #define NVREG_LINKSPEED_10 1000
221 #define NVREG_LINKSPEED_100 100
222 #define NVREG_LINKSPEED_1000 50
223 #define NVREG_LINKSPEED_MASK (0xFFF)
224 NvRegUnknownSetupReg5
= 0x130,
225 #define NVREG_UNKSETUP5_BIT31 (1<<31)
226 NvRegUnknownSetupReg3
= 0x13c,
227 #define NVREG_UNKSETUP3_VAL1 0x200010
228 NvRegTxRxControl
= 0x144,
229 #define NVREG_TXRXCTL_KICK 0x0001
230 #define NVREG_TXRXCTL_BIT1 0x0002
231 #define NVREG_TXRXCTL_BIT2 0x0004
232 #define NVREG_TXRXCTL_IDLE 0x0008
233 #define NVREG_TXRXCTL_RESET 0x0010
234 #define NVREG_TXRXCTL_RXCHECK 0x0400
235 NvRegMIIStatus
= 0x180,
236 #define NVREG_MIISTAT_ERROR 0x0001
237 #define NVREG_MIISTAT_LINKCHANGE 0x0008
238 #define NVREG_MIISTAT_MASK 0x000f
239 #define NVREG_MIISTAT_MASK2 0x000f
240 NvRegUnknownSetupReg4
= 0x184,
241 #define NVREG_UNKSETUP4_VAL 8
243 NvRegAdapterControl
= 0x188,
244 #define NVREG_ADAPTCTL_START 0x02
245 #define NVREG_ADAPTCTL_LINKUP 0x04
246 #define NVREG_ADAPTCTL_PHYVALID 0x40000
247 #define NVREG_ADAPTCTL_RUNNING 0x100000
248 #define NVREG_ADAPTCTL_PHYSHIFT 24
249 NvRegMIISpeed
= 0x18c,
250 #define NVREG_MIISPEED_BIT8 (1<<8)
251 #define NVREG_MIIDELAY 5
252 NvRegMIIControl
= 0x190,
253 #define NVREG_MIICTL_INUSE 0x08000
254 #define NVREG_MIICTL_WRITE 0x00400
255 #define NVREG_MIICTL_ADDRSHIFT 5
256 NvRegMIIData
= 0x194,
257 NvRegWakeUpFlags
= 0x200,
258 #define NVREG_WAKEUPFLAGS_VAL 0x7770
259 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
260 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
261 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
262 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
263 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
264 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
265 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
266 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
267 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
268 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
270 NvRegPatternCRC
= 0x204,
271 NvRegPatternMask
= 0x208,
272 NvRegPowerCap
= 0x268,
273 #define NVREG_POWERCAP_D3SUPP (1<<30)
274 #define NVREG_POWERCAP_D2SUPP (1<<26)
275 #define NVREG_POWERCAP_D1SUPP (1<<25)
276 NvRegPowerState
= 0x26c,
277 #define NVREG_POWERSTATE_POWEREDUP 0x8000
278 #define NVREG_POWERSTATE_VALID 0x0100
279 #define NVREG_POWERSTATE_MASK 0x0003
280 #define NVREG_POWERSTATE_D0 0x0000
281 #define NVREG_POWERSTATE_D1 0x0001
282 #define NVREG_POWERSTATE_D2 0x0002
283 #define NVREG_POWERSTATE_D3 0x0003
286 /* Big endian: should work, but is untested */
292 #define FLAG_MASK_V1 0xffff0000
293 #define FLAG_MASK_V2 0xffffc000
294 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
295 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
297 #define NV_TX_LASTPACKET (1<<16)
298 #define NV_TX_RETRYERROR (1<<19)
299 #define NV_TX_LASTPACKET1 (1<<24)
300 #define NV_TX_DEFERRED (1<<26)
301 #define NV_TX_CARRIERLOST (1<<27)
302 #define NV_TX_LATECOLLISION (1<<28)
303 #define NV_TX_UNDERFLOW (1<<29)
304 #define NV_TX_ERROR (1<<30)
305 #define NV_TX_VALID (1<<31)
307 #define NV_TX2_LASTPACKET (1<<29)
308 #define NV_TX2_RETRYERROR (1<<18)
309 #define NV_TX2_LASTPACKET1 (1<<23)
310 #define NV_TX2_DEFERRED (1<<25)
311 #define NV_TX2_CARRIERLOST (1<<26)
312 #define NV_TX2_LATECOLLISION (1<<27)
313 #define NV_TX2_UNDERFLOW (1<<28)
314 /* error and valid are the same for both */
315 #define NV_TX2_ERROR (1<<30)
316 #define NV_TX2_VALID (1<<31)
318 #define NV_RX_DESCRIPTORVALID (1<<16)
319 #define NV_RX_MISSEDFRAME (1<<17)
320 #define NV_RX_SUBSTRACT1 (1<<18)
321 #define NV_RX_ERROR1 (1<<23)
322 #define NV_RX_ERROR2 (1<<24)
323 #define NV_RX_ERROR3 (1<<25)
324 #define NV_RX_ERROR4 (1<<26)
325 #define NV_RX_CRCERR (1<<27)
326 #define NV_RX_OVERFLOW (1<<28)
327 #define NV_RX_FRAMINGERR (1<<29)
328 #define NV_RX_ERROR (1<<30)
329 #define NV_RX_AVAIL (1<<31)
331 #define NV_RX2_CHECKSUMMASK (0x1C000000)
332 #define NV_RX2_CHECKSUMOK1 (0x10000000)
333 #define NV_RX2_CHECKSUMOK2 (0x14000000)
334 #define NV_RX2_CHECKSUMOK3 (0x18000000)
335 #define NV_RX2_DESCRIPTORVALID (1<<29)
336 #define NV_RX2_SUBSTRACT1 (1<<25)
337 #define NV_RX2_ERROR1 (1<<18)
338 #define NV_RX2_ERROR2 (1<<19)
339 #define NV_RX2_ERROR3 (1<<20)
340 #define NV_RX2_ERROR4 (1<<21)
341 #define NV_RX2_CRCERR (1<<22)
342 #define NV_RX2_OVERFLOW (1<<23)
343 #define NV_RX2_FRAMINGERR (1<<24)
344 /* error and avail are the same for both */
345 #define NV_RX2_ERROR (1<<30)
346 #define NV_RX2_AVAIL (1<<31)
348 /* Miscelaneous hardware related defines: */
349 #define NV_PCI_REGSZ 0x270
351 /* various timeout delays: all in usec */
352 #define NV_TXRX_RESET_DELAY 4
353 #define NV_TXSTOP_DELAY1 10
354 #define NV_TXSTOP_DELAY1MAX 500000
355 #define NV_TXSTOP_DELAY2 100
356 #define NV_RXSTOP_DELAY1 10
357 #define NV_RXSTOP_DELAY1MAX 500000
358 #define NV_RXSTOP_DELAY2 100
359 #define NV_SETUP5_DELAY 5
360 #define NV_SETUP5_DELAYMAX 50000
361 #define NV_POWERUP_DELAY 5
362 #define NV_POWERUP_DELAYMAX 5000
363 #define NV_MIIBUSY_DELAY 50
364 #define NV_MIIPHY_DELAY 10
365 #define NV_MIIPHY_DELAYMAX 10000
367 #define NV_WAKEUPPATTERNS 5
368 #define NV_WAKEUPMASKENTRIES 4
370 /* General driver defaults */
371 #define NV_WATCHDOG_TIMEO (5*HZ)
376 * If your nic mysteriously hangs then try to reduce the limits
377 * to 1/0: It might be required to set NV_TX_LASTPACKET in the
378 * last valid ring entry. But this would be impossible to
379 * implement - probably a disassembly error.
381 #define TX_LIMIT_STOP 63
382 #define TX_LIMIT_START 62
384 /* rx/tx mac addr + type + vlan + align + slack*/
385 #define NV_RX_HEADERS (64)
386 /* even more slack. */
387 #define NV_RX_ALLOC_PAD (64)
389 /* maximum mtu size */
390 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
391 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
393 #define OOM_REFILL (1+HZ/20)
394 #define POLL_WAIT (1+HZ/100)
395 #define LINK_TIMEOUT (3*HZ)
399 * This field has two purposes:
400 * - Newer nics uses a different ring layout. The layout is selected by
401 * comparing np->desc_ver with DESC_VER_xy.
402 * - It contains bits that are forced on when writing to NvRegTxRxControl.
404 #define DESC_VER_1 0x0
405 #define DESC_VER_2 (0x02100|NVREG_TXRXCTL_RXCHECK)
408 #define PHY_OUI_MARVELL 0x5043
409 #define PHY_OUI_CICADA 0x03f1
410 #define PHYID1_OUI_MASK 0x03ff
411 #define PHYID1_OUI_SHFT 6
412 #define PHYID2_OUI_MASK 0xfc00
413 #define PHYID2_OUI_SHFT 10
414 #define PHY_INIT1 0x0f000
415 #define PHY_INIT2 0x0e00
416 #define PHY_INIT3 0x01000
417 #define PHY_INIT4 0x0200
418 #define PHY_INIT5 0x0004
419 #define PHY_INIT6 0x02000
420 #define PHY_GIGABIT 0x0100
422 #define PHY_TIMEOUT 0x1
423 #define PHY_ERROR 0x2
427 #define PHY_HALF 0x100
429 /* FIXME: MII defines that should be added to <linux/mii.h> */
430 #define MII_1000BT_CR 0x09
431 #define MII_1000BT_SR 0x0a
432 #define ADVERTISE_1000FULL 0x0200
433 #define ADVERTISE_1000HALF 0x0100
434 #define LPA_1000FULL 0x0800
435 #define LPA_1000HALF 0x0400
440 * All hardware access under dev->priv->lock, except the performance
442 * - rx is (pseudo-) lockless: it relies on the single-threading provided
443 * by the arch code for interrupts.
444 * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission
445 * needs dev->priv->lock :-(
446 * - set_multicast_list: preparation lockless, relies on dev->xmit_lock.
449 /* in dev: base, irq */
454 * Locking: spin_lock(&np->lock); */
455 struct net_device_stats stats
;
463 unsigned int phy_oui
;
466 /* General data: RO fields */
467 dma_addr_t ring_addr
;
468 struct pci_dev
*pci_dev
;
475 /* rx specific fields.
476 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
478 struct ring_desc
*rx_ring
;
479 unsigned int cur_rx
, refill_rx
;
480 struct sk_buff
*rx_skbuff
[RX_RING
];
481 dma_addr_t rx_dma
[RX_RING
];
482 unsigned int rx_buf_sz
;
483 unsigned int pkt_limit
;
484 struct timer_list oom_kick
;
485 struct timer_list nic_poll
;
487 /* media detection workaround.
488 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
491 unsigned long link_timeout
;
493 * tx specific fields.
495 struct ring_desc
*tx_ring
;
496 unsigned int next_tx
, nic_tx
;
497 struct sk_buff
*tx_skbuff
[TX_RING
];
498 dma_addr_t tx_dma
[TX_RING
];
503 * Maximum number of loops until we assume that a bit in the irq mask
504 * is stuck. Overridable with module param.
506 static int max_interrupt_work
= 5;
508 static inline struct fe_priv
*get_nvpriv(struct net_device
*dev
)
510 return netdev_priv(dev
);
513 static inline u8 __iomem
*get_hwbase(struct net_device
*dev
)
515 return get_nvpriv(dev
)->base
;
518 static inline void pci_push(u8 __iomem
*base
)
520 /* force out pending posted writes */
524 static inline u32
nv_descr_getlength(struct ring_desc
*prd
, u32 v
)
526 return le32_to_cpu(prd
->FlagLen
)
527 & ((v
== DESC_VER_1
) ? LEN_MASK_V1
: LEN_MASK_V2
);
530 static int reg_delay(struct net_device
*dev
, int offset
, u32 mask
, u32 target
,
531 int delay
, int delaymax
, const char *msg
)
533 u8 __iomem
*base
= get_hwbase(dev
);
544 } while ((readl(base
+ offset
) & mask
) != target
);
548 #define MII_READ (-1)
549 /* mii_rw: read/write a register on the PHY.
551 * Caller must guarantee serialization
553 static int mii_rw(struct net_device
*dev
, int addr
, int miireg
, int value
)
555 u8 __iomem
*base
= get_hwbase(dev
);
559 writel(NVREG_MIISTAT_MASK
, base
+ NvRegMIIStatus
);
561 reg
= readl(base
+ NvRegMIIControl
);
562 if (reg
& NVREG_MIICTL_INUSE
) {
563 writel(NVREG_MIICTL_INUSE
, base
+ NvRegMIIControl
);
564 udelay(NV_MIIBUSY_DELAY
);
567 reg
= (addr
<< NVREG_MIICTL_ADDRSHIFT
) | miireg
;
568 if (value
!= MII_READ
) {
569 writel(value
, base
+ NvRegMIIData
);
570 reg
|= NVREG_MIICTL_WRITE
;
572 writel(reg
, base
+ NvRegMIIControl
);
574 if (reg_delay(dev
, NvRegMIIControl
, NVREG_MIICTL_INUSE
, 0,
575 NV_MIIPHY_DELAY
, NV_MIIPHY_DELAYMAX
, NULL
)) {
576 dprintk(KERN_DEBUG
"%s: mii_rw of reg %d at PHY %d timed out.\n",
577 dev
->name
, miireg
, addr
);
579 } else if (value
!= MII_READ
) {
580 /* it was a write operation - fewer failures are detectable */
581 dprintk(KERN_DEBUG
"%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
582 dev
->name
, value
, miireg
, addr
);
584 } else if (readl(base
+ NvRegMIIStatus
) & NVREG_MIISTAT_ERROR
) {
585 dprintk(KERN_DEBUG
"%s: mii_rw of reg %d at PHY %d failed.\n",
586 dev
->name
, miireg
, addr
);
589 retval
= readl(base
+ NvRegMIIData
);
590 dprintk(KERN_DEBUG
"%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
591 dev
->name
, miireg
, addr
, retval
);
597 static int phy_reset(struct net_device
*dev
)
599 struct fe_priv
*np
= get_nvpriv(dev
);
601 unsigned int tries
= 0;
603 miicontrol
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
604 miicontrol
|= BMCR_RESET
;
605 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, miicontrol
)) {
612 /* must wait till reset is deasserted */
613 while (miicontrol
& BMCR_RESET
) {
615 miicontrol
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
616 /* FIXME: 100 tries seem excessive */
623 static int phy_init(struct net_device
*dev
)
625 struct fe_priv
*np
= get_nvpriv(dev
);
626 u8 __iomem
*base
= get_hwbase(dev
);
627 u32 phyinterface
, phy_reserved
, mii_status
, mii_control
, mii_control_1000
,reg
;
629 /* set advertise register */
630 reg
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
631 reg
|= (ADVERTISE_10HALF
|ADVERTISE_10FULL
|ADVERTISE_100HALF
|ADVERTISE_100FULL
|0x800|0x400);
632 if (mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, reg
)) {
633 printk(KERN_INFO
"%s: phy write to advertise failed.\n", pci_name(np
->pci_dev
));
637 /* get phy interface type */
638 phyinterface
= readl(base
+ NvRegPhyInterface
);
640 /* see if gigabit phy */
641 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
642 if (mii_status
& PHY_GIGABIT
) {
643 np
->gigabit
= PHY_GIGABIT
;
644 mii_control_1000
= mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, MII_READ
);
645 mii_control_1000
&= ~ADVERTISE_1000HALF
;
646 if (phyinterface
& PHY_RGMII
)
647 mii_control_1000
|= ADVERTISE_1000FULL
;
649 mii_control_1000
&= ~ADVERTISE_1000FULL
;
651 if (mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, mii_control_1000
)) {
652 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
660 if (phy_reset(dev
)) {
661 printk(KERN_INFO
"%s: phy reset failed\n", pci_name(np
->pci_dev
));
665 /* phy vendor specific configuration */
666 if ((np
->phy_oui
== PHY_OUI_CICADA
) && (phyinterface
& PHY_RGMII
) ) {
667 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_RESV1
, MII_READ
);
668 phy_reserved
&= ~(PHY_INIT1
| PHY_INIT2
);
669 phy_reserved
|= (PHY_INIT3
| PHY_INIT4
);
670 if (mii_rw(dev
, np
->phyaddr
, MII_RESV1
, phy_reserved
)) {
671 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
674 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, MII_READ
);
675 phy_reserved
|= PHY_INIT5
;
676 if (mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, phy_reserved
)) {
677 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
681 if (np
->phy_oui
== PHY_OUI_CICADA
) {
682 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_SREVISION
, MII_READ
);
683 phy_reserved
|= PHY_INIT6
;
684 if (mii_rw(dev
, np
->phyaddr
, MII_SREVISION
, phy_reserved
)) {
685 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
690 /* restart auto negotiation */
691 mii_control
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
692 mii_control
|= (BMCR_ANRESTART
| BMCR_ANENABLE
);
693 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, mii_control
)) {
700 static void nv_start_rx(struct net_device
*dev
)
702 struct fe_priv
*np
= get_nvpriv(dev
);
703 u8 __iomem
*base
= get_hwbase(dev
);
705 dprintk(KERN_DEBUG
"%s: nv_start_rx\n", dev
->name
);
706 /* Already running? Stop it. */
707 if (readl(base
+ NvRegReceiverControl
) & NVREG_RCVCTL_START
) {
708 writel(0, base
+ NvRegReceiverControl
);
711 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
713 writel(NVREG_RCVCTL_START
, base
+ NvRegReceiverControl
);
714 dprintk(KERN_DEBUG
"%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
715 dev
->name
, np
->duplex
, np
->linkspeed
);
719 static void nv_stop_rx(struct net_device
*dev
)
721 u8 __iomem
*base
= get_hwbase(dev
);
723 dprintk(KERN_DEBUG
"%s: nv_stop_rx\n", dev
->name
);
724 writel(0, base
+ NvRegReceiverControl
);
725 reg_delay(dev
, NvRegReceiverStatus
, NVREG_RCVSTAT_BUSY
, 0,
726 NV_RXSTOP_DELAY1
, NV_RXSTOP_DELAY1MAX
,
727 KERN_INFO
"nv_stop_rx: ReceiverStatus remained busy");
729 udelay(NV_RXSTOP_DELAY2
);
730 writel(0, base
+ NvRegLinkSpeed
);
733 static void nv_start_tx(struct net_device
*dev
)
735 u8 __iomem
*base
= get_hwbase(dev
);
737 dprintk(KERN_DEBUG
"%s: nv_start_tx\n", dev
->name
);
738 writel(NVREG_XMITCTL_START
, base
+ NvRegTransmitterControl
);
742 static void nv_stop_tx(struct net_device
*dev
)
744 u8 __iomem
*base
= get_hwbase(dev
);
746 dprintk(KERN_DEBUG
"%s: nv_stop_tx\n", dev
->name
);
747 writel(0, base
+ NvRegTransmitterControl
);
748 reg_delay(dev
, NvRegTransmitterStatus
, NVREG_XMITSTAT_BUSY
, 0,
749 NV_TXSTOP_DELAY1
, NV_TXSTOP_DELAY1MAX
,
750 KERN_INFO
"nv_stop_tx: TransmitterStatus remained busy");
752 udelay(NV_TXSTOP_DELAY2
);
753 writel(0, base
+ NvRegUnknownTransmitterReg
);
756 static void nv_txrx_reset(struct net_device
*dev
)
758 struct fe_priv
*np
= get_nvpriv(dev
);
759 u8 __iomem
*base
= get_hwbase(dev
);
761 dprintk(KERN_DEBUG
"%s: nv_txrx_reset\n", dev
->name
);
762 writel(NVREG_TXRXCTL_BIT2
| NVREG_TXRXCTL_RESET
| np
->desc_ver
, base
+ NvRegTxRxControl
);
764 udelay(NV_TXRX_RESET_DELAY
);
765 writel(NVREG_TXRXCTL_BIT2
| np
->desc_ver
, base
+ NvRegTxRxControl
);
770 * nv_get_stats: dev->get_stats function
771 * Get latest stats value from the nic.
772 * Called with read_lock(&dev_base_lock) held for read -
773 * only synchronized against unregister_netdevice.
775 static struct net_device_stats
*nv_get_stats(struct net_device
*dev
)
777 struct fe_priv
*np
= get_nvpriv(dev
);
779 /* It seems that the nic always generates interrupts and doesn't
780 * accumulate errors internally. Thus the current values in np->stats
781 * are already up to date.
787 * nv_alloc_rx: fill rx ring entries.
788 * Return 1 if the allocations for the skbs failed and the
789 * rx engine is without Available descriptors
791 static int nv_alloc_rx(struct net_device
*dev
)
793 struct fe_priv
*np
= get_nvpriv(dev
);
794 unsigned int refill_rx
= np
->refill_rx
;
797 while (np
->cur_rx
!= refill_rx
) {
800 nr
= refill_rx
% RX_RING
;
801 if (np
->rx_skbuff
[nr
] == NULL
) {
803 skb
= dev_alloc_skb(np
->rx_buf_sz
+ NV_RX_ALLOC_PAD
);
808 np
->rx_skbuff
[nr
] = skb
;
810 skb
= np
->rx_skbuff
[nr
];
812 np
->rx_dma
[nr
] = pci_map_single(np
->pci_dev
, skb
->data
, skb
->len
,
814 np
->rx_ring
[nr
].PacketBuffer
= cpu_to_le32(np
->rx_dma
[nr
]);
816 np
->rx_ring
[nr
].FlagLen
= cpu_to_le32(np
->rx_buf_sz
| NV_RX_AVAIL
);
817 dprintk(KERN_DEBUG
"%s: nv_alloc_rx: Packet %d marked as Available\n",
818 dev
->name
, refill_rx
);
821 np
->refill_rx
= refill_rx
;
822 if (np
->cur_rx
- refill_rx
== RX_RING
)
827 static void nv_do_rx_refill(unsigned long data
)
829 struct net_device
*dev
= (struct net_device
*) data
;
830 struct fe_priv
*np
= get_nvpriv(dev
);
832 disable_irq(dev
->irq
);
833 if (nv_alloc_rx(dev
)) {
834 spin_lock(&np
->lock
);
835 if (!np
->in_shutdown
)
836 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
837 spin_unlock(&np
->lock
);
839 enable_irq(dev
->irq
);
842 static void nv_init_rx(struct net_device
*dev
)
844 struct fe_priv
*np
= get_nvpriv(dev
);
847 np
->cur_rx
= RX_RING
;
849 for (i
= 0; i
< RX_RING
; i
++)
850 np
->rx_ring
[i
].FlagLen
= 0;
853 static void nv_init_tx(struct net_device
*dev
)
855 struct fe_priv
*np
= get_nvpriv(dev
);
858 np
->next_tx
= np
->nic_tx
= 0;
859 for (i
= 0; i
< TX_RING
; i
++)
860 np
->tx_ring
[i
].FlagLen
= 0;
863 static int nv_init_ring(struct net_device
*dev
)
867 return nv_alloc_rx(dev
);
870 static void nv_drain_tx(struct net_device
*dev
)
872 struct fe_priv
*np
= get_nvpriv(dev
);
874 for (i
= 0; i
< TX_RING
; i
++) {
875 np
->tx_ring
[i
].FlagLen
= 0;
876 if (np
->tx_skbuff
[i
]) {
877 pci_unmap_single(np
->pci_dev
, np
->tx_dma
[i
],
878 np
->tx_skbuff
[i
]->len
,
880 dev_kfree_skb(np
->tx_skbuff
[i
]);
881 np
->tx_skbuff
[i
] = NULL
;
882 np
->stats
.tx_dropped
++;
887 static void nv_drain_rx(struct net_device
*dev
)
889 struct fe_priv
*np
= get_nvpriv(dev
);
891 for (i
= 0; i
< RX_RING
; i
++) {
892 np
->rx_ring
[i
].FlagLen
= 0;
894 if (np
->rx_skbuff
[i
]) {
895 pci_unmap_single(np
->pci_dev
, np
->rx_dma
[i
],
896 np
->rx_skbuff
[i
]->len
,
898 dev_kfree_skb(np
->rx_skbuff
[i
]);
899 np
->rx_skbuff
[i
] = NULL
;
904 static void drain_ring(struct net_device
*dev
)
911 * nv_start_xmit: dev->hard_start_xmit function
912 * Called with dev->xmit_lock held.
914 static int nv_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
916 struct fe_priv
*np
= get_nvpriv(dev
);
917 int nr
= np
->next_tx
% TX_RING
;
919 np
->tx_skbuff
[nr
] = skb
;
920 np
->tx_dma
[nr
] = pci_map_single(np
->pci_dev
, skb
->data
,skb
->len
,
923 np
->tx_ring
[nr
].PacketBuffer
= cpu_to_le32(np
->tx_dma
[nr
]);
925 spin_lock_irq(&np
->lock
);
927 np
->tx_ring
[nr
].FlagLen
= cpu_to_le32( (skb
->len
-1) | np
->tx_flags
);
928 dprintk(KERN_DEBUG
"%s: nv_start_xmit: packet packet %d queued for transmission.\n",
929 dev
->name
, np
->next_tx
);
932 for (j
=0; j
<64; j
++) {
934 dprintk("\n%03x:", j
);
935 dprintk(" %02x", ((unsigned char*)skb
->data
)[j
]);
942 dev
->trans_start
= jiffies
;
943 if (np
->next_tx
- np
->nic_tx
>= TX_LIMIT_STOP
)
944 netif_stop_queue(dev
);
945 spin_unlock_irq(&np
->lock
);
946 writel(NVREG_TXRXCTL_KICK
|np
->desc_ver
, get_hwbase(dev
) + NvRegTxRxControl
);
947 pci_push(get_hwbase(dev
));
952 * nv_tx_done: check for completed packets, release the skbs.
954 * Caller must own np->lock.
956 static void nv_tx_done(struct net_device
*dev
)
958 struct fe_priv
*np
= get_nvpriv(dev
);
962 while (np
->nic_tx
!= np
->next_tx
) {
963 i
= np
->nic_tx
% TX_RING
;
965 Flags
= le32_to_cpu(np
->tx_ring
[i
].FlagLen
);
967 dprintk(KERN_DEBUG
"%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
968 dev
->name
, np
->nic_tx
, Flags
);
969 if (Flags
& NV_TX_VALID
)
971 if (np
->desc_ver
== DESC_VER_1
) {
972 if (Flags
& (NV_TX_RETRYERROR
|NV_TX_CARRIERLOST
|NV_TX_LATECOLLISION
|
973 NV_TX_UNDERFLOW
|NV_TX_ERROR
)) {
974 if (Flags
& NV_TX_UNDERFLOW
)
975 np
->stats
.tx_fifo_errors
++;
976 if (Flags
& NV_TX_CARRIERLOST
)
977 np
->stats
.tx_carrier_errors
++;
978 np
->stats
.tx_errors
++;
980 np
->stats
.tx_packets
++;
981 np
->stats
.tx_bytes
+= np
->tx_skbuff
[i
]->len
;
984 if (Flags
& (NV_TX2_RETRYERROR
|NV_TX2_CARRIERLOST
|NV_TX2_LATECOLLISION
|
985 NV_TX2_UNDERFLOW
|NV_TX2_ERROR
)) {
986 if (Flags
& NV_TX2_UNDERFLOW
)
987 np
->stats
.tx_fifo_errors
++;
988 if (Flags
& NV_TX2_CARRIERLOST
)
989 np
->stats
.tx_carrier_errors
++;
990 np
->stats
.tx_errors
++;
992 np
->stats
.tx_packets
++;
993 np
->stats
.tx_bytes
+= np
->tx_skbuff
[i
]->len
;
996 pci_unmap_single(np
->pci_dev
, np
->tx_dma
[i
],
997 np
->tx_skbuff
[i
]->len
,
999 dev_kfree_skb_irq(np
->tx_skbuff
[i
]);
1000 np
->tx_skbuff
[i
] = NULL
;
1003 if (np
->next_tx
- np
->nic_tx
< TX_LIMIT_START
)
1004 netif_wake_queue(dev
);
1008 * nv_tx_timeout: dev->tx_timeout function
1009 * Called with dev->xmit_lock held.
1011 static void nv_tx_timeout(struct net_device
*dev
)
1013 struct fe_priv
*np
= get_nvpriv(dev
);
1014 u8 __iomem
*base
= get_hwbase(dev
);
1016 dprintk(KERN_DEBUG
"%s: Got tx_timeout. irq: %08x\n", dev
->name
,
1017 readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
);
1019 spin_lock_irq(&np
->lock
);
1021 /* 1) stop tx engine */
1024 /* 2) check that the packets were not sent already: */
1027 /* 3) if there are dead entries: clear everything */
1028 if (np
->next_tx
!= np
->nic_tx
) {
1029 printk(KERN_DEBUG
"%s: tx_timeout: dead entries!\n", dev
->name
);
1031 np
->next_tx
= np
->nic_tx
= 0;
1032 writel((u32
) (np
->ring_addr
+ RX_RING
*sizeof(struct ring_desc
)), base
+ NvRegTxRingPhysAddr
);
1033 netif_wake_queue(dev
);
1036 /* 4) restart tx engine */
1038 spin_unlock_irq(&np
->lock
);
1042 * Called when the nic notices a mismatch between the actual data len on the
1043 * wire and the len indicated in the 802 header
1045 static int nv_getlen(struct net_device
*dev
, void *packet
, int datalen
)
1047 int hdrlen
; /* length of the 802 header */
1048 int protolen
; /* length as stored in the proto field */
1050 /* 1) calculate len according to header */
1051 if ( ((struct vlan_ethhdr
*)packet
)->h_vlan_proto
== __constant_htons(ETH_P_8021Q
)) {
1052 protolen
= ntohs( ((struct vlan_ethhdr
*)packet
)->h_vlan_encapsulated_proto
);
1055 protolen
= ntohs( ((struct ethhdr
*)packet
)->h_proto
);
1058 dprintk(KERN_DEBUG
"%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1059 dev
->name
, datalen
, protolen
, hdrlen
);
1060 if (protolen
> ETH_DATA_LEN
)
1061 return datalen
; /* Value in proto field not a len, no checks possible */
1064 /* consistency checks: */
1065 if (datalen
> ETH_ZLEN
) {
1066 if (datalen
>= protolen
) {
1067 /* more data on wire than in 802 header, trim of
1070 dprintk(KERN_DEBUG
"%s: nv_getlen: accepting %d bytes.\n",
1071 dev
->name
, protolen
);
1074 /* less data on wire than mentioned in header.
1075 * Discard the packet.
1077 dprintk(KERN_DEBUG
"%s: nv_getlen: discarding long packet.\n",
1082 /* short packet. Accept only if 802 values are also short */
1083 if (protolen
> ETH_ZLEN
) {
1084 dprintk(KERN_DEBUG
"%s: nv_getlen: discarding short packet.\n",
1088 dprintk(KERN_DEBUG
"%s: nv_getlen: accepting %d bytes.\n",
1089 dev
->name
, datalen
);
1094 static void nv_rx_process(struct net_device
*dev
)
1096 struct fe_priv
*np
= get_nvpriv(dev
);
1100 struct sk_buff
*skb
;
1103 if (np
->cur_rx
- np
->refill_rx
>= RX_RING
)
1104 break; /* we scanned the whole ring - do not continue */
1106 i
= np
->cur_rx
% RX_RING
;
1107 Flags
= le32_to_cpu(np
->rx_ring
[i
].FlagLen
);
1108 len
= nv_descr_getlength(&np
->rx_ring
[i
], np
->desc_ver
);
1110 dprintk(KERN_DEBUG
"%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
1111 dev
->name
, np
->cur_rx
, Flags
);
1113 if (Flags
& NV_RX_AVAIL
)
1114 break; /* still owned by hardware, */
1117 * the packet is for us - immediately tear down the pci mapping.
1118 * TODO: check if a prefetch of the first cacheline improves
1121 pci_unmap_single(np
->pci_dev
, np
->rx_dma
[i
],
1122 np
->rx_skbuff
[i
]->len
,
1123 PCI_DMA_FROMDEVICE
);
1127 dprintk(KERN_DEBUG
"Dumping packet (flags 0x%x).",Flags
);
1128 for (j
=0; j
<64; j
++) {
1130 dprintk("\n%03x:", j
);
1131 dprintk(" %02x", ((unsigned char*)np
->rx_skbuff
[i
]->data
)[j
]);
1135 /* look at what we actually got: */
1136 if (np
->desc_ver
== DESC_VER_1
) {
1137 if (!(Flags
& NV_RX_DESCRIPTORVALID
))
1140 if (Flags
& NV_RX_MISSEDFRAME
) {
1141 np
->stats
.rx_missed_errors
++;
1142 np
->stats
.rx_errors
++;
1145 if (Flags
& (NV_RX_ERROR1
|NV_RX_ERROR2
|NV_RX_ERROR3
)) {
1146 np
->stats
.rx_errors
++;
1149 if (Flags
& NV_RX_CRCERR
) {
1150 np
->stats
.rx_crc_errors
++;
1151 np
->stats
.rx_errors
++;
1154 if (Flags
& NV_RX_OVERFLOW
) {
1155 np
->stats
.rx_over_errors
++;
1156 np
->stats
.rx_errors
++;
1159 if (Flags
& NV_RX_ERROR4
) {
1160 len
= nv_getlen(dev
, np
->rx_skbuff
[i
]->data
, len
);
1162 np
->stats
.rx_errors
++;
1166 /* framing errors are soft errors. */
1167 if (Flags
& NV_RX_FRAMINGERR
) {
1168 if (Flags
& NV_RX_SUBSTRACT1
) {
1173 if (!(Flags
& NV_RX2_DESCRIPTORVALID
))
1176 if (Flags
& (NV_RX2_ERROR1
|NV_RX2_ERROR2
|NV_RX2_ERROR3
)) {
1177 np
->stats
.rx_errors
++;
1180 if (Flags
& NV_RX2_CRCERR
) {
1181 np
->stats
.rx_crc_errors
++;
1182 np
->stats
.rx_errors
++;
1185 if (Flags
& NV_RX2_OVERFLOW
) {
1186 np
->stats
.rx_over_errors
++;
1187 np
->stats
.rx_errors
++;
1190 if (Flags
& NV_RX2_ERROR4
) {
1191 len
= nv_getlen(dev
, np
->rx_skbuff
[i
]->data
, len
);
1193 np
->stats
.rx_errors
++;
1197 /* framing errors are soft errors */
1198 if (Flags
& NV_RX2_FRAMINGERR
) {
1199 if (Flags
& NV_RX2_SUBSTRACT1
) {
1203 Flags
&= NV_RX2_CHECKSUMMASK
;
1204 if (Flags
== NV_RX2_CHECKSUMOK1
||
1205 Flags
== NV_RX2_CHECKSUMOK2
||
1206 Flags
== NV_RX2_CHECKSUMOK3
) {
1207 dprintk(KERN_DEBUG
"%s: hw checksum hit!.\n", dev
->name
);
1208 np
->rx_skbuff
[i
]->ip_summed
= CHECKSUM_UNNECESSARY
;
1210 dprintk(KERN_DEBUG
"%s: hwchecksum miss!.\n", dev
->name
);
1213 /* got a valid packet - forward it to the network core */
1214 skb
= np
->rx_skbuff
[i
];
1215 np
->rx_skbuff
[i
] = NULL
;
1218 skb
->protocol
= eth_type_trans(skb
, dev
);
1219 dprintk(KERN_DEBUG
"%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1220 dev
->name
, np
->cur_rx
, len
, skb
->protocol
);
1222 dev
->last_rx
= jiffies
;
1223 np
->stats
.rx_packets
++;
1224 np
->stats
.rx_bytes
+= len
;
1230 static void set_bufsize(struct net_device
*dev
)
1232 struct fe_priv
*np
= netdev_priv(dev
);
1234 if (dev
->mtu
<= ETH_DATA_LEN
)
1235 np
->rx_buf_sz
= ETH_DATA_LEN
+ NV_RX_HEADERS
;
1237 np
->rx_buf_sz
= dev
->mtu
+ NV_RX_HEADERS
;
1241 * nv_change_mtu: dev->change_mtu function
1242 * Called with dev_base_lock held for read.
1244 static int nv_change_mtu(struct net_device
*dev
, int new_mtu
)
1246 struct fe_priv
*np
= get_nvpriv(dev
);
1249 if (new_mtu
< 64 || new_mtu
> np
->pkt_limit
)
1255 /* return early if the buffer sizes will not change */
1256 if (old_mtu
<= ETH_DATA_LEN
&& new_mtu
<= ETH_DATA_LEN
)
1258 if (old_mtu
== new_mtu
)
1261 /* synchronized against open : rtnl_lock() held by caller */
1262 if (netif_running(dev
)) {
1263 u8
*base
= get_hwbase(dev
);
1265 * It seems that the nic preloads valid ring entries into an
1266 * internal buffer. The procedure for flushing everything is
1267 * guessed, there is probably a simpler approach.
1268 * Changing the MTU is a rare event, it shouldn't matter.
1270 disable_irq(dev
->irq
);
1271 spin_lock_bh(&dev
->xmit_lock
);
1272 spin_lock(&np
->lock
);
1277 /* drain rx queue */
1280 /* reinit driver view of the rx queue */
1283 /* alloc new rx buffers */
1285 if (nv_alloc_rx(dev
)) {
1286 if (!np
->in_shutdown
)
1287 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
1289 /* reinit nic view of the rx queue */
1290 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
1291 writel((u32
) np
->ring_addr
, base
+ NvRegRxRingPhysAddr
);
1292 writel((u32
) (np
->ring_addr
+ RX_RING
*sizeof(struct ring_desc
)), base
+ NvRegTxRingPhysAddr
);
1293 writel( ((RX_RING
-1) << NVREG_RINGSZ_RXSHIFT
) + ((TX_RING
-1) << NVREG_RINGSZ_TXSHIFT
),
1294 base
+ NvRegRingSizes
);
1296 writel(NVREG_TXRXCTL_KICK
|np
->desc_ver
, get_hwbase(dev
) + NvRegTxRxControl
);
1299 /* restart rx engine */
1302 spin_unlock(&np
->lock
);
1303 spin_unlock_bh(&dev
->xmit_lock
);
1304 enable_irq(dev
->irq
);
1310 * nv_set_multicast: dev->set_multicast function
1311 * Called with dev->xmit_lock held.
1313 static void nv_set_multicast(struct net_device
*dev
)
1315 struct fe_priv
*np
= get_nvpriv(dev
);
1316 u8 __iomem
*base
= get_hwbase(dev
);
1321 memset(addr
, 0, sizeof(addr
));
1322 memset(mask
, 0, sizeof(mask
));
1324 if (dev
->flags
& IFF_PROMISC
) {
1325 printk(KERN_NOTICE
"%s: Promiscuous mode enabled.\n", dev
->name
);
1326 pff
= NVREG_PFF_PROMISC
;
1328 pff
= NVREG_PFF_MYADDR
;
1330 if (dev
->flags
& IFF_ALLMULTI
|| dev
->mc_list
) {
1334 alwaysOn
[0] = alwaysOn
[1] = alwaysOff
[0] = alwaysOff
[1] = 0xffffffff;
1335 if (dev
->flags
& IFF_ALLMULTI
) {
1336 alwaysOn
[0] = alwaysOn
[1] = alwaysOff
[0] = alwaysOff
[1] = 0;
1338 struct dev_mc_list
*walk
;
1340 walk
= dev
->mc_list
;
1341 while (walk
!= NULL
) {
1343 a
= le32_to_cpu(*(u32
*) walk
->dmi_addr
);
1344 b
= le16_to_cpu(*(u16
*) (&walk
->dmi_addr
[4]));
1352 addr
[0] = alwaysOn
[0];
1353 addr
[1] = alwaysOn
[1];
1354 mask
[0] = alwaysOn
[0] | alwaysOff
[0];
1355 mask
[1] = alwaysOn
[1] | alwaysOff
[1];
1358 addr
[0] |= NVREG_MCASTADDRA_FORCE
;
1359 pff
|= NVREG_PFF_ALWAYS
;
1360 spin_lock_irq(&np
->lock
);
1362 writel(addr
[0], base
+ NvRegMulticastAddrA
);
1363 writel(addr
[1], base
+ NvRegMulticastAddrB
);
1364 writel(mask
[0], base
+ NvRegMulticastMaskA
);
1365 writel(mask
[1], base
+ NvRegMulticastMaskB
);
1366 writel(pff
, base
+ NvRegPacketFilterFlags
);
1367 dprintk(KERN_INFO
"%s: reconfiguration for multicast lists.\n",
1370 spin_unlock_irq(&np
->lock
);
1373 static int nv_update_linkspeed(struct net_device
*dev
)
1375 struct fe_priv
*np
= get_nvpriv(dev
);
1376 u8 __iomem
*base
= get_hwbase(dev
);
1378 int newls
= np
->linkspeed
;
1379 int newdup
= np
->duplex
;
1382 u32 control_1000
, status_1000
, phyreg
;
1384 /* BMSR_LSTATUS is latched, read it twice:
1385 * we want the current value.
1387 mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
1388 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
1390 if (!(mii_status
& BMSR_LSTATUS
)) {
1391 dprintk(KERN_DEBUG
"%s: no link detected by phy - falling back to 10HD.\n",
1393 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1399 if (np
->autoneg
== 0) {
1400 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
1401 dev
->name
, np
->fixed_mode
);
1402 if (np
->fixed_mode
& LPA_100FULL
) {
1403 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
1405 } else if (np
->fixed_mode
& LPA_100HALF
) {
1406 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
1408 } else if (np
->fixed_mode
& LPA_10FULL
) {
1409 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1412 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1418 /* check auto negotiation is complete */
1419 if (!(mii_status
& BMSR_ANEGCOMPLETE
)) {
1420 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
1421 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1424 dprintk(KERN_DEBUG
"%s: autoneg not completed - falling back to 10HD.\n", dev
->name
);
1429 if (np
->gigabit
== PHY_GIGABIT
) {
1430 control_1000
= mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, MII_READ
);
1431 status_1000
= mii_rw(dev
, np
->phyaddr
, MII_1000BT_SR
, MII_READ
);
1433 if ((control_1000
& ADVERTISE_1000FULL
) &&
1434 (status_1000
& LPA_1000FULL
)) {
1435 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: GBit ethernet detected.\n",
1437 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_1000
;
1443 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
1444 lpa
= mii_rw(dev
, np
->phyaddr
, MII_LPA
, MII_READ
);
1445 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
1446 dev
->name
, adv
, lpa
);
1448 /* FIXME: handle parallel detection properly */
1450 if (lpa
& LPA_100FULL
) {
1451 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
1453 } else if (lpa
& LPA_100HALF
) {
1454 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
1456 } else if (lpa
& LPA_10FULL
) {
1457 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1459 } else if (lpa
& LPA_10HALF
) {
1460 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1463 dprintk(KERN_DEBUG
"%s: bad ability %04x - falling back to 10HD.\n", dev
->name
, lpa
);
1464 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1469 if (np
->duplex
== newdup
&& np
->linkspeed
== newls
)
1472 dprintk(KERN_INFO
"%s: changing link setting from %d/%d to %d/%d.\n",
1473 dev
->name
, np
->linkspeed
, np
->duplex
, newls
, newdup
);
1475 np
->duplex
= newdup
;
1476 np
->linkspeed
= newls
;
1478 if (np
->gigabit
== PHY_GIGABIT
) {
1479 phyreg
= readl(base
+ NvRegRandomSeed
);
1480 phyreg
&= ~(0x3FF00);
1481 if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_10
)
1482 phyreg
|= NVREG_RNDSEED_FORCE3
;
1483 else if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_100
)
1484 phyreg
|= NVREG_RNDSEED_FORCE2
;
1485 else if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_1000
)
1486 phyreg
|= NVREG_RNDSEED_FORCE
;
1487 writel(phyreg
, base
+ NvRegRandomSeed
);
1490 phyreg
= readl(base
+ NvRegPhyInterface
);
1491 phyreg
&= ~(PHY_HALF
|PHY_100
|PHY_1000
);
1492 if (np
->duplex
== 0)
1494 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_100
)
1496 else if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_1000
)
1498 writel(phyreg
, base
+ NvRegPhyInterface
);
1500 writel(NVREG_MISC1_FORCE
| ( np
->duplex
? 0 : NVREG_MISC1_HD
),
1503 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
1509 static void nv_linkchange(struct net_device
*dev
)
1511 if (nv_update_linkspeed(dev
)) {
1512 if (netif_carrier_ok(dev
)) {
1515 netif_carrier_on(dev
);
1516 printk(KERN_INFO
"%s: link up.\n", dev
->name
);
1520 if (netif_carrier_ok(dev
)) {
1521 netif_carrier_off(dev
);
1522 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
1528 static void nv_link_irq(struct net_device
*dev
)
1530 u8 __iomem
*base
= get_hwbase(dev
);
1533 miistat
= readl(base
+ NvRegMIIStatus
);
1534 writel(NVREG_MIISTAT_MASK
, base
+ NvRegMIIStatus
);
1535 dprintk(KERN_INFO
"%s: link change irq, status 0x%x.\n", dev
->name
, miistat
);
1537 if (miistat
& (NVREG_MIISTAT_LINKCHANGE
))
1539 dprintk(KERN_DEBUG
"%s: link change notification done.\n", dev
->name
);
1542 static irqreturn_t
nv_nic_irq(int foo
, void *data
, struct pt_regs
*regs
)
1544 struct net_device
*dev
= (struct net_device
*) data
;
1545 struct fe_priv
*np
= get_nvpriv(dev
);
1546 u8 __iomem
*base
= get_hwbase(dev
);
1550 dprintk(KERN_DEBUG
"%s: nv_nic_irq\n", dev
->name
);
1553 events
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
1554 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
1556 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, events
);
1557 if (!(events
& np
->irqmask
))
1560 if (events
& (NVREG_IRQ_TX1
|NVREG_IRQ_TX2
|NVREG_IRQ_TX_ERR
)) {
1561 spin_lock(&np
->lock
);
1563 spin_unlock(&np
->lock
);
1566 if (events
& (NVREG_IRQ_RX_ERROR
|NVREG_IRQ_RX
|NVREG_IRQ_RX_NOBUF
)) {
1568 if (nv_alloc_rx(dev
)) {
1569 spin_lock(&np
->lock
);
1570 if (!np
->in_shutdown
)
1571 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
1572 spin_unlock(&np
->lock
);
1576 if (events
& NVREG_IRQ_LINK
) {
1577 spin_lock(&np
->lock
);
1579 spin_unlock(&np
->lock
);
1581 if (np
->need_linktimer
&& time_after(jiffies
, np
->link_timeout
)) {
1582 spin_lock(&np
->lock
);
1584 spin_unlock(&np
->lock
);
1585 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
1587 if (events
& (NVREG_IRQ_TX_ERR
)) {
1588 dprintk(KERN_DEBUG
"%s: received irq with events 0x%x. Probably TX fail.\n",
1591 if (events
& (NVREG_IRQ_UNKNOWN
)) {
1592 printk(KERN_DEBUG
"%s: received irq with unknown events 0x%x. Please report\n",
1595 if (i
> max_interrupt_work
) {
1596 spin_lock(&np
->lock
);
1597 /* disable interrupts on the nic */
1598 writel(0, base
+ NvRegIrqMask
);
1601 if (!np
->in_shutdown
)
1602 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
1603 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq.\n", dev
->name
, i
);
1604 spin_unlock(&np
->lock
);
1609 dprintk(KERN_DEBUG
"%s: nv_nic_irq completed\n", dev
->name
);
1611 return IRQ_RETVAL(i
);
1614 static void nv_do_nic_poll(unsigned long data
)
1616 struct net_device
*dev
= (struct net_device
*) data
;
1617 struct fe_priv
*np
= get_nvpriv(dev
);
1618 u8 __iomem
*base
= get_hwbase(dev
);
1620 disable_irq(dev
->irq
);
1621 /* FIXME: Do we need synchronize_irq(dev->irq) here? */
1623 * reenable interrupts on the nic, we have to do this before calling
1624 * nv_nic_irq because that may decide to do otherwise
1626 writel(np
->irqmask
, base
+ NvRegIrqMask
);
1628 nv_nic_irq((int) 0, (void *) data
, (struct pt_regs
*) NULL
);
1629 enable_irq(dev
->irq
);
1632 #ifdef CONFIG_NET_POLL_CONTROLLER
1633 static void nv_poll_controller(struct net_device
*dev
)
1635 nv_do_nic_poll((unsigned long) dev
);
1639 static void nv_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
1641 struct fe_priv
*np
= get_nvpriv(dev
);
1642 strcpy(info
->driver
, "forcedeth");
1643 strcpy(info
->version
, FORCEDETH_VERSION
);
1644 strcpy(info
->bus_info
, pci_name(np
->pci_dev
));
1647 static void nv_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wolinfo
)
1649 struct fe_priv
*np
= get_nvpriv(dev
);
1650 wolinfo
->supported
= WAKE_MAGIC
;
1652 spin_lock_irq(&np
->lock
);
1654 wolinfo
->wolopts
= WAKE_MAGIC
;
1655 spin_unlock_irq(&np
->lock
);
1658 static int nv_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wolinfo
)
1660 struct fe_priv
*np
= get_nvpriv(dev
);
1661 u8 __iomem
*base
= get_hwbase(dev
);
1663 spin_lock_irq(&np
->lock
);
1664 if (wolinfo
->wolopts
== 0) {
1665 writel(0, base
+ NvRegWakeUpFlags
);
1668 if (wolinfo
->wolopts
& WAKE_MAGIC
) {
1669 writel(NVREG_WAKEUPFLAGS_ENABLE
, base
+ NvRegWakeUpFlags
);
1672 spin_unlock_irq(&np
->lock
);
1676 static int nv_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
1678 struct fe_priv
*np
= netdev_priv(dev
);
1681 spin_lock_irq(&np
->lock
);
1682 ecmd
->port
= PORT_MII
;
1683 if (!netif_running(dev
)) {
1684 /* We do not track link speed / duplex setting if the
1685 * interface is disabled. Force a link check */
1686 nv_update_linkspeed(dev
);
1688 switch(np
->linkspeed
& (NVREG_LINKSPEED_MASK
)) {
1689 case NVREG_LINKSPEED_10
:
1690 ecmd
->speed
= SPEED_10
;
1692 case NVREG_LINKSPEED_100
:
1693 ecmd
->speed
= SPEED_100
;
1695 case NVREG_LINKSPEED_1000
:
1696 ecmd
->speed
= SPEED_1000
;
1699 ecmd
->duplex
= DUPLEX_HALF
;
1701 ecmd
->duplex
= DUPLEX_FULL
;
1703 ecmd
->autoneg
= np
->autoneg
;
1705 ecmd
->advertising
= ADVERTISED_MII
;
1707 ecmd
->advertising
|= ADVERTISED_Autoneg
;
1708 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
1710 adv
= np
->fixed_mode
;
1712 if (adv
& ADVERTISE_10HALF
)
1713 ecmd
->advertising
|= ADVERTISED_10baseT_Half
;
1714 if (adv
& ADVERTISE_10FULL
)
1715 ecmd
->advertising
|= ADVERTISED_10baseT_Full
;
1716 if (adv
& ADVERTISE_100HALF
)
1717 ecmd
->advertising
|= ADVERTISED_100baseT_Half
;
1718 if (adv
& ADVERTISE_100FULL
)
1719 ecmd
->advertising
|= ADVERTISED_100baseT_Full
;
1720 if (np
->autoneg
&& np
->gigabit
== PHY_GIGABIT
) {
1721 adv
= mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, MII_READ
);
1722 if (adv
& ADVERTISE_1000FULL
)
1723 ecmd
->advertising
|= ADVERTISED_1000baseT_Full
;
1726 ecmd
->supported
= (SUPPORTED_Autoneg
|
1727 SUPPORTED_10baseT_Half
| SUPPORTED_10baseT_Full
|
1728 SUPPORTED_100baseT_Half
| SUPPORTED_100baseT_Full
|
1730 if (np
->gigabit
== PHY_GIGABIT
)
1731 ecmd
->supported
|= SUPPORTED_1000baseT_Full
;
1733 ecmd
->phy_address
= np
->phyaddr
;
1734 ecmd
->transceiver
= XCVR_EXTERNAL
;
1736 /* ignore maxtxpkt, maxrxpkt for now */
1737 spin_unlock_irq(&np
->lock
);
1741 static int nv_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
1743 struct fe_priv
*np
= netdev_priv(dev
);
1745 if (ecmd
->port
!= PORT_MII
)
1747 if (ecmd
->transceiver
!= XCVR_EXTERNAL
)
1749 if (ecmd
->phy_address
!= np
->phyaddr
) {
1750 /* TODO: support switching between multiple phys. Should be
1751 * trivial, but not enabled due to lack of test hardware. */
1754 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
1757 mask
= ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
1758 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
;
1759 if (np
->gigabit
== PHY_GIGABIT
)
1760 mask
|= ADVERTISED_1000baseT_Full
;
1762 if ((ecmd
->advertising
& mask
) == 0)
1765 } else if (ecmd
->autoneg
== AUTONEG_DISABLE
) {
1766 /* Note: autonegotiation disable, speed 1000 intentionally
1767 * forbidden - noone should need that. */
1769 if (ecmd
->speed
!= SPEED_10
&& ecmd
->speed
!= SPEED_100
)
1771 if (ecmd
->duplex
!= DUPLEX_HALF
&& ecmd
->duplex
!= DUPLEX_FULL
)
1777 spin_lock_irq(&np
->lock
);
1778 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
1783 /* advertise only what has been requested */
1784 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
1785 adv
&= ~(ADVERTISE_ALL
| ADVERTISE_100BASE4
);
1786 if (ecmd
->advertising
& ADVERTISED_10baseT_Half
)
1787 adv
|= ADVERTISE_10HALF
;
1788 if (ecmd
->advertising
& ADVERTISED_10baseT_Full
)
1789 adv
|= ADVERTISE_10FULL
;
1790 if (ecmd
->advertising
& ADVERTISED_100baseT_Half
)
1791 adv
|= ADVERTISE_100HALF
;
1792 if (ecmd
->advertising
& ADVERTISED_100baseT_Full
)
1793 adv
|= ADVERTISE_100FULL
;
1794 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
1796 if (np
->gigabit
== PHY_GIGABIT
) {
1797 adv
= mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, MII_READ
);
1798 adv
&= ~ADVERTISE_1000FULL
;
1799 if (ecmd
->advertising
& ADVERTISED_1000baseT_Full
)
1800 adv
|= ADVERTISE_1000FULL
;
1801 mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, adv
);
1804 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
1805 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
1806 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
1813 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
1814 adv
&= ~(ADVERTISE_ALL
| ADVERTISE_100BASE4
);
1815 if (ecmd
->speed
== SPEED_10
&& ecmd
->duplex
== DUPLEX_HALF
)
1816 adv
|= ADVERTISE_10HALF
;
1817 if (ecmd
->speed
== SPEED_10
&& ecmd
->duplex
== DUPLEX_FULL
)
1818 adv
|= ADVERTISE_10FULL
;
1819 if (ecmd
->speed
== SPEED_100
&& ecmd
->duplex
== DUPLEX_HALF
)
1820 adv
|= ADVERTISE_100HALF
;
1821 if (ecmd
->speed
== SPEED_100
&& ecmd
->duplex
== DUPLEX_FULL
)
1822 adv
|= ADVERTISE_100FULL
;
1823 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
1824 np
->fixed_mode
= adv
;
1826 if (np
->gigabit
== PHY_GIGABIT
) {
1827 adv
= mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, MII_READ
);
1828 adv
&= ~ADVERTISE_1000FULL
;
1829 mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, adv
);
1832 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
1833 bmcr
|= ~(BMCR_ANENABLE
|BMCR_SPEED100
|BMCR_FULLDPLX
);
1834 if (adv
& (ADVERTISE_10FULL
|ADVERTISE_100FULL
))
1835 bmcr
|= BMCR_FULLDPLX
;
1836 if (adv
& (ADVERTISE_100HALF
|ADVERTISE_100FULL
))
1837 bmcr
|= BMCR_SPEED100
;
1838 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
1840 if (netif_running(dev
)) {
1841 /* Wait a bit and then reconfigure the nic. */
1846 spin_unlock_irq(&np
->lock
);
1851 #define FORCEDETH_REGS_VER 1
1852 #define FORCEDETH_REGS_SIZE 0x400 /* 256 32-bit registers */
1854 static int nv_get_regs_len(struct net_device
*dev
)
1856 return FORCEDETH_REGS_SIZE
;
1859 static void nv_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
, void *buf
)
1861 struct fe_priv
*np
= get_nvpriv(dev
);
1862 u8 __iomem
*base
= get_hwbase(dev
);
1866 regs
->version
= FORCEDETH_REGS_VER
;
1867 spin_lock_irq(&np
->lock
);
1868 for (i
=0;i
<FORCEDETH_REGS_SIZE
/sizeof(u32
);i
++)
1869 rbuf
[i
] = readl(base
+ i
*sizeof(u32
));
1870 spin_unlock_irq(&np
->lock
);
1873 static int nv_nway_reset(struct net_device
*dev
)
1875 struct fe_priv
*np
= get_nvpriv(dev
);
1878 spin_lock_irq(&np
->lock
);
1882 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
1883 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
1884 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
1890 spin_unlock_irq(&np
->lock
);
1895 static struct ethtool_ops ops
= {
1896 .get_drvinfo
= nv_get_drvinfo
,
1897 .get_link
= ethtool_op_get_link
,
1898 .get_wol
= nv_get_wol
,
1899 .set_wol
= nv_set_wol
,
1900 .get_settings
= nv_get_settings
,
1901 .set_settings
= nv_set_settings
,
1902 .get_regs_len
= nv_get_regs_len
,
1903 .get_regs
= nv_get_regs
,
1904 .nway_reset
= nv_nway_reset
,
1907 static int nv_open(struct net_device
*dev
)
1909 struct fe_priv
*np
= get_nvpriv(dev
);
1910 u8 __iomem
*base
= get_hwbase(dev
);
1913 dprintk(KERN_DEBUG
"nv_open: begin\n");
1915 /* 1) erase previous misconfiguration */
1916 /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
1917 writel(NVREG_MCASTADDRA_FORCE
, base
+ NvRegMulticastAddrA
);
1918 writel(0, base
+ NvRegMulticastAddrB
);
1919 writel(0, base
+ NvRegMulticastMaskA
);
1920 writel(0, base
+ NvRegMulticastMaskB
);
1921 writel(0, base
+ NvRegPacketFilterFlags
);
1923 writel(0, base
+ NvRegTransmitterControl
);
1924 writel(0, base
+ NvRegReceiverControl
);
1926 writel(0, base
+ NvRegAdapterControl
);
1928 /* 2) initialize descriptor rings */
1930 oom
= nv_init_ring(dev
);
1932 writel(0, base
+ NvRegLinkSpeed
);
1933 writel(0, base
+ NvRegUnknownTransmitterReg
);
1935 writel(0, base
+ NvRegUnknownSetupReg6
);
1937 np
->in_shutdown
= 0;
1939 /* 3) set mac address */
1943 mac
[0] = (dev
->dev_addr
[0] << 0) + (dev
->dev_addr
[1] << 8) +
1944 (dev
->dev_addr
[2] << 16) + (dev
->dev_addr
[3] << 24);
1945 mac
[1] = (dev
->dev_addr
[4] << 0) + (dev
->dev_addr
[5] << 8);
1947 writel(mac
[0], base
+ NvRegMacAddrA
);
1948 writel(mac
[1], base
+ NvRegMacAddrB
);
1951 /* 4) give hw rings */
1952 writel((u32
) np
->ring_addr
, base
+ NvRegRxRingPhysAddr
);
1953 writel((u32
) (np
->ring_addr
+ RX_RING
*sizeof(struct ring_desc
)), base
+ NvRegTxRingPhysAddr
);
1954 writel( ((RX_RING
-1) << NVREG_RINGSZ_RXSHIFT
) + ((TX_RING
-1) << NVREG_RINGSZ_TXSHIFT
),
1955 base
+ NvRegRingSizes
);
1957 /* 5) continue setup */
1958 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
1959 writel(NVREG_UNKSETUP3_VAL1
, base
+ NvRegUnknownSetupReg3
);
1960 writel(np
->desc_ver
, base
+ NvRegTxRxControl
);
1962 writel(NVREG_TXRXCTL_BIT1
|np
->desc_ver
, base
+ NvRegTxRxControl
);
1963 reg_delay(dev
, NvRegUnknownSetupReg5
, NVREG_UNKSETUP5_BIT31
, NVREG_UNKSETUP5_BIT31
,
1964 NV_SETUP5_DELAY
, NV_SETUP5_DELAYMAX
,
1965 KERN_INFO
"open: SetupReg5, Bit 31 remained off\n");
1967 writel(0, base
+ NvRegUnknownSetupReg4
);
1968 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
1969 writel(NVREG_MIISTAT_MASK2
, base
+ NvRegMIIStatus
);
1971 /* 6) continue setup */
1972 writel(NVREG_MISC1_FORCE
| NVREG_MISC1_HD
, base
+ NvRegMisc1
);
1973 writel(readl(base
+ NvRegTransmitterStatus
), base
+ NvRegTransmitterStatus
);
1974 writel(NVREG_PFF_ALWAYS
, base
+ NvRegPacketFilterFlags
);
1975 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
1977 writel(readl(base
+ NvRegReceiverStatus
), base
+ NvRegReceiverStatus
);
1978 get_random_bytes(&i
, sizeof(i
));
1979 writel(NVREG_RNDSEED_FORCE
| (i
&NVREG_RNDSEED_MASK
), base
+ NvRegRandomSeed
);
1980 writel(NVREG_UNKSETUP1_VAL
, base
+ NvRegUnknownSetupReg1
);
1981 writel(NVREG_UNKSETUP2_VAL
, base
+ NvRegUnknownSetupReg2
);
1982 writel(NVREG_POLL_DEFAULT
, base
+ NvRegPollingInterval
);
1983 writel(NVREG_UNKSETUP6_VAL
, base
+ NvRegUnknownSetupReg6
);
1984 writel((np
->phyaddr
<< NVREG_ADAPTCTL_PHYSHIFT
)|NVREG_ADAPTCTL_PHYVALID
|NVREG_ADAPTCTL_RUNNING
,
1985 base
+ NvRegAdapterControl
);
1986 writel(NVREG_MIISPEED_BIT8
|NVREG_MIIDELAY
, base
+ NvRegMIISpeed
);
1987 writel(NVREG_UNKSETUP4_VAL
, base
+ NvRegUnknownSetupReg4
);
1988 writel(NVREG_WAKEUPFLAGS_VAL
, base
+ NvRegWakeUpFlags
);
1990 i
= readl(base
+ NvRegPowerState
);
1991 if ( (i
& NVREG_POWERSTATE_POWEREDUP
) == 0)
1992 writel(NVREG_POWERSTATE_POWEREDUP
|i
, base
+ NvRegPowerState
);
1996 writel(readl(base
+ NvRegPowerState
) | NVREG_POWERSTATE_VALID
, base
+ NvRegPowerState
);
1998 writel(0, base
+ NvRegIrqMask
);
2000 writel(NVREG_MIISTAT_MASK2
, base
+ NvRegMIIStatus
);
2001 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
2004 ret
= request_irq(dev
->irq
, &nv_nic_irq
, SA_SHIRQ
, dev
->name
, dev
);
2008 /* ask for interrupts */
2009 writel(np
->irqmask
, base
+ NvRegIrqMask
);
2011 spin_lock_irq(&np
->lock
);
2012 writel(NVREG_MCASTADDRA_FORCE
, base
+ NvRegMulticastAddrA
);
2013 writel(0, base
+ NvRegMulticastAddrB
);
2014 writel(0, base
+ NvRegMulticastMaskA
);
2015 writel(0, base
+ NvRegMulticastMaskB
);
2016 writel(NVREG_PFF_ALWAYS
|NVREG_PFF_MYADDR
, base
+ NvRegPacketFilterFlags
);
2017 /* One manual link speed update: Interrupts are enabled, future link
2018 * speed changes cause interrupts and are handled by nv_link_irq().
2022 miistat
= readl(base
+ NvRegMIIStatus
);
2023 writel(NVREG_MIISTAT_MASK
, base
+ NvRegMIIStatus
);
2024 dprintk(KERN_INFO
"startup: got 0x%08x.\n", miistat
);
2026 ret
= nv_update_linkspeed(dev
);
2029 netif_start_queue(dev
);
2031 netif_carrier_on(dev
);
2033 printk("%s: no link during initialization.\n", dev
->name
);
2034 netif_carrier_off(dev
);
2037 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
2038 spin_unlock_irq(&np
->lock
);
2046 static int nv_close(struct net_device
*dev
)
2048 struct fe_priv
*np
= get_nvpriv(dev
);
2051 spin_lock_irq(&np
->lock
);
2052 np
->in_shutdown
= 1;
2053 spin_unlock_irq(&np
->lock
);
2054 synchronize_irq(dev
->irq
);
2056 del_timer_sync(&np
->oom_kick
);
2057 del_timer_sync(&np
->nic_poll
);
2059 netif_stop_queue(dev
);
2060 spin_lock_irq(&np
->lock
);
2065 /* disable interrupts on the nic or we will lock up */
2066 base
= get_hwbase(dev
);
2067 writel(0, base
+ NvRegIrqMask
);
2069 dprintk(KERN_INFO
"%s: Irqmask is zero again\n", dev
->name
);
2071 spin_unlock_irq(&np
->lock
);
2073 free_irq(dev
->irq
, dev
);
2080 /* FIXME: power down nic */
2085 static int __devinit
nv_probe(struct pci_dev
*pci_dev
, const struct pci_device_id
*id
)
2087 struct net_device
*dev
;
2093 dev
= alloc_etherdev(sizeof(struct fe_priv
));
2098 np
= get_nvpriv(dev
);
2099 np
->pci_dev
= pci_dev
;
2100 spin_lock_init(&np
->lock
);
2101 SET_MODULE_OWNER(dev
);
2102 SET_NETDEV_DEV(dev
, &pci_dev
->dev
);
2104 init_timer(&np
->oom_kick
);
2105 np
->oom_kick
.data
= (unsigned long) dev
;
2106 np
->oom_kick
.function
= &nv_do_rx_refill
; /* timer handler */
2107 init_timer(&np
->nic_poll
);
2108 np
->nic_poll
.data
= (unsigned long) dev
;
2109 np
->nic_poll
.function
= &nv_do_nic_poll
; /* timer handler */
2111 err
= pci_enable_device(pci_dev
);
2113 printk(KERN_INFO
"forcedeth: pci_enable_dev failed (%d) for device %s\n",
2114 err
, pci_name(pci_dev
));
2118 pci_set_master(pci_dev
);
2120 err
= pci_request_regions(pci_dev
, DRV_NAME
);
2126 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
2127 dprintk(KERN_DEBUG
"%s: resource %d start %p len %ld flags 0x%08lx.\n",
2128 pci_name(pci_dev
), i
, (void*)pci_resource_start(pci_dev
, i
),
2129 pci_resource_len(pci_dev
, i
),
2130 pci_resource_flags(pci_dev
, i
));
2131 if (pci_resource_flags(pci_dev
, i
) & IORESOURCE_MEM
&&
2132 pci_resource_len(pci_dev
, i
) >= NV_PCI_REGSZ
) {
2133 addr
= pci_resource_start(pci_dev
, i
);
2137 if (i
== DEVICE_COUNT_RESOURCE
) {
2138 printk(KERN_INFO
"forcedeth: Couldn't find register window for device %s.\n",
2143 /* handle different descriptor versions */
2144 np
->desc_ver
= DESC_VER_1
;
2145 np
->pkt_limit
= NV_PKTLIMIT_1
;
2146 if (id
->driver_data
& DEV_HAS_LARGEDESC
) {
2147 np
->desc_ver
= DESC_VER_2
;
2148 np
->pkt_limit
= NV_PKTLIMIT_2
;
2152 np
->base
= ioremap(addr
, NV_PCI_REGSZ
);
2155 dev
->base_addr
= (unsigned long)np
->base
;
2156 dev
->irq
= pci_dev
->irq
;
2157 np
->rx_ring
= pci_alloc_consistent(pci_dev
, sizeof(struct ring_desc
) * (RX_RING
+ TX_RING
),
2161 np
->tx_ring
= &np
->rx_ring
[RX_RING
];
2163 dev
->open
= nv_open
;
2164 dev
->stop
= nv_close
;
2165 dev
->hard_start_xmit
= nv_start_xmit
;
2166 dev
->get_stats
= nv_get_stats
;
2167 dev
->change_mtu
= nv_change_mtu
;
2168 dev
->set_multicast_list
= nv_set_multicast
;
2169 #ifdef CONFIG_NET_POLL_CONTROLLER
2170 dev
->poll_controller
= nv_poll_controller
;
2172 SET_ETHTOOL_OPS(dev
, &ops
);
2173 dev
->tx_timeout
= nv_tx_timeout
;
2174 dev
->watchdog_timeo
= NV_WATCHDOG_TIMEO
;
2176 pci_set_drvdata(pci_dev
, dev
);
2178 /* read the mac address */
2179 base
= get_hwbase(dev
);
2180 np
->orig_mac
[0] = readl(base
+ NvRegMacAddrA
);
2181 np
->orig_mac
[1] = readl(base
+ NvRegMacAddrB
);
2183 dev
->dev_addr
[0] = (np
->orig_mac
[1] >> 8) & 0xff;
2184 dev
->dev_addr
[1] = (np
->orig_mac
[1] >> 0) & 0xff;
2185 dev
->dev_addr
[2] = (np
->orig_mac
[0] >> 24) & 0xff;
2186 dev
->dev_addr
[3] = (np
->orig_mac
[0] >> 16) & 0xff;
2187 dev
->dev_addr
[4] = (np
->orig_mac
[0] >> 8) & 0xff;
2188 dev
->dev_addr
[5] = (np
->orig_mac
[0] >> 0) & 0xff;
2190 if (!is_valid_ether_addr(dev
->dev_addr
)) {
2192 * Bad mac address. At least one bios sets the mac address
2193 * to 01:23:45:67:89:ab
2195 printk(KERN_ERR
"%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
2197 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
2198 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
2199 printk(KERN_ERR
"Please complain to your hardware vendor. Switching to a random MAC.\n");
2200 dev
->dev_addr
[0] = 0x00;
2201 dev
->dev_addr
[1] = 0x00;
2202 dev
->dev_addr
[2] = 0x6c;
2203 get_random_bytes(&dev
->dev_addr
[3], 3);
2206 dprintk(KERN_DEBUG
"%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev
),
2207 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
2208 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
2211 writel(0, base
+ NvRegWakeUpFlags
);
2214 if (np
->desc_ver
== DESC_VER_1
) {
2215 np
->tx_flags
= NV_TX_LASTPACKET
|NV_TX_VALID
;
2216 if (id
->driver_data
& DEV_NEED_LASTPACKET1
)
2217 np
->tx_flags
|= NV_TX_LASTPACKET1
;
2219 np
->tx_flags
= NV_TX2_LASTPACKET
|NV_TX2_VALID
;
2220 if (id
->driver_data
& DEV_NEED_LASTPACKET1
)
2221 np
->tx_flags
|= NV_TX2_LASTPACKET1
;
2223 if (id
->driver_data
& DEV_IRQMASK_1
)
2224 np
->irqmask
= NVREG_IRQMASK_WANTED_1
;
2225 if (id
->driver_data
& DEV_IRQMASK_2
)
2226 np
->irqmask
= NVREG_IRQMASK_WANTED_2
;
2227 if (id
->driver_data
& DEV_NEED_TIMERIRQ
)
2228 np
->irqmask
|= NVREG_IRQ_TIMER
;
2229 if (id
->driver_data
& DEV_NEED_LINKTIMER
) {
2230 dprintk(KERN_INFO
"%s: link timer on.\n", pci_name(pci_dev
));
2231 np
->need_linktimer
= 1;
2232 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
2234 dprintk(KERN_INFO
"%s: link timer off.\n", pci_name(pci_dev
));
2235 np
->need_linktimer
= 0;
2238 /* find a suitable phy */
2239 for (i
= 1; i
< 32; i
++) {
2242 spin_lock_irq(&np
->lock
);
2243 id1
= mii_rw(dev
, i
, MII_PHYSID1
, MII_READ
);
2244 spin_unlock_irq(&np
->lock
);
2245 if (id1
< 0 || id1
== 0xffff)
2247 spin_lock_irq(&np
->lock
);
2248 id2
= mii_rw(dev
, i
, MII_PHYSID2
, MII_READ
);
2249 spin_unlock_irq(&np
->lock
);
2250 if (id2
< 0 || id2
== 0xffff)
2253 id1
= (id1
& PHYID1_OUI_MASK
) << PHYID1_OUI_SHFT
;
2254 id2
= (id2
& PHYID2_OUI_MASK
) >> PHYID2_OUI_SHFT
;
2255 dprintk(KERN_DEBUG
"%s: open: Found PHY %04x:%04x at address %d.\n",
2256 pci_name(pci_dev
), id1
, id2
, i
);
2258 np
->phy_oui
= id1
| id2
;
2262 /* PHY in isolate mode? No phy attached and user wants to
2263 * test loopback? Very odd, but can be correct.
2265 printk(KERN_INFO
"%s: open: Could not find a valid PHY.\n",
2274 /* set default link speed settings */
2275 np
->linkspeed
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
2279 err
= register_netdev(dev
);
2281 printk(KERN_INFO
"forcedeth: unable to register netdev: %d\n", err
);
2284 printk(KERN_INFO
"%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
2285 dev
->name
, pci_dev
->subsystem_vendor
, pci_dev
->subsystem_device
,
2291 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc
) * (RX_RING
+ TX_RING
),
2292 np
->rx_ring
, np
->ring_addr
);
2293 pci_set_drvdata(pci_dev
, NULL
);
2295 iounmap(get_hwbase(dev
));
2297 pci_release_regions(pci_dev
);
2299 pci_disable_device(pci_dev
);
2306 static void __devexit
nv_remove(struct pci_dev
*pci_dev
)
2308 struct net_device
*dev
= pci_get_drvdata(pci_dev
);
2309 struct fe_priv
*np
= get_nvpriv(dev
);
2310 u8 __iomem
*base
= get_hwbase(dev
);
2312 unregister_netdev(dev
);
2314 /* special op: write back the misordered MAC address - otherwise
2315 * the next nv_probe would see a wrong address.
2317 writel(np
->orig_mac
[0], base
+ NvRegMacAddrA
);
2318 writel(np
->orig_mac
[1], base
+ NvRegMacAddrB
);
2320 /* free all structures */
2321 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc
) * (RX_RING
+ TX_RING
), np
->rx_ring
, np
->ring_addr
);
2322 iounmap(get_hwbase(dev
));
2323 pci_release_regions(pci_dev
);
2324 pci_disable_device(pci_dev
);
2326 pci_set_drvdata(pci_dev
, NULL
);
2329 static struct pci_device_id pci_tbl
[] = {
2330 { /* nForce Ethernet Controller */
2331 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_1
),
2332 .driver_data
= DEV_IRQMASK_1
|DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
2334 { /* nForce2 Ethernet Controller */
2335 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_2
),
2336 .driver_data
= DEV_NEED_LASTPACKET1
|DEV_IRQMASK_2
|DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
2338 { /* nForce3 Ethernet Controller */
2339 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_3
),
2340 .driver_data
= DEV_NEED_LASTPACKET1
|DEV_IRQMASK_2
|DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
2342 { /* nForce3 Ethernet Controller */
2343 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_4
),
2344 .driver_data
= DEV_NEED_LASTPACKET1
|DEV_IRQMASK_2
|DEV_NEED_TIMERIRQ
|
2345 DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
,
2347 { /* nForce3 Ethernet Controller */
2348 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_5
),
2349 .driver_data
= DEV_NEED_LASTPACKET1
|DEV_IRQMASK_2
|DEV_NEED_TIMERIRQ
|
2350 DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
,
2352 { /* nForce3 Ethernet Controller */
2353 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_6
),
2354 .driver_data
= DEV_NEED_LASTPACKET1
|DEV_IRQMASK_2
|DEV_NEED_TIMERIRQ
|
2355 DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
,
2357 { /* nForce3 Ethernet Controller */
2358 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_7
),
2359 .driver_data
= DEV_NEED_LASTPACKET1
|DEV_IRQMASK_2
|DEV_NEED_TIMERIRQ
|
2360 DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
,
2362 { /* CK804 Ethernet Controller */
2363 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_8
),
2364 .driver_data
= DEV_NEED_LASTPACKET1
|DEV_IRQMASK_2
|DEV_NEED_TIMERIRQ
|
2365 DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
,
2367 { /* CK804 Ethernet Controller */
2368 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_9
),
2369 .driver_data
= DEV_NEED_LASTPACKET1
|DEV_IRQMASK_2
|DEV_NEED_TIMERIRQ
|
2370 DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
,
2372 { /* MCP04 Ethernet Controller */
2373 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_10
),
2374 .driver_data
= DEV_NEED_LASTPACKET1
|DEV_IRQMASK_2
|DEV_NEED_TIMERIRQ
|
2375 DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
,
2377 { /* MCP04 Ethernet Controller */
2378 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_11
),
2379 .driver_data
= DEV_NEED_LASTPACKET1
|DEV_IRQMASK_2
|DEV_NEED_TIMERIRQ
|
2380 DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
,
2382 { /* MCP51 Ethernet Controller */
2383 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_12
),
2384 .driver_data
= DEV_NEED_LASTPACKET1
|DEV_IRQMASK_2
|DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
2386 { /* MCP51 Ethernet Controller */
2387 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_13
),
2388 .driver_data
= DEV_NEED_LASTPACKET1
|DEV_IRQMASK_2
|DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
2390 { /* MCP55 Ethernet Controller */
2391 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_14
),
2392 .driver_data
= DEV_NEED_LASTPACKET1
|DEV_IRQMASK_2
|DEV_NEED_TIMERIRQ
|
2393 DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
,
2395 { /* MCP55 Ethernet Controller */
2396 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_15
),
2397 .driver_data
= DEV_NEED_LASTPACKET1
|DEV_IRQMASK_2
|DEV_NEED_TIMERIRQ
|
2398 DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
,
2403 static struct pci_driver driver
= {
2404 .name
= "forcedeth",
2405 .id_table
= pci_tbl
,
2407 .remove
= __devexit_p(nv_remove
),
2411 static int __init
init_nic(void)
2413 printk(KERN_INFO
"forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION
);
2414 return pci_module_init(&driver
);
2417 static void __exit
exit_nic(void)
2419 pci_unregister_driver(&driver
);
2422 module_param(max_interrupt_work
, int, 0);
2423 MODULE_PARM_DESC(max_interrupt_work
, "forcedeth maximum events handled per interrupt");
2425 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
2426 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
2427 MODULE_LICENSE("GPL");
2429 MODULE_DEVICE_TABLE(pci
, pci_tbl
);
2431 module_init(init_nic
);
2432 module_exit(exit_nic
);