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[DCCP] Only call the HC _exit() routines in dccp_v4_destroy_sock
[linux-2.6/mini2440.git] / drivers / video / tgafb.c
blob9d9d2009ad8caa3af457d263afa5c8717227016a
1 /*
2 * linux/drivers/video/tgafb.c -- DEC 21030 TGA frame buffer device
3 *
4 * Copyright (C) 1995 Jay Estabrook
5 * Copyright (C) 1997 Geert Uytterhoeven
6 * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha
7 * Copyright (C) 2002 Richard Henderson
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file COPYING in the main directory of this archive for
11 * more details.
12 */
13
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/sched.h>
17 #include <linux/errno.h>
18 #include <linux/string.h>
19 #include <linux/mm.h>
20 #include <linux/tty.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/init.h>
24 #include <linux/fb.h>
25 #include <linux/pci.h>
26 #include <linux/selection.h>
27 #include <asm/io.h>
28 #include <video/tgafb.h>
29 #include <linux/selection.h>
30
31 /*
32 * Local functions.
33 */
34
35 static int tgafb_check_var(struct fb_var_screeninfo *, struct fb_info *);
36 static int tgafb_set_par(struct fb_info *);
37 static void tgafb_set_pll(struct tga_par *, int);
38 static int tgafb_setcolreg(unsigned, unsigned, unsigned, unsigned,
39 unsigned, struct fb_info *);
40 static int tgafb_blank(int, struct fb_info *);
41 static void tgafb_init_fix(struct fb_info *);
42
43 static void tgafb_imageblit(struct fb_info *, const struct fb_image *);
44 static void tgafb_fillrect(struct fb_info *, const struct fb_fillrect *);
45 static void tgafb_copyarea(struct fb_info *, const struct fb_copyarea *);
46
47 static int tgafb_pci_register(struct pci_dev *, const struct pci_device_id *);
48 static void tgafb_pci_unregister(struct pci_dev *);
49
50 static const char *mode_option = "640x480@60";
51
52
53 /*
54 * Frame buffer operations
55 */
56
57 static struct fb_ops tgafb_ops = {
58 .owner = THIS_MODULE,
59 .fb_check_var = tgafb_check_var,
60 .fb_set_par = tgafb_set_par,
61 .fb_setcolreg = tgafb_setcolreg,
62 .fb_blank = tgafb_blank,
63 .fb_fillrect = tgafb_fillrect,
64 .fb_copyarea = tgafb_copyarea,
65 .fb_imageblit = tgafb_imageblit,
66 .fb_cursor = soft_cursor,
67 };
68
69
70 /*
71 * PCI registration operations
72 */
73
74 static struct pci_device_id const tgafb_pci_table[] = {
75 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TGA, PCI_ANY_ID, PCI_ANY_ID,
76 0, 0, 0 }
77 };
78
79 static struct pci_driver tgafb_driver = {
80 .name = "tgafb",
81 .id_table = tgafb_pci_table,
82 .probe = tgafb_pci_register,
83 .remove = __devexit_p(tgafb_pci_unregister),
84 };
85
86
87 /**
88 * tgafb_check_var - Optional function. Validates a var passed in.
89 * @var: frame buffer variable screen structure
90 * @info: frame buffer structure that represents a single frame buffer
91 */
92 static int
93 tgafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
94 {
95 struct tga_par *par = (struct tga_par *)info->par;
96
97 if (par->tga_type == TGA_TYPE_8PLANE) {
98 if (var->bits_per_pixel != 8)
99 return -EINVAL;
100 } else {
101 if (var->bits_per_pixel != 32)
102 return -EINVAL;
103 }
104
105 if (var->xres_virtual != var->xres || var->yres_virtual != var->yres)
106 return -EINVAL;
107 if (var->nonstd)
108 return -EINVAL;
109 if (1000000000 / var->pixclock > TGA_PLL_MAX_FREQ)
110 return -EINVAL;
111 if ((var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
112 return -EINVAL;
113
114 /* Some of the acceleration routines assume the line width is
115 a multiple of 64 bytes. */
116 if (var->xres * (par->tga_type == TGA_TYPE_8PLANE ? 1 : 4) % 64)
117 return -EINVAL;
118
119 return 0;
120 }
121
122 /**
123 * tgafb_set_par - Optional function. Alters the hardware state.
124 * @info: frame buffer structure that represents a single frame buffer
125 */
126 static int
127 tgafb_set_par(struct fb_info *info)
128 {
129 static unsigned int const deep_presets[4] = {
130 0x00014000,
131 0x0001440d,
132 0xffffffff,
133 0x0001441d
134 };
135 static unsigned int const rasterop_presets[4] = {
136 0x00000003,
137 0x00000303,
138 0xffffffff,
139 0x00000303
140 };
141 static unsigned int const mode_presets[4] = {
142 0x00002000,
143 0x00002300,
144 0xffffffff,
145 0x00002300
146 };
147 static unsigned int const base_addr_presets[4] = {
148 0x00000000,
149 0x00000001,
150 0xffffffff,
151 0x00000001
152 };
153
154 struct tga_par *par = (struct tga_par *) info->par;
155 u32 htimings, vtimings, pll_freq;
156 u8 tga_type;
157 int i, j;
158
159 /* Encode video timings. */
160 htimings = (((info->var.xres/4) & TGA_HORIZ_ACT_LSB)
161 | (((info->var.xres/4) & 0x600 << 19) & TGA_HORIZ_ACT_MSB));
162 vtimings = (info->var.yres & TGA_VERT_ACTIVE);
163 htimings |= ((info->var.right_margin/4) << 9) & TGA_HORIZ_FP;
164 vtimings |= (info->var.lower_margin << 11) & TGA_VERT_FP;
165 htimings |= ((info->var.hsync_len/4) << 14) & TGA_HORIZ_SYNC;
166 vtimings |= (info->var.vsync_len << 16) & TGA_VERT_SYNC;
167 htimings |= ((info->var.left_margin/4) << 21) & TGA_HORIZ_BP;
168 vtimings |= (info->var.upper_margin << 22) & TGA_VERT_BP;
169
170 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
171 htimings |= TGA_HORIZ_POLARITY;
172 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
173 vtimings |= TGA_VERT_POLARITY;
174
175 par->htimings = htimings;
176 par->vtimings = vtimings;
177
178 par->sync_on_green = !!(info->var.sync & FB_SYNC_ON_GREEN);
179
180 /* Store other useful values in par. */
181 par->xres = info->var.xres;
182 par->yres = info->var.yres;
183 par->pll_freq = pll_freq = 1000000000 / info->var.pixclock;
184 par->bits_per_pixel = info->var.bits_per_pixel;
185
186 tga_type = par->tga_type;
187
188 /* First, disable video. */
189 TGA_WRITE_REG(par, TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG);
190
191 /* Write the DEEP register. */
192 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
193 continue;
194 mb();
195 TGA_WRITE_REG(par, deep_presets[tga_type], TGA_DEEP_REG);
196 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
197 continue;
198 mb();
199
200 /* Write some more registers. */
201 TGA_WRITE_REG(par, rasterop_presets[tga_type], TGA_RASTEROP_REG);
202 TGA_WRITE_REG(par, mode_presets[tga_type], TGA_MODE_REG);
203 TGA_WRITE_REG(par, base_addr_presets[tga_type], TGA_BASE_ADDR_REG);
204
205 /* Calculate & write the PLL. */
206 tgafb_set_pll(par, pll_freq);
207
208 /* Write some more registers. */
209 TGA_WRITE_REG(par, 0xffffffff, TGA_PLANEMASK_REG);
210 TGA_WRITE_REG(par, 0xffffffff, TGA_PIXELMASK_REG);
211
212 /* Init video timing regs. */
213 TGA_WRITE_REG(par, htimings, TGA_HORIZ_REG);
214 TGA_WRITE_REG(par, vtimings, TGA_VERT_REG);
215
216 /* Initalise RAMDAC. */
217 if (tga_type == TGA_TYPE_8PLANE) {
218
219 /* Init BT485 RAMDAC registers. */
220 BT485_WRITE(par, 0xa2 | (par->sync_on_green ? 0x8 : 0x0),
221 BT485_CMD_0);
222 BT485_WRITE(par, 0x01, BT485_ADDR_PAL_WRITE);
223 BT485_WRITE(par, 0x14, BT485_CMD_3); /* cursor 64x64 */
224 BT485_WRITE(par, 0x40, BT485_CMD_1);
225 BT485_WRITE(par, 0x20, BT485_CMD_2); /* cursor off, for now */
226 BT485_WRITE(par, 0xff, BT485_PIXEL_MASK);
227
228 /* Fill palette registers. */
229 BT485_WRITE(par, 0x00, BT485_ADDR_PAL_WRITE);
230 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
231
232 for (i = 0; i < 16; i++) {
233 j = color_table[i];
234 TGA_WRITE_REG(par, default_red[j]|(BT485_DATA_PAL<<8),
235 TGA_RAMDAC_REG);
236 TGA_WRITE_REG(par, default_grn[j]|(BT485_DATA_PAL<<8),
237 TGA_RAMDAC_REG);
238 TGA_WRITE_REG(par, default_blu[j]|(BT485_DATA_PAL<<8),
239 TGA_RAMDAC_REG);
240 }
241 for (i = 0; i < 240*3; i += 4) {
242 TGA_WRITE_REG(par, 0x55|(BT485_DATA_PAL<<8),
243 TGA_RAMDAC_REG);
244 TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
245 TGA_RAMDAC_REG);
246 TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
247 TGA_RAMDAC_REG);
248 TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
249 TGA_RAMDAC_REG);
250 }
251
252 } else { /* 24-plane or 24plusZ */
253
254 /* Init BT463 registers. */
255 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_0, 0x40);
256 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_1, 0x08);
257 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_2,
258 (par->sync_on_green ? 0x80 : 0x40));
259
260 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_0, 0xff);
261 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_1, 0xff);
262 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_2, 0xff);
263 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_3, 0x0f);
264
265 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_0, 0x00);
266 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_1, 0x00);
267 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_2, 0x00);
268 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_3, 0x00);
269
270 /* Fill the palette. */
271 BT463_LOAD_ADDR(par, 0x0000);
272 TGA_WRITE_REG(par, BT463_PALETTE<<2, TGA_RAMDAC_REG);
273
274 for (i = 0; i < 16; i++) {
275 j = color_table[i];
276 TGA_WRITE_REG(par, default_red[j]|(BT463_PALETTE<<10),
277 TGA_RAMDAC_REG);
278 TGA_WRITE_REG(par, default_grn[j]|(BT463_PALETTE<<10),
279 TGA_RAMDAC_REG);
280 TGA_WRITE_REG(par, default_blu[j]|(BT463_PALETTE<<10),
281 TGA_RAMDAC_REG);
282 }
283 for (i = 0; i < 512*3; i += 4) {
284 TGA_WRITE_REG(par, 0x55|(BT463_PALETTE<<10),
285 TGA_RAMDAC_REG);
286 TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
287 TGA_RAMDAC_REG);
288 TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
289 TGA_RAMDAC_REG);
290 TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
291 TGA_RAMDAC_REG);
292 }
293
294 /* Fill window type table after start of vertical retrace. */
295 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
296 continue;
297 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
298 mb();
299 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
300 continue;
301 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
302
303 BT463_LOAD_ADDR(par, BT463_WINDOW_TYPE_BASE);
304 TGA_WRITE_REG(par, BT463_REG_ACC<<2, TGA_RAMDAC_SETUP_REG);
305
306 for (i = 0; i < 16; i++) {
307 TGA_WRITE_REG(par, 0x00|(BT463_REG_ACC<<10),
308 TGA_RAMDAC_REG);
309 TGA_WRITE_REG(par, 0x01|(BT463_REG_ACC<<10),
310 TGA_RAMDAC_REG);
311 TGA_WRITE_REG(par, 0x80|(BT463_REG_ACC<<10),
312 TGA_RAMDAC_REG);
313 }
314
315 }
316
317 /* Finally, enable video scan (and pray for the monitor... :-) */
318 TGA_WRITE_REG(par, TGA_VALID_VIDEO, TGA_VALID_REG);
319
320 return 0;
321 }
322
323 #define DIFFCHECK(X) \
324 do { \
325 if (m <= 0x3f) { \
326 int delta = f - (TGA_PLL_BASE_FREQ * (X)) / (r << shift); \
327 if (delta < 0) \
328 delta = -delta; \
329 if (delta < min_diff) \
330 min_diff = delta, vm = m, va = a, vr = r; \
331 } \
332 } while (0)
333
334 static void
335 tgafb_set_pll(struct tga_par *par, int f)
336 {
337 int n, shift, base, min_diff, target;
338 int r,a,m,vm = 34, va = 1, vr = 30;
339
340 for (r = 0 ; r < 12 ; r++)
341 TGA_WRITE_REG(par, !r, TGA_CLOCK_REG);
342
343 if (f > TGA_PLL_MAX_FREQ)
344 f = TGA_PLL_MAX_FREQ;
345
346 if (f >= TGA_PLL_MAX_FREQ / 2)
347 shift = 0;
348 else if (f >= TGA_PLL_MAX_FREQ / 4)
349 shift = 1;
350 else
351 shift = 2;
352
353 TGA_WRITE_REG(par, shift & 1, TGA_CLOCK_REG);
354 TGA_WRITE_REG(par, shift >> 1, TGA_CLOCK_REG);
355
356 for (r = 0 ; r < 10 ; r++)
357 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
358
359 if (f <= 120000) {
360 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
361 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
362 }
363 else if (f <= 200000) {
364 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
365 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
366 }
367 else {
368 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
369 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
370 }
371
372 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
373 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
374 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
375 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
376 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
377 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
378
379 target = (f << shift) / TGA_PLL_BASE_FREQ;
380 min_diff = TGA_PLL_MAX_FREQ;
381
382 r = 7 / target;
383 if (!r) r = 1;
384
385 base = target * r;
386 while (base < 449) {
387 for (n = base < 7 ? 7 : base; n < base + target && n < 449; n++) {
388 m = ((n + 3) / 7) - 1;
389 a = 0;
390 DIFFCHECK((m + 1) * 7);
391 m++;
392 DIFFCHECK((m + 1) * 7);
393 m = (n / 6) - 1;
394 if ((a = n % 6))
395 DIFFCHECK(n);
396 }
397 r++;
398 base += target;
399 }
400
401 vr--;
402
403 for (r = 0; r < 8; r++)
404 TGA_WRITE_REG(par, (vm >> r) & 1, TGA_CLOCK_REG);
405 for (r = 0; r < 8 ; r++)
406 TGA_WRITE_REG(par, (va >> r) & 1, TGA_CLOCK_REG);
407 for (r = 0; r < 7 ; r++)
408 TGA_WRITE_REG(par, (vr >> r) & 1, TGA_CLOCK_REG);
409 TGA_WRITE_REG(par, ((vr >> 7) & 1)|2, TGA_CLOCK_REG);
410 }
411
412
413 /**
414 * tgafb_setcolreg - Optional function. Sets a color register.
415 * @regno: boolean, 0 copy local, 1 get_user() function
416 * @red: frame buffer colormap structure
417 * @green: The green value which can be up to 16 bits wide
418 * @blue: The blue value which can be up to 16 bits wide.
419 * @transp: If supported the alpha value which can be up to 16 bits wide.
420 * @info: frame buffer info structure
421 */
422 static int
423 tgafb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
424 unsigned transp, struct fb_info *info)
425 {
426 struct tga_par *par = (struct tga_par *) info->par;
427
428 if (regno > 255)
429 return 1;
430 red >>= 8;
431 green >>= 8;
432 blue >>= 8;
433
434 if (par->tga_type == TGA_TYPE_8PLANE) {
435 BT485_WRITE(par, regno, BT485_ADDR_PAL_WRITE);
436 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
437 TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
438 TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
439 TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
440 } else if (regno < 16) {
441 u32 value = (red << 16) | (green << 8) | blue;
442 ((u32 *)info->pseudo_palette)[regno] = value;
443 }
444
445 return 0;
446 }
447
448
449 /**
450 * tgafb_blank - Optional function. Blanks the display.
451 * @blank_mode: the blank mode we want.
452 * @info: frame buffer structure that represents a single frame buffer
453 */
454 static int
455 tgafb_blank(int blank, struct fb_info *info)
456 {
457 struct tga_par *par = (struct tga_par *) info->par;
458 u32 vhcr, vvcr, vvvr;
459 unsigned long flags;
460
461 local_irq_save(flags);
462
463 vhcr = TGA_READ_REG(par, TGA_HORIZ_REG);
464 vvcr = TGA_READ_REG(par, TGA_VERT_REG);
465 vvvr = TGA_READ_REG(par, TGA_VALID_REG);
466 vvvr &= ~(TGA_VALID_VIDEO | TGA_VALID_BLANK);
467
468 switch (blank) {
469 case FB_BLANK_UNBLANK: /* Unblanking */
470 if (par->vesa_blanked) {
471 TGA_WRITE_REG(par, vhcr & 0xbfffffff, TGA_HORIZ_REG);
472 TGA_WRITE_REG(par, vvcr & 0xbfffffff, TGA_VERT_REG);
473 par->vesa_blanked = 0;
474 }
475 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO, TGA_VALID_REG);
476 break;
477
478 case FB_BLANK_NORMAL: /* Normal blanking */
479 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO | TGA_VALID_BLANK,
480 TGA_VALID_REG);
481 break;
482
483 case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
484 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
485 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
486 par->vesa_blanked = 1;
487 break;
488
489 case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
490 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
491 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
492 par->vesa_blanked = 1;
493 break;
494
495 case FB_BLANK_POWERDOWN: /* Poweroff */
496 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
497 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
498 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
499 par->vesa_blanked = 1;
500 break;
501 }
502
503 local_irq_restore(flags);
504 return 0;
505 }
506
507
508 /*
509 * Acceleration.
510 */
511
512 /**
513 * tgafb_imageblit - REQUIRED function. Can use generic routines if
514 * non acclerated hardware and packed pixel based.
515 * Copies a image from system memory to the screen.
516 *
517 * @info: frame buffer structure that represents a single frame buffer
518 * @image: structure defining the image.
519 */
520 static void
521 tgafb_imageblit(struct fb_info *info, const struct fb_image *image)
522 {
523 static unsigned char const bitrev[256] = {
524 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
525 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
526 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
527 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
528 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
529 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
530 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
531 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
532 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
533 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
534 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
535 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
536 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
537 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
538 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
539 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
540 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
541 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
542 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
543 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
544 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
545 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
546 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
547 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
548 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
549 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
550 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
551 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
552 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
553 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
554 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
555 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff
556 };
557
558 struct tga_par *par = (struct tga_par *) info->par;
559 u32 fgcolor, bgcolor, dx, dy, width, height, vxres, vyres, pixelmask;
560 unsigned long rincr, line_length, shift, pos, is8bpp;
561 unsigned long i, j;
562 const unsigned char *data;
563 void __iomem *regs_base;
564 void __iomem *fb_base;
565
566 dx = image->dx;
567 dy = image->dy;
568 width = image->width;
569 height = image->height;
570 vxres = info->var.xres_virtual;
571 vyres = info->var.yres_virtual;
572 line_length = info->fix.line_length;
573 rincr = (width + 7) / 8;
574
575 /* Crop the image to the screen. */
576 if (dx > vxres || dy > vyres)
577 return;
578 if (dx + width > vxres)
579 width = vxres - dx;
580 if (dy + height > vyres)
581 height = vyres - dy;
582
583 /* For copies that aren't pixel expansion, there's little we
584 can do better than the generic code. */
585 /* ??? There is a DMA write mode; I wonder if that could be
586 made to pull the data from the image buffer... */
587 if (image->depth > 1) {
588 cfb_imageblit(info, image);
589 return;
590 }
591
592 regs_base = par->tga_regs_base;
593 fb_base = par->tga_fb_base;
594 is8bpp = info->var.bits_per_pixel == 8;
595
596 /* Expand the color values to fill 32-bits. */
597 /* ??? Would be nice to notice colour changes elsewhere, so
598 that we can do this only when necessary. */
599 fgcolor = image->fg_color;
600 bgcolor = image->bg_color;
601 if (is8bpp) {
602 fgcolor |= fgcolor << 8;
603 fgcolor |= fgcolor << 16;
604 bgcolor |= bgcolor << 8;
605 bgcolor |= bgcolor << 16;
606 } else {
607 if (fgcolor < 16)
608 fgcolor = ((u32 *)info->pseudo_palette)[fgcolor];
609 if (bgcolor < 16)
610 bgcolor = ((u32 *)info->pseudo_palette)[bgcolor];
611 }
612 __raw_writel(fgcolor, regs_base + TGA_FOREGROUND_REG);
613 __raw_writel(bgcolor, regs_base + TGA_BACKGROUND_REG);
614
615 /* Acquire proper alignment; set up the PIXELMASK register
616 so that we only write the proper character cell. */
617 pos = dy * line_length;
618 if (is8bpp) {
619 pos += dx;
620 shift = pos & 3;
621 pos &= -4;
622 } else {
623 pos += dx * 4;
624 shift = (pos & 7) >> 2;
625 pos &= -8;
626 }
627
628 data = (const unsigned char *) image->data;
629
630 /* Enable opaque stipple mode. */
631 __raw_writel((is8bpp
632 ? TGA_MODE_SBM_8BPP | TGA_MODE_OPAQUE_STIPPLE
633 : TGA_MODE_SBM_24BPP | TGA_MODE_OPAQUE_STIPPLE),
634 regs_base + TGA_MODE_REG);
635
636 if (width + shift <= 32) {
637 unsigned long bwidth;
638
639 /* Handle common case of imaging a single character, in
640 a font less than 32 pixels wide. */
641
642 pixelmask = (1 << width) - 1;
643 pixelmask <<= shift;
644 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
645 wmb();
646
647 bwidth = (width + 7) / 8;
648
649 for (i = 0; i < height; ++i) {
650 u32 mask = 0;
651
652 /* The image data is bit big endian; we need
653 little endian. */
654 for (j = 0; j < bwidth; ++j)
655 mask |= bitrev[data[j]] << (j * 8);
656
657 __raw_writel(mask << shift, fb_base + pos);
658
659 pos += line_length;
660 data += rincr;
661 }
662 wmb();
663 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
664 } else if (shift == 0) {
665 unsigned long pos0 = pos;
666 const unsigned char *data0 = data;
667 unsigned long bincr = (is8bpp ? 8 : 8*4);
668 unsigned long bwidth;
669
670 /* Handle another common case in which accel_putcs
671 generates a large bitmap, which happens to be aligned.
672 Allow the tail to be misaligned. This case is
673 interesting because we've not got to hold partial
674 bytes across the words being written. */
675
676 wmb();
677
678 bwidth = (width / 8) & -4;
679 for (i = 0; i < height; ++i) {
680 for (j = 0; j < bwidth; j += 4) {
681 u32 mask = 0;
682 mask |= bitrev[data[j+0]] << (0 * 8);
683 mask |= bitrev[data[j+1]] << (1 * 8);
684 mask |= bitrev[data[j+2]] << (2 * 8);
685 mask |= bitrev[data[j+3]] << (3 * 8);
686 __raw_writel(mask, fb_base + pos + j*bincr);
687 }
688 pos += line_length;
689 data += rincr;
690 }
691 wmb();
692
693 pixelmask = (1ul << (width & 31)) - 1;
694 if (pixelmask) {
695 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
696 wmb();
697
698 pos = pos0 + bwidth*bincr;
699 data = data0 + bwidth;
700 bwidth = ((width & 31) + 7) / 8;
701
702 for (i = 0; i < height; ++i) {
703 u32 mask = 0;
704 for (j = 0; j < bwidth; ++j)
705 mask |= bitrev[data[j]] << (j * 8);
706 __raw_writel(mask, fb_base + pos);
707 pos += line_length;
708 data += rincr;
709 }
710 wmb();
711 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
712 }
713 } else {
714 unsigned long pos0 = pos;
715 const unsigned char *data0 = data;
716 unsigned long bincr = (is8bpp ? 8 : 8*4);
717 unsigned long bwidth;
718
719 /* Finally, handle the generic case of misaligned start.
720 Here we split the write into 16-bit spans. This allows
721 us to use only one pixel mask, instead of four as would
722 be required by writing 24-bit spans. */
723
724 pixelmask = 0xffff << shift;
725 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
726 wmb();
727
728 bwidth = (width / 8) & -2;
729 for (i = 0; i < height; ++i) {
730 for (j = 0; j < bwidth; j += 2) {
731 u32 mask = 0;
732 mask |= bitrev[data[j+0]] << (0 * 8);
733 mask |= bitrev[data[j+1]] << (1 * 8);
734 mask <<= shift;
735 __raw_writel(mask, fb_base + pos + j*bincr);
736 }
737 pos += line_length;
738 data += rincr;
739 }
740 wmb();
741
742 pixelmask = ((1ul << (width & 15)) - 1) << shift;
743 if (pixelmask) {
744 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
745 wmb();
746
747 pos = pos0 + bwidth*bincr;
748 data = data0 + bwidth;
749 bwidth = (width & 15) > 8;
750
751 for (i = 0; i < height; ++i) {
752 u32 mask = bitrev[data[0]];
753 if (bwidth)
754 mask |= bitrev[data[1]] << 8;
755 mask <<= shift;
756 __raw_writel(mask, fb_base + pos);
757 pos += line_length;
758 data += rincr;
759 }
760 wmb();
761 }
762 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
763 }
764
765 /* Disable opaque stipple mode. */
766 __raw_writel((is8bpp
767 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
768 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
769 regs_base + TGA_MODE_REG);
770 }
771
772 /**
773 * tgafb_fillrect - REQUIRED function. Can use generic routines if
774 * non acclerated hardware and packed pixel based.
775 * Draws a rectangle on the screen.
776 *
777 * @info: frame buffer structure that represents a single frame buffer
778 * @rect: structure defining the rectagle and operation.
779 */
780 static void
781 tgafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
782 {
783 struct tga_par *par = (struct tga_par *) info->par;
784 int is8bpp = info->var.bits_per_pixel == 8;
785 u32 dx, dy, width, height, vxres, vyres, color;
786 unsigned long pos, align, line_length, i, j;
787 void __iomem *regs_base;
788 void __iomem *fb_base;
789
790 dx = rect->dx;
791 dy = rect->dy;
792 width = rect->width;
793 height = rect->height;
794 vxres = info->var.xres_virtual;
795 vyres = info->var.yres_virtual;
796 line_length = info->fix.line_length;
797 regs_base = par->tga_regs_base;
798 fb_base = par->tga_fb_base;
799
800 /* Crop the rectangle to the screen. */
801 if (dx > vxres || dy > vyres || !width || !height)
802 return;
803 if (dx + width > vxres)
804 width = vxres - dx;
805 if (dy + height > vyres)
806 height = vyres - dy;
807
808 pos = dy * line_length + dx * (is8bpp ? 1 : 4);
809
810 /* ??? We could implement ROP_XOR with opaque fill mode
811 and a RasterOp setting of GXxor, but as far as I can
812 tell, this mode is not actually used in the kernel.
813 Thus I am ignoring it for now. */
814 if (rect->rop != ROP_COPY) {
815 cfb_fillrect(info, rect);
816 return;
817 }
818
819 /* Expand the color value to fill 8 pixels. */
820 color = rect->color;
821 if (is8bpp) {
822 color |= color << 8;
823 color |= color << 16;
824 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
825 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
826 } else {
827 if (color < 16)
828 color = ((u32 *)info->pseudo_palette)[color];
829 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
830 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
831 __raw_writel(color, regs_base + TGA_BLOCK_COLOR2_REG);
832 __raw_writel(color, regs_base + TGA_BLOCK_COLOR3_REG);
833 __raw_writel(color, regs_base + TGA_BLOCK_COLOR4_REG);
834 __raw_writel(color, regs_base + TGA_BLOCK_COLOR5_REG);
835 __raw_writel(color, regs_base + TGA_BLOCK_COLOR6_REG);
836 __raw_writel(color, regs_base + TGA_BLOCK_COLOR7_REG);
837 }
838
839 /* The DATA register holds the fill mask for block fill mode.
840 Since we're not stippling, this is all ones. */
841 __raw_writel(0xffffffff, regs_base + TGA_DATA_REG);
842
843 /* Enable block fill mode. */
844 __raw_writel((is8bpp
845 ? TGA_MODE_SBM_8BPP | TGA_MODE_BLOCK_FILL
846 : TGA_MODE_SBM_24BPP | TGA_MODE_BLOCK_FILL),
847 regs_base + TGA_MODE_REG);
848 wmb();
849
850 /* We can fill 2k pixels per operation. Notice blocks that fit
851 the width of the screen so that we can take advantage of this
852 and fill more than one line per write. */
853 if (width == line_length)
854 width *= height, height = 1;
855
856 /* The write into the frame buffer must be aligned to 4 bytes,
857 but we are allowed to encode the offset within the word in
858 the data word written. */
859 align = (pos & 3) << 16;
860 pos &= -4;
861
862 if (width <= 2048) {
863 u32 data;
864
865 data = (width - 1) | align;
866
867 for (i = 0; i < height; ++i) {
868 __raw_writel(data, fb_base + pos);
869 pos += line_length;
870 }
871 } else {
872 unsigned long Bpp = (is8bpp ? 1 : 4);
873 unsigned long nwidth = width & -2048;
874 u32 fdata, ldata;
875
876 fdata = (2048 - 1) | align;
877 ldata = ((width & 2047) - 1) | align;
878
879 for (i = 0; i < height; ++i) {
880 for (j = 0; j < nwidth; j += 2048)
881 __raw_writel(fdata, fb_base + pos + j*Bpp);
882 if (j < width)
883 __raw_writel(ldata, fb_base + pos + j*Bpp);
884 pos += line_length;
885 }
886 }
887 wmb();
888
889 /* Disable block fill mode. */
890 __raw_writel((is8bpp
891 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
892 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
893 regs_base + TGA_MODE_REG);
894 }
895
896 /**
897 * tgafb_copyarea - REQUIRED function. Can use generic routines if
898 * non acclerated hardware and packed pixel based.
899 * Copies on area of the screen to another area.
900 *
901 * @info: frame buffer structure that represents a single frame buffer
902 * @area: structure defining the source and destination.
903 */
904
905 /* Handle the special case of copying entire lines, e.g. during scrolling.
906 We can avoid a lot of needless computation in this case. In the 8bpp
907 case we need to use the COPY64 registers instead of mask writes into
908 the frame buffer to achieve maximum performance. */
909
910 static inline void
911 copyarea_line_8bpp(struct fb_info *info, u32 dy, u32 sy,
912 u32 height, u32 width)
913 {
914 struct tga_par *par = (struct tga_par *) info->par;
915 void __iomem *tga_regs = par->tga_regs_base;
916 unsigned long dpos, spos, i, n64;
917
918 /* Set up the MODE and PIXELSHIFT registers. */
919 __raw_writel(TGA_MODE_SBM_8BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
920 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
921 wmb();
922
923 n64 = (height * width) / 64;
924
925 if (dy < sy) {
926 spos = (sy + height) * width;
927 dpos = (dy + height) * width;
928
929 for (i = 0; i < n64; ++i) {
930 spos -= 64;
931 dpos -= 64;
932 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
933 wmb();
934 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
935 wmb();
936 }
937 } else {
938 spos = sy * width;
939 dpos = dy * width;
940
941 for (i = 0; i < n64; ++i) {
942 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
943 wmb();
944 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
945 wmb();
946 spos += 64;
947 dpos += 64;
948 }
949 }
950
951 /* Reset the MODE register to normal. */
952 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
953 }
954
955 static inline void
956 copyarea_line_32bpp(struct fb_info *info, u32 dy, u32 sy,
957 u32 height, u32 width)
958 {
959 struct tga_par *par = (struct tga_par *) info->par;
960 void __iomem *tga_regs = par->tga_regs_base;
961 void __iomem *tga_fb = par->tga_fb_base;
962 void __iomem *src;
963 void __iomem *dst;
964 unsigned long i, n16;
965
966 /* Set up the MODE and PIXELSHIFT registers. */
967 __raw_writel(TGA_MODE_SBM_24BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
968 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
969 wmb();
970
971 n16 = (height * width) / 16;
972
973 if (dy < sy) {
974 src = tga_fb + (sy + height) * width * 4;
975 dst = tga_fb + (dy + height) * width * 4;
976
977 for (i = 0; i < n16; ++i) {
978 src -= 64;
979 dst -= 64;
980 __raw_writel(0xffff, src);
981 wmb();
982 __raw_writel(0xffff, dst);
983 wmb();
984 }
985 } else {
986 src = tga_fb + sy * width * 4;
987 dst = tga_fb + dy * width * 4;
988
989 for (i = 0; i < n16; ++i) {
990 __raw_writel(0xffff, src);
991 wmb();
992 __raw_writel(0xffff, dst);
993 wmb();
994 src += 64;
995 dst += 64;
996 }
997 }
998
999 /* Reset the MODE register to normal. */
1000 __raw_writel(TGA_MODE_SBM_24BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1001 }
1002
1003 /* The general case of forward copy in 8bpp mode. */
1004 static inline void
1005 copyarea_foreward_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy,
1006 u32 height, u32 width, u32 line_length)
1007 {
1008 struct tga_par *par = (struct tga_par *) info->par;
1009 unsigned long i, copied, left;
1010 unsigned long dpos, spos, dalign, salign, yincr;
1011 u32 smask_first, dmask_first, dmask_last;
1012 int pixel_shift, need_prime, need_second;
1013 unsigned long n64, n32, xincr_first;
1014 void __iomem *tga_regs;
1015 void __iomem *tga_fb;
1016
1017 yincr = line_length;
1018 if (dy > sy) {
1019 dy += height - 1;
1020 sy += height - 1;
1021 yincr = -yincr;
1022 }
1023
1024 /* Compute the offsets and alignments in the frame buffer.
1025 More than anything else, these control how we do copies. */
1026 dpos = dy * line_length + dx;
1027 spos = sy * line_length + sx;
1028 dalign = dpos & 7;
1029 salign = spos & 7;
1030 dpos &= -8;
1031 spos &= -8;
1032
1033 /* Compute the value for the PIXELSHIFT register. This controls
1034 both non-co-aligned source and destination and copy direction. */
1035 if (dalign >= salign)
1036 pixel_shift = dalign - salign;
1037 else
1038 pixel_shift = 8 - (salign - dalign);
1039
1040 /* Figure out if we need an additional priming step for the
1041 residue register. */
1042 need_prime = (salign > dalign);
1043 if (need_prime)
1044 dpos -= 8;
1045
1046 /* Begin by copying the leading unaligned destination. Copy enough
1047 to make the next destination address 32-byte aligned. */
1048 copied = 32 - (dalign + (dpos & 31));
1049 if (copied == 32)
1050 copied = 0;
1051 xincr_first = (copied + 7) & -8;
1052 smask_first = dmask_first = (1ul << copied) - 1;
1053 smask_first <<= salign;
1054 dmask_first <<= dalign + need_prime*8;
1055 if (need_prime && copied > 24)
1056 copied -= 8;
1057 left = width - copied;
1058
1059 /* Care for small copies. */
1060 if (copied > width) {
1061 u32 t;
1062 t = (1ul << width) - 1;
1063 t <<= dalign + need_prime*8;
1064 dmask_first &= t;
1065 left = 0;
1066 }
1067
1068 /* Attempt to use 64-byte copies. This is only possible if the
1069 source and destination are co-aligned at 64 bytes. */
1070 n64 = need_second = 0;
1071 if ((dpos & 63) == (spos & 63)
1072 && (height == 1 || line_length % 64 == 0)) {
1073 /* We may need a 32-byte copy to ensure 64 byte alignment. */
1074 need_second = (dpos + xincr_first) & 63;
1075 if ((need_second & 32) != need_second)
1076 printk(KERN_ERR "tgafb: need_second wrong\n");
1077 if (left >= need_second + 64) {
1078 left -= need_second;
1079 n64 = left / 64;
1080 left %= 64;
1081 } else
1082 need_second = 0;
1083 }
1084
1085 /* Copy trailing full 32-byte sections. This will be the main
1086 loop if the 64 byte loop can't be used. */
1087 n32 = left / 32;
1088 left %= 32;
1089
1090 /* Copy the trailing unaligned destination. */
1091 dmask_last = (1ul << left) - 1;
1092
1093 tga_regs = par->tga_regs_base;
1094 tga_fb = par->tga_fb_base;
1095
1096 /* Set up the MODE and PIXELSHIFT registers. */
1097 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1098 __raw_writel(pixel_shift, tga_regs+TGA_PIXELSHIFT_REG);
1099 wmb();
1100
1101 for (i = 0; i < height; ++i) {
1102 unsigned long j;
1103 void __iomem *sfb;
1104 void __iomem *dfb;
1105
1106 sfb = tga_fb + spos;
1107 dfb = tga_fb + dpos;
1108 if (dmask_first) {
1109 __raw_writel(smask_first, sfb);
1110 wmb();
1111 __raw_writel(dmask_first, dfb);
1112 wmb();
1113 sfb += xincr_first;
1114 dfb += xincr_first;
1115 }
1116
1117 if (need_second) {
1118 __raw_writel(0xffffffff, sfb);
1119 wmb();
1120 __raw_writel(0xffffffff, dfb);
1121 wmb();
1122 sfb += 32;
1123 dfb += 32;
1124 }
1125
1126 if (n64 && (((unsigned long)sfb | (unsigned long)dfb) & 63))
1127 printk(KERN_ERR
1128 "tgafb: misaligned copy64 (s:%p, d:%p)\n",
1129 sfb, dfb);
1130
1131 for (j = 0; j < n64; ++j) {
1132 __raw_writel(sfb - tga_fb, tga_regs+TGA_COPY64_SRC);
1133 wmb();
1134 __raw_writel(dfb - tga_fb, tga_regs+TGA_COPY64_DST);
1135 wmb();
1136 sfb += 64;
1137 dfb += 64;
1138 }
1139
1140 for (j = 0; j < n32; ++j) {
1141 __raw_writel(0xffffffff, sfb);
1142 wmb();
1143 __raw_writel(0xffffffff, dfb);
1144 wmb();
1145 sfb += 32;
1146 dfb += 32;
1147 }
1148
1149 if (dmask_last) {
1150 __raw_writel(0xffffffff, sfb);
1151 wmb();
1152 __raw_writel(dmask_last, dfb);
1153 wmb();
1154 }
1155
1156 spos += yincr;
1157 dpos += yincr;
1158 }
1159
1160 /* Reset the MODE register to normal. */
1161 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1162 }
1163
1164 /* The (almost) general case of backward copy in 8bpp mode. */
1165 static inline void
1166 copyarea_backward_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy,
1167 u32 height, u32 width, u32 line_length,
1168 const struct fb_copyarea *area)
1169 {
1170 struct tga_par *par = (struct tga_par *) info->par;
1171 unsigned long i, left, yincr;
1172 unsigned long depos, sepos, dealign, sealign;
1173 u32 mask_first, mask_last;
1174 unsigned long n32;
1175 void __iomem *tga_regs;
1176 void __iomem *tga_fb;
1177
1178 yincr = line_length;
1179 if (dy > sy) {
1180 dy += height - 1;
1181 sy += height - 1;
1182 yincr = -yincr;
1183 }
1184
1185 /* Compute the offsets and alignments in the frame buffer.
1186 More than anything else, these control how we do copies. */
1187 depos = dy * line_length + dx + width;
1188 sepos = sy * line_length + sx + width;
1189 dealign = depos & 7;
1190 sealign = sepos & 7;
1191
1192 /* ??? The documentation appears to be incorrect (or very
1193 misleading) wrt how pixel shifting works in backward copy
1194 mode, i.e. when PIXELSHIFT is negative. I give up for now.
1195 Do handle the common case of co-aligned backward copies,
1196 but frob everything else back on generic code. */
1197 if (dealign != sealign) {
1198 cfb_copyarea(info, area);
1199 return;
1200 }
1201
1202 /* We begin the copy with the trailing pixels of the
1203 unaligned destination. */
1204 mask_first = (1ul << dealign) - 1;
1205 left = width - dealign;
1206
1207 /* Care for small copies. */
1208 if (dealign > width) {
1209 mask_first ^= (1ul << (dealign - width)) - 1;
1210 left = 0;
1211 }
1212
1213 /* Next copy full words at a time. */
1214 n32 = left / 32;
1215 left %= 32;
1216
1217 /* Finally copy the unaligned head of the span. */
1218 mask_last = -1 << (32 - left);
1219
1220 tga_regs = par->tga_regs_base;
1221 tga_fb = par->tga_fb_base;
1222
1223 /* Set up the MODE and PIXELSHIFT registers. */
1224 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1225 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
1226 wmb();
1227
1228 for (i = 0; i < height; ++i) {
1229 unsigned long j;
1230 void __iomem *sfb;
1231 void __iomem *dfb;
1232
1233 sfb = tga_fb + sepos;
1234 dfb = tga_fb + depos;
1235 if (mask_first) {
1236 __raw_writel(mask_first, sfb);
1237 wmb();
1238 __raw_writel(mask_first, dfb);
1239 wmb();
1240 }
1241
1242 for (j = 0; j < n32; ++j) {
1243 sfb -= 32;
1244 dfb -= 32;
1245 __raw_writel(0xffffffff, sfb);
1246 wmb();
1247 __raw_writel(0xffffffff, dfb);
1248 wmb();
1249 }
1250
1251 if (mask_last) {
1252 sfb -= 32;
1253 dfb -= 32;
1254 __raw_writel(mask_last, sfb);
1255 wmb();
1256 __raw_writel(mask_last, dfb);
1257 wmb();
1258 }
1259
1260 sepos += yincr;
1261 depos += yincr;
1262 }
1263
1264 /* Reset the MODE register to normal. */
1265 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1266 }
1267
1268 static void
1269 tgafb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
1270 {
1271 unsigned long dx, dy, width, height, sx, sy, vxres, vyres;
1272 unsigned long line_length, bpp;
1273
1274 dx = area->dx;
1275 dy = area->dy;
1276 width = area->width;
1277 height = area->height;
1278 sx = area->sx;
1279 sy = area->sy;
1280 vxres = info->var.xres_virtual;
1281 vyres = info->var.yres_virtual;
1282 line_length = info->fix.line_length;
1283
1284 /* The top left corners must be in the virtual screen. */
1285 if (dx > vxres || sx > vxres || dy > vyres || sy > vyres)
1286 return;
1287
1288 /* Clip the destination. */
1289 if (dx + width > vxres)
1290 width = vxres - dx;
1291 if (dy + height > vyres)
1292 height = vyres - dy;
1293
1294 /* The source must be completely inside the virtual screen. */
1295 if (sx + width > vxres || sy + height > vyres)
1296 return;
1297
1298 bpp = info->var.bits_per_pixel;
1299
1300 /* Detect copies of the entire line. */
1301 if (width * (bpp >> 3) == line_length) {
1302 if (bpp == 8)
1303 copyarea_line_8bpp(info, dy, sy, height, width);
1304 else
1305 copyarea_line_32bpp(info, dy, sy, height, width);
1306 }
1307
1308 /* ??? The documentation is unclear to me exactly how the pixelshift
1309 register works in 32bpp mode. Since I don't have hardware to test,
1310 give up for now and fall back on the generic routines. */
1311 else if (bpp == 32)
1312 cfb_copyarea(info, area);
1313
1314 /* Detect overlapping source and destination that requires
1315 a backward copy. */
1316 else if (dy == sy && dx > sx && dx < sx + width)
1317 copyarea_backward_8bpp(info, dx, dy, sx, sy, height,
1318 width, line_length, area);
1319 else
1320 copyarea_foreward_8bpp(info, dx, dy, sx, sy, height,
1321 width, line_length);
1322 }
1323
1324
1325 /*
1326 * Initialisation
1327 */
1328
1329 static void
1330 tgafb_init_fix(struct fb_info *info)
1331 {
1332 struct tga_par *par = (struct tga_par *)info->par;
1333 u8 tga_type = par->tga_type;
1334 const char *tga_type_name;
1335
1336 switch (tga_type) {
1337 case TGA_TYPE_8PLANE:
1338 tga_type_name = "Digital ZLXp-E1";
1339 break;
1340 case TGA_TYPE_24PLANE:
1341 tga_type_name = "Digital ZLXp-E2";
1342 break;
1343 case TGA_TYPE_24PLUSZ:
1344 tga_type_name = "Digital ZLXp-E3";
1345 break;
1346 default:
1347 tga_type_name = "Unknown";
1348 break;
1349 }
1350
1351 strlcpy(info->fix.id, tga_type_name, sizeof(info->fix.id));
1352
1353 info->fix.type = FB_TYPE_PACKED_PIXELS;
1354 info->fix.type_aux = 0;
1355 info->fix.visual = (tga_type == TGA_TYPE_8PLANE
1356 ? FB_VISUAL_PSEUDOCOLOR
1357 : FB_VISUAL_TRUECOLOR);
1358
1359 info->fix.line_length = par->xres * (par->bits_per_pixel >> 3);
1360 info->fix.smem_start = (size_t) par->tga_fb_base;
1361 info->fix.smem_len = info->fix.line_length * par->yres;
1362 info->fix.mmio_start = (size_t) par->tga_regs_base;
1363 info->fix.mmio_len = 512;
1364
1365 info->fix.xpanstep = 0;
1366 info->fix.ypanstep = 0;
1367 info->fix.ywrapstep = 0;
1368
1369 info->fix.accel = FB_ACCEL_DEC_TGA;
1370 }
1371
1372 static __devinit int
1373 tgafb_pci_register(struct pci_dev *pdev, const struct pci_device_id *ent)
1374 {
1375 static unsigned int const fb_offset_presets[4] = {
1376 TGA_8PLANE_FB_OFFSET,
1377 TGA_24PLANE_FB_OFFSET,
1378 0xffffffff,
1379 TGA_24PLUSZ_FB_OFFSET
1380 };
1381
1382 struct all_info {
1383 struct fb_info info;
1384 struct tga_par par;
1385 u32 pseudo_palette[16];
1386 } *all;
1387
1388 void __iomem *mem_base;
1389 unsigned long bar0_start, bar0_len;
1390 u8 tga_type;
1391 int ret;
1392
1393 /* Enable device in PCI config. */
1394 if (pci_enable_device(pdev)) {
1395 printk(KERN_ERR "tgafb: Cannot enable PCI device\n");
1396 return -ENODEV;
1397 }
1398
1399 /* Allocate the fb and par structures. */
1400 all = kmalloc(sizeof(*all), GFP_KERNEL);
1401 if (!all) {
1402 printk(KERN_ERR "tgafb: Cannot allocate memory\n");
1403 return -ENOMEM;
1404 }
1405 memset(all, 0, sizeof(*all));
1406 pci_set_drvdata(pdev, all);
1407
1408 /* Request the mem regions. */
1409 bar0_start = pci_resource_start(pdev, 0);
1410 bar0_len = pci_resource_len(pdev, 0);
1411 ret = -ENODEV;
1412 if (!request_mem_region (bar0_start, bar0_len, "tgafb")) {
1413 printk(KERN_ERR "tgafb: cannot reserve FB region\n");
1414 goto err0;
1415 }
1416
1417 /* Map the framebuffer. */
1418 mem_base = ioremap(bar0_start, bar0_len);
1419 if (!mem_base) {
1420 printk(KERN_ERR "tgafb: Cannot map MMIO\n");
1421 goto err1;
1422 }
1423
1424 /* Grab info about the card. */
1425 tga_type = (readl(mem_base) >> 12) & 0x0f;
1426 all->par.pdev = pdev;
1427 all->par.tga_mem_base = mem_base;
1428 all->par.tga_fb_base = mem_base + fb_offset_presets[tga_type];
1429 all->par.tga_regs_base = mem_base + TGA_REGS_OFFSET;
1430 all->par.tga_type = tga_type;
1431 pci_read_config_byte(pdev, PCI_REVISION_ID, &all->par.tga_chip_rev);
1432
1433 /* Setup framebuffer. */
1434 all->info.flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA |
1435 FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT;
1436 all->info.fbops = &tgafb_ops;
1437 all->info.screen_base = all->par.tga_fb_base;
1438 all->info.par = &all->par;
1439 all->info.pseudo_palette = all->pseudo_palette;
1440
1441 /* This should give a reasonable default video mode. */
1442
1443 ret = fb_find_mode(&all->info.var, &all->info, mode_option,
1444 NULL, 0, NULL,
1445 tga_type == TGA_TYPE_8PLANE ? 8 : 32);
1446 if (ret == 0 || ret == 4) {
1447 printk(KERN_ERR "tgafb: Could not find valid video mode\n");
1448 ret = -EINVAL;
1449 goto err1;
1450 }
1451
1452 if (fb_alloc_cmap(&all->info.cmap, 256, 0)) {
1453 printk(KERN_ERR "tgafb: Could not allocate color map\n");
1454 ret = -ENOMEM;
1455 goto err1;
1456 }
1457
1458 tgafb_set_par(&all->info);
1459 tgafb_init_fix(&all->info);
1460
1461 all->info.device = &pdev->dev;
1462 if (register_framebuffer(&all->info) < 0) {
1463 printk(KERN_ERR "tgafb: Could not register framebuffer\n");
1464 ret = -EINVAL;
1465 goto err1;
1466 }
1467
1468 printk(KERN_INFO "tgafb: DC21030 [TGA] detected, rev=0x%02x\n",
1469 all->par.tga_chip_rev);
1470 printk(KERN_INFO "tgafb: at PCI bus %d, device %d, function %d\n",
1471 pdev->bus->number, PCI_SLOT(pdev->devfn),
1472 PCI_FUNC(pdev->devfn));
1473 printk(KERN_INFO "fb%d: %s frame buffer device at 0x%lx\n",
1474 all->info.node, all->info.fix.id, bar0_start);
1475
1476 return 0;
1477
1478 err1:
1479 release_mem_region(bar0_start, bar0_len);
1480 err0:
1481 kfree(all);
1482 return ret;
1483 }
1484
1485 static void __exit
1486 tgafb_pci_unregister(struct pci_dev *pdev)
1487 {
1488 struct fb_info *info = pci_get_drvdata(pdev);
1489 struct tga_par *par = info->par;
1490
1491 if (!info)
1492 return;
1493 unregister_framebuffer(info);
1494 iounmap(par->tga_mem_base);
1495 release_mem_region(pci_resource_start(pdev, 0),
1496 pci_resource_len(pdev, 0));
1497 kfree(info);
1498 }
1499
1500 #ifdef MODULE
1501 static void __exit
1502 tgafb_exit(void)
1503 {
1504 pci_unregister_driver(&tgafb_driver);
1505 }
1506 #endif /* MODULE */
1507
1508 #ifndef MODULE
1509 int __init
1510 tgafb_setup(char *arg)
1511 {
1512 char *this_opt;
1513
1514 if (arg && *arg) {
1515 while ((this_opt = strsep(&arg, ","))) {
1516 if (!*this_opt)
1517 continue;
1518 if (!strncmp(this_opt, "mode:", 5))
1519 mode_option = this_opt+5;
1520 else
1521 printk(KERN_ERR
1522 "tgafb: unknown parameter %s\n",
1523 this_opt);
1524 }
1525 }
1526
1527 return 0;
1528 }
1529 #endif /* !MODULE */
1530
1531 int __init
1532 tgafb_init(void)
1533 {
1534 #ifndef MODULE
1535 char *option = NULL;
1536
1537 if (fb_get_options("tgafb", &option))
1538 return -ENODEV;
1539 tgafb_setup(option);
1540 #endif
1541 return pci_register_driver(&tgafb_driver);
1542 }
1543
1544 /*
1545 * Modularisation
1546 */
1547
1548 module_init(tgafb_init);
1549
1550 #ifdef MODULE
1551 module_exit(tgafb_exit);
1552 #endif
1553
1554 MODULE_DESCRIPTION("framebuffer driver for TGA chipset");
1555 MODULE_LICENSE("GPL");
Support for the Chinese Samsung S3C2440 based development boards