drivers/pci/hotplug/pciehp_hpc.c

   1 /*
   2  * PCI Express PCI Hot Plug Driver
   3  *
   4  * Copyright (C) 1995,2001 Compaq Computer Corporation
   5  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
   6  * Copyright (C) 2001 IBM Corp.
   7  * Copyright (C) 2003-2004 Intel Corporation
   8  *
   9  * All rights reserved.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  19  * NON INFRINGEMENT.  See the GNU General Public License for more
  20  * details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  *
  26  * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
  27  *
  28  */
  29
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/types.h>
  33 #include <linux/signal.h>
  34 #include <linux/jiffies.h>
  35 #include <linux/timer.h>
  36 #include <linux/pci.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/time.h>
  39
  40 #include "../pci.h"
  41 #include "pciehp.h"
  42
  43 static atomic_t pciehp_num_controllers = ATOMIC_INIT(0);
  44
  45 struct ctrl_reg {
  46         u8 cap_id;
  47         u8 nxt_ptr;
  48         u16 cap_reg;
  49         u32 dev_cap;
  50         u16 dev_ctrl;
  51         u16 dev_status;
  52         u32 lnk_cap;
  53         u16 lnk_ctrl;
  54         u16 lnk_status;
  55         u32 slot_cap;
  56         u16 slot_ctrl;
  57         u16 slot_status;
  58         u16 root_ctrl;
  59         u16 rsvp;
  60         u32 root_status;
  61 } __attribute__ ((packed));
  62
  63 /* offsets to the controller registers based on the above structure layout */
  64 enum ctrl_offsets {
  65         PCIECAPID       =       offsetof(struct ctrl_reg, cap_id),
  66         NXTCAPPTR       =       offsetof(struct ctrl_reg, nxt_ptr),
  67         CAPREG          =       offsetof(struct ctrl_reg, cap_reg),
  68         DEVCAP          =       offsetof(struct ctrl_reg, dev_cap),
  69         DEVCTRL         =       offsetof(struct ctrl_reg, dev_ctrl),
  70         DEVSTATUS       =       offsetof(struct ctrl_reg, dev_status),
  71         LNKCAP          =       offsetof(struct ctrl_reg, lnk_cap),
  72         LNKCTRL         =       offsetof(struct ctrl_reg, lnk_ctrl),
  73         LNKSTATUS       =       offsetof(struct ctrl_reg, lnk_status),
  74         SLOTCAP         =       offsetof(struct ctrl_reg, slot_cap),
  75         SLOTCTRL        =       offsetof(struct ctrl_reg, slot_ctrl),
  76         SLOTSTATUS      =       offsetof(struct ctrl_reg, slot_status),
  77         ROOTCTRL        =       offsetof(struct ctrl_reg, root_ctrl),
  78         ROOTSTATUS      =       offsetof(struct ctrl_reg, root_status),
  79 };
  80
  81 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
  82 {
  83         struct pci_dev *dev = ctrl->pci_dev;
  84         return pci_read_config_word(dev, ctrl->cap_base + reg, value);
  85 }
  86
  87 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
  88 {
  89         struct pci_dev *dev = ctrl->pci_dev;
  90         return pci_read_config_dword(dev, ctrl->cap_base + reg, value);
  91 }
  92
  93 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
  94 {
  95         struct pci_dev *dev = ctrl->pci_dev;
  96         return pci_write_config_word(dev, ctrl->cap_base + reg, value);
  97 }
  98
  99 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
 100 {
 101         struct pci_dev *dev = ctrl->pci_dev;
 102         return pci_write_config_dword(dev, ctrl->cap_base + reg, value);
 103 }
 104
 105 /* Field definitions in PCI Express Capabilities Register */
 106 #define CAP_VER                 0x000F
 107 #define DEV_PORT_TYPE           0x00F0
 108 #define SLOT_IMPL               0x0100
 109 #define MSG_NUM                 0x3E00
 110
 111 /* Device or Port Type */
 112 #define NAT_ENDPT               0x00
 113 #define LEG_ENDPT               0x01
 114 #define ROOT_PORT               0x04
 115 #define UP_STREAM               0x05
 116 #define DN_STREAM               0x06
 117 #define PCIE_PCI_BRDG           0x07
 118 #define PCI_PCIE_BRDG           0x10
 119
 120 /* Field definitions in Device Capabilities Register */
 121 #define DATTN_BUTTN_PRSN        0x1000
 122 #define DATTN_LED_PRSN          0x2000
 123 #define DPWR_LED_PRSN           0x4000
 124
 125 /* Field definitions in Link Capabilities Register */
 126 #define MAX_LNK_SPEED           0x000F
 127 #define MAX_LNK_WIDTH           0x03F0
 128
 129 /* Link Width Encoding */
 130 #define LNK_X1          0x01
 131 #define LNK_X2          0x02
 132 #define LNK_X4          0x04
 133 #define LNK_X8          0x08
 134 #define LNK_X12         0x0C
 135 #define LNK_X16         0x10
 136 #define LNK_X32         0x20
 137
 138 /*Field definitions of Link Status Register */
 139 #define LNK_SPEED       0x000F
 140 #define NEG_LINK_WD     0x03F0
 141 #define LNK_TRN_ERR     0x0400
 142 #define LNK_TRN         0x0800
 143 #define SLOT_CLK_CONF   0x1000
 144
 145 /* Field definitions in Slot Capabilities Register */
 146 #define ATTN_BUTTN_PRSN 0x00000001
 147 #define PWR_CTRL_PRSN   0x00000002
 148 #define MRL_SENS_PRSN   0x00000004
 149 #define ATTN_LED_PRSN   0x00000008
 150 #define PWR_LED_PRSN    0x00000010
 151 #define HP_SUPR_RM_SUP  0x00000020
 152 #define HP_CAP          0x00000040
 153 #define SLOT_PWR_VALUE  0x000003F8
 154 #define SLOT_PWR_LIMIT  0x00000C00
 155 #define PSN             0xFFF80000      /* PSN: Physical Slot Number */
 156
 157 /* Field definitions in Slot Control Register */
 158 #define ATTN_BUTTN_ENABLE               0x0001
 159 #define PWR_FAULT_DETECT_ENABLE         0x0002
 160 #define MRL_DETECT_ENABLE               0x0004
 161 #define PRSN_DETECT_ENABLE              0x0008
 162 #define CMD_CMPL_INTR_ENABLE            0x0010
 163 #define HP_INTR_ENABLE                  0x0020
 164 #define ATTN_LED_CTRL                   0x00C0
 165 #define PWR_LED_CTRL                    0x0300
 166 #define PWR_CTRL                        0x0400
 167 #define EMI_CTRL                        0x0800
 168
 169 /* Attention indicator and Power indicator states */
 170 #define LED_ON          0x01
 171 #define LED_BLINK       0x10
 172 #define LED_OFF         0x11
 173
 174 /* Power Control Command */
 175 #define POWER_ON        0
 176 #define POWER_OFF       0x0400
 177
 178 /* EMI Status defines */
 179 #define EMI_DISENGAGED  0
 180 #define EMI_ENGAGED     1
 181
 182 /* Field definitions in Slot Status Register */
 183 #define ATTN_BUTTN_PRESSED      0x0001
 184 #define PWR_FAULT_DETECTED      0x0002
 185 #define MRL_SENS_CHANGED        0x0004
 186 #define PRSN_DETECT_CHANGED     0x0008
 187 #define CMD_COMPLETED           0x0010
 188 #define MRL_STATE               0x0020
 189 #define PRSN_STATE              0x0040
 190 #define EMI_STATE               0x0080
 191 #define EMI_STATUS_BIT          7
 192
 193 static irqreturn_t pcie_isr(int irq, void *dev_id);
 194 static void start_int_poll_timer(struct controller *ctrl, int sec);
 195
 196 /* This is the interrupt polling timeout function. */
 197 static void int_poll_timeout(unsigned long data)
 198 {
 199         struct controller *ctrl = (struct controller *)data;
 200
 201         /* Poll for interrupt events.  regs == NULL => polling */
 202         pcie_isr(0, ctrl);
 203
 204         init_timer(&ctrl->poll_timer);
 205         if (!pciehp_poll_time)
 206                 pciehp_poll_time = 2; /* default polling interval is 2 sec */
 207
 208         start_int_poll_timer(ctrl, pciehp_poll_time);
 209 }
 210
 211 /* This function starts the interrupt polling timer. */
 212 static void start_int_poll_timer(struct controller *ctrl, int sec)
 213 {
 214         /* Clamp to sane value */
 215         if ((sec <= 0) || (sec > 60))
 216                 sec = 2;
 217
 218         ctrl->poll_timer.function = &int_poll_timeout;
 219         ctrl->poll_timer.data = (unsigned long)ctrl;
 220         ctrl->poll_timer.expires = jiffies + sec * HZ;
 221         add_timer(&ctrl->poll_timer);
 222 }
 223
 224 static inline int pciehp_request_irq(struct controller *ctrl)
 225 {
 226         int retval, irq = ctrl->pci_dev->irq;
 227
 228         /* Install interrupt polling timer. Start with 10 sec delay */
 229         if (pciehp_poll_mode) {
 230                 init_timer(&ctrl->poll_timer);
 231                 start_int_poll_timer(ctrl, 10);
 232                 return 0;
 233         }
 234
 235         /* Installs the interrupt handler */
 236         retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
 237         if (retval)
 238                 err("Cannot get irq %d for the hotplug controller\n", irq);
 239         return retval;
 240 }
 241
 242 static inline void pciehp_free_irq(struct controller *ctrl)
 243 {
 244         if (pciehp_poll_mode)
 245                 del_timer_sync(&ctrl->poll_timer);
 246         else
 247                 free_irq(ctrl->pci_dev->irq, ctrl);
 248 }
 249
 250 static inline int pcie_wait_cmd(struct controller *ctrl)
 251 {
 252         int retval = 0;
 253         unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
 254         unsigned long timeout = msecs_to_jiffies(msecs);
 255         int rc;
 256
 257         rc = wait_event_interruptible_timeout(ctrl->queue,
 258                                               !ctrl->cmd_busy, timeout);
 259         if (!rc)
 260                 dbg("Command not completed in 1000 msec\n");
 261         else if (rc < 0) {
 262                 retval = -EINTR;
 263                 info("Command was interrupted by a signal\n");
 264         }
 265
 266         return retval;
 267 }
 268
 269 /**
 270  * pcie_write_cmd - Issue controller command
 271  * @ctrl: controller to which the command is issued
 272  * @cmd:  command value written to slot control register
 273  * @mask: bitmask of slot control register to be modified
 274  */
 275 static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
 276 {
 277         int retval = 0;
 278         u16 slot_status;
 279         u16 slot_ctrl;
 280
 281         mutex_lock(&ctrl->ctrl_lock);
 282
 283         retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
 284         if (retval) {
 285                 err("%s: Cannot read SLOTSTATUS register\n", __func__);
 286                 goto out;
 287         }
 288
 289         if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) {
 290                 /* After 1 sec and CMD_COMPLETED still not set, just
 291                    proceed forward to issue the next command according
 292                    to spec.  Just print out the error message */
 293                 dbg("%s: CMD_COMPLETED not clear after 1 sec.\n",
 294                     __func__);
 295         }
 296
 297         retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
 298         if (retval) {
 299                 err("%s: Cannot read SLOTCTRL register\n", __func__);
 300                 goto out;
 301         }
 302
 303         slot_ctrl &= ~mask;
 304         slot_ctrl |= (cmd & mask);
 305         /* Don't enable command completed if caller is changing it. */
 306         if (!(mask & CMD_CMPL_INTR_ENABLE))
 307                 slot_ctrl |= CMD_CMPL_INTR_ENABLE;
 308
 309         ctrl->cmd_busy = 1;
 310         smp_mb();
 311         retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl);
 312         if (retval)
 313                 err("%s: Cannot write to SLOTCTRL register\n", __func__);
 314
 315         /*
 316          * Wait for command completion.
 317          */
 318         if (!retval)
 319                 retval = pcie_wait_cmd(ctrl);
 320  out:
 321         mutex_unlock(&ctrl->ctrl_lock);
 322         return retval;
 323 }
 324
 325 static int hpc_check_lnk_status(struct controller *ctrl)
 326 {
 327         u16 lnk_status;
 328         int retval = 0;
 329
 330         retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
 331         if (retval) {
 332                 err("%s: Cannot read LNKSTATUS register\n", __func__);
 333                 return retval;
 334         }
 335
 336         dbg("%s: lnk_status = %x\n", __func__, lnk_status);
 337         if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) ||
 338                 !(lnk_status & NEG_LINK_WD)) {
 339                 err("%s : Link Training Error occurs \n", __func__);
 340                 retval = -1;
 341                 return retval;
 342         }
 343
 344         return retval;
 345 }
 346
 347 static int hpc_get_attention_status(struct slot *slot, u8 *status)
 348 {
 349         struct controller *ctrl = slot->ctrl;
 350         u16 slot_ctrl;
 351         u8 atten_led_state;
 352         int retval = 0;
 353
 354         retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
 355         if (retval) {
 356                 err("%s: Cannot read SLOTCTRL register\n", __func__);
 357                 return retval;
 358         }
 359
 360         dbg("%s: SLOTCTRL %x, value read %x\n",
 361             __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
 362
 363         atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6;
 364
 365         switch (atten_led_state) {
 366         case 0:
 367                 *status = 0xFF; /* Reserved */
 368                 break;
 369         case 1:
 370                 *status = 1;    /* On */
 371                 break;
 372         case 2:
 373                 *status = 2;    /* Blink */
 374                 break;
 375         case 3:
 376                 *status = 0;    /* Off */
 377                 break;
 378         default:
 379                 *status = 0xFF;
 380                 break;
 381         }
 382
 383         return 0;
 384 }
 385
 386 static int hpc_get_power_status(struct slot *slot, u8 *status)
 387 {
 388         struct controller *ctrl = slot->ctrl;
 389         u16 slot_ctrl;
 390         u8 pwr_state;
 391         int     retval = 0;
 392
 393         retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
 394         if (retval) {
 395                 err("%s: Cannot read SLOTCTRL register\n", __func__);
 396                 return retval;
 397         }
 398         dbg("%s: SLOTCTRL %x value read %x\n",
 399             __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
 400
 401         pwr_state = (slot_ctrl & PWR_CTRL) >> 10;
 402
 403         switch (pwr_state) {
 404         case 0:
 405                 *status = 1;
 406                 break;
 407         case 1:
 408                 *status = 0;
 409                 break;
 410         default:
 411                 *status = 0xFF;
 412                 break;
 413         }
 414
 415         return retval;
 416 }
 417
 418 static int hpc_get_latch_status(struct slot *slot, u8 *status)
 419 {
 420         struct controller *ctrl = slot->ctrl;
 421         u16 slot_status;
 422         int retval = 0;
 423
 424         retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
 425         if (retval) {
 426                 err("%s: Cannot read SLOTSTATUS register\n", __func__);
 427                 return retval;
 428         }
 429
 430         *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1;
 431
 432         return 0;
 433 }
 434
 435 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
 436 {
 437         struct controller *ctrl = slot->ctrl;
 438         u16 slot_status;
 439         u8 card_state;
 440         int retval = 0;
 441
 442         retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
 443         if (retval) {
 444                 err("%s: Cannot read SLOTSTATUS register\n", __func__);
 445                 return retval;
 446         }
 447         card_state = (u8)((slot_status & PRSN_STATE) >> 6);
 448         *status = (card_state == 1) ? 1 : 0;
 449
 450         return 0;
 451 }
 452
 453 static int hpc_query_power_fault(struct slot *slot)
 454 {
 455         struct controller *ctrl = slot->ctrl;
 456         u16 slot_status;
 457         u8 pwr_fault;
 458         int retval = 0;
 459
 460         retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
 461         if (retval) {
 462                 err("%s: Cannot check for power fault\n", __func__);
 463                 return retval;
 464         }
 465         pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1);
 466
 467         return pwr_fault;
 468 }
 469
 470 static int hpc_get_emi_status(struct slot *slot, u8 *status)
 471 {
 472         struct controller *ctrl = slot->ctrl;
 473         u16 slot_status;
 474         int retval = 0;
 475
 476         retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
 477         if (retval) {
 478                 err("%s : Cannot check EMI status\n", __func__);
 479                 return retval;
 480         }
 481         *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT;
 482
 483         return retval;
 484 }
 485
 486 static int hpc_toggle_emi(struct slot *slot)
 487 {
 488         u16 slot_cmd;
 489         u16 cmd_mask;
 490         int rc;
 491
 492         slot_cmd = EMI_CTRL;
 493         cmd_mask = EMI_CTRL;
 494         rc = pcie_write_cmd(slot->ctrl, slot_cmd, cmd_mask);
 495         slot->last_emi_toggle = get_seconds();
 496
 497         return rc;
 498 }
 499
 500 static int hpc_set_attention_status(struct slot *slot, u8 value)
 501 {
 502         struct controller *ctrl = slot->ctrl;
 503         u16 slot_cmd;
 504         u16 cmd_mask;
 505         int rc;
 506
 507         cmd_mask = ATTN_LED_CTRL;
 508         switch (value) {
 509                 case 0 :        /* turn off */
 510                         slot_cmd = 0x00C0;
 511                         break;
 512                 case 1:         /* turn on */
 513                         slot_cmd = 0x0040;
 514                         break;
 515                 case 2:         /* turn blink */
 516                         slot_cmd = 0x0080;
 517                         break;
 518                 default:
 519                         return -1;
 520         }
 521         rc = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 522         dbg("%s: SLOTCTRL %x write cmd %x\n",
 523             __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
 524
 525         return rc;
 526 }
 527
 528 static void hpc_set_green_led_on(struct slot *slot)
 529 {
 530         struct controller *ctrl = slot->ctrl;
 531         u16 slot_cmd;
 532         u16 cmd_mask;
 533
 534         slot_cmd = 0x0100;
 535         cmd_mask = PWR_LED_CTRL;
 536         pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 537         dbg("%s: SLOTCTRL %x write cmd %x\n",
 538             __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
 539 }
 540
 541 static void hpc_set_green_led_off(struct slot *slot)
 542 {
 543         struct controller *ctrl = slot->ctrl;
 544         u16 slot_cmd;
 545         u16 cmd_mask;
 546
 547         slot_cmd = 0x0300;
 548         cmd_mask = PWR_LED_CTRL;
 549         pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 550         dbg("%s: SLOTCTRL %x write cmd %x\n",
 551             __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
 552 }
 553
 554 static void hpc_set_green_led_blink(struct slot *slot)
 555 {
 556         struct controller *ctrl = slot->ctrl;
 557         u16 slot_cmd;
 558         u16 cmd_mask;
 559
 560         slot_cmd = 0x0200;
 561         cmd_mask = PWR_LED_CTRL;
 562         pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 563         dbg("%s: SLOTCTRL %x write cmd %x\n",
 564             __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
 565 }
 566
 567 static void hpc_release_ctlr(struct controller *ctrl)
 568 {
 569         /* Mask Hot-plug Interrupt Enable */
 570         if (pcie_write_cmd(ctrl, 0, HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE))
 571                 err("%s: Cannot mask hotplut interrupt enable\n", __func__);
 572
 573         /* Free interrupt handler or interrupt polling timer */
 574         pciehp_free_irq(ctrl);
 575
 576         /*
 577          * If this is the last controller to be released, destroy the
 578          * pciehp work queue
 579          */
 580         if (atomic_dec_and_test(&pciehp_num_controllers))
 581                 destroy_workqueue(pciehp_wq);
 582 }
 583
 584 static int hpc_power_on_slot(struct slot * slot)
 585 {
 586         struct controller *ctrl = slot->ctrl;
 587         u16 slot_cmd;
 588         u16 cmd_mask;
 589         u16 slot_status;
 590         int retval = 0;
 591
 592         dbg("%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
 593
 594         /* Clear sticky power-fault bit from previous power failures */
 595         retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
 596         if (retval) {
 597                 err("%s: Cannot read SLOTSTATUS register\n", __func__);
 598                 return retval;
 599         }
 600         slot_status &= PWR_FAULT_DETECTED;
 601         if (slot_status) {
 602                 retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status);
 603                 if (retval) {
 604                         err("%s: Cannot write to SLOTSTATUS register\n",
 605                             __func__);
 606                         return retval;
 607                 }
 608         }
 609
 610         slot_cmd = POWER_ON;
 611         cmd_mask = PWR_CTRL;
 612         /* Enable detection that we turned off at slot power-off time */
 613         if (!pciehp_poll_mode) {
 614                 slot_cmd |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
 615                              PRSN_DETECT_ENABLE);
 616                 cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
 617                              PRSN_DETECT_ENABLE);
 618         }
 619
 620         retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 621
 622         if (retval) {
 623                 err("%s: Write %x command failed!\n", __func__, slot_cmd);
 624                 return -1;
 625         }
 626         dbg("%s: SLOTCTRL %x write cmd %x\n",
 627             __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
 628
 629         return retval;
 630 }
 631
 632 static inline int pcie_mask_bad_dllp(struct controller *ctrl)
 633 {
 634         struct pci_dev *dev = ctrl->pci_dev;
 635         int pos;
 636         u32 reg;
 637
 638         pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
 639         if (!pos)
 640                 return 0;
 641         pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg);
 642         if (reg & PCI_ERR_COR_BAD_DLLP)
 643                 return 0;
 644         reg |= PCI_ERR_COR_BAD_DLLP;
 645         pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
 646         return 1;
 647 }
 648
 649 static inline void pcie_unmask_bad_dllp(struct controller *ctrl)
 650 {
 651         struct pci_dev *dev = ctrl->pci_dev;
 652         u32 reg;
 653         int pos;
 654
 655         pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
 656         if (!pos)
 657                 return;
 658         pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg);
 659         if (!(reg & PCI_ERR_COR_BAD_DLLP))
 660                 return;
 661         reg &= ~PCI_ERR_COR_BAD_DLLP;
 662         pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
 663 }
 664
 665 static int hpc_power_off_slot(struct slot * slot)
 666 {
 667         struct controller *ctrl = slot->ctrl;
 668         u16 slot_cmd;
 669         u16 cmd_mask;
 670         int retval = 0;
 671         int changed;
 672
 673         dbg("%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
 674
 675         /*
 676          * Set Bad DLLP Mask bit in Correctable Error Mask
 677          * Register. This is the workaround against Bad DLLP error
 678          * that sometimes happens during turning power off the slot
 679          * which conforms to PCI Express 1.0a spec.
 680          */
 681         changed = pcie_mask_bad_dllp(ctrl);
 682
 683         slot_cmd = POWER_OFF;
 684         cmd_mask = PWR_CTRL;
 685         /*
 686          * If we get MRL or presence detect interrupts now, the isr
 687          * will notice the sticky power-fault bit too and issue power
 688          * indicator change commands. This will lead to an endless loop
 689          * of command completions, since the power-fault bit remains on
 690          * till the slot is powered on again.
 691          */
 692         if (!pciehp_poll_mode) {
 693                 slot_cmd &= ~(PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
 694                               PRSN_DETECT_ENABLE);
 695                 cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
 696                              PRSN_DETECT_ENABLE);
 697         }
 698
 699         retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 700         if (retval) {
 701                 err("%s: Write command failed!\n", __func__);
 702                 retval = -1;
 703                 goto out;
 704         }
 705         dbg("%s: SLOTCTRL %x write cmd %x\n",
 706             __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
 707
 708         /*
 709          * After turning power off, we must wait for at least 1 second
 710          * before taking any action that relies on power having been
 711          * removed from the slot/adapter.
 712          */
 713         msleep(1000);
 714  out:
 715         if (changed)
 716                 pcie_unmask_bad_dllp(ctrl);
 717
 718         return retval;
 719 }
 720
 721 static irqreturn_t pcie_isr(int irq, void *dev_id)
 722 {
 723         struct controller *ctrl = (struct controller *)dev_id;
 724         u16 detected, intr_loc;
 725         struct slot *p_slot;
 726
 727         /*
 728          * In order to guarantee that all interrupt events are
 729          * serviced, we need to re-inspect Slot Status register after
 730          * clearing what is presumed to be the last pending interrupt.
 731          */
 732         intr_loc = 0;
 733         do {
 734                 if (pciehp_readw(ctrl, SLOTSTATUS, &detected)) {
 735                         err("%s: Cannot read SLOTSTATUS\n", __func__);
 736                         return IRQ_NONE;
 737                 }
 738
 739                 detected &= (ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED |
 740                              MRL_SENS_CHANGED | PRSN_DETECT_CHANGED |
 741                              CMD_COMPLETED);
 742                 intr_loc |= detected;
 743                 if (!intr_loc)
 744                         return IRQ_NONE;
 745                 if (pciehp_writew(ctrl, SLOTSTATUS, detected)) {
 746                         err("%s: Cannot write to SLOTSTATUS\n", __func__);
 747                         return IRQ_NONE;
 748                 }
 749         } while (detected);
 750
 751         dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc);
 752
 753         /* Check Command Complete Interrupt Pending */
 754         if (intr_loc & CMD_COMPLETED) {
 755                 ctrl->cmd_busy = 0;
 756                 smp_mb();
 757                 wake_up_interruptible(&ctrl->queue);
 758         }
 759
 760         if (!(intr_loc & ~CMD_COMPLETED))
 761                 return IRQ_HANDLED;
 762
 763         /*
 764          * Return without handling events if this handler routine is
 765          * called before controller initialization is done. This may
 766          * happen if hotplug event or another interrupt that shares
 767          * the IRQ with pciehp arrives before slot initialization is
 768          * done after interrupt handler is registered.
 769          *
 770          * FIXME - Need more structural fixes. We need to be ready to
 771          * handle the event before installing interrupt handler.
 772          */
 773         p_slot = pciehp_find_slot(ctrl, ctrl->slot_device_offset);
 774         if (!p_slot || !p_slot->hpc_ops)
 775                 return IRQ_HANDLED;
 776
 777         /* Check MRL Sensor Changed */
 778         if (intr_loc & MRL_SENS_CHANGED)
 779                 pciehp_handle_switch_change(p_slot);
 780
 781         /* Check Attention Button Pressed */
 782         if (intr_loc & ATTN_BUTTN_PRESSED)
 783                 pciehp_handle_attention_button(p_slot);
 784
 785         /* Check Presence Detect Changed */
 786         if (intr_loc & PRSN_DETECT_CHANGED)
 787                 pciehp_handle_presence_change(p_slot);
 788
 789         /* Check Power Fault Detected */
 790         if (intr_loc & PWR_FAULT_DETECTED)
 791                 pciehp_handle_power_fault(p_slot);
 792
 793         return IRQ_HANDLED;
 794 }
 795
 796 static int hpc_get_max_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
 797 {
 798         struct controller *ctrl = slot->ctrl;
 799         enum pcie_link_speed lnk_speed;
 800         u32     lnk_cap;
 801         int retval = 0;
 802
 803         retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
 804         if (retval) {
 805                 err("%s: Cannot read LNKCAP register\n", __func__);
 806                 return retval;
 807         }
 808
 809         switch (lnk_cap & 0x000F) {
 810         case 1:
 811                 lnk_speed = PCIE_2PT5GB;
 812                 break;
 813         default:
 814                 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
 815                 break;
 816         }
 817
 818         *value = lnk_speed;
 819         dbg("Max link speed = %d\n", lnk_speed);
 820
 821         return retval;
 822 }
 823
 824 static int hpc_get_max_lnk_width(struct slot *slot,
 825                                  enum pcie_link_width *value)
 826 {
 827         struct controller *ctrl = slot->ctrl;
 828         enum pcie_link_width lnk_wdth;
 829         u32     lnk_cap;
 830         int retval = 0;
 831
 832         retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
 833         if (retval) {
 834                 err("%s: Cannot read LNKCAP register\n", __func__);
 835                 return retval;
 836         }
 837
 838         switch ((lnk_cap & 0x03F0) >> 4){
 839         case 0:
 840                 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
 841                 break;
 842         case 1:
 843                 lnk_wdth = PCIE_LNK_X1;
 844                 break;
 845         case 2:
 846                 lnk_wdth = PCIE_LNK_X2;
 847                 break;
 848         case 4:
 849                 lnk_wdth = PCIE_LNK_X4;
 850                 break;
 851         case 8:
 852                 lnk_wdth = PCIE_LNK_X8;
 853                 break;
 854         case 12:
 855                 lnk_wdth = PCIE_LNK_X12;
 856                 break;
 857         case 16:
 858                 lnk_wdth = PCIE_LNK_X16;
 859                 break;
 860         case 32:
 861                 lnk_wdth = PCIE_LNK_X32;
 862                 break;
 863         default:
 864                 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
 865                 break;
 866         }
 867
 868         *value = lnk_wdth;
 869         dbg("Max link width = %d\n", lnk_wdth);
 870
 871         return retval;
 872 }
 873
 874 static int hpc_get_cur_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
 875 {
 876         struct controller *ctrl = slot->ctrl;
 877         enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
 878         int retval = 0;
 879         u16 lnk_status;
 880
 881         retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
 882         if (retval) {
 883                 err("%s: Cannot read LNKSTATUS register\n", __func__);
 884                 return retval;
 885         }
 886
 887         switch (lnk_status & 0x0F) {
 888         case 1:
 889                 lnk_speed = PCIE_2PT5GB;
 890                 break;
 891         default:
 892                 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
 893                 break;
 894         }
 895
 896         *value = lnk_speed;
 897         dbg("Current link speed = %d\n", lnk_speed);
 898
 899         return retval;
 900 }
 901
 902 static int hpc_get_cur_lnk_width(struct slot *slot,
 903                                  enum pcie_link_width *value)
 904 {
 905         struct controller *ctrl = slot->ctrl;
 906         enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
 907         int retval = 0;
 908         u16 lnk_status;
 909
 910         retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
 911         if (retval) {
 912                 err("%s: Cannot read LNKSTATUS register\n", __func__);
 913                 return retval;
 914         }
 915
 916         switch ((lnk_status & 0x03F0) >> 4){
 917         case 0:
 918                 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
 919                 break;
 920         case 1:
 921                 lnk_wdth = PCIE_LNK_X1;
 922                 break;
 923         case 2:
 924                 lnk_wdth = PCIE_LNK_X2;
 925                 break;
 926         case 4:
 927                 lnk_wdth = PCIE_LNK_X4;
 928                 break;
 929         case 8:
 930                 lnk_wdth = PCIE_LNK_X8;
 931                 break;
 932         case 12:
 933                 lnk_wdth = PCIE_LNK_X12;
 934                 break;
 935         case 16:
 936                 lnk_wdth = PCIE_LNK_X16;
 937                 break;
 938         case 32:
 939                 lnk_wdth = PCIE_LNK_X32;
 940                 break;
 941         default:
 942                 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
 943                 break;
 944         }
 945
 946         *value = lnk_wdth;
 947         dbg("Current link width = %d\n", lnk_wdth);
 948
 949         return retval;
 950 }
 951
 952 static struct hpc_ops pciehp_hpc_ops = {
 953         .power_on_slot                  = hpc_power_on_slot,
 954         .power_off_slot                 = hpc_power_off_slot,
 955         .set_attention_status           = hpc_set_attention_status,
 956         .get_power_status               = hpc_get_power_status,
 957         .get_attention_status           = hpc_get_attention_status,
 958         .get_latch_status               = hpc_get_latch_status,
 959         .get_adapter_status             = hpc_get_adapter_status,
 960         .get_emi_status                 = hpc_get_emi_status,
 961         .toggle_emi                     = hpc_toggle_emi,
 962
 963         .get_max_bus_speed              = hpc_get_max_lnk_speed,
 964         .get_cur_bus_speed              = hpc_get_cur_lnk_speed,
 965         .get_max_lnk_width              = hpc_get_max_lnk_width,
 966         .get_cur_lnk_width              = hpc_get_cur_lnk_width,
 967
 968         .query_power_fault              = hpc_query_power_fault,
 969         .green_led_on                   = hpc_set_green_led_on,
 970         .green_led_off                  = hpc_set_green_led_off,
 971         .green_led_blink                = hpc_set_green_led_blink,
 972
 973         .release_ctlr                   = hpc_release_ctlr,
 974         .check_lnk_status               = hpc_check_lnk_status,
 975 };
 976
 977 #ifdef CONFIG_ACPI
 978 static int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev)
 979 {
 980         acpi_status status;
 981         acpi_handle chandle, handle = DEVICE_ACPI_HANDLE(&(dev->dev));
 982         struct pci_dev *pdev = dev;
 983         struct pci_bus *parent;
 984         struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
 985
 986         /*
 987          * Per PCI firmware specification, we should run the ACPI _OSC
 988          * method to get control of hotplug hardware before using it.
 989          * If an _OSC is missing, we look for an OSHP to do the same thing.
 990          * To handle different BIOS behavior, we look for _OSC and OSHP
 991          * within the scope of the hotplug controller and its parents, upto
 992          * the host bridge under which this controller exists.
 993          */
 994         while (!handle) {
 995                 /*
 996                  * This hotplug controller was not listed in the ACPI name
 997                  * space at all. Try to get acpi handle of parent pci bus.
 998                  */
 999                 if (!pdev || !pdev->bus->parent)
1000                         break;
1001                 parent = pdev->bus->parent;
1002                 dbg("Could not find %s in acpi namespace, trying parent\n",
1003                                 pci_name(pdev));
1004                 if (!parent->self)
1005                         /* Parent must be a host bridge */
1006                         handle = acpi_get_pci_rootbridge_handle(
1007                                         pci_domain_nr(parent),
1008                                         parent->number);
1009                 else
1010                         handle = DEVICE_ACPI_HANDLE(
1011                                         &(parent->self->dev));
1012                 pdev = parent->self;
1013         }
1014
1015         while (handle) {
1016                 acpi_get_name(handle, ACPI_FULL_PATHNAME, &string);
1017                 dbg("Trying to get hotplug control for %s \n",
1018                         (char *)string.pointer);
1019                 status = pci_osc_control_set(handle,
1020                                 OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL |
1021                                 OSC_PCI_EXPRESS_NATIVE_HP_CONTROL);
1022                 if (status == AE_NOT_FOUND)
1023                         status = acpi_run_oshp(handle);
1024                 if (ACPI_SUCCESS(status)) {
1025                         dbg("Gained control for hotplug HW for pci %s (%s)\n",
1026                                 pci_name(dev), (char *)string.pointer);
1027                         kfree(string.pointer);
1028                         return 0;
1029                 }
1030                 if (acpi_root_bridge(handle))
1031                         break;
1032                 chandle = handle;
1033                 status = acpi_get_parent(chandle, &handle);
1034                 if (ACPI_FAILURE(status))
1035                         break;
1036         }
1037
1038         dbg("Cannot get control of hotplug hardware for pci %s\n",
1039                         pci_name(dev));
1040
1041         kfree(string.pointer);
1042         return -1;
1043 }
1044 #endif
1045
1046 static int pcie_init_hardware_part1(struct controller *ctrl,
1047                                     struct pcie_device *dev)
1048 {
1049         /* Clear all remaining event bits in Slot Status register */
1050         if (pciehp_writew(ctrl, SLOTSTATUS, 0x1f)) {
1051                 err("%s: Cannot write to SLOTSTATUS register\n", __func__);
1052                 return -1;
1053         }
1054
1055         /* Mask Hot-plug Interrupt Enable */
1056         if (pcie_write_cmd(ctrl, 0, HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE)) {
1057                 err("%s: Cannot mask hotplug interrupt enable\n", __func__);
1058                 return -1;
1059         }
1060         return 0;
1061 }
1062
1063 int pcie_init_hardware_part2(struct controller *ctrl, struct pcie_device *dev)
1064 {
1065         u16 cmd, mask;
1066
1067         cmd = PRSN_DETECT_ENABLE;
1068         if (ATTN_BUTTN(ctrl))
1069                 cmd |= ATTN_BUTTN_ENABLE;
1070         if (POWER_CTRL(ctrl))
1071                 cmd |= PWR_FAULT_DETECT_ENABLE;
1072         if (MRL_SENS(ctrl))
1073                 cmd |= MRL_DETECT_ENABLE;
1074         if (!pciehp_poll_mode)
1075                 cmd |= HP_INTR_ENABLE;
1076
1077         mask = PRSN_DETECT_ENABLE | ATTN_BUTTN_ENABLE |
1078                 PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | HP_INTR_ENABLE;
1079
1080         if (pcie_write_cmd(ctrl, cmd, mask)) {
1081                 err("%s: Cannot enable software notification\n", __func__);
1082                 goto abort;
1083         }
1084
1085         if (pciehp_force)
1086                 dbg("Bypassing BIOS check for pciehp use on %s\n",
1087                                 pci_name(ctrl->pci_dev));
1088         else if (pciehp_get_hp_hw_control_from_firmware(ctrl->pci_dev))
1089                 goto abort_disable_intr;
1090
1091         return 0;
1092
1093         /* We end up here for the many possible ways to fail this API. */
1094 abort_disable_intr:
1095         if (pcie_write_cmd(ctrl, 0, HP_INTR_ENABLE))
1096                 err("%s : disabling interrupts failed\n", __func__);
1097 abort:
1098         return -1;
1099 }
1100
1101 static inline void dbg_ctrl(struct controller *ctrl)
1102 {
1103         int i;
1104         u16 reg16;
1105         struct pci_dev *pdev = ctrl->pci_dev;
1106
1107         if (!pciehp_debug)
1108                 return;
1109
1110         dbg("Hotplug Controller:\n");
1111         dbg("  Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", pci_name(pdev), pdev->irq);
1112         dbg("  Vendor ID            : 0x%04x\n", pdev->vendor);
1113         dbg("  Device ID            : 0x%04x\n", pdev->device);
1114         dbg("  Subsystem ID         : 0x%04x\n", pdev->subsystem_device);
1115         dbg("  Subsystem Vendor ID  : 0x%04x\n", pdev->subsystem_vendor);
1116         dbg("  PCIe Cap offset      : 0x%02x\n", ctrl->cap_base);
1117         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1118                 if (!pci_resource_len(pdev, i))
1119                         continue;
1120                 dbg("  PCI resource [%d]     : 0x%llx@0x%llx\n", i,
1121                     (unsigned long long)pci_resource_len(pdev, i),
1122                     (unsigned long long)pci_resource_start(pdev, i));
1123         }
1124         dbg("Slot Capabilities      : 0x%08x\n", ctrl->slot_cap);
1125         dbg("  Physical Slot Number : %d\n", ctrl->first_slot);
1126         dbg("  Attention Button     : %3s\n", ATTN_BUTTN(ctrl) ? "yes" : "no");
1127         dbg("  Power Controller     : %3s\n", POWER_CTRL(ctrl) ? "yes" : "no");
1128         dbg("  MRL Sensor           : %3s\n", MRL_SENS(ctrl)   ? "yes" : "no");
1129         dbg("  Attention Indicator  : %3s\n", ATTN_LED(ctrl)   ? "yes" : "no");
1130         dbg("  Power Indicator      : %3s\n", PWR_LED(ctrl)    ? "yes" : "no");
1131         dbg("  Hot-Plug Surprise    : %3s\n", HP_SUPR_RM(ctrl) ? "yes" : "no");
1132         dbg("  EMI Present          : %3s\n", EMI(ctrl)        ? "yes" : "no");
1133         pciehp_readw(ctrl, SLOTSTATUS, &reg16);
1134         dbg("Slot Status            : 0x%04x\n", reg16);
1135         pciehp_readw(ctrl, SLOTSTATUS, &reg16);
1136         dbg("Slot Control           : 0x%04x\n", reg16);
1137 }
1138
1139 int pcie_init(struct controller *ctrl, struct pcie_device *dev)
1140 {
1141         u32 slot_cap;
1142         struct pci_dev *pdev = dev->port;
1143
1144         ctrl->pci_dev = pdev;
1145         ctrl->cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1146         if (!ctrl->cap_base) {
1147                 err("%s: Cannot find PCI Express capability\n", __func__);
1148                 goto abort;
1149         }
1150         if (pciehp_readl(ctrl, SLOTCAP, &slot_cap)) {
1151                 err("%s: Cannot read SLOTCAP register\n", __func__);
1152                 goto abort;
1153         }
1154
1155         ctrl->slot_cap = slot_cap;
1156         ctrl->first_slot = slot_cap >> 19;
1157         ctrl->slot_device_offset = 0;
1158         ctrl->num_slots = 1;
1159         ctrl->hpc_ops = &pciehp_hpc_ops;
1160         mutex_init(&ctrl->crit_sect);
1161         mutex_init(&ctrl->ctrl_lock);
1162         init_waitqueue_head(&ctrl->queue);
1163         dbg_ctrl(ctrl);
1164
1165         info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
1166              pdev->vendor, pdev->device,
1167              pdev->subsystem_vendor, pdev->subsystem_device);
1168
1169         if (pcie_init_hardware_part1(ctrl, dev))
1170                 goto abort;
1171
1172         if (pciehp_request_irq(ctrl))
1173                 goto abort;
1174
1175         /*
1176          * If this is the first controller to be initialized,
1177          * initialize the pciehp work queue
1178          */
1179         if (atomic_add_return(1, &pciehp_num_controllers) == 1) {
1180                 pciehp_wq = create_singlethread_workqueue("pciehpd");
1181                 if (!pciehp_wq) {
1182                         goto abort_free_irq;
1183                 }
1184         }
1185
1186         if (pcie_init_hardware_part2(ctrl, dev))
1187                 goto abort_free_irq;
1188
1189         return 0;
1190
1191 abort_free_irq:
1192         pciehp_free_irq(ctrl);
1193 abort:
1194         return -1;
1195 }