2 * Copyright (C) 2001,2002,2003,2004 Broadcom Corporation
3 * Copyright (c) 2006, 2007 Maciej W. Rozycki
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 * This driver is designed for the Broadcom SiByte SOC built-in
21 * Ethernet controllers. Written by Mitch Lichtenberg at Broadcom Corp.
23 * Updated to the driver model and the PHY abstraction layer
24 * by Maciej W. Rozycki.
27 #include <linux/bug.h>
28 #include <linux/module.h>
29 #include <linux/kernel.h>
30 #include <linux/string.h>
31 #include <linux/timer.h>
32 #include <linux/errno.h>
33 #include <linux/ioport.h>
34 #include <linux/slab.h>
35 #include <linux/interrupt.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/skbuff.h>
39 #include <linux/init.h>
40 #include <linux/bitops.h>
41 #include <linux/err.h>
42 #include <linux/ethtool.h>
43 #include <linux/mii.h>
44 #include <linux/phy.h>
45 #include <linux/platform_device.h>
47 #include <asm/cache.h>
49 #include <asm/processor.h> /* Processor type for cache alignment. */
51 /* This is only here until the firmware is ready. In that case,
52 the firmware leaves the ethernet address in the register for us. */
53 #ifdef CONFIG_SIBYTE_STANDALONE
54 #define SBMAC_ETH0_HWADDR "40:00:00:00:01:00"
55 #define SBMAC_ETH1_HWADDR "40:00:00:00:01:01"
56 #define SBMAC_ETH2_HWADDR "40:00:00:00:01:02"
57 #define SBMAC_ETH3_HWADDR "40:00:00:00:01:03"
61 /* These identify the driver base version and may not be removed. */
63 static char version1
[] __initdata
=
64 "sb1250-mac.c:1.00 1/11/2001 Written by Mitch Lichtenberg\n";
68 /* Operational parameters that usually are not changed. */
70 #define CONFIG_SBMAC_COALESCE
72 /* Time in jiffies before concluding the transmitter is hung. */
73 #define TX_TIMEOUT (2*HZ)
76 MODULE_AUTHOR("Mitch Lichtenberg (Broadcom Corp.)");
77 MODULE_DESCRIPTION("Broadcom SiByte SOC GB Ethernet driver");
79 /* A few user-configurable values which may be modified when a driver
82 /* 1 normal messages, 0 quiet .. 7 verbose. */
84 module_param(debug
, int, S_IRUGO
);
85 MODULE_PARM_DESC(debug
, "Debug messages");
87 #ifdef CONFIG_SBMAC_COALESCE
88 static int int_pktcnt_tx
= 255;
89 module_param(int_pktcnt_tx
, int, S_IRUGO
);
90 MODULE_PARM_DESC(int_pktcnt_tx
, "TX packet count");
92 static int int_timeout_tx
= 255;
93 module_param(int_timeout_tx
, int, S_IRUGO
);
94 MODULE_PARM_DESC(int_timeout_tx
, "TX timeout value");
96 static int int_pktcnt_rx
= 64;
97 module_param(int_pktcnt_rx
, int, S_IRUGO
);
98 MODULE_PARM_DESC(int_pktcnt_rx
, "RX packet count");
100 static int int_timeout_rx
= 64;
101 module_param(int_timeout_rx
, int, S_IRUGO
);
102 MODULE_PARM_DESC(int_timeout_rx
, "RX timeout value");
105 #include <asm/sibyte/board.h>
106 #include <asm/sibyte/sb1250.h>
107 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
108 #include <asm/sibyte/bcm1480_regs.h>
109 #include <asm/sibyte/bcm1480_int.h>
110 #define R_MAC_DMA_OODPKTLOST_RX R_MAC_DMA_OODPKTLOST
111 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
112 #include <asm/sibyte/sb1250_regs.h>
113 #include <asm/sibyte/sb1250_int.h>
115 #error invalid SiByte MAC configuation
117 #include <asm/sibyte/sb1250_scd.h>
118 #include <asm/sibyte/sb1250_mac.h>
119 #include <asm/sibyte/sb1250_dma.h>
121 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
122 #define UNIT_INT(n) (K_BCM1480_INT_MAC_0 + ((n) * 2))
123 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
124 #define UNIT_INT(n) (K_INT_MAC_0 + (n))
126 #error invalid SiByte MAC configuation
130 #define SBMAC_PHY_INT K_INT_PHY
132 #define SBMAC_PHY_INT PHY_POLL
135 /**********************************************************************
137 ********************************************************************* */
140 sbmac_speed_none
= 0,
141 sbmac_speed_10
= SPEED_10
,
142 sbmac_speed_100
= SPEED_100
,
143 sbmac_speed_1000
= SPEED_1000
,
147 sbmac_duplex_none
= -1,
148 sbmac_duplex_half
= DUPLEX_HALF
,
149 sbmac_duplex_full
= DUPLEX_FULL
,
168 /**********************************************************************
170 ********************************************************************* */
173 #define SBDMA_NEXTBUF(d,f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \
174 (d)->sbdma_dscrtable : (d)->f+1)
177 #define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES)
179 #define SBMAC_MAX_TXDESCR 256
180 #define SBMAC_MAX_RXDESCR 256
182 #define ETHER_ADDR_LEN 6
183 #define ENET_PACKET_SIZE 1518
184 /*#define ENET_PACKET_SIZE 9216 */
186 /**********************************************************************
187 * DMA Descriptor structure
188 ********************************************************************* */
195 /**********************************************************************
196 * DMA Controller structure
197 ********************************************************************* */
202 * This stuff is used to identify the channel and the registers
203 * associated with it.
205 struct sbmac_softc
*sbdma_eth
; /* back pointer to associated
207 int sbdma_channel
; /* channel number */
208 int sbdma_txdir
; /* direction (1=transmit) */
209 int sbdma_maxdescr
; /* total # of descriptors
211 #ifdef CONFIG_SBMAC_COALESCE
212 int sbdma_int_pktcnt
;
213 /* # descriptors rx/tx
215 int sbdma_int_timeout
;
216 /* # usec rx/tx interrupt */
218 void __iomem
*sbdma_config0
; /* DMA config register 0 */
219 void __iomem
*sbdma_config1
; /* DMA config register 1 */
220 void __iomem
*sbdma_dscrbase
;
221 /* descriptor base address */
222 void __iomem
*sbdma_dscrcnt
; /* descriptor count register */
223 void __iomem
*sbdma_curdscr
; /* current descriptor
225 void __iomem
*sbdma_oodpktlost
;
226 /* pkt drop (rx only) */
229 * This stuff is for maintenance of the ring
231 void *sbdma_dscrtable_unaligned
;
232 struct sbdmadscr
*sbdma_dscrtable
;
233 /* base of descriptor table */
234 struct sbdmadscr
*sbdma_dscrtable_end
;
235 /* end of descriptor table */
236 struct sk_buff
**sbdma_ctxtable
;
237 /* context table, one
239 dma_addr_t sbdma_dscrtable_phys
;
240 /* and also the phys addr */
241 struct sbdmadscr
*sbdma_addptr
; /* next dscr for sw to add */
242 struct sbdmadscr
*sbdma_remptr
; /* next dscr for sw
247 /**********************************************************************
248 * Ethernet softc structure
249 ********************************************************************* */
254 * Linux-specific things
256 struct net_device
*sbm_dev
; /* pointer to linux device */
257 struct napi_struct napi
;
258 struct phy_device
*phy_dev
; /* the associated PHY device */
259 struct mii_bus
*mii_bus
; /* the MII bus */
260 int phy_irq
[PHY_MAX_ADDR
];
261 spinlock_t sbm_lock
; /* spin lock */
262 int sbm_devflags
; /* current device flags */
265 * Controller-specific things
267 void __iomem
*sbm_base
; /* MAC's base address */
268 enum sbmac_state sbm_state
; /* current state */
270 void __iomem
*sbm_macenable
; /* MAC Enable Register */
271 void __iomem
*sbm_maccfg
; /* MAC Config Register */
272 void __iomem
*sbm_fifocfg
; /* FIFO Config Register */
273 void __iomem
*sbm_framecfg
; /* Frame Config Register */
274 void __iomem
*sbm_rxfilter
; /* Receive Filter Register */
275 void __iomem
*sbm_isr
; /* Interrupt Status Register */
276 void __iomem
*sbm_imr
; /* Interrupt Mask Register */
277 void __iomem
*sbm_mdio
; /* MDIO Register */
279 enum sbmac_speed sbm_speed
; /* current speed */
280 enum sbmac_duplex sbm_duplex
; /* current duplex */
281 enum sbmac_fc sbm_fc
; /* cur. flow control setting */
282 int sbm_pause
; /* current pause setting */
283 int sbm_link
; /* current link state */
285 unsigned char sbm_hwaddr
[ETHER_ADDR_LEN
];
287 struct sbmacdma sbm_txdma
; /* only channel 0 for now */
288 struct sbmacdma sbm_rxdma
;
294 /**********************************************************************
296 ********************************************************************* */
298 /**********************************************************************
300 ********************************************************************* */
302 static void sbdma_initctx(struct sbmacdma
*d
, struct sbmac_softc
*s
, int chan
,
303 int txrx
, int maxdescr
);
304 static void sbdma_channel_start(struct sbmacdma
*d
, int rxtx
);
305 static int sbdma_add_rcvbuffer(struct sbmac_softc
*sc
, struct sbmacdma
*d
,
307 static int sbdma_add_txbuffer(struct sbmacdma
*d
, struct sk_buff
*m
);
308 static void sbdma_emptyring(struct sbmacdma
*d
);
309 static void sbdma_fillring(struct sbmac_softc
*sc
, struct sbmacdma
*d
);
310 static int sbdma_rx_process(struct sbmac_softc
*sc
, struct sbmacdma
*d
,
311 int work_to_do
, int poll
);
312 static void sbdma_tx_process(struct sbmac_softc
*sc
, struct sbmacdma
*d
,
314 static int sbmac_initctx(struct sbmac_softc
*s
);
315 static void sbmac_channel_start(struct sbmac_softc
*s
);
316 static void sbmac_channel_stop(struct sbmac_softc
*s
);
317 static enum sbmac_state
sbmac_set_channel_state(struct sbmac_softc
*,
319 static void sbmac_promiscuous_mode(struct sbmac_softc
*sc
, int onoff
);
320 static uint64_t sbmac_addr2reg(unsigned char *ptr
);
321 static irqreturn_t
sbmac_intr(int irq
, void *dev_instance
);
322 static int sbmac_start_tx(struct sk_buff
*skb
, struct net_device
*dev
);
323 static void sbmac_setmulti(struct sbmac_softc
*sc
);
324 static int sbmac_init(struct platform_device
*pldev
, long long base
);
325 static int sbmac_set_speed(struct sbmac_softc
*s
, enum sbmac_speed speed
);
326 static int sbmac_set_duplex(struct sbmac_softc
*s
, enum sbmac_duplex duplex
,
329 static int sbmac_open(struct net_device
*dev
);
330 static void sbmac_tx_timeout (struct net_device
*dev
);
331 static void sbmac_set_rx_mode(struct net_device
*dev
);
332 static int sbmac_mii_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
);
333 static int sbmac_close(struct net_device
*dev
);
334 static int sbmac_poll(struct napi_struct
*napi
, int budget
);
336 static void sbmac_mii_poll(struct net_device
*dev
);
337 static int sbmac_mii_probe(struct net_device
*dev
);
339 static void sbmac_mii_sync(void __iomem
*sbm_mdio
);
340 static void sbmac_mii_senddata(void __iomem
*sbm_mdio
, unsigned int data
,
342 static int sbmac_mii_read(struct mii_bus
*bus
, int phyaddr
, int regidx
);
343 static int sbmac_mii_write(struct mii_bus
*bus
, int phyaddr
, int regidx
,
347 /**********************************************************************
349 ********************************************************************* */
351 static char sbmac_string
[] = "sb1250-mac";
352 static char sbmac_pretty
[] = "SB1250 MAC";
354 static char sbmac_mdio_string
[] = "sb1250-mac-mdio";
357 /**********************************************************************
359 ********************************************************************* */
361 #define MII_COMMAND_START 0x01
362 #define MII_COMMAND_READ 0x02
363 #define MII_COMMAND_WRITE 0x01
364 #define MII_COMMAND_ACK 0x02
366 #define M_MAC_MDIO_DIR_OUTPUT 0 /* for clarity */
371 /**********************************************************************
372 * SBMAC_MII_SYNC(sbm_mdio)
374 * Synchronize with the MII - send a pattern of bits to the MII
375 * that will guarantee that it is ready to accept a command.
378 * sbm_mdio - address of the MAC's MDIO register
382 ********************************************************************* */
384 static void sbmac_mii_sync(void __iomem
*sbm_mdio
)
390 mac_mdio_genc
= __raw_readq(sbm_mdio
) & M_MAC_GENC
;
392 bits
= M_MAC_MDIO_DIR_OUTPUT
| M_MAC_MDIO_OUT
;
394 __raw_writeq(bits
| mac_mdio_genc
, sbm_mdio
);
396 for (cnt
= 0; cnt
< 32; cnt
++) {
397 __raw_writeq(bits
| M_MAC_MDC
| mac_mdio_genc
, sbm_mdio
);
398 __raw_writeq(bits
| mac_mdio_genc
, sbm_mdio
);
402 /**********************************************************************
403 * SBMAC_MII_SENDDATA(sbm_mdio, data, bitcnt)
405 * Send some bits to the MII. The bits to be sent are right-
406 * justified in the 'data' parameter.
409 * sbm_mdio - address of the MAC's MDIO register
410 * data - data to send
411 * bitcnt - number of bits to send
412 ********************************************************************* */
414 static void sbmac_mii_senddata(void __iomem
*sbm_mdio
, unsigned int data
,
419 unsigned int curmask
;
422 mac_mdio_genc
= __raw_readq(sbm_mdio
) & M_MAC_GENC
;
424 bits
= M_MAC_MDIO_DIR_OUTPUT
;
425 __raw_writeq(bits
| mac_mdio_genc
, sbm_mdio
);
427 curmask
= 1 << (bitcnt
- 1);
429 for (i
= 0; i
< bitcnt
; i
++) {
431 bits
|= M_MAC_MDIO_OUT
;
432 else bits
&= ~M_MAC_MDIO_OUT
;
433 __raw_writeq(bits
| mac_mdio_genc
, sbm_mdio
);
434 __raw_writeq(bits
| M_MAC_MDC
| mac_mdio_genc
, sbm_mdio
);
435 __raw_writeq(bits
| mac_mdio_genc
, sbm_mdio
);
442 /**********************************************************************
443 * SBMAC_MII_READ(bus, phyaddr, regidx)
444 * Read a PHY register.
447 * bus - MDIO bus handle
448 * phyaddr - PHY's address
449 * regnum - index of register to read
452 * value read, or 0xffff if an error occurred.
453 ********************************************************************* */
455 static int sbmac_mii_read(struct mii_bus
*bus
, int phyaddr
, int regidx
)
457 struct sbmac_softc
*sc
= (struct sbmac_softc
*)bus
->priv
;
458 void __iomem
*sbm_mdio
= sc
->sbm_mdio
;
465 * Synchronize ourselves so that the PHY knows the next
466 * thing coming down is a command
468 sbmac_mii_sync(sbm_mdio
);
471 * Send the data to the PHY. The sequence is
472 * a "start" command (2 bits)
473 * a "read" command (2 bits)
474 * the PHY addr (5 bits)
475 * the register index (5 bits)
477 sbmac_mii_senddata(sbm_mdio
, MII_COMMAND_START
, 2);
478 sbmac_mii_senddata(sbm_mdio
, MII_COMMAND_READ
, 2);
479 sbmac_mii_senddata(sbm_mdio
, phyaddr
, 5);
480 sbmac_mii_senddata(sbm_mdio
, regidx
, 5);
482 mac_mdio_genc
= __raw_readq(sbm_mdio
) & M_MAC_GENC
;
485 * Switch the port around without a clock transition.
487 __raw_writeq(M_MAC_MDIO_DIR_INPUT
| mac_mdio_genc
, sbm_mdio
);
490 * Send out a clock pulse to signal we want the status
492 __raw_writeq(M_MAC_MDIO_DIR_INPUT
| M_MAC_MDC
| mac_mdio_genc
,
494 __raw_writeq(M_MAC_MDIO_DIR_INPUT
| mac_mdio_genc
, sbm_mdio
);
497 * If an error occurred, the PHY will signal '1' back
499 error
= __raw_readq(sbm_mdio
) & M_MAC_MDIO_IN
;
502 * Issue an 'idle' clock pulse, but keep the direction
505 __raw_writeq(M_MAC_MDIO_DIR_INPUT
| M_MAC_MDC
| mac_mdio_genc
,
507 __raw_writeq(M_MAC_MDIO_DIR_INPUT
| mac_mdio_genc
, sbm_mdio
);
511 for (idx
= 0; idx
< 16; idx
++) {
515 if (__raw_readq(sbm_mdio
) & M_MAC_MDIO_IN
)
519 __raw_writeq(M_MAC_MDIO_DIR_INPUT
| M_MAC_MDC
| mac_mdio_genc
,
521 __raw_writeq(M_MAC_MDIO_DIR_INPUT
| mac_mdio_genc
, sbm_mdio
);
524 /* Switch back to output */
525 __raw_writeq(M_MAC_MDIO_DIR_OUTPUT
| mac_mdio_genc
, sbm_mdio
);
533 /**********************************************************************
534 * SBMAC_MII_WRITE(bus, phyaddr, regidx, regval)
536 * Write a value to a PHY register.
539 * bus - MDIO bus handle
540 * phyaddr - PHY to use
541 * regidx - register within the PHY
542 * regval - data to write to register
546 ********************************************************************* */
548 static int sbmac_mii_write(struct mii_bus
*bus
, int phyaddr
, int regidx
,
551 struct sbmac_softc
*sc
= (struct sbmac_softc
*)bus
->priv
;
552 void __iomem
*sbm_mdio
= sc
->sbm_mdio
;
555 sbmac_mii_sync(sbm_mdio
);
557 sbmac_mii_senddata(sbm_mdio
, MII_COMMAND_START
, 2);
558 sbmac_mii_senddata(sbm_mdio
, MII_COMMAND_WRITE
, 2);
559 sbmac_mii_senddata(sbm_mdio
, phyaddr
, 5);
560 sbmac_mii_senddata(sbm_mdio
, regidx
, 5);
561 sbmac_mii_senddata(sbm_mdio
, MII_COMMAND_ACK
, 2);
562 sbmac_mii_senddata(sbm_mdio
, regval
, 16);
564 mac_mdio_genc
= __raw_readq(sbm_mdio
) & M_MAC_GENC
;
566 __raw_writeq(M_MAC_MDIO_DIR_OUTPUT
| mac_mdio_genc
, sbm_mdio
);
573 /**********************************************************************
574 * SBDMA_INITCTX(d,s,chan,txrx,maxdescr)
576 * Initialize a DMA channel context. Since there are potentially
577 * eight DMA channels per MAC, it's nice to do this in a standard
581 * d - struct sbmacdma (DMA channel context)
582 * s - struct sbmac_softc (pointer to a MAC)
583 * chan - channel number (0..1 right now)
584 * txrx - Identifies DMA_TX or DMA_RX for channel direction
585 * maxdescr - number of descriptors
589 ********************************************************************* */
591 static void sbdma_initctx(struct sbmacdma
*d
, struct sbmac_softc
*s
, int chan
,
592 int txrx
, int maxdescr
)
594 #ifdef CONFIG_SBMAC_COALESCE
595 int int_pktcnt
, int_timeout
;
599 * Save away interesting stuff in the structure
603 d
->sbdma_channel
= chan
;
604 d
->sbdma_txdir
= txrx
;
608 s
->sbe_idx
=(s
->sbm_base
- A_MAC_BASE_0
)/MAC_SPACING
;
611 __raw_writeq(0, s
->sbm_base
+ R_MAC_RMON_TX_BYTES
);
612 __raw_writeq(0, s
->sbm_base
+ R_MAC_RMON_COLLISIONS
);
613 __raw_writeq(0, s
->sbm_base
+ R_MAC_RMON_LATE_COL
);
614 __raw_writeq(0, s
->sbm_base
+ R_MAC_RMON_EX_COL
);
615 __raw_writeq(0, s
->sbm_base
+ R_MAC_RMON_FCS_ERROR
);
616 __raw_writeq(0, s
->sbm_base
+ R_MAC_RMON_TX_ABORT
);
617 __raw_writeq(0, s
->sbm_base
+ R_MAC_RMON_TX_BAD
);
618 __raw_writeq(0, s
->sbm_base
+ R_MAC_RMON_TX_GOOD
);
619 __raw_writeq(0, s
->sbm_base
+ R_MAC_RMON_TX_RUNT
);
620 __raw_writeq(0, s
->sbm_base
+ R_MAC_RMON_TX_OVERSIZE
);
621 __raw_writeq(0, s
->sbm_base
+ R_MAC_RMON_RX_BYTES
);
622 __raw_writeq(0, s
->sbm_base
+ R_MAC_RMON_RX_MCAST
);
623 __raw_writeq(0, s
->sbm_base
+ R_MAC_RMON_RX_BCAST
);
624 __raw_writeq(0, s
->sbm_base
+ R_MAC_RMON_RX_BAD
);
625 __raw_writeq(0, s
->sbm_base
+ R_MAC_RMON_RX_GOOD
);
626 __raw_writeq(0, s
->sbm_base
+ R_MAC_RMON_RX_RUNT
);
627 __raw_writeq(0, s
->sbm_base
+ R_MAC_RMON_RX_OVERSIZE
);
628 __raw_writeq(0, s
->sbm_base
+ R_MAC_RMON_RX_FCS_ERROR
);
629 __raw_writeq(0, s
->sbm_base
+ R_MAC_RMON_RX_LENGTH_ERROR
);
630 __raw_writeq(0, s
->sbm_base
+ R_MAC_RMON_RX_CODE_ERROR
);
631 __raw_writeq(0, s
->sbm_base
+ R_MAC_RMON_RX_ALIGN_ERROR
);
634 * initialize register pointers
638 s
->sbm_base
+ R_MAC_DMA_REGISTER(txrx
,chan
,R_MAC_DMA_CONFIG0
);
640 s
->sbm_base
+ R_MAC_DMA_REGISTER(txrx
,chan
,R_MAC_DMA_CONFIG1
);
642 s
->sbm_base
+ R_MAC_DMA_REGISTER(txrx
,chan
,R_MAC_DMA_DSCR_BASE
);
644 s
->sbm_base
+ R_MAC_DMA_REGISTER(txrx
,chan
,R_MAC_DMA_DSCR_CNT
);
646 s
->sbm_base
+ R_MAC_DMA_REGISTER(txrx
,chan
,R_MAC_DMA_CUR_DSCRADDR
);
648 d
->sbdma_oodpktlost
= NULL
;
650 d
->sbdma_oodpktlost
=
651 s
->sbm_base
+ R_MAC_DMA_REGISTER(txrx
,chan
,R_MAC_DMA_OODPKTLOST_RX
);
654 * Allocate memory for the ring
657 d
->sbdma_maxdescr
= maxdescr
;
659 d
->sbdma_dscrtable_unaligned
= kcalloc(d
->sbdma_maxdescr
+ 1,
660 sizeof(*d
->sbdma_dscrtable
),
664 * The descriptor table must be aligned to at least 16 bytes or the
665 * MAC will corrupt it.
667 d
->sbdma_dscrtable
= (struct sbdmadscr
*)
668 ALIGN((unsigned long)d
->sbdma_dscrtable_unaligned
,
669 sizeof(*d
->sbdma_dscrtable
));
671 d
->sbdma_dscrtable_end
= d
->sbdma_dscrtable
+ d
->sbdma_maxdescr
;
673 d
->sbdma_dscrtable_phys
= virt_to_phys(d
->sbdma_dscrtable
);
679 d
->sbdma_ctxtable
= kcalloc(d
->sbdma_maxdescr
,
680 sizeof(*d
->sbdma_ctxtable
), GFP_KERNEL
);
682 #ifdef CONFIG_SBMAC_COALESCE
684 * Setup Rx/Tx DMA coalescing defaults
687 int_pktcnt
= (txrx
== DMA_TX
) ? int_pktcnt_tx
: int_pktcnt_rx
;
689 d
->sbdma_int_pktcnt
= int_pktcnt
;
691 d
->sbdma_int_pktcnt
= 1;
694 int_timeout
= (txrx
== DMA_TX
) ? int_timeout_tx
: int_timeout_rx
;
696 d
->sbdma_int_timeout
= int_timeout
;
698 d
->sbdma_int_timeout
= 0;
704 /**********************************************************************
705 * SBDMA_CHANNEL_START(d)
707 * Initialize the hardware registers for a DMA channel.
710 * d - DMA channel to init (context must be previously init'd
711 * rxtx - DMA_RX or DMA_TX depending on what type of channel
715 ********************************************************************* */
717 static void sbdma_channel_start(struct sbmacdma
*d
, int rxtx
)
720 * Turn on the DMA channel
723 #ifdef CONFIG_SBMAC_COALESCE
724 __raw_writeq(V_DMA_INT_TIMEOUT(d
->sbdma_int_timeout
) |
725 0, d
->sbdma_config1
);
726 __raw_writeq(M_DMA_EOP_INT_EN
|
727 V_DMA_RINGSZ(d
->sbdma_maxdescr
) |
728 V_DMA_INT_PKTCNT(d
->sbdma_int_pktcnt
) |
729 0, d
->sbdma_config0
);
731 __raw_writeq(0, d
->sbdma_config1
);
732 __raw_writeq(V_DMA_RINGSZ(d
->sbdma_maxdescr
) |
733 0, d
->sbdma_config0
);
736 __raw_writeq(d
->sbdma_dscrtable_phys
, d
->sbdma_dscrbase
);
739 * Initialize ring pointers
742 d
->sbdma_addptr
= d
->sbdma_dscrtable
;
743 d
->sbdma_remptr
= d
->sbdma_dscrtable
;
746 /**********************************************************************
747 * SBDMA_CHANNEL_STOP(d)
749 * Initialize the hardware registers for a DMA channel.
752 * d - DMA channel to init (context must be previously init'd
756 ********************************************************************* */
758 static void sbdma_channel_stop(struct sbmacdma
*d
)
761 * Turn off the DMA channel
764 __raw_writeq(0, d
->sbdma_config1
);
766 __raw_writeq(0, d
->sbdma_dscrbase
);
768 __raw_writeq(0, d
->sbdma_config0
);
774 d
->sbdma_addptr
= NULL
;
775 d
->sbdma_remptr
= NULL
;
778 static inline void sbdma_align_skb(struct sk_buff
*skb
,
779 unsigned int power2
, unsigned int offset
)
781 unsigned char *addr
= skb
->data
;
782 unsigned char *newaddr
= PTR_ALIGN(addr
, power2
);
784 skb_reserve(skb
, newaddr
- addr
+ offset
);
788 /**********************************************************************
789 * SBDMA_ADD_RCVBUFFER(d,sb)
791 * Add a buffer to the specified DMA channel. For receive channels,
792 * this queues a buffer for inbound packets.
795 * sc - softc structure
796 * d - DMA channel descriptor
797 * sb - sk_buff to add, or NULL if we should allocate one
800 * 0 if buffer could not be added (ring is full)
801 * 1 if buffer added successfully
802 ********************************************************************* */
805 static int sbdma_add_rcvbuffer(struct sbmac_softc
*sc
, struct sbmacdma
*d
,
808 struct net_device
*dev
= sc
->sbm_dev
;
809 struct sbdmadscr
*dsc
;
810 struct sbdmadscr
*nextdsc
;
811 struct sk_buff
*sb_new
= NULL
;
812 int pktsize
= ENET_PACKET_SIZE
;
814 /* get pointer to our current place in the ring */
816 dsc
= d
->sbdma_addptr
;
817 nextdsc
= SBDMA_NEXTBUF(d
,sbdma_addptr
);
820 * figure out if the ring is full - if the next descriptor
821 * is the same as the one that we're going to remove from
822 * the ring, the ring is full
825 if (nextdsc
== d
->sbdma_remptr
) {
830 * Allocate a sk_buff if we don't already have one.
831 * If we do have an sk_buff, reset it so that it's empty.
833 * Note: sk_buffs don't seem to be guaranteed to have any sort
834 * of alignment when they are allocated. Therefore, allocate enough
835 * extra space to make sure that:
837 * 1. the data does not start in the middle of a cache line.
838 * 2. The data does not end in the middle of a cache line
839 * 3. The buffer can be aligned such that the IP addresses are
842 * Remember, the SOCs MAC writes whole cache lines at a time,
843 * without reading the old contents first. So, if the sk_buff's
844 * data portion starts in the middle of a cache line, the SOC
845 * DMA will trash the beginning (and ending) portions.
849 sb_new
= netdev_alloc_skb(dev
, ENET_PACKET_SIZE
+
850 SMP_CACHE_BYTES
* 2 +
852 if (sb_new
== NULL
) {
853 pr_info("%s: sk_buff allocation failed\n",
854 d
->sbdma_eth
->sbm_dev
->name
);
858 sbdma_align_skb(sb_new
, SMP_CACHE_BYTES
, NET_IP_ALIGN
);
863 * nothing special to reinit buffer, it's already aligned
864 * and sb->data already points to a good place.
869 * fill in the descriptor
872 #ifdef CONFIG_SBMAC_COALESCE
874 * Do not interrupt per DMA transfer.
876 dsc
->dscr_a
= virt_to_phys(sb_new
->data
) |
877 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize
+ NET_IP_ALIGN
)) | 0;
879 dsc
->dscr_a
= virt_to_phys(sb_new
->data
) |
880 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize
+ NET_IP_ALIGN
)) |
881 M_DMA_DSCRA_INTERRUPT
;
884 /* receiving: no options */
888 * fill in the context
891 d
->sbdma_ctxtable
[dsc
-d
->sbdma_dscrtable
] = sb_new
;
894 * point at next packet
897 d
->sbdma_addptr
= nextdsc
;
900 * Give the buffer to the DMA engine.
903 __raw_writeq(1, d
->sbdma_dscrcnt
);
905 return 0; /* we did it */
908 /**********************************************************************
909 * SBDMA_ADD_TXBUFFER(d,sb)
911 * Add a transmit buffer to the specified DMA channel, causing a
915 * d - DMA channel descriptor
916 * sb - sk_buff to add
919 * 0 transmit queued successfully
920 * otherwise error code
921 ********************************************************************* */
924 static int sbdma_add_txbuffer(struct sbmacdma
*d
, struct sk_buff
*sb
)
926 struct sbdmadscr
*dsc
;
927 struct sbdmadscr
*nextdsc
;
932 /* get pointer to our current place in the ring */
934 dsc
= d
->sbdma_addptr
;
935 nextdsc
= SBDMA_NEXTBUF(d
,sbdma_addptr
);
938 * figure out if the ring is full - if the next descriptor
939 * is the same as the one that we're going to remove from
940 * the ring, the ring is full
943 if (nextdsc
== d
->sbdma_remptr
) {
948 * Under Linux, it's not necessary to copy/coalesce buffers
949 * like it is on NetBSD. We think they're all contiguous,
950 * but that may not be true for GBE.
956 * fill in the descriptor. Note that the number of cache
957 * blocks in the descriptor is the number of blocks
958 * *spanned*, so we need to add in the offset (if any)
959 * while doing the calculation.
962 phys
= virt_to_phys(sb
->data
);
963 ncb
= NUMCACHEBLKS(length
+(phys
& (SMP_CACHE_BYTES
- 1)));
966 V_DMA_DSCRA_A_SIZE(ncb
) |
967 #ifndef CONFIG_SBMAC_COALESCE
968 M_DMA_DSCRA_INTERRUPT
|
972 /* transmitting: set outbound options and length */
974 dsc
->dscr_b
= V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD
) |
975 V_DMA_DSCRB_PKT_SIZE(length
);
978 * fill in the context
981 d
->sbdma_ctxtable
[dsc
-d
->sbdma_dscrtable
] = sb
;
984 * point at next packet
987 d
->sbdma_addptr
= nextdsc
;
990 * Give the buffer to the DMA engine.
993 __raw_writeq(1, d
->sbdma_dscrcnt
);
995 return 0; /* we did it */
1001 /**********************************************************************
1002 * SBDMA_EMPTYRING(d)
1004 * Free all allocated sk_buffs on the specified DMA channel;
1011 ********************************************************************* */
1013 static void sbdma_emptyring(struct sbmacdma
*d
)
1018 for (idx
= 0; idx
< d
->sbdma_maxdescr
; idx
++) {
1019 sb
= d
->sbdma_ctxtable
[idx
];
1022 d
->sbdma_ctxtable
[idx
] = NULL
;
1028 /**********************************************************************
1031 * Fill the specified DMA channel (must be receive channel)
1035 * sc - softc structure
1040 ********************************************************************* */
1042 static void sbdma_fillring(struct sbmac_softc
*sc
, struct sbmacdma
*d
)
1046 for (idx
= 0; idx
< SBMAC_MAX_RXDESCR
- 1; idx
++) {
1047 if (sbdma_add_rcvbuffer(sc
, d
, NULL
) != 0)
1052 #ifdef CONFIG_NET_POLL_CONTROLLER
1053 static void sbmac_netpoll(struct net_device
*netdev
)
1055 struct sbmac_softc
*sc
= netdev_priv(netdev
);
1056 int irq
= sc
->sbm_dev
->irq
;
1058 __raw_writeq(0, sc
->sbm_imr
);
1060 sbmac_intr(irq
, netdev
);
1062 #ifdef CONFIG_SBMAC_COALESCE
1063 __raw_writeq(((M_MAC_INT_EOP_COUNT
| M_MAC_INT_EOP_TIMER
) << S_MAC_TX_CH0
) |
1064 ((M_MAC_INT_EOP_COUNT
| M_MAC_INT_EOP_TIMER
) << S_MAC_RX_CH0
),
1067 __raw_writeq((M_MAC_INT_CHANNEL
<< S_MAC_TX_CH0
) |
1068 (M_MAC_INT_CHANNEL
<< S_MAC_RX_CH0
), sc
->sbm_imr
);
1073 /**********************************************************************
1074 * SBDMA_RX_PROCESS(sc,d,work_to_do,poll)
1076 * Process "completed" receive buffers on the specified DMA channel.
1079 * sc - softc structure
1080 * d - DMA channel context
1081 * work_to_do - no. of packets to process before enabling interrupt
1083 * poll - 1: using polling (for NAPI)
1087 ********************************************************************* */
1089 static int sbdma_rx_process(struct sbmac_softc
*sc
, struct sbmacdma
*d
,
1090 int work_to_do
, int poll
)
1092 struct net_device
*dev
= sc
->sbm_dev
;
1095 struct sbdmadscr
*dsc
;
1104 /* Check if the HW dropped any frames */
1105 dev
->stats
.rx_fifo_errors
1106 += __raw_readq(sc
->sbm_rxdma
.sbdma_oodpktlost
) & 0xffff;
1107 __raw_writeq(0, sc
->sbm_rxdma
.sbdma_oodpktlost
);
1109 while (work_to_do
-- > 0) {
1111 * figure out where we are (as an index) and where
1112 * the hardware is (also as an index)
1114 * This could be done faster if (for example) the
1115 * descriptor table was page-aligned and contiguous in
1116 * both virtual and physical memory -- you could then
1117 * just compare the low-order bits of the virtual address
1118 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1121 dsc
= d
->sbdma_remptr
;
1122 curidx
= dsc
- d
->sbdma_dscrtable
;
1125 prefetch(&d
->sbdma_ctxtable
[curidx
]);
1127 hwidx
= ((__raw_readq(d
->sbdma_curdscr
) & M_DMA_CURDSCR_ADDR
) -
1128 d
->sbdma_dscrtable_phys
) /
1129 sizeof(*d
->sbdma_dscrtable
);
1132 * If they're the same, that means we've processed all
1133 * of the descriptors up to (but not including) the one that
1134 * the hardware is working on right now.
1137 if (curidx
== hwidx
)
1141 * Otherwise, get the packet's sk_buff ptr back
1144 sb
= d
->sbdma_ctxtable
[curidx
];
1145 d
->sbdma_ctxtable
[curidx
] = NULL
;
1147 len
= (int)G_DMA_DSCRB_PKT_SIZE(dsc
->dscr_b
) - 4;
1150 * Check packet status. If good, process it.
1151 * If not, silently drop it and put it back on the
1155 if (likely (!(dsc
->dscr_a
& M_DMA_ETHRX_BAD
))) {
1158 * Add a new buffer to replace the old one. If we fail
1159 * to allocate a buffer, we're going to drop this
1160 * packet and put it right back on the receive ring.
1163 if (unlikely(sbdma_add_rcvbuffer(sc
, d
, NULL
) ==
1165 dev
->stats
.rx_dropped
++;
1166 /* Re-add old buffer */
1167 sbdma_add_rcvbuffer(sc
, d
, sb
);
1168 /* No point in continuing at the moment */
1169 printk(KERN_ERR
"dropped packet (1)\n");
1170 d
->sbdma_remptr
= SBDMA_NEXTBUF(d
,sbdma_remptr
);
1174 * Set length into the packet
1179 * Buffer has been replaced on the
1180 * receive ring. Pass the buffer to
1183 sb
->protocol
= eth_type_trans(sb
,d
->sbdma_eth
->sbm_dev
);
1184 /* Check hw IPv4/TCP checksum if supported */
1185 if (sc
->rx_hw_checksum
== ENABLE
) {
1186 if (!((dsc
->dscr_a
) & M_DMA_ETHRX_BADIP4CS
) &&
1187 !((dsc
->dscr_a
) & M_DMA_ETHRX_BADTCPCS
)) {
1188 sb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1189 /* don't need to set sb->csum */
1191 sb
->ip_summed
= CHECKSUM_NONE
;
1195 prefetch((const void *)(((char *)sb
->data
)+32));
1197 dropped
= netif_receive_skb(sb
);
1199 dropped
= netif_rx(sb
);
1201 if (dropped
== NET_RX_DROP
) {
1202 dev
->stats
.rx_dropped
++;
1203 d
->sbdma_remptr
= SBDMA_NEXTBUF(d
,sbdma_remptr
);
1207 dev
->stats
.rx_bytes
+= len
;
1208 dev
->stats
.rx_packets
++;
1213 * Packet was mangled somehow. Just drop it and
1214 * put it back on the receive ring.
1216 dev
->stats
.rx_errors
++;
1217 sbdma_add_rcvbuffer(sc
, d
, sb
);
1222 * .. and advance to the next buffer.
1225 d
->sbdma_remptr
= SBDMA_NEXTBUF(d
,sbdma_remptr
);
1230 goto again
; /* collect fifo drop statistics again */
1236 /**********************************************************************
1237 * SBDMA_TX_PROCESS(sc,d)
1239 * Process "completed" transmit buffers on the specified DMA channel.
1240 * This is normally called within the interrupt service routine.
1241 * Note that this isn't really ideal for priority channels, since
1242 * it processes all of the packets on a given channel before
1246 * sc - softc structure
1247 * d - DMA channel context
1248 * poll - 1: using polling (for NAPI)
1252 ********************************************************************* */
1254 static void sbdma_tx_process(struct sbmac_softc
*sc
, struct sbmacdma
*d
,
1257 struct net_device
*dev
= sc
->sbm_dev
;
1260 struct sbdmadscr
*dsc
;
1262 unsigned long flags
;
1263 int packets_handled
= 0;
1265 spin_lock_irqsave(&(sc
->sbm_lock
), flags
);
1267 if (d
->sbdma_remptr
== d
->sbdma_addptr
)
1270 hwidx
= ((__raw_readq(d
->sbdma_curdscr
) & M_DMA_CURDSCR_ADDR
) -
1271 d
->sbdma_dscrtable_phys
) / sizeof(*d
->sbdma_dscrtable
);
1275 * figure out where we are (as an index) and where
1276 * the hardware is (also as an index)
1278 * This could be done faster if (for example) the
1279 * descriptor table was page-aligned and contiguous in
1280 * both virtual and physical memory -- you could then
1281 * just compare the low-order bits of the virtual address
1282 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1285 curidx
= d
->sbdma_remptr
- d
->sbdma_dscrtable
;
1288 * If they're the same, that means we've processed all
1289 * of the descriptors up to (but not including) the one that
1290 * the hardware is working on right now.
1293 if (curidx
== hwidx
)
1297 * Otherwise, get the packet's sk_buff ptr back
1300 dsc
= &(d
->sbdma_dscrtable
[curidx
]);
1301 sb
= d
->sbdma_ctxtable
[curidx
];
1302 d
->sbdma_ctxtable
[curidx
] = NULL
;
1308 dev
->stats
.tx_bytes
+= sb
->len
;
1309 dev
->stats
.tx_packets
++;
1312 * for transmits, we just free buffers.
1315 dev_kfree_skb_irq(sb
);
1318 * .. and advance to the next buffer.
1321 d
->sbdma_remptr
= SBDMA_NEXTBUF(d
,sbdma_remptr
);
1328 * Decide if we should wake up the protocol or not.
1329 * Other drivers seem to do this when we reach a low
1330 * watermark on the transmit queue.
1333 if (packets_handled
)
1334 netif_wake_queue(d
->sbdma_eth
->sbm_dev
);
1337 spin_unlock_irqrestore(&(sc
->sbm_lock
), flags
);
1343 /**********************************************************************
1346 * Initialize an Ethernet context structure - this is called
1347 * once per MAC on the 1250. Memory is allocated here, so don't
1348 * call it again from inside the ioctl routines that bring the
1352 * s - sbmac context structure
1356 ********************************************************************* */
1358 static int sbmac_initctx(struct sbmac_softc
*s
)
1362 * figure out the addresses of some ports
1365 s
->sbm_macenable
= s
->sbm_base
+ R_MAC_ENABLE
;
1366 s
->sbm_maccfg
= s
->sbm_base
+ R_MAC_CFG
;
1367 s
->sbm_fifocfg
= s
->sbm_base
+ R_MAC_THRSH_CFG
;
1368 s
->sbm_framecfg
= s
->sbm_base
+ R_MAC_FRAMECFG
;
1369 s
->sbm_rxfilter
= s
->sbm_base
+ R_MAC_ADFILTER_CFG
;
1370 s
->sbm_isr
= s
->sbm_base
+ R_MAC_STATUS
;
1371 s
->sbm_imr
= s
->sbm_base
+ R_MAC_INT_MASK
;
1372 s
->sbm_mdio
= s
->sbm_base
+ R_MAC_MDIO
;
1375 * Initialize the DMA channels. Right now, only one per MAC is used
1376 * Note: Only do this _once_, as it allocates memory from the kernel!
1379 sbdma_initctx(&(s
->sbm_txdma
),s
,0,DMA_TX
,SBMAC_MAX_TXDESCR
);
1380 sbdma_initctx(&(s
->sbm_rxdma
),s
,0,DMA_RX
,SBMAC_MAX_RXDESCR
);
1383 * initial state is OFF
1386 s
->sbm_state
= sbmac_state_off
;
1392 static void sbdma_uninitctx(struct sbmacdma
*d
)
1394 if (d
->sbdma_dscrtable_unaligned
) {
1395 kfree(d
->sbdma_dscrtable_unaligned
);
1396 d
->sbdma_dscrtable_unaligned
= d
->sbdma_dscrtable
= NULL
;
1399 if (d
->sbdma_ctxtable
) {
1400 kfree(d
->sbdma_ctxtable
);
1401 d
->sbdma_ctxtable
= NULL
;
1406 static void sbmac_uninitctx(struct sbmac_softc
*sc
)
1408 sbdma_uninitctx(&(sc
->sbm_txdma
));
1409 sbdma_uninitctx(&(sc
->sbm_rxdma
));
1413 /**********************************************************************
1414 * SBMAC_CHANNEL_START(s)
1416 * Start packet processing on this MAC.
1419 * s - sbmac structure
1423 ********************************************************************* */
1425 static void sbmac_channel_start(struct sbmac_softc
*s
)
1429 uint64_t cfg
,fifo
,framecfg
;
1433 * Don't do this if running
1436 if (s
->sbm_state
== sbmac_state_on
)
1440 * Bring the controller out of reset, but leave it off.
1443 __raw_writeq(0, s
->sbm_macenable
);
1446 * Ignore all received packets
1449 __raw_writeq(0, s
->sbm_rxfilter
);
1452 * Calculate values for various control registers.
1455 cfg
= M_MAC_RETRY_EN
|
1456 M_MAC_TX_HOLD_SOP_EN
|
1457 V_MAC_TX_PAUSE_CNT_16K
|
1464 * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars
1465 * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above
1466 * Use a larger RD_THRSH for gigabit
1468 if (soc_type
== K_SYS_SOC_TYPE_BCM1250
&& periph_rev
< 2)
1473 fifo
= V_MAC_TX_WR_THRSH(4) | /* Must be '4' or '8' */
1474 ((s
->sbm_speed
== sbmac_speed_1000
)
1475 ? V_MAC_TX_RD_THRSH(th_value
) : V_MAC_TX_RD_THRSH(4)) |
1476 V_MAC_TX_RL_THRSH(4) |
1477 V_MAC_RX_PL_THRSH(4) |
1478 V_MAC_RX_RD_THRSH(4) | /* Must be '4' */
1479 V_MAC_RX_PL_THRSH(4) |
1480 V_MAC_RX_RL_THRSH(8) |
1483 framecfg
= V_MAC_MIN_FRAMESZ_DEFAULT
|
1484 V_MAC_MAX_FRAMESZ_DEFAULT
|
1485 V_MAC_BACKOFF_SEL(1);
1488 * Clear out the hash address map
1491 port
= s
->sbm_base
+ R_MAC_HASH_BASE
;
1492 for (idx
= 0; idx
< MAC_HASH_COUNT
; idx
++) {
1493 __raw_writeq(0, port
);
1494 port
+= sizeof(uint64_t);
1498 * Clear out the exact-match table
1501 port
= s
->sbm_base
+ R_MAC_ADDR_BASE
;
1502 for (idx
= 0; idx
< MAC_ADDR_COUNT
; idx
++) {
1503 __raw_writeq(0, port
);
1504 port
+= sizeof(uint64_t);
1508 * Clear out the DMA Channel mapping table registers
1511 port
= s
->sbm_base
+ R_MAC_CHUP0_BASE
;
1512 for (idx
= 0; idx
< MAC_CHMAP_COUNT
; idx
++) {
1513 __raw_writeq(0, port
);
1514 port
+= sizeof(uint64_t);
1518 port
= s
->sbm_base
+ R_MAC_CHLO0_BASE
;
1519 for (idx
= 0; idx
< MAC_CHMAP_COUNT
; idx
++) {
1520 __raw_writeq(0, port
);
1521 port
+= sizeof(uint64_t);
1525 * Program the hardware address. It goes into the hardware-address
1526 * register as well as the first filter register.
1529 reg
= sbmac_addr2reg(s
->sbm_hwaddr
);
1531 port
= s
->sbm_base
+ R_MAC_ADDR_BASE
;
1532 __raw_writeq(reg
, port
);
1533 port
= s
->sbm_base
+ R_MAC_ETHERNET_ADDR
;
1535 #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
1537 * Pass1 SOCs do not receive packets addressed to the
1538 * destination address in the R_MAC_ETHERNET_ADDR register.
1539 * Set the value to zero.
1541 __raw_writeq(0, port
);
1543 __raw_writeq(reg
, port
);
1547 * Set the receive filter for no packets, and write values
1548 * to the various config registers
1551 __raw_writeq(0, s
->sbm_rxfilter
);
1552 __raw_writeq(0, s
->sbm_imr
);
1553 __raw_writeq(framecfg
, s
->sbm_framecfg
);
1554 __raw_writeq(fifo
, s
->sbm_fifocfg
);
1555 __raw_writeq(cfg
, s
->sbm_maccfg
);
1558 * Initialize DMA channels (rings should be ok now)
1561 sbdma_channel_start(&(s
->sbm_rxdma
), DMA_RX
);
1562 sbdma_channel_start(&(s
->sbm_txdma
), DMA_TX
);
1565 * Configure the speed, duplex, and flow control
1568 sbmac_set_speed(s
,s
->sbm_speed
);
1569 sbmac_set_duplex(s
,s
->sbm_duplex
,s
->sbm_fc
);
1572 * Fill the receive ring
1575 sbdma_fillring(s
, &(s
->sbm_rxdma
));
1578 * Turn on the rest of the bits in the enable register
1581 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
1582 __raw_writeq(M_MAC_RXDMA_EN0
|
1583 M_MAC_TXDMA_EN0
, s
->sbm_macenable
);
1584 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
1585 __raw_writeq(M_MAC_RXDMA_EN0
|
1588 M_MAC_TX_ENABLE
, s
->sbm_macenable
);
1590 #error invalid SiByte MAC configuation
1593 #ifdef CONFIG_SBMAC_COALESCE
1594 __raw_writeq(((M_MAC_INT_EOP_COUNT
| M_MAC_INT_EOP_TIMER
) << S_MAC_TX_CH0
) |
1595 ((M_MAC_INT_EOP_COUNT
| M_MAC_INT_EOP_TIMER
) << S_MAC_RX_CH0
), s
->sbm_imr
);
1597 __raw_writeq((M_MAC_INT_CHANNEL
<< S_MAC_TX_CH0
) |
1598 (M_MAC_INT_CHANNEL
<< S_MAC_RX_CH0
), s
->sbm_imr
);
1602 * Enable receiving unicasts and broadcasts
1605 __raw_writeq(M_MAC_UCAST_EN
| M_MAC_BCAST_EN
, s
->sbm_rxfilter
);
1608 * we're running now.
1611 s
->sbm_state
= sbmac_state_on
;
1614 * Program multicast addresses
1620 * If channel was in promiscuous mode before, turn that on
1623 if (s
->sbm_devflags
& IFF_PROMISC
) {
1624 sbmac_promiscuous_mode(s
,1);
1630 /**********************************************************************
1631 * SBMAC_CHANNEL_STOP(s)
1633 * Stop packet processing on this MAC.
1636 * s - sbmac structure
1640 ********************************************************************* */
1642 static void sbmac_channel_stop(struct sbmac_softc
*s
)
1644 /* don't do this if already stopped */
1646 if (s
->sbm_state
== sbmac_state_off
)
1649 /* don't accept any packets, disable all interrupts */
1651 __raw_writeq(0, s
->sbm_rxfilter
);
1652 __raw_writeq(0, s
->sbm_imr
);
1654 /* Turn off ticker */
1658 /* turn off receiver and transmitter */
1660 __raw_writeq(0, s
->sbm_macenable
);
1662 /* We're stopped now. */
1664 s
->sbm_state
= sbmac_state_off
;
1667 * Stop DMA channels (rings should be ok now)
1670 sbdma_channel_stop(&(s
->sbm_rxdma
));
1671 sbdma_channel_stop(&(s
->sbm_txdma
));
1673 /* Empty the receive and transmit rings */
1675 sbdma_emptyring(&(s
->sbm_rxdma
));
1676 sbdma_emptyring(&(s
->sbm_txdma
));
1680 /**********************************************************************
1681 * SBMAC_SET_CHANNEL_STATE(state)
1683 * Set the channel's state ON or OFF
1690 ********************************************************************* */
1691 static enum sbmac_state
sbmac_set_channel_state(struct sbmac_softc
*sc
,
1692 enum sbmac_state state
)
1694 enum sbmac_state oldstate
= sc
->sbm_state
;
1697 * If same as previous state, return
1700 if (state
== oldstate
) {
1705 * If new state is ON, turn channel on
1708 if (state
== sbmac_state_on
) {
1709 sbmac_channel_start(sc
);
1712 sbmac_channel_stop(sc
);
1716 * Return previous state
1723 /**********************************************************************
1724 * SBMAC_PROMISCUOUS_MODE(sc,onoff)
1726 * Turn on or off promiscuous mode
1730 * onoff - 1 to turn on, 0 to turn off
1734 ********************************************************************* */
1736 static void sbmac_promiscuous_mode(struct sbmac_softc
*sc
,int onoff
)
1740 if (sc
->sbm_state
!= sbmac_state_on
)
1744 reg
= __raw_readq(sc
->sbm_rxfilter
);
1745 reg
|= M_MAC_ALLPKT_EN
;
1746 __raw_writeq(reg
, sc
->sbm_rxfilter
);
1749 reg
= __raw_readq(sc
->sbm_rxfilter
);
1750 reg
&= ~M_MAC_ALLPKT_EN
;
1751 __raw_writeq(reg
, sc
->sbm_rxfilter
);
1755 /**********************************************************************
1756 * SBMAC_SETIPHDR_OFFSET(sc,onoff)
1758 * Set the iphdr offset as 15 assuming ethernet encapsulation
1765 ********************************************************************* */
1767 static void sbmac_set_iphdr_offset(struct sbmac_softc
*sc
)
1771 /* Hard code the off set to 15 for now */
1772 reg
= __raw_readq(sc
->sbm_rxfilter
);
1773 reg
&= ~M_MAC_IPHDR_OFFSET
| V_MAC_IPHDR_OFFSET(15);
1774 __raw_writeq(reg
, sc
->sbm_rxfilter
);
1776 /* BCM1250 pass1 didn't have hardware checksum. Everything
1778 if (soc_type
== K_SYS_SOC_TYPE_BCM1250
&& periph_rev
< 2) {
1779 sc
->rx_hw_checksum
= DISABLE
;
1781 sc
->rx_hw_checksum
= ENABLE
;
1786 /**********************************************************************
1787 * SBMAC_ADDR2REG(ptr)
1789 * Convert six bytes into the 64-bit register value that
1790 * we typically write into the SBMAC's address/mcast registers
1793 * ptr - pointer to 6 bytes
1797 ********************************************************************* */
1799 static uint64_t sbmac_addr2reg(unsigned char *ptr
)
1805 reg
|= (uint64_t) *(--ptr
);
1807 reg
|= (uint64_t) *(--ptr
);
1809 reg
|= (uint64_t) *(--ptr
);
1811 reg
|= (uint64_t) *(--ptr
);
1813 reg
|= (uint64_t) *(--ptr
);
1815 reg
|= (uint64_t) *(--ptr
);
1821 /**********************************************************************
1822 * SBMAC_SET_SPEED(s,speed)
1824 * Configure LAN speed for the specified MAC.
1825 * Warning: must be called when MAC is off!
1828 * s - sbmac structure
1829 * speed - speed to set MAC to (see enum sbmac_speed)
1833 * 0 indicates invalid parameters
1834 ********************************************************************* */
1836 static int sbmac_set_speed(struct sbmac_softc
*s
, enum sbmac_speed speed
)
1842 * Save new current values
1845 s
->sbm_speed
= speed
;
1847 if (s
->sbm_state
== sbmac_state_on
)
1848 return 0; /* save for next restart */
1851 * Read current register values
1854 cfg
= __raw_readq(s
->sbm_maccfg
);
1855 framecfg
= __raw_readq(s
->sbm_framecfg
);
1858 * Mask out the stuff we want to change
1861 cfg
&= ~(M_MAC_BURST_EN
| M_MAC_SPEED_SEL
);
1862 framecfg
&= ~(M_MAC_IFG_RX
| M_MAC_IFG_TX
| M_MAC_IFG_THRSH
|
1866 * Now add in the new bits
1870 case sbmac_speed_10
:
1871 framecfg
|= V_MAC_IFG_RX_10
|
1873 K_MAC_IFG_THRSH_10
|
1875 cfg
|= V_MAC_SPEED_SEL_10MBPS
;
1878 case sbmac_speed_100
:
1879 framecfg
|= V_MAC_IFG_RX_100
|
1881 V_MAC_IFG_THRSH_100
|
1882 V_MAC_SLOT_SIZE_100
;
1883 cfg
|= V_MAC_SPEED_SEL_100MBPS
;
1886 case sbmac_speed_1000
:
1887 framecfg
|= V_MAC_IFG_RX_1000
|
1889 V_MAC_IFG_THRSH_1000
|
1890 V_MAC_SLOT_SIZE_1000
;
1891 cfg
|= V_MAC_SPEED_SEL_1000MBPS
| M_MAC_BURST_EN
;
1899 * Send the bits back to the hardware
1902 __raw_writeq(framecfg
, s
->sbm_framecfg
);
1903 __raw_writeq(cfg
, s
->sbm_maccfg
);
1908 /**********************************************************************
1909 * SBMAC_SET_DUPLEX(s,duplex,fc)
1911 * Set Ethernet duplex and flow control options for this MAC
1912 * Warning: must be called when MAC is off!
1915 * s - sbmac structure
1916 * duplex - duplex setting (see enum sbmac_duplex)
1917 * fc - flow control setting (see enum sbmac_fc)
1921 * 0 if an invalid parameter combination was specified
1922 ********************************************************************* */
1924 static int sbmac_set_duplex(struct sbmac_softc
*s
, enum sbmac_duplex duplex
,
1930 * Save new current values
1933 s
->sbm_duplex
= duplex
;
1936 if (s
->sbm_state
== sbmac_state_on
)
1937 return 0; /* save for next restart */
1940 * Read current register values
1943 cfg
= __raw_readq(s
->sbm_maccfg
);
1946 * Mask off the stuff we're about to change
1949 cfg
&= ~(M_MAC_FC_SEL
| M_MAC_FC_CMD
| M_MAC_HDX_EN
);
1953 case sbmac_duplex_half
:
1955 case sbmac_fc_disabled
:
1956 cfg
|= M_MAC_HDX_EN
| V_MAC_FC_CMD_DISABLED
;
1959 case sbmac_fc_collision
:
1960 cfg
|= M_MAC_HDX_EN
| V_MAC_FC_CMD_ENABLED
;
1963 case sbmac_fc_carrier
:
1964 cfg
|= M_MAC_HDX_EN
| V_MAC_FC_CMD_ENAB_FALSECARR
;
1967 case sbmac_fc_frame
: /* not valid in half duplex */
1968 default: /* invalid selection */
1973 case sbmac_duplex_full
:
1975 case sbmac_fc_disabled
:
1976 cfg
|= V_MAC_FC_CMD_DISABLED
;
1979 case sbmac_fc_frame
:
1980 cfg
|= V_MAC_FC_CMD_ENABLED
;
1983 case sbmac_fc_collision
: /* not valid in full duplex */
1984 case sbmac_fc_carrier
: /* not valid in full duplex */
1994 * Send the bits back to the hardware
1997 __raw_writeq(cfg
, s
->sbm_maccfg
);
2005 /**********************************************************************
2008 * Interrupt handler for MAC interrupts
2015 ********************************************************************* */
2016 static irqreturn_t
sbmac_intr(int irq
,void *dev_instance
)
2018 struct net_device
*dev
= (struct net_device
*) dev_instance
;
2019 struct sbmac_softc
*sc
= netdev_priv(dev
);
2024 * Read the ISR (this clears the bits in the real
2025 * register, except for counter addr)
2028 isr
= __raw_readq(sc
->sbm_isr
) & ~M_MAC_COUNTER_ADDR
;
2031 return IRQ_RETVAL(0);
2035 * Transmits on channel 0
2038 if (isr
& (M_MAC_INT_CHANNEL
<< S_MAC_TX_CH0
))
2039 sbdma_tx_process(sc
,&(sc
->sbm_txdma
), 0);
2041 if (isr
& (M_MAC_INT_CHANNEL
<< S_MAC_RX_CH0
)) {
2042 if (napi_schedule_prep(&sc
->napi
)) {
2043 __raw_writeq(0, sc
->sbm_imr
);
2044 __napi_schedule(&sc
->napi
);
2045 /* Depend on the exit from poll to reenable intr */
2048 /* may leave some packets behind */
2049 sbdma_rx_process(sc
,&(sc
->sbm_rxdma
),
2050 SBMAC_MAX_RXDESCR
* 2, 0);
2053 return IRQ_RETVAL(handled
);
2056 /**********************************************************************
2057 * SBMAC_START_TX(skb,dev)
2059 * Start output on the specified interface. Basically, we
2060 * queue as many buffers as we can until the ring fills up, or
2061 * we run off the end of the queue, whichever comes first.
2068 ********************************************************************* */
2069 static int sbmac_start_tx(struct sk_buff
*skb
, struct net_device
*dev
)
2071 struct sbmac_softc
*sc
= netdev_priv(dev
);
2072 unsigned long flags
;
2075 spin_lock_irqsave(&sc
->sbm_lock
, flags
);
2078 * Put the buffer on the transmit ring. If we
2079 * don't have room, stop the queue.
2082 if (sbdma_add_txbuffer(&(sc
->sbm_txdma
),skb
)) {
2083 /* XXX save skb that we could not send */
2084 netif_stop_queue(dev
);
2085 spin_unlock_irqrestore(&sc
->sbm_lock
, flags
);
2090 dev
->trans_start
= jiffies
;
2092 spin_unlock_irqrestore(&sc
->sbm_lock
, flags
);
2097 /**********************************************************************
2098 * SBMAC_SETMULTI(sc)
2100 * Reprogram the multicast table into the hardware, given
2101 * the list of multicasts associated with the interface
2109 ********************************************************************* */
2111 static void sbmac_setmulti(struct sbmac_softc
*sc
)
2116 struct dev_mc_list
*mclist
;
2117 struct net_device
*dev
= sc
->sbm_dev
;
2120 * Clear out entire multicast table. We do this by nuking
2121 * the entire hash table and all the direct matches except
2122 * the first one, which is used for our station address
2125 for (idx
= 1; idx
< MAC_ADDR_COUNT
; idx
++) {
2126 port
= sc
->sbm_base
+ R_MAC_ADDR_BASE
+(idx
*sizeof(uint64_t));
2127 __raw_writeq(0, port
);
2130 for (idx
= 0; idx
< MAC_HASH_COUNT
; idx
++) {
2131 port
= sc
->sbm_base
+ R_MAC_HASH_BASE
+(idx
*sizeof(uint64_t));
2132 __raw_writeq(0, port
);
2136 * Clear the filter to say we don't want any multicasts.
2139 reg
= __raw_readq(sc
->sbm_rxfilter
);
2140 reg
&= ~(M_MAC_MCAST_INV
| M_MAC_MCAST_EN
);
2141 __raw_writeq(reg
, sc
->sbm_rxfilter
);
2143 if (dev
->flags
& IFF_ALLMULTI
) {
2145 * Enable ALL multicasts. Do this by inverting the
2146 * multicast enable bit.
2148 reg
= __raw_readq(sc
->sbm_rxfilter
);
2149 reg
|= (M_MAC_MCAST_INV
| M_MAC_MCAST_EN
);
2150 __raw_writeq(reg
, sc
->sbm_rxfilter
);
2156 * Progam new multicast entries. For now, only use the
2157 * perfect filter. In the future we'll need to use the
2158 * hash filter if the perfect filter overflows
2161 /* XXX only using perfect filter for now, need to use hash
2162 * XXX if the table overflows */
2164 idx
= 1; /* skip station address */
2165 mclist
= dev
->mc_list
;
2166 while (mclist
&& (idx
< MAC_ADDR_COUNT
)) {
2167 reg
= sbmac_addr2reg(mclist
->dmi_addr
);
2168 port
= sc
->sbm_base
+ R_MAC_ADDR_BASE
+(idx
* sizeof(uint64_t));
2169 __raw_writeq(reg
, port
);
2171 mclist
= mclist
->next
;
2175 * Enable the "accept multicast bits" if we programmed at least one
2180 reg
= __raw_readq(sc
->sbm_rxfilter
);
2181 reg
|= M_MAC_MCAST_EN
;
2182 __raw_writeq(reg
, sc
->sbm_rxfilter
);
2186 #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) || defined(SBMAC_ETH3_HWADDR)
2187 /**********************************************************************
2188 * SBMAC_PARSE_XDIGIT(str)
2190 * Parse a hex digit, returning its value
2196 * hex value, or -1 if invalid
2197 ********************************************************************* */
2199 static int sbmac_parse_xdigit(char str
)
2203 if ((str
>= '0') && (str
<= '9'))
2205 else if ((str
>= 'a') && (str
<= 'f'))
2206 digit
= str
- 'a' + 10;
2207 else if ((str
>= 'A') && (str
<= 'F'))
2208 digit
= str
- 'A' + 10;
2215 /**********************************************************************
2216 * SBMAC_PARSE_HWADDR(str,hwaddr)
2218 * Convert a string in the form xx:xx:xx:xx:xx:xx into a 6-byte
2223 * hwaddr - pointer to hardware address
2227 ********************************************************************* */
2229 static int sbmac_parse_hwaddr(char *str
, unsigned char *hwaddr
)
2234 while (*str
&& (idx
> 0)) {
2235 digit1
= sbmac_parse_xdigit(*str
);
2242 if ((*str
== ':') || (*str
== '-')) {
2247 digit2
= sbmac_parse_xdigit(*str
);
2253 *hwaddr
++ = (digit1
<< 4) | digit2
;
2265 static int sb1250_change_mtu(struct net_device
*_dev
, int new_mtu
)
2267 if (new_mtu
> ENET_PACKET_SIZE
)
2269 _dev
->mtu
= new_mtu
;
2270 pr_info("changing the mtu to %d\n", new_mtu
);
2274 /**********************************************************************
2277 * Attach routine - init hardware and hook ourselves into linux
2280 * dev - net_device structure
2284 ********************************************************************* */
2286 static int sbmac_init(struct platform_device
*pldev
, long long base
)
2288 struct net_device
*dev
= pldev
->dev
.driver_data
;
2289 int idx
= pldev
->id
;
2290 struct sbmac_softc
*sc
= netdev_priv(dev
);
2291 unsigned char *eaddr
;
2299 eaddr
= sc
->sbm_hwaddr
;
2302 * Read the ethernet address. The firmware left this programmed
2303 * for us in the ethernet address register for each mac.
2306 ea_reg
= __raw_readq(sc
->sbm_base
+ R_MAC_ETHERNET_ADDR
);
2307 __raw_writeq(0, sc
->sbm_base
+ R_MAC_ETHERNET_ADDR
);
2308 for (i
= 0; i
< 6; i
++) {
2309 eaddr
[i
] = (uint8_t) (ea_reg
& 0xFF);
2313 for (i
= 0; i
< 6; i
++) {
2314 dev
->dev_addr
[i
] = eaddr
[i
];
2318 * Initialize context (get pointers to registers and stuff), then
2319 * allocate the memory for the descriptor tables.
2325 * Set up Linux device callins
2328 spin_lock_init(&(sc
->sbm_lock
));
2330 dev
->open
= sbmac_open
;
2331 dev
->hard_start_xmit
= sbmac_start_tx
;
2332 dev
->stop
= sbmac_close
;
2333 dev
->set_multicast_list
= sbmac_set_rx_mode
;
2334 dev
->do_ioctl
= sbmac_mii_ioctl
;
2335 dev
->tx_timeout
= sbmac_tx_timeout
;
2336 dev
->watchdog_timeo
= TX_TIMEOUT
;
2338 netif_napi_add(dev
, &sc
->napi
, sbmac_poll
, 16);
2340 dev
->change_mtu
= sb1250_change_mtu
;
2341 #ifdef CONFIG_NET_POLL_CONTROLLER
2342 dev
->poll_controller
= sbmac_netpoll
;
2345 dev
->irq
= UNIT_INT(idx
);
2347 /* This is needed for PASS2 for Rx H/W checksum feature */
2348 sbmac_set_iphdr_offset(sc
);
2350 sc
->mii_bus
= mdiobus_alloc();
2351 if (sc
->mii_bus
== NULL
) {
2352 sbmac_uninitctx(sc
);
2356 err
= register_netdev(dev
);
2358 printk(KERN_ERR
"%s.%d: unable to register netdev\n",
2360 mdiobus_free(sc
->mii_bus
);
2361 sbmac_uninitctx(sc
);
2365 pr_info("%s.%d: registered as %s\n", sbmac_string
, idx
, dev
->name
);
2367 if (sc
->rx_hw_checksum
== ENABLE
)
2368 pr_info("%s: enabling TCP rcv checksum\n", dev
->name
);
2371 * Display Ethernet address (this is called during the config
2372 * process so we need to finish off the config message that
2373 * was being displayed)
2375 pr_info("%s: SiByte Ethernet at 0x%08Lx, address: %pM\n",
2376 dev
->name
, base
, eaddr
);
2378 sc
->mii_bus
->name
= sbmac_mdio_string
;
2379 snprintf(sc
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%x", idx
);
2380 sc
->mii_bus
->priv
= sc
;
2381 sc
->mii_bus
->read
= sbmac_mii_read
;
2382 sc
->mii_bus
->write
= sbmac_mii_write
;
2383 sc
->mii_bus
->irq
= sc
->phy_irq
;
2384 for (i
= 0; i
< PHY_MAX_ADDR
; ++i
)
2385 sc
->mii_bus
->irq
[i
] = SBMAC_PHY_INT
;
2387 sc
->mii_bus
->parent
= &pldev
->dev
;
2388 dev_set_drvdata(&pldev
->dev
, sc
->mii_bus
);
2394 static int sbmac_open(struct net_device
*dev
)
2396 struct sbmac_softc
*sc
= netdev_priv(dev
);
2400 pr_debug("%s: sbmac_open() irq %d.\n", dev
->name
, dev
->irq
);
2403 * map/route interrupt (clear status first, in case something
2404 * weird is pending; we haven't initialized the mac registers
2408 __raw_readq(sc
->sbm_isr
);
2409 err
= request_irq(dev
->irq
, &sbmac_intr
, IRQF_SHARED
, dev
->name
, dev
);
2411 printk(KERN_ERR
"%s: unable to get IRQ %d\n", dev
->name
,
2419 err
= mdiobus_register(sc
->mii_bus
);
2421 printk(KERN_ERR
"%s: unable to register MDIO bus\n",
2426 sc
->sbm_speed
= sbmac_speed_none
;
2427 sc
->sbm_duplex
= sbmac_duplex_none
;
2428 sc
->sbm_fc
= sbmac_fc_none
;
2435 err
= sbmac_mii_probe(dev
);
2437 goto out_unregister
;
2440 * Turn on the channel
2443 sbmac_set_channel_state(sc
,sbmac_state_on
);
2445 netif_start_queue(dev
);
2447 sbmac_set_rx_mode(dev
);
2449 phy_start(sc
->phy_dev
);
2451 napi_enable(&sc
->napi
);
2456 mdiobus_unregister(sc
->mii_bus
);
2459 free_irq(dev
->irq
, dev
);
2465 static int sbmac_mii_probe(struct net_device
*dev
)
2467 struct sbmac_softc
*sc
= netdev_priv(dev
);
2468 struct phy_device
*phy_dev
;
2471 for (i
= 0; i
< PHY_MAX_ADDR
; i
++) {
2472 phy_dev
= sc
->mii_bus
->phy_map
[i
];
2477 printk(KERN_ERR
"%s: no PHY found\n", dev
->name
);
2481 phy_dev
= phy_connect(dev
, dev_name(&phy_dev
->dev
), &sbmac_mii_poll
, 0,
2482 PHY_INTERFACE_MODE_GMII
);
2483 if (IS_ERR(phy_dev
)) {
2484 printk(KERN_ERR
"%s: could not attach to PHY\n", dev
->name
);
2485 return PTR_ERR(phy_dev
);
2488 /* Remove any features not supported by the controller */
2489 phy_dev
->supported
&= SUPPORTED_10baseT_Half
|
2490 SUPPORTED_10baseT_Full
|
2491 SUPPORTED_100baseT_Half
|
2492 SUPPORTED_100baseT_Full
|
2493 SUPPORTED_1000baseT_Half
|
2494 SUPPORTED_1000baseT_Full
|
2498 SUPPORTED_Asym_Pause
;
2499 phy_dev
->advertising
= phy_dev
->supported
;
2501 pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
2502 dev
->name
, phy_dev
->drv
->name
,
2503 dev_name(&phy_dev
->dev
), phy_dev
->irq
);
2505 sc
->phy_dev
= phy_dev
;
2511 static void sbmac_mii_poll(struct net_device
*dev
)
2513 struct sbmac_softc
*sc
= netdev_priv(dev
);
2514 struct phy_device
*phy_dev
= sc
->phy_dev
;
2515 unsigned long flags
;
2517 int link_chg
, speed_chg
, duplex_chg
, pause_chg
, fc_chg
;
2519 link_chg
= (sc
->sbm_link
!= phy_dev
->link
);
2520 speed_chg
= (sc
->sbm_speed
!= phy_dev
->speed
);
2521 duplex_chg
= (sc
->sbm_duplex
!= phy_dev
->duplex
);
2522 pause_chg
= (sc
->sbm_pause
!= phy_dev
->pause
);
2524 if (!link_chg
&& !speed_chg
&& !duplex_chg
&& !pause_chg
)
2525 return; /* Hmmm... */
2527 if (!phy_dev
->link
) {
2529 sc
->sbm_link
= phy_dev
->link
;
2530 sc
->sbm_speed
= sbmac_speed_none
;
2531 sc
->sbm_duplex
= sbmac_duplex_none
;
2532 sc
->sbm_fc
= sbmac_fc_disabled
;
2534 pr_info("%s: link unavailable\n", dev
->name
);
2539 if (phy_dev
->duplex
== DUPLEX_FULL
) {
2541 fc
= sbmac_fc_frame
;
2543 fc
= sbmac_fc_disabled
;
2545 fc
= sbmac_fc_collision
;
2546 fc_chg
= (sc
->sbm_fc
!= fc
);
2548 pr_info("%s: link available: %dbase-%cD\n", dev
->name
, phy_dev
->speed
,
2549 phy_dev
->duplex
== DUPLEX_FULL
? 'F' : 'H');
2551 spin_lock_irqsave(&sc
->sbm_lock
, flags
);
2553 sc
->sbm_speed
= phy_dev
->speed
;
2554 sc
->sbm_duplex
= phy_dev
->duplex
;
2556 sc
->sbm_pause
= phy_dev
->pause
;
2557 sc
->sbm_link
= phy_dev
->link
;
2559 if ((speed_chg
|| duplex_chg
|| fc_chg
) &&
2560 sc
->sbm_state
!= sbmac_state_off
) {
2562 * something changed, restart the channel
2565 pr_debug("%s: restarting channel "
2566 "because PHY state changed\n", dev
->name
);
2567 sbmac_channel_stop(sc
);
2568 sbmac_channel_start(sc
);
2571 spin_unlock_irqrestore(&sc
->sbm_lock
, flags
);
2575 static void sbmac_tx_timeout (struct net_device
*dev
)
2577 struct sbmac_softc
*sc
= netdev_priv(dev
);
2578 unsigned long flags
;
2580 spin_lock_irqsave(&sc
->sbm_lock
, flags
);
2583 dev
->trans_start
= jiffies
;
2584 dev
->stats
.tx_errors
++;
2586 spin_unlock_irqrestore(&sc
->sbm_lock
, flags
);
2588 printk (KERN_WARNING
"%s: Transmit timed out\n",dev
->name
);
2594 static void sbmac_set_rx_mode(struct net_device
*dev
)
2596 unsigned long flags
;
2597 struct sbmac_softc
*sc
= netdev_priv(dev
);
2599 spin_lock_irqsave(&sc
->sbm_lock
, flags
);
2600 if ((dev
->flags
^ sc
->sbm_devflags
) & IFF_PROMISC
) {
2602 * Promiscuous changed.
2605 if (dev
->flags
& IFF_PROMISC
) {
2606 sbmac_promiscuous_mode(sc
,1);
2609 sbmac_promiscuous_mode(sc
,0);
2612 spin_unlock_irqrestore(&sc
->sbm_lock
, flags
);
2615 * Program the multicasts. Do this every time.
2622 static int sbmac_mii_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
2624 struct sbmac_softc
*sc
= netdev_priv(dev
);
2626 if (!netif_running(dev
) || !sc
->phy_dev
)
2629 return phy_mii_ioctl(sc
->phy_dev
, if_mii(rq
), cmd
);
2632 static int sbmac_close(struct net_device
*dev
)
2634 struct sbmac_softc
*sc
= netdev_priv(dev
);
2636 napi_disable(&sc
->napi
);
2638 phy_stop(sc
->phy_dev
);
2640 sbmac_set_channel_state(sc
, sbmac_state_off
);
2642 netif_stop_queue(dev
);
2645 pr_debug("%s: Shutting down ethercard\n", dev
->name
);
2647 phy_disconnect(sc
->phy_dev
);
2650 mdiobus_unregister(sc
->mii_bus
);
2652 free_irq(dev
->irq
, dev
);
2654 sbdma_emptyring(&(sc
->sbm_txdma
));
2655 sbdma_emptyring(&(sc
->sbm_rxdma
));
2660 static int sbmac_poll(struct napi_struct
*napi
, int budget
)
2662 struct sbmac_softc
*sc
= container_of(napi
, struct sbmac_softc
, napi
);
2663 struct net_device
*dev
= sc
->sbm_dev
;
2666 work_done
= sbdma_rx_process(sc
, &(sc
->sbm_rxdma
), budget
, 1);
2667 sbdma_tx_process(sc
, &(sc
->sbm_txdma
), 1);
2669 if (work_done
< budget
) {
2670 napi_complete(napi
);
2672 #ifdef CONFIG_SBMAC_COALESCE
2673 __raw_writeq(((M_MAC_INT_EOP_COUNT
| M_MAC_INT_EOP_TIMER
) << S_MAC_TX_CH0
) |
2674 ((M_MAC_INT_EOP_COUNT
| M_MAC_INT_EOP_TIMER
) << S_MAC_RX_CH0
),
2677 __raw_writeq((M_MAC_INT_CHANNEL
<< S_MAC_TX_CH0
) |
2678 (M_MAC_INT_CHANNEL
<< S_MAC_RX_CH0
), sc
->sbm_imr
);
2686 static int __init
sbmac_probe(struct platform_device
*pldev
)
2688 struct net_device
*dev
;
2689 struct sbmac_softc
*sc
;
2690 void __iomem
*sbm_base
;
2691 struct resource
*res
;
2692 u64 sbmac_orig_hwaddr
;
2695 res
= platform_get_resource(pldev
, IORESOURCE_MEM
, 0);
2697 sbm_base
= ioremap_nocache(res
->start
, res
->end
- res
->start
+ 1);
2699 printk(KERN_ERR
"%s: unable to map device registers\n",
2700 dev_name(&pldev
->dev
));
2706 * The R_MAC_ETHERNET_ADDR register will be set to some nonzero
2707 * value for us by the firmware if we're going to use this MAC.
2708 * If we find a zero, skip this MAC.
2710 sbmac_orig_hwaddr
= __raw_readq(sbm_base
+ R_MAC_ETHERNET_ADDR
);
2711 pr_debug("%s: %sconfiguring MAC at 0x%08Lx\n", dev_name(&pldev
->dev
),
2712 sbmac_orig_hwaddr
? "" : "not ", (long long)res
->start
);
2713 if (sbmac_orig_hwaddr
== 0) {
2719 * Okay, cool. Initialize this MAC.
2721 dev
= alloc_etherdev(sizeof(struct sbmac_softc
));
2723 printk(KERN_ERR
"%s: unable to allocate etherdev\n",
2724 dev_name(&pldev
->dev
));
2729 pldev
->dev
.driver_data
= dev
;
2730 SET_NETDEV_DEV(dev
, &pldev
->dev
);
2732 sc
= netdev_priv(dev
);
2733 sc
->sbm_base
= sbm_base
;
2735 err
= sbmac_init(pldev
, res
->start
);
2743 __raw_writeq(sbmac_orig_hwaddr
, sbm_base
+ R_MAC_ETHERNET_ADDR
);
2752 static int __exit
sbmac_remove(struct platform_device
*pldev
)
2754 struct net_device
*dev
= pldev
->dev
.driver_data
;
2755 struct sbmac_softc
*sc
= netdev_priv(dev
);
2757 unregister_netdev(dev
);
2758 sbmac_uninitctx(sc
);
2759 mdiobus_free(sc
->mii_bus
);
2760 iounmap(sc
->sbm_base
);
2767 static struct platform_device
**sbmac_pldev
;
2768 static int sbmac_max_units
;
2770 #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) || defined(SBMAC_ETH3_HWADDR)
2771 static void __init
sbmac_setup_hwaddr(int idx
, char *addr
)
2773 void __iomem
*sbm_base
;
2774 unsigned long start
, end
;
2778 if (idx
>= sbmac_max_units
)
2781 start
= A_MAC_CHANNEL_BASE(idx
);
2782 end
= A_MAC_CHANNEL_BASE(idx
+ 1) - 1;
2784 sbm_base
= ioremap_nocache(start
, end
- start
+ 1);
2786 printk(KERN_ERR
"%s: unable to map device registers\n",
2791 sbmac_parse_hwaddr(addr
, eaddr
);
2792 val
= sbmac_addr2reg(eaddr
);
2793 __raw_writeq(val
, sbm_base
+ R_MAC_ETHERNET_ADDR
);
2794 val
= __raw_readq(sbm_base
+ R_MAC_ETHERNET_ADDR
);
2800 static int __init
sbmac_platform_probe_one(int idx
)
2802 struct platform_device
*pldev
;
2805 char name
[strlen(sbmac_pretty
) + 4];
2809 res
= kzalloc(sizeof(*res
), GFP_KERNEL
);
2811 printk(KERN_ERR
"%s.%d: unable to allocate memory\n",
2818 * This is the base address of the MAC.
2820 snprintf(res
->name
, sizeof(res
->name
), "%s %d", sbmac_pretty
, idx
);
2821 res
->r
.name
= res
->name
;
2822 res
->r
.flags
= IORESOURCE_MEM
;
2823 res
->r
.start
= A_MAC_CHANNEL_BASE(idx
);
2824 res
->r
.end
= A_MAC_CHANNEL_BASE(idx
+ 1) - 1;
2826 pldev
= platform_device_register_simple(sbmac_string
, idx
, &res
->r
, 1);
2827 if (IS_ERR(pldev
)) {
2828 printk(KERN_ERR
"%s.%d: unable to register platform device\n",
2830 err
= PTR_ERR(pldev
);
2834 if (!pldev
->dev
.driver
) {
2835 err
= 0; /* No hardware at this address. */
2836 goto out_unregister
;
2839 sbmac_pldev
[idx
] = pldev
;
2843 platform_device_unregister(pldev
);
2852 static void __init
sbmac_platform_probe(void)
2856 /* Set the number of available units based on the SOC type. */
2858 case K_SYS_SOC_TYPE_BCM1250
:
2859 case K_SYS_SOC_TYPE_BCM1250_ALT
:
2860 sbmac_max_units
= 3;
2862 case K_SYS_SOC_TYPE_BCM1120
:
2863 case K_SYS_SOC_TYPE_BCM1125
:
2864 case K_SYS_SOC_TYPE_BCM1125H
:
2865 case K_SYS_SOC_TYPE_BCM1250_ALT2
: /* Hybrid */
2866 sbmac_max_units
= 2;
2868 case K_SYS_SOC_TYPE_BCM1x55
:
2869 case K_SYS_SOC_TYPE_BCM1x80
:
2870 sbmac_max_units
= 4;
2877 * For bringup when not using the firmware, we can pre-fill
2878 * the MAC addresses using the environment variables
2879 * specified in this file (or maybe from the config file?)
2881 #ifdef SBMAC_ETH0_HWADDR
2882 sbmac_setup_hwaddr(0, SBMAC_ETH0_HWADDR
);
2884 #ifdef SBMAC_ETH1_HWADDR
2885 sbmac_setup_hwaddr(1, SBMAC_ETH1_HWADDR
);
2887 #ifdef SBMAC_ETH2_HWADDR
2888 sbmac_setup_hwaddr(2, SBMAC_ETH2_HWADDR
);
2890 #ifdef SBMAC_ETH3_HWADDR
2891 sbmac_setup_hwaddr(3, SBMAC_ETH3_HWADDR
);
2894 sbmac_pldev
= kcalloc(sbmac_max_units
, sizeof(*sbmac_pldev
),
2897 printk(KERN_ERR
"%s: unable to allocate memory\n",
2903 * Walk through the Ethernet controllers and find
2904 * those who have their MAC addresses set.
2906 for (i
= 0; i
< sbmac_max_units
; i
++)
2907 if (sbmac_platform_probe_one(i
))
2912 static void __exit
sbmac_platform_cleanup(void)
2916 for (i
= 0; i
< sbmac_max_units
; i
++)
2917 platform_device_unregister(sbmac_pldev
[i
]);
2922 static struct platform_driver sbmac_driver
= {
2923 .probe
= sbmac_probe
,
2924 .remove
= __exit_p(sbmac_remove
),
2926 .name
= sbmac_string
,
2930 static int __init
sbmac_init_module(void)
2934 err
= platform_driver_register(&sbmac_driver
);
2938 sbmac_platform_probe();
2943 static void __exit
sbmac_cleanup_module(void)
2945 sbmac_platform_cleanup();
2946 platform_driver_unregister(&sbmac_driver
);
2949 module_init(sbmac_init_module
);
2950 module_exit(sbmac_cleanup_module
);