1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
3 * Copyright 1996-1999 Thomas Bogendoerfer
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
13 * This driver is for PCnet32 and PCnetPCI based ethercards
15 /**************************************************************************
17 * Fixed a few bugs, related to running the controller in 32bit mode.
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
22 *************************************************************************/
24 #define DRV_NAME "pcnet32"
25 #define DRV_VERSION "1.35"
26 #define DRV_RELDATE "21.Apr.2008"
27 #define PFX DRV_NAME ": "
29 static const char *const version
=
30 DRV_NAME
".c:v" DRV_VERSION
" " DRV_RELDATE
" tsbogend@alpha.franken.de\n";
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/string.h>
35 #include <linux/errno.h>
36 #include <linux/ioport.h>
37 #include <linux/slab.h>
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
40 #include <linux/delay.h>
41 #include <linux/init.h>
42 #include <linux/ethtool.h>
43 #include <linux/mii.h>
44 #include <linux/crc32.h>
45 #include <linux/netdevice.h>
46 #include <linux/etherdevice.h>
47 #include <linux/skbuff.h>
48 #include <linux/spinlock.h>
49 #include <linux/moduleparam.h>
50 #include <linux/bitops.h>
54 #include <asm/uaccess.h>
58 * PCI device identifiers for "new style" Linux PCI Device Drivers
60 static struct pci_device_id pcnet32_pci_tbl
[] = {
61 { PCI_DEVICE(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_LANCE_HOME
), },
62 { PCI_DEVICE(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_LANCE
), },
65 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
66 * the incorrect vendor id.
68 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT
, PCI_DEVICE_ID_AMD_LANCE
),
69 .class = (PCI_CLASS_NETWORK_ETHERNET
<< 8), .class_mask
= 0xffff00, },
71 { } /* terminate list */
74 MODULE_DEVICE_TABLE(pci
, pcnet32_pci_tbl
);
76 static int cards_found
;
81 static unsigned int pcnet32_portlist
[] __initdata
=
82 { 0x300, 0x320, 0x340, 0x360, 0 };
84 static int pcnet32_debug
= 0;
85 static int tx_start
= 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
86 static int pcnet32vlb
; /* check for VLB cards ? */
88 static struct net_device
*pcnet32_dev
;
90 static int max_interrupt_work
= 2;
91 static int rx_copybreak
= 200;
93 #define PCNET32_PORT_AUI 0x00
94 #define PCNET32_PORT_10BT 0x01
95 #define PCNET32_PORT_GPSI 0x02
96 #define PCNET32_PORT_MII 0x03
98 #define PCNET32_PORT_PORTSEL 0x03
99 #define PCNET32_PORT_ASEL 0x04
100 #define PCNET32_PORT_100 0x40
101 #define PCNET32_PORT_FD 0x80
103 #define PCNET32_DMA_MASK 0xffffffff
105 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
106 #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
109 * table to translate option values from tulip
110 * to internal options
112 static const unsigned char options_mapping
[] = {
113 PCNET32_PORT_ASEL
, /* 0 Auto-select */
114 PCNET32_PORT_AUI
, /* 1 BNC/AUI */
115 PCNET32_PORT_AUI
, /* 2 AUI/BNC */
116 PCNET32_PORT_ASEL
, /* 3 not supported */
117 PCNET32_PORT_10BT
| PCNET32_PORT_FD
, /* 4 10baseT-FD */
118 PCNET32_PORT_ASEL
, /* 5 not supported */
119 PCNET32_PORT_ASEL
, /* 6 not supported */
120 PCNET32_PORT_ASEL
, /* 7 not supported */
121 PCNET32_PORT_ASEL
, /* 8 not supported */
122 PCNET32_PORT_MII
, /* 9 MII 10baseT */
123 PCNET32_PORT_MII
| PCNET32_PORT_FD
, /* 10 MII 10baseT-FD */
124 PCNET32_PORT_MII
, /* 11 MII (autosel) */
125 PCNET32_PORT_10BT
, /* 12 10BaseT */
126 PCNET32_PORT_MII
| PCNET32_PORT_100
, /* 13 MII 100BaseTx */
127 /* 14 MII 100BaseTx-FD */
128 PCNET32_PORT_MII
| PCNET32_PORT_100
| PCNET32_PORT_FD
,
129 PCNET32_PORT_ASEL
/* 15 not supported */
132 static const char pcnet32_gstrings_test
[][ETH_GSTRING_LEN
] = {
133 "Loopback test (offline)"
136 #define PCNET32_TEST_LEN ARRAY_SIZE(pcnet32_gstrings_test)
138 #define PCNET32_NUM_REGS 136
140 #define MAX_UNITS 8 /* More are supported, limit only on options */
141 static int options
[MAX_UNITS
];
142 static int full_duplex
[MAX_UNITS
];
143 static int homepna
[MAX_UNITS
];
146 * Theory of Operation
148 * This driver uses the same software structure as the normal lance
149 * driver. So look for a verbose description in lance.c. The differences
150 * to the normal lance driver is the use of the 32bit mode of PCnet32
151 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
152 * 16MB limitation and we don't need bounce buffers.
156 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
157 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
158 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
160 #ifndef PCNET32_LOG_TX_BUFFERS
161 #define PCNET32_LOG_TX_BUFFERS 4
162 #define PCNET32_LOG_RX_BUFFERS 5
163 #define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
164 #define PCNET32_LOG_MAX_RX_BUFFERS 9
167 #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
168 #define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
170 #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
171 #define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
173 #define PKT_BUF_SKB 1544
174 /* actual buffer length after being aligned */
175 #define PKT_BUF_SIZE (PKT_BUF_SKB - NET_IP_ALIGN)
176 /* chip wants twos complement of the (aligned) buffer length */
177 #define NEG_BUF_SIZE (NET_IP_ALIGN - PKT_BUF_SKB)
179 /* Offsets from base I/O address. */
180 #define PCNET32_WIO_RDP 0x10
181 #define PCNET32_WIO_RAP 0x12
182 #define PCNET32_WIO_RESET 0x14
183 #define PCNET32_WIO_BDP 0x16
185 #define PCNET32_DWIO_RDP 0x10
186 #define PCNET32_DWIO_RAP 0x14
187 #define PCNET32_DWIO_RESET 0x18
188 #define PCNET32_DWIO_BDP 0x1C
190 #define PCNET32_TOTAL_SIZE 0x20
193 #define CSR0_INIT 0x1
194 #define CSR0_START 0x2
195 #define CSR0_STOP 0x4
196 #define CSR0_TXPOLL 0x8
197 #define CSR0_INTEN 0x40
198 #define CSR0_IDON 0x0100
199 #define CSR0_NORMAL (CSR0_START | CSR0_INTEN)
200 #define PCNET32_INIT_LOW 1
201 #define PCNET32_INIT_HIGH 2
205 #define CSR5_SUSPEND 0x0001
207 #define PCNET32_MC_FILTER 8
209 #define PCNET32_79C970A 0x2621
211 /* The PCNET32 Rx and Tx ring descriptors. */
212 struct pcnet32_rx_head
{
214 __le16 buf_length
; /* two`s complement of length */
220 struct pcnet32_tx_head
{
222 __le16 length
; /* two`s complement of length */
228 /* The PCNET32 32-Bit initialization block, described in databook. */
229 struct pcnet32_init_block
{
235 /* Receive and transmit ring base, along with extra bits. */
240 /* PCnet32 access functions */
241 struct pcnet32_access
{
242 u16 (*read_csr
) (unsigned long, int);
243 void (*write_csr
) (unsigned long, int, u16
);
244 u16 (*read_bcr
) (unsigned long, int);
245 void (*write_bcr
) (unsigned long, int, u16
);
246 u16 (*read_rap
) (unsigned long);
247 void (*write_rap
) (unsigned long, u16
);
248 void (*reset
) (unsigned long);
252 * The first field of pcnet32_private is read by the ethernet device
253 * so the structure should be allocated using pci_alloc_consistent().
255 struct pcnet32_private
{
256 struct pcnet32_init_block
*init_block
;
257 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
258 struct pcnet32_rx_head
*rx_ring
;
259 struct pcnet32_tx_head
*tx_ring
;
260 dma_addr_t init_dma_addr
;/* DMA address of beginning of the init block,
261 returned by pci_alloc_consistent */
262 struct pci_dev
*pci_dev
;
264 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
265 struct sk_buff
**tx_skbuff
;
266 struct sk_buff
**rx_skbuff
;
267 dma_addr_t
*tx_dma_addr
;
268 dma_addr_t
*rx_dma_addr
;
269 struct pcnet32_access a
;
270 spinlock_t lock
; /* Guard lock */
271 unsigned int cur_rx
, cur_tx
; /* The next free ring entry */
272 unsigned int rx_ring_size
; /* current rx ring size */
273 unsigned int tx_ring_size
; /* current tx ring size */
274 unsigned int rx_mod_mask
; /* rx ring modular mask */
275 unsigned int tx_mod_mask
; /* tx ring modular mask */
276 unsigned short rx_len_bits
;
277 unsigned short tx_len_bits
;
278 dma_addr_t rx_ring_dma_addr
;
279 dma_addr_t tx_ring_dma_addr
;
280 unsigned int dirty_rx
, /* ring entries to be freed. */
283 struct net_device
*dev
;
284 struct napi_struct napi
;
286 char phycount
; /* number of phys found */
288 unsigned int shared_irq
:1, /* shared irq possible */
289 dxsuflo
:1, /* disable transmit stop on uflo */
290 mii
:1; /* mii port available */
291 struct net_device
*next
;
292 struct mii_if_info mii_if
;
293 struct timer_list watchdog_timer
;
294 struct timer_list blink_timer
;
295 u32 msg_enable
; /* debug message level */
297 /* each bit indicates an available PHY */
299 unsigned short chip_version
; /* which variant this is */
302 static int pcnet32_probe_pci(struct pci_dev
*, const struct pci_device_id
*);
303 static int pcnet32_probe1(unsigned long, int, struct pci_dev
*);
304 static int pcnet32_open(struct net_device
*);
305 static int pcnet32_init_ring(struct net_device
*);
306 static int pcnet32_start_xmit(struct sk_buff
*, struct net_device
*);
307 static void pcnet32_tx_timeout(struct net_device
*dev
);
308 static irqreturn_t
pcnet32_interrupt(int, void *);
309 static int pcnet32_close(struct net_device
*);
310 static struct net_device_stats
*pcnet32_get_stats(struct net_device
*);
311 static void pcnet32_load_multicast(struct net_device
*dev
);
312 static void pcnet32_set_multicast_list(struct net_device
*);
313 static int pcnet32_ioctl(struct net_device
*, struct ifreq
*, int);
314 static void pcnet32_watchdog(struct net_device
*);
315 static int mdio_read(struct net_device
*dev
, int phy_id
, int reg_num
);
316 static void mdio_write(struct net_device
*dev
, int phy_id
, int reg_num
,
318 static void pcnet32_restart(struct net_device
*dev
, unsigned int csr0_bits
);
319 static void pcnet32_ethtool_test(struct net_device
*dev
,
320 struct ethtool_test
*eth_test
, u64
* data
);
321 static int pcnet32_loopback_test(struct net_device
*dev
, uint64_t * data1
);
322 static int pcnet32_phys_id(struct net_device
*dev
, u32 data
);
323 static void pcnet32_led_blink_callback(struct net_device
*dev
);
324 static int pcnet32_get_regs_len(struct net_device
*dev
);
325 static void pcnet32_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
327 static void pcnet32_purge_tx_ring(struct net_device
*dev
);
328 static int pcnet32_alloc_ring(struct net_device
*dev
, const char *name
);
329 static void pcnet32_free_ring(struct net_device
*dev
);
330 static void pcnet32_check_media(struct net_device
*dev
, int verbose
);
332 static u16
pcnet32_wio_read_csr(unsigned long addr
, int index
)
334 outw(index
, addr
+ PCNET32_WIO_RAP
);
335 return inw(addr
+ PCNET32_WIO_RDP
);
338 static void pcnet32_wio_write_csr(unsigned long addr
, int index
, u16 val
)
340 outw(index
, addr
+ PCNET32_WIO_RAP
);
341 outw(val
, addr
+ PCNET32_WIO_RDP
);
344 static u16
pcnet32_wio_read_bcr(unsigned long addr
, int index
)
346 outw(index
, addr
+ PCNET32_WIO_RAP
);
347 return inw(addr
+ PCNET32_WIO_BDP
);
350 static void pcnet32_wio_write_bcr(unsigned long addr
, int index
, u16 val
)
352 outw(index
, addr
+ PCNET32_WIO_RAP
);
353 outw(val
, addr
+ PCNET32_WIO_BDP
);
356 static u16
pcnet32_wio_read_rap(unsigned long addr
)
358 return inw(addr
+ PCNET32_WIO_RAP
);
361 static void pcnet32_wio_write_rap(unsigned long addr
, u16 val
)
363 outw(val
, addr
+ PCNET32_WIO_RAP
);
366 static void pcnet32_wio_reset(unsigned long addr
)
368 inw(addr
+ PCNET32_WIO_RESET
);
371 static int pcnet32_wio_check(unsigned long addr
)
373 outw(88, addr
+ PCNET32_WIO_RAP
);
374 return (inw(addr
+ PCNET32_WIO_RAP
) == 88);
377 static struct pcnet32_access pcnet32_wio
= {
378 .read_csr
= pcnet32_wio_read_csr
,
379 .write_csr
= pcnet32_wio_write_csr
,
380 .read_bcr
= pcnet32_wio_read_bcr
,
381 .write_bcr
= pcnet32_wio_write_bcr
,
382 .read_rap
= pcnet32_wio_read_rap
,
383 .write_rap
= pcnet32_wio_write_rap
,
384 .reset
= pcnet32_wio_reset
387 static u16
pcnet32_dwio_read_csr(unsigned long addr
, int index
)
389 outl(index
, addr
+ PCNET32_DWIO_RAP
);
390 return (inl(addr
+ PCNET32_DWIO_RDP
) & 0xffff);
393 static void pcnet32_dwio_write_csr(unsigned long addr
, int index
, u16 val
)
395 outl(index
, addr
+ PCNET32_DWIO_RAP
);
396 outl(val
, addr
+ PCNET32_DWIO_RDP
);
399 static u16
pcnet32_dwio_read_bcr(unsigned long addr
, int index
)
401 outl(index
, addr
+ PCNET32_DWIO_RAP
);
402 return (inl(addr
+ PCNET32_DWIO_BDP
) & 0xffff);
405 static void pcnet32_dwio_write_bcr(unsigned long addr
, int index
, u16 val
)
407 outl(index
, addr
+ PCNET32_DWIO_RAP
);
408 outl(val
, addr
+ PCNET32_DWIO_BDP
);
411 static u16
pcnet32_dwio_read_rap(unsigned long addr
)
413 return (inl(addr
+ PCNET32_DWIO_RAP
) & 0xffff);
416 static void pcnet32_dwio_write_rap(unsigned long addr
, u16 val
)
418 outl(val
, addr
+ PCNET32_DWIO_RAP
);
421 static void pcnet32_dwio_reset(unsigned long addr
)
423 inl(addr
+ PCNET32_DWIO_RESET
);
426 static int pcnet32_dwio_check(unsigned long addr
)
428 outl(88, addr
+ PCNET32_DWIO_RAP
);
429 return ((inl(addr
+ PCNET32_DWIO_RAP
) & 0xffff) == 88);
432 static struct pcnet32_access pcnet32_dwio
= {
433 .read_csr
= pcnet32_dwio_read_csr
,
434 .write_csr
= pcnet32_dwio_write_csr
,
435 .read_bcr
= pcnet32_dwio_read_bcr
,
436 .write_bcr
= pcnet32_dwio_write_bcr
,
437 .read_rap
= pcnet32_dwio_read_rap
,
438 .write_rap
= pcnet32_dwio_write_rap
,
439 .reset
= pcnet32_dwio_reset
442 static void pcnet32_netif_stop(struct net_device
*dev
)
444 struct pcnet32_private
*lp
= netdev_priv(dev
);
446 dev
->trans_start
= jiffies
;
447 napi_disable(&lp
->napi
);
448 netif_tx_disable(dev
);
451 static void pcnet32_netif_start(struct net_device
*dev
)
453 struct pcnet32_private
*lp
= netdev_priv(dev
);
454 ulong ioaddr
= dev
->base_addr
;
457 netif_wake_queue(dev
);
458 val
= lp
->a
.read_csr(ioaddr
, CSR3
);
460 lp
->a
.write_csr(ioaddr
, CSR3
, val
);
461 napi_enable(&lp
->napi
);
465 * Allocate space for the new sized tx ring.
467 * Save new resources.
468 * Any failure keeps old resources.
469 * Must be called with lp->lock held.
471 static void pcnet32_realloc_tx_ring(struct net_device
*dev
,
472 struct pcnet32_private
*lp
,
475 dma_addr_t new_ring_dma_addr
;
476 dma_addr_t
*new_dma_addr_list
;
477 struct pcnet32_tx_head
*new_tx_ring
;
478 struct sk_buff
**new_skb_list
;
480 pcnet32_purge_tx_ring(dev
);
482 new_tx_ring
= pci_alloc_consistent(lp
->pci_dev
,
483 sizeof(struct pcnet32_tx_head
) *
486 if (new_tx_ring
== NULL
) {
487 if (netif_msg_drv(lp
))
489 "%s: Consistent memory allocation failed.\n",
493 memset(new_tx_ring
, 0, sizeof(struct pcnet32_tx_head
) * (1 << size
));
495 new_dma_addr_list
= kcalloc((1 << size
), sizeof(dma_addr_t
),
497 if (!new_dma_addr_list
) {
498 if (netif_msg_drv(lp
))
500 "%s: Memory allocation failed.\n", dev
->name
);
501 goto free_new_tx_ring
;
504 new_skb_list
= kcalloc((1 << size
), sizeof(struct sk_buff
*),
507 if (netif_msg_drv(lp
))
509 "%s: Memory allocation failed.\n", dev
->name
);
513 kfree(lp
->tx_skbuff
);
514 kfree(lp
->tx_dma_addr
);
515 pci_free_consistent(lp
->pci_dev
,
516 sizeof(struct pcnet32_tx_head
) *
517 lp
->tx_ring_size
, lp
->tx_ring
,
518 lp
->tx_ring_dma_addr
);
520 lp
->tx_ring_size
= (1 << size
);
521 lp
->tx_mod_mask
= lp
->tx_ring_size
- 1;
522 lp
->tx_len_bits
= (size
<< 12);
523 lp
->tx_ring
= new_tx_ring
;
524 lp
->tx_ring_dma_addr
= new_ring_dma_addr
;
525 lp
->tx_dma_addr
= new_dma_addr_list
;
526 lp
->tx_skbuff
= new_skb_list
;
530 kfree(new_dma_addr_list
);
532 pci_free_consistent(lp
->pci_dev
,
533 sizeof(struct pcnet32_tx_head
) *
541 * Allocate space for the new sized rx ring.
542 * Re-use old receive buffers.
543 * alloc extra buffers
544 * free unneeded buffers
545 * free unneeded buffers
546 * Save new resources.
547 * Any failure keeps old resources.
548 * Must be called with lp->lock held.
550 static void pcnet32_realloc_rx_ring(struct net_device
*dev
,
551 struct pcnet32_private
*lp
,
554 dma_addr_t new_ring_dma_addr
;
555 dma_addr_t
*new_dma_addr_list
;
556 struct pcnet32_rx_head
*new_rx_ring
;
557 struct sk_buff
**new_skb_list
;
560 new_rx_ring
= pci_alloc_consistent(lp
->pci_dev
,
561 sizeof(struct pcnet32_rx_head
) *
564 if (new_rx_ring
== NULL
) {
565 if (netif_msg_drv(lp
))
567 "%s: Consistent memory allocation failed.\n",
571 memset(new_rx_ring
, 0, sizeof(struct pcnet32_rx_head
) * (1 << size
));
573 new_dma_addr_list
= kcalloc((1 << size
), sizeof(dma_addr_t
),
575 if (!new_dma_addr_list
) {
576 if (netif_msg_drv(lp
))
578 "%s: Memory allocation failed.\n", dev
->name
);
579 goto free_new_rx_ring
;
582 new_skb_list
= kcalloc((1 << size
), sizeof(struct sk_buff
*),
585 if (netif_msg_drv(lp
))
587 "%s: Memory allocation failed.\n", dev
->name
);
591 /* first copy the current receive buffers */
592 overlap
= min(size
, lp
->rx_ring_size
);
593 for (new = 0; new < overlap
; new++) {
594 new_rx_ring
[new] = lp
->rx_ring
[new];
595 new_dma_addr_list
[new] = lp
->rx_dma_addr
[new];
596 new_skb_list
[new] = lp
->rx_skbuff
[new];
598 /* now allocate any new buffers needed */
599 for (; new < size
; new++ ) {
600 struct sk_buff
*rx_skbuff
;
601 new_skb_list
[new] = dev_alloc_skb(PKT_BUF_SKB
);
602 if (!(rx_skbuff
= new_skb_list
[new])) {
603 /* keep the original lists and buffers */
604 if (netif_msg_drv(lp
))
606 "%s: pcnet32_realloc_rx_ring dev_alloc_skb failed.\n",
610 skb_reserve(rx_skbuff
, NET_IP_ALIGN
);
612 new_dma_addr_list
[new] =
613 pci_map_single(lp
->pci_dev
, rx_skbuff
->data
,
614 PKT_BUF_SIZE
, PCI_DMA_FROMDEVICE
);
615 new_rx_ring
[new].base
= cpu_to_le32(new_dma_addr_list
[new]);
616 new_rx_ring
[new].buf_length
= cpu_to_le16(NEG_BUF_SIZE
);
617 new_rx_ring
[new].status
= cpu_to_le16(0x8000);
619 /* and free any unneeded buffers */
620 for (; new < lp
->rx_ring_size
; new++) {
621 if (lp
->rx_skbuff
[new]) {
622 pci_unmap_single(lp
->pci_dev
, lp
->rx_dma_addr
[new],
623 PKT_BUF_SIZE
, PCI_DMA_FROMDEVICE
);
624 dev_kfree_skb(lp
->rx_skbuff
[new]);
628 kfree(lp
->rx_skbuff
);
629 kfree(lp
->rx_dma_addr
);
630 pci_free_consistent(lp
->pci_dev
,
631 sizeof(struct pcnet32_rx_head
) *
632 lp
->rx_ring_size
, lp
->rx_ring
,
633 lp
->rx_ring_dma_addr
);
635 lp
->rx_ring_size
= (1 << size
);
636 lp
->rx_mod_mask
= lp
->rx_ring_size
- 1;
637 lp
->rx_len_bits
= (size
<< 4);
638 lp
->rx_ring
= new_rx_ring
;
639 lp
->rx_ring_dma_addr
= new_ring_dma_addr
;
640 lp
->rx_dma_addr
= new_dma_addr_list
;
641 lp
->rx_skbuff
= new_skb_list
;
645 for (; --new >= lp
->rx_ring_size
; ) {
646 if (new_skb_list
[new]) {
647 pci_unmap_single(lp
->pci_dev
, new_dma_addr_list
[new],
648 PKT_BUF_SIZE
, PCI_DMA_FROMDEVICE
);
649 dev_kfree_skb(new_skb_list
[new]);
654 kfree(new_dma_addr_list
);
656 pci_free_consistent(lp
->pci_dev
,
657 sizeof(struct pcnet32_rx_head
) *
664 static void pcnet32_purge_rx_ring(struct net_device
*dev
)
666 struct pcnet32_private
*lp
= netdev_priv(dev
);
669 /* free all allocated skbuffs */
670 for (i
= 0; i
< lp
->rx_ring_size
; i
++) {
671 lp
->rx_ring
[i
].status
= 0; /* CPU owns buffer */
672 wmb(); /* Make sure adapter sees owner change */
673 if (lp
->rx_skbuff
[i
]) {
674 pci_unmap_single(lp
->pci_dev
, lp
->rx_dma_addr
[i
],
675 PKT_BUF_SIZE
, PCI_DMA_FROMDEVICE
);
676 dev_kfree_skb_any(lp
->rx_skbuff
[i
]);
678 lp
->rx_skbuff
[i
] = NULL
;
679 lp
->rx_dma_addr
[i
] = 0;
683 #ifdef CONFIG_NET_POLL_CONTROLLER
684 static void pcnet32_poll_controller(struct net_device
*dev
)
686 disable_irq(dev
->irq
);
687 pcnet32_interrupt(0, dev
);
688 enable_irq(dev
->irq
);
692 static int pcnet32_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
694 struct pcnet32_private
*lp
= netdev_priv(dev
);
699 spin_lock_irqsave(&lp
->lock
, flags
);
700 mii_ethtool_gset(&lp
->mii_if
, cmd
);
701 spin_unlock_irqrestore(&lp
->lock
, flags
);
707 static int pcnet32_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
709 struct pcnet32_private
*lp
= netdev_priv(dev
);
714 spin_lock_irqsave(&lp
->lock
, flags
);
715 r
= mii_ethtool_sset(&lp
->mii_if
, cmd
);
716 spin_unlock_irqrestore(&lp
->lock
, flags
);
721 static void pcnet32_get_drvinfo(struct net_device
*dev
,
722 struct ethtool_drvinfo
*info
)
724 struct pcnet32_private
*lp
= netdev_priv(dev
);
726 strcpy(info
->driver
, DRV_NAME
);
727 strcpy(info
->version
, DRV_VERSION
);
729 strcpy(info
->bus_info
, pci_name(lp
->pci_dev
));
731 sprintf(info
->bus_info
, "VLB 0x%lx", dev
->base_addr
);
734 static u32
pcnet32_get_link(struct net_device
*dev
)
736 struct pcnet32_private
*lp
= netdev_priv(dev
);
740 spin_lock_irqsave(&lp
->lock
, flags
);
742 r
= mii_link_ok(&lp
->mii_if
);
743 } else if (lp
->chip_version
>= PCNET32_79C970A
) {
744 ulong ioaddr
= dev
->base_addr
; /* card base I/O address */
745 r
= (lp
->a
.read_bcr(ioaddr
, 4) != 0xc0);
746 } else { /* can not detect link on really old chips */
749 spin_unlock_irqrestore(&lp
->lock
, flags
);
754 static u32
pcnet32_get_msglevel(struct net_device
*dev
)
756 struct pcnet32_private
*lp
= netdev_priv(dev
);
757 return lp
->msg_enable
;
760 static void pcnet32_set_msglevel(struct net_device
*dev
, u32 value
)
762 struct pcnet32_private
*lp
= netdev_priv(dev
);
763 lp
->msg_enable
= value
;
766 static int pcnet32_nway_reset(struct net_device
*dev
)
768 struct pcnet32_private
*lp
= netdev_priv(dev
);
773 spin_lock_irqsave(&lp
->lock
, flags
);
774 r
= mii_nway_restart(&lp
->mii_if
);
775 spin_unlock_irqrestore(&lp
->lock
, flags
);
780 static void pcnet32_get_ringparam(struct net_device
*dev
,
781 struct ethtool_ringparam
*ering
)
783 struct pcnet32_private
*lp
= netdev_priv(dev
);
785 ering
->tx_max_pending
= TX_MAX_RING_SIZE
;
786 ering
->tx_pending
= lp
->tx_ring_size
;
787 ering
->rx_max_pending
= RX_MAX_RING_SIZE
;
788 ering
->rx_pending
= lp
->rx_ring_size
;
791 static int pcnet32_set_ringparam(struct net_device
*dev
,
792 struct ethtool_ringparam
*ering
)
794 struct pcnet32_private
*lp
= netdev_priv(dev
);
797 ulong ioaddr
= dev
->base_addr
;
800 if (ering
->rx_mini_pending
|| ering
->rx_jumbo_pending
)
803 if (netif_running(dev
))
804 pcnet32_netif_stop(dev
);
806 spin_lock_irqsave(&lp
->lock
, flags
);
807 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_STOP
); /* stop the chip */
809 size
= min(ering
->tx_pending
, (unsigned int)TX_MAX_RING_SIZE
);
811 /* set the minimum ring size to 4, to allow the loopback test to work
814 for (i
= 2; i
<= PCNET32_LOG_MAX_TX_BUFFERS
; i
++) {
815 if (size
<= (1 << i
))
818 if ((1 << i
) != lp
->tx_ring_size
)
819 pcnet32_realloc_tx_ring(dev
, lp
, i
);
821 size
= min(ering
->rx_pending
, (unsigned int)RX_MAX_RING_SIZE
);
822 for (i
= 2; i
<= PCNET32_LOG_MAX_RX_BUFFERS
; i
++) {
823 if (size
<= (1 << i
))
826 if ((1 << i
) != lp
->rx_ring_size
)
827 pcnet32_realloc_rx_ring(dev
, lp
, i
);
829 lp
->napi
.weight
= lp
->rx_ring_size
/ 2;
831 if (netif_running(dev
)) {
832 pcnet32_netif_start(dev
);
833 pcnet32_restart(dev
, CSR0_NORMAL
);
836 spin_unlock_irqrestore(&lp
->lock
, flags
);
838 if (netif_msg_drv(lp
))
840 "%s: Ring Param Settings: RX: %d, TX: %d\n", dev
->name
,
841 lp
->rx_ring_size
, lp
->tx_ring_size
);
846 static void pcnet32_get_strings(struct net_device
*dev
, u32 stringset
,
849 memcpy(data
, pcnet32_gstrings_test
, sizeof(pcnet32_gstrings_test
));
852 static int pcnet32_get_sset_count(struct net_device
*dev
, int sset
)
856 return PCNET32_TEST_LEN
;
862 static void pcnet32_ethtool_test(struct net_device
*dev
,
863 struct ethtool_test
*test
, u64
* data
)
865 struct pcnet32_private
*lp
= netdev_priv(dev
);
868 if (test
->flags
== ETH_TEST_FL_OFFLINE
) {
869 rc
= pcnet32_loopback_test(dev
, data
);
871 if (netif_msg_hw(lp
))
872 printk(KERN_DEBUG
"%s: Loopback test failed.\n",
874 test
->flags
|= ETH_TEST_FL_FAILED
;
875 } else if (netif_msg_hw(lp
))
876 printk(KERN_DEBUG
"%s: Loopback test passed.\n",
878 } else if (netif_msg_hw(lp
))
880 "%s: No tests to run (specify 'Offline' on ethtool).",
882 } /* end pcnet32_ethtool_test */
884 static int pcnet32_loopback_test(struct net_device
*dev
, uint64_t * data1
)
886 struct pcnet32_private
*lp
= netdev_priv(dev
);
887 struct pcnet32_access
*a
= &lp
->a
; /* access to registers */
888 ulong ioaddr
= dev
->base_addr
; /* card base I/O address */
889 struct sk_buff
*skb
; /* sk buff */
890 int x
, i
; /* counters */
891 int numbuffs
= 4; /* number of TX/RX buffers and descs */
892 u16 status
= 0x8300; /* TX ring status */
893 __le16 teststatus
; /* test of ring status */
894 int rc
; /* return code */
895 int size
; /* size of packets */
896 unsigned char *packet
; /* source packet data */
897 static const int data_len
= 60; /* length of source packets */
901 rc
= 1; /* default to fail */
903 if (netif_running(dev
))
904 pcnet32_netif_stop(dev
);
906 spin_lock_irqsave(&lp
->lock
, flags
);
907 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_STOP
); /* stop the chip */
909 numbuffs
= min(numbuffs
, (int)min(lp
->rx_ring_size
, lp
->tx_ring_size
));
911 /* Reset the PCNET32 */
913 lp
->a
.write_csr(ioaddr
, CSR4
, 0x0915); /* auto tx pad */
915 /* switch pcnet32 to 32bit mode */
916 lp
->a
.write_bcr(ioaddr
, 20, 2);
918 /* purge & init rings but don't actually restart */
919 pcnet32_restart(dev
, 0x0000);
921 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_STOP
); /* Set STOP bit */
923 /* Initialize Transmit buffers. */
924 size
= data_len
+ 15;
925 for (x
= 0; x
< numbuffs
; x
++) {
926 if (!(skb
= dev_alloc_skb(size
))) {
927 if (netif_msg_hw(lp
))
929 "%s: Cannot allocate skb at line: %d!\n",
930 dev
->name
, __LINE__
);
934 skb_put(skb
, size
); /* create space for data */
935 lp
->tx_skbuff
[x
] = skb
;
936 lp
->tx_ring
[x
].length
= cpu_to_le16(-skb
->len
);
937 lp
->tx_ring
[x
].misc
= 0;
939 /* put DA and SA into the skb */
940 for (i
= 0; i
< 6; i
++)
941 *packet
++ = dev
->dev_addr
[i
];
942 for (i
= 0; i
< 6; i
++)
943 *packet
++ = dev
->dev_addr
[i
];
949 /* fill packet with data */
950 for (i
= 0; i
< data_len
; i
++)
954 pci_map_single(lp
->pci_dev
, skb
->data
, skb
->len
,
956 lp
->tx_ring
[x
].base
= cpu_to_le32(lp
->tx_dma_addr
[x
]);
957 wmb(); /* Make sure owner changes after all others are visible */
958 lp
->tx_ring
[x
].status
= cpu_to_le16(status
);
962 x
= a
->read_bcr(ioaddr
, 32); /* set internal loopback in BCR32 */
963 a
->write_bcr(ioaddr
, 32, x
| 0x0002);
965 /* set int loopback in CSR15 */
966 x
= a
->read_csr(ioaddr
, CSR15
) & 0xfffc;
967 lp
->a
.write_csr(ioaddr
, CSR15
, x
| 0x0044);
969 teststatus
= cpu_to_le16(0x8000);
970 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_START
); /* Set STRT bit */
972 /* Check status of descriptors */
973 for (x
= 0; x
< numbuffs
; x
++) {
976 while ((lp
->rx_ring
[x
].status
& teststatus
) && (ticks
< 200)) {
977 spin_unlock_irqrestore(&lp
->lock
, flags
);
979 spin_lock_irqsave(&lp
->lock
, flags
);
984 if (netif_msg_hw(lp
))
985 printk("%s: Desc %d failed to reset!\n",
991 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_STOP
); /* Set STOP bit */
993 if (netif_msg_hw(lp
) && netif_msg_pktdata(lp
)) {
994 printk(KERN_DEBUG
"%s: RX loopback packets:\n", dev
->name
);
996 for (x
= 0; x
< numbuffs
; x
++) {
997 printk(KERN_DEBUG
"%s: Packet %d:\n", dev
->name
, x
);
998 skb
= lp
->rx_skbuff
[x
];
999 for (i
= 0; i
< size
; i
++) {
1000 printk("%02x ", *(skb
->data
+ i
));
1008 while (x
< numbuffs
&& !rc
) {
1009 skb
= lp
->rx_skbuff
[x
];
1010 packet
= lp
->tx_skbuff
[x
]->data
;
1011 for (i
= 0; i
< size
; i
++) {
1012 if (*(skb
->data
+ i
) != packet
[i
]) {
1013 if (netif_msg_hw(lp
))
1015 "%s: Error in compare! %2x - %02x %02x\n",
1016 dev
->name
, i
, *(skb
->data
+ i
),
1027 pcnet32_purge_tx_ring(dev
);
1029 x
= a
->read_csr(ioaddr
, CSR15
);
1030 a
->write_csr(ioaddr
, CSR15
, (x
& ~0x0044)); /* reset bits 6 and 2 */
1032 x
= a
->read_bcr(ioaddr
, 32); /* reset internal loopback */
1033 a
->write_bcr(ioaddr
, 32, (x
& ~0x0002));
1035 if (netif_running(dev
)) {
1036 pcnet32_netif_start(dev
);
1037 pcnet32_restart(dev
, CSR0_NORMAL
);
1039 pcnet32_purge_rx_ring(dev
);
1040 lp
->a
.write_bcr(ioaddr
, 20, 4); /* return to 16bit mode */
1042 spin_unlock_irqrestore(&lp
->lock
, flags
);
1045 } /* end pcnet32_loopback_test */
1047 static void pcnet32_led_blink_callback(struct net_device
*dev
)
1049 struct pcnet32_private
*lp
= netdev_priv(dev
);
1050 struct pcnet32_access
*a
= &lp
->a
;
1051 ulong ioaddr
= dev
->base_addr
;
1052 unsigned long flags
;
1055 spin_lock_irqsave(&lp
->lock
, flags
);
1056 for (i
= 4; i
< 8; i
++) {
1057 a
->write_bcr(ioaddr
, i
, a
->read_bcr(ioaddr
, i
) ^ 0x4000);
1059 spin_unlock_irqrestore(&lp
->lock
, flags
);
1061 mod_timer(&lp
->blink_timer
, PCNET32_BLINK_TIMEOUT
);
1064 static int pcnet32_phys_id(struct net_device
*dev
, u32 data
)
1066 struct pcnet32_private
*lp
= netdev_priv(dev
);
1067 struct pcnet32_access
*a
= &lp
->a
;
1068 ulong ioaddr
= dev
->base_addr
;
1069 unsigned long flags
;
1072 if (!lp
->blink_timer
.function
) {
1073 init_timer(&lp
->blink_timer
);
1074 lp
->blink_timer
.function
= (void *)pcnet32_led_blink_callback
;
1075 lp
->blink_timer
.data
= (unsigned long)dev
;
1078 /* Save the current value of the bcrs */
1079 spin_lock_irqsave(&lp
->lock
, flags
);
1080 for (i
= 4; i
< 8; i
++) {
1081 regs
[i
- 4] = a
->read_bcr(ioaddr
, i
);
1083 spin_unlock_irqrestore(&lp
->lock
, flags
);
1085 mod_timer(&lp
->blink_timer
, jiffies
);
1086 set_current_state(TASK_INTERRUPTIBLE
);
1088 /* AV: the limit here makes no sense whatsoever */
1089 if ((!data
) || (data
> (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
)))
1090 data
= (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
);
1092 msleep_interruptible(data
* 1000);
1093 del_timer_sync(&lp
->blink_timer
);
1095 /* Restore the original value of the bcrs */
1096 spin_lock_irqsave(&lp
->lock
, flags
);
1097 for (i
= 4; i
< 8; i
++) {
1098 a
->write_bcr(ioaddr
, i
, regs
[i
- 4]);
1100 spin_unlock_irqrestore(&lp
->lock
, flags
);
1106 * lp->lock must be held.
1108 static int pcnet32_suspend(struct net_device
*dev
, unsigned long *flags
,
1112 struct pcnet32_private
*lp
= netdev_priv(dev
);
1113 struct pcnet32_access
*a
= &lp
->a
;
1114 ulong ioaddr
= dev
->base_addr
;
1117 /* really old chips have to be stopped. */
1118 if (lp
->chip_version
< PCNET32_79C970A
)
1121 /* set SUSPEND (SPND) - CSR5 bit 0 */
1122 csr5
= a
->read_csr(ioaddr
, CSR5
);
1123 a
->write_csr(ioaddr
, CSR5
, csr5
| CSR5_SUSPEND
);
1125 /* poll waiting for bit to be set */
1127 while (!(a
->read_csr(ioaddr
, CSR5
) & CSR5_SUSPEND
)) {
1128 spin_unlock_irqrestore(&lp
->lock
, *flags
);
1133 spin_lock_irqsave(&lp
->lock
, *flags
);
1136 if (netif_msg_hw(lp
))
1138 "%s: Error getting into suspend!\n",
1147 * process one receive descriptor entry
1150 static void pcnet32_rx_entry(struct net_device
*dev
,
1151 struct pcnet32_private
*lp
,
1152 struct pcnet32_rx_head
*rxp
,
1155 int status
= (short)le16_to_cpu(rxp
->status
) >> 8;
1156 int rx_in_place
= 0;
1157 struct sk_buff
*skb
;
1160 if (status
!= 0x03) { /* There was an error. */
1162 * There is a tricky error noted by John Murphy,
1163 * <murf@perftech.com> to Russ Nelson: Even with full-sized
1164 * buffers it's possible for a jabber packet to use two
1165 * buffers, with only the last correctly noting the error.
1167 if (status
& 0x01) /* Only count a general error at the */
1168 dev
->stats
.rx_errors
++; /* end of a packet. */
1170 dev
->stats
.rx_frame_errors
++;
1172 dev
->stats
.rx_over_errors
++;
1174 dev
->stats
.rx_crc_errors
++;
1176 dev
->stats
.rx_fifo_errors
++;
1180 pkt_len
= (le32_to_cpu(rxp
->msg_length
) & 0xfff) - 4;
1182 /* Discard oversize frames. */
1183 if (unlikely(pkt_len
> PKT_BUF_SIZE
)) {
1184 if (netif_msg_drv(lp
))
1185 printk(KERN_ERR
"%s: Impossible packet size %d!\n",
1186 dev
->name
, pkt_len
);
1187 dev
->stats
.rx_errors
++;
1191 if (netif_msg_rx_err(lp
))
1192 printk(KERN_ERR
"%s: Runt packet!\n", dev
->name
);
1193 dev
->stats
.rx_errors
++;
1197 if (pkt_len
> rx_copybreak
) {
1198 struct sk_buff
*newskb
;
1200 if ((newskb
= dev_alloc_skb(PKT_BUF_SKB
))) {
1201 skb_reserve(newskb
, NET_IP_ALIGN
);
1202 skb
= lp
->rx_skbuff
[entry
];
1203 pci_unmap_single(lp
->pci_dev
,
1204 lp
->rx_dma_addr
[entry
],
1206 PCI_DMA_FROMDEVICE
);
1207 skb_put(skb
, pkt_len
);
1208 lp
->rx_skbuff
[entry
] = newskb
;
1209 lp
->rx_dma_addr
[entry
] =
1210 pci_map_single(lp
->pci_dev
,
1213 PCI_DMA_FROMDEVICE
);
1214 rxp
->base
= cpu_to_le32(lp
->rx_dma_addr
[entry
]);
1219 skb
= dev_alloc_skb(pkt_len
+ NET_IP_ALIGN
);
1223 if (netif_msg_drv(lp
))
1225 "%s: Memory squeeze, dropping packet.\n",
1227 dev
->stats
.rx_dropped
++;
1232 skb_reserve(skb
, NET_IP_ALIGN
);
1233 skb_put(skb
, pkt_len
); /* Make room */
1234 pci_dma_sync_single_for_cpu(lp
->pci_dev
,
1235 lp
->rx_dma_addr
[entry
],
1237 PCI_DMA_FROMDEVICE
);
1238 skb_copy_to_linear_data(skb
,
1239 (unsigned char *)(lp
->rx_skbuff
[entry
]->data
),
1241 pci_dma_sync_single_for_device(lp
->pci_dev
,
1242 lp
->rx_dma_addr
[entry
],
1244 PCI_DMA_FROMDEVICE
);
1246 dev
->stats
.rx_bytes
+= skb
->len
;
1247 skb
->protocol
= eth_type_trans(skb
, dev
);
1248 netif_receive_skb(skb
);
1249 dev
->stats
.rx_packets
++;
1253 static int pcnet32_rx(struct net_device
*dev
, int budget
)
1255 struct pcnet32_private
*lp
= netdev_priv(dev
);
1256 int entry
= lp
->cur_rx
& lp
->rx_mod_mask
;
1257 struct pcnet32_rx_head
*rxp
= &lp
->rx_ring
[entry
];
1260 /* If we own the next entry, it's a new packet. Send it up. */
1261 while (npackets
< budget
&& (short)le16_to_cpu(rxp
->status
) >= 0) {
1262 pcnet32_rx_entry(dev
, lp
, rxp
, entry
);
1265 * The docs say that the buffer length isn't touched, but Andrew
1266 * Boyd of QNX reports that some revs of the 79C965 clear it.
1268 rxp
->buf_length
= cpu_to_le16(NEG_BUF_SIZE
);
1269 wmb(); /* Make sure owner changes after others are visible */
1270 rxp
->status
= cpu_to_le16(0x8000);
1271 entry
= (++lp
->cur_rx
) & lp
->rx_mod_mask
;
1272 rxp
= &lp
->rx_ring
[entry
];
1278 static int pcnet32_tx(struct net_device
*dev
)
1280 struct pcnet32_private
*lp
= netdev_priv(dev
);
1281 unsigned int dirty_tx
= lp
->dirty_tx
;
1283 int must_restart
= 0;
1285 while (dirty_tx
!= lp
->cur_tx
) {
1286 int entry
= dirty_tx
& lp
->tx_mod_mask
;
1287 int status
= (short)le16_to_cpu(lp
->tx_ring
[entry
].status
);
1290 break; /* It still hasn't been Txed */
1292 lp
->tx_ring
[entry
].base
= 0;
1294 if (status
& 0x4000) {
1295 /* There was a major error, log it. */
1296 int err_status
= le32_to_cpu(lp
->tx_ring
[entry
].misc
);
1297 dev
->stats
.tx_errors
++;
1298 if (netif_msg_tx_err(lp
))
1300 "%s: Tx error status=%04x err_status=%08x\n",
1303 if (err_status
& 0x04000000)
1304 dev
->stats
.tx_aborted_errors
++;
1305 if (err_status
& 0x08000000)
1306 dev
->stats
.tx_carrier_errors
++;
1307 if (err_status
& 0x10000000)
1308 dev
->stats
.tx_window_errors
++;
1310 if (err_status
& 0x40000000) {
1311 dev
->stats
.tx_fifo_errors
++;
1312 /* Ackk! On FIFO errors the Tx unit is turned off! */
1313 /* Remove this verbosity later! */
1314 if (netif_msg_tx_err(lp
))
1316 "%s: Tx FIFO error!\n",
1321 if (err_status
& 0x40000000) {
1322 dev
->stats
.tx_fifo_errors
++;
1323 if (!lp
->dxsuflo
) { /* If controller doesn't recover ... */
1324 /* Ackk! On FIFO errors the Tx unit is turned off! */
1325 /* Remove this verbosity later! */
1326 if (netif_msg_tx_err(lp
))
1328 "%s: Tx FIFO error!\n",
1335 if (status
& 0x1800)
1336 dev
->stats
.collisions
++;
1337 dev
->stats
.tx_packets
++;
1340 /* We must free the original skb */
1341 if (lp
->tx_skbuff
[entry
]) {
1342 pci_unmap_single(lp
->pci_dev
,
1343 lp
->tx_dma_addr
[entry
],
1344 lp
->tx_skbuff
[entry
]->
1345 len
, PCI_DMA_TODEVICE
);
1346 dev_kfree_skb_any(lp
->tx_skbuff
[entry
]);
1347 lp
->tx_skbuff
[entry
] = NULL
;
1348 lp
->tx_dma_addr
[entry
] = 0;
1353 delta
= (lp
->cur_tx
- dirty_tx
) & (lp
->tx_mod_mask
+ lp
->tx_ring_size
);
1354 if (delta
> lp
->tx_ring_size
) {
1355 if (netif_msg_drv(lp
))
1357 "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1358 dev
->name
, dirty_tx
, lp
->cur_tx
,
1360 dirty_tx
+= lp
->tx_ring_size
;
1361 delta
-= lp
->tx_ring_size
;
1365 netif_queue_stopped(dev
) &&
1366 delta
< lp
->tx_ring_size
- 2) {
1367 /* The ring is no longer full, clear tbusy. */
1369 netif_wake_queue(dev
);
1371 lp
->dirty_tx
= dirty_tx
;
1373 return must_restart
;
1376 static int pcnet32_poll(struct napi_struct
*napi
, int budget
)
1378 struct pcnet32_private
*lp
= container_of(napi
, struct pcnet32_private
, napi
);
1379 struct net_device
*dev
= lp
->dev
;
1380 unsigned long ioaddr
= dev
->base_addr
;
1381 unsigned long flags
;
1385 work_done
= pcnet32_rx(dev
, budget
);
1387 spin_lock_irqsave(&lp
->lock
, flags
);
1388 if (pcnet32_tx(dev
)) {
1389 /* reset the chip to clear the error condition, then restart */
1390 lp
->a
.reset(ioaddr
);
1391 lp
->a
.write_csr(ioaddr
, CSR4
, 0x0915); /* auto tx pad */
1392 pcnet32_restart(dev
, CSR0_START
);
1393 netif_wake_queue(dev
);
1395 spin_unlock_irqrestore(&lp
->lock
, flags
);
1397 if (work_done
< budget
) {
1398 spin_lock_irqsave(&lp
->lock
, flags
);
1400 __napi_complete(napi
);
1402 /* clear interrupt masks */
1403 val
= lp
->a
.read_csr(ioaddr
, CSR3
);
1405 lp
->a
.write_csr(ioaddr
, CSR3
, val
);
1407 /* Set interrupt enable. */
1408 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_INTEN
);
1410 spin_unlock_irqrestore(&lp
->lock
, flags
);
1415 #define PCNET32_REGS_PER_PHY 32
1416 #define PCNET32_MAX_PHYS 32
1417 static int pcnet32_get_regs_len(struct net_device
*dev
)
1419 struct pcnet32_private
*lp
= netdev_priv(dev
);
1420 int j
= lp
->phycount
* PCNET32_REGS_PER_PHY
;
1422 return ((PCNET32_NUM_REGS
+ j
) * sizeof(u16
));
1425 static void pcnet32_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1430 struct pcnet32_private
*lp
= netdev_priv(dev
);
1431 struct pcnet32_access
*a
= &lp
->a
;
1432 ulong ioaddr
= dev
->base_addr
;
1433 unsigned long flags
;
1435 spin_lock_irqsave(&lp
->lock
, flags
);
1437 csr0
= a
->read_csr(ioaddr
, CSR0
);
1438 if (!(csr0
& CSR0_STOP
)) /* If not stopped */
1439 pcnet32_suspend(dev
, &flags
, 1);
1441 /* read address PROM */
1442 for (i
= 0; i
< 16; i
+= 2)
1443 *buff
++ = inw(ioaddr
+ i
);
1445 /* read control and status registers */
1446 for (i
= 0; i
< 90; i
++) {
1447 *buff
++ = a
->read_csr(ioaddr
, i
);
1450 *buff
++ = a
->read_csr(ioaddr
, 112);
1451 *buff
++ = a
->read_csr(ioaddr
, 114);
1453 /* read bus configuration registers */
1454 for (i
= 0; i
< 30; i
++) {
1455 *buff
++ = a
->read_bcr(ioaddr
, i
);
1457 *buff
++ = 0; /* skip bcr30 so as not to hang 79C976 */
1458 for (i
= 31; i
< 36; i
++) {
1459 *buff
++ = a
->read_bcr(ioaddr
, i
);
1462 /* read mii phy registers */
1465 for (j
= 0; j
< PCNET32_MAX_PHYS
; j
++) {
1466 if (lp
->phymask
& (1 << j
)) {
1467 for (i
= 0; i
< PCNET32_REGS_PER_PHY
; i
++) {
1468 lp
->a
.write_bcr(ioaddr
, 33,
1470 *buff
++ = lp
->a
.read_bcr(ioaddr
, 34);
1476 if (!(csr0
& CSR0_STOP
)) { /* If not stopped */
1479 /* clear SUSPEND (SPND) - CSR5 bit 0 */
1480 csr5
= a
->read_csr(ioaddr
, CSR5
);
1481 a
->write_csr(ioaddr
, CSR5
, csr5
& (~CSR5_SUSPEND
));
1484 spin_unlock_irqrestore(&lp
->lock
, flags
);
1487 static const struct ethtool_ops pcnet32_ethtool_ops
= {
1488 .get_settings
= pcnet32_get_settings
,
1489 .set_settings
= pcnet32_set_settings
,
1490 .get_drvinfo
= pcnet32_get_drvinfo
,
1491 .get_msglevel
= pcnet32_get_msglevel
,
1492 .set_msglevel
= pcnet32_set_msglevel
,
1493 .nway_reset
= pcnet32_nway_reset
,
1494 .get_link
= pcnet32_get_link
,
1495 .get_ringparam
= pcnet32_get_ringparam
,
1496 .set_ringparam
= pcnet32_set_ringparam
,
1497 .get_strings
= pcnet32_get_strings
,
1498 .self_test
= pcnet32_ethtool_test
,
1499 .phys_id
= pcnet32_phys_id
,
1500 .get_regs_len
= pcnet32_get_regs_len
,
1501 .get_regs
= pcnet32_get_regs
,
1502 .get_sset_count
= pcnet32_get_sset_count
,
1505 /* only probes for non-PCI devices, the rest are handled by
1506 * pci_register_driver via pcnet32_probe_pci */
1508 static void __devinit
pcnet32_probe_vlbus(unsigned int *pcnet32_portlist
)
1510 unsigned int *port
, ioaddr
;
1512 /* search for PCnet32 VLB cards at known addresses */
1513 for (port
= pcnet32_portlist
; (ioaddr
= *port
); port
++) {
1515 (ioaddr
, PCNET32_TOTAL_SIZE
, "pcnet32_probe_vlbus")) {
1516 /* check if there is really a pcnet chip on that ioaddr */
1517 if ((inb(ioaddr
+ 14) == 0x57)
1518 && (inb(ioaddr
+ 15) == 0x57)) {
1519 pcnet32_probe1(ioaddr
, 0, NULL
);
1521 release_region(ioaddr
, PCNET32_TOTAL_SIZE
);
1527 static int __devinit
1528 pcnet32_probe_pci(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1530 unsigned long ioaddr
;
1533 err
= pci_enable_device(pdev
);
1535 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1537 "failed to enable device -- err=%d\n", err
);
1540 pci_set_master(pdev
);
1542 ioaddr
= pci_resource_start(pdev
, 0);
1544 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1546 "card has no PCI IO resources, aborting\n");
1550 if (!pci_dma_supported(pdev
, PCNET32_DMA_MASK
)) {
1551 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1553 "architecture does not support 32bit PCI busmaster DMA\n");
1556 if (request_region(ioaddr
, PCNET32_TOTAL_SIZE
, "pcnet32_probe_pci") ==
1558 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1560 "io address range already allocated\n");
1564 err
= pcnet32_probe1(ioaddr
, 1, pdev
);
1566 pci_disable_device(pdev
);
1571 static const struct net_device_ops pcnet32_netdev_ops
= {
1572 .ndo_open
= pcnet32_open
,
1573 .ndo_stop
= pcnet32_close
,
1574 .ndo_start_xmit
= pcnet32_start_xmit
,
1575 .ndo_tx_timeout
= pcnet32_tx_timeout
,
1576 .ndo_get_stats
= pcnet32_get_stats
,
1577 .ndo_set_multicast_list
= pcnet32_set_multicast_list
,
1578 .ndo_do_ioctl
= pcnet32_ioctl
,
1579 .ndo_change_mtu
= eth_change_mtu
,
1580 .ndo_set_mac_address
= eth_mac_addr
,
1581 .ndo_validate_addr
= eth_validate_addr
,
1582 #ifdef CONFIG_NET_POLL_CONTROLLER
1583 .ndo_poll_controller
= pcnet32_poll_controller
,
1588 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1589 * pdev will be NULL when called from pcnet32_probe_vlbus.
1591 static int __devinit
1592 pcnet32_probe1(unsigned long ioaddr
, int shared
, struct pci_dev
*pdev
)
1594 struct pcnet32_private
*lp
;
1596 int fdx
, mii
, fset
, dxsuflo
;
1599 struct net_device
*dev
;
1600 struct pcnet32_access
*a
= NULL
;
1604 /* reset the chip */
1605 pcnet32_wio_reset(ioaddr
);
1607 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1608 if (pcnet32_wio_read_csr(ioaddr
, 0) == 4 && pcnet32_wio_check(ioaddr
)) {
1611 pcnet32_dwio_reset(ioaddr
);
1612 if (pcnet32_dwio_read_csr(ioaddr
, 0) == 4
1613 && pcnet32_dwio_check(ioaddr
)) {
1616 goto err_release_region
;
1620 a
->read_csr(ioaddr
, 88) | (a
->read_csr(ioaddr
, 89) << 16);
1621 if ((pcnet32_debug
& NETIF_MSG_PROBE
) && (pcnet32_debug
& NETIF_MSG_HW
))
1622 printk(KERN_INFO
" PCnet chip version is %#x.\n",
1624 if ((chip_version
& 0xfff) != 0x003) {
1625 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1626 printk(KERN_INFO PFX
"Unsupported chip version.\n");
1627 goto err_release_region
;
1630 /* initialize variables */
1631 fdx
= mii
= fset
= dxsuflo
= 0;
1632 chip_version
= (chip_version
>> 12) & 0xffff;
1634 switch (chip_version
) {
1636 chipname
= "PCnet/PCI 79C970"; /* PCI */
1640 chipname
= "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1642 chipname
= "PCnet/32 79C965"; /* 486/VL bus */
1645 chipname
= "PCnet/PCI II 79C970A"; /* PCI */
1649 chipname
= "PCnet/FAST 79C971"; /* PCI */
1655 chipname
= "PCnet/FAST+ 79C972"; /* PCI */
1661 chipname
= "PCnet/FAST III 79C973"; /* PCI */
1666 chipname
= "PCnet/Home 79C978"; /* PCI */
1669 * This is based on specs published at www.amd.com. This section
1670 * assumes that a card with a 79C978 wants to go into standard
1671 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1672 * and the module option homepna=1 can select this instead.
1674 media
= a
->read_bcr(ioaddr
, 49);
1675 media
&= ~3; /* default to 10Mb ethernet */
1676 if (cards_found
< MAX_UNITS
&& homepna
[cards_found
])
1677 media
|= 1; /* switch to home wiring mode */
1678 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1679 printk(KERN_DEBUG PFX
"media set to %sMbit mode.\n",
1680 (media
& 1) ? "1" : "10");
1681 a
->write_bcr(ioaddr
, 49, media
);
1684 chipname
= "PCnet/FAST III 79C975"; /* PCI */
1689 chipname
= "PCnet/PRO 79C976";
1694 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1695 printk(KERN_INFO PFX
1696 "PCnet version %#x, no PCnet32 chip.\n",
1698 goto err_release_region
;
1702 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1703 * starting until the packet is loaded. Strike one for reliability, lose
1704 * one for latency - although on PCI this isnt a big loss. Older chips
1705 * have FIFO's smaller than a packet, so you can't do this.
1706 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1710 a
->write_bcr(ioaddr
, 18, (a
->read_bcr(ioaddr
, 18) | 0x0860));
1711 a
->write_csr(ioaddr
, 80,
1712 (a
->read_csr(ioaddr
, 80) & 0x0C00) | 0x0c00);
1716 dev
= alloc_etherdev(sizeof(*lp
));
1718 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1719 printk(KERN_ERR PFX
"Memory allocation failed.\n");
1721 goto err_release_region
;
1723 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1725 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1726 printk(KERN_INFO PFX
"%s at %#3lx,", chipname
, ioaddr
);
1728 /* In most chips, after a chip reset, the ethernet address is read from the
1729 * station address PROM at the base address and programmed into the
1730 * "Physical Address Registers" CSR12-14.
1731 * As a precautionary measure, we read the PROM values and complain if
1732 * they disagree with the CSRs. If they miscompare, and the PROM addr
1733 * is valid, then the PROM addr is used.
1735 for (i
= 0; i
< 3; i
++) {
1737 val
= a
->read_csr(ioaddr
, i
+ 12) & 0x0ffff;
1738 /* There may be endianness issues here. */
1739 dev
->dev_addr
[2 * i
] = val
& 0x0ff;
1740 dev
->dev_addr
[2 * i
+ 1] = (val
>> 8) & 0x0ff;
1743 /* read PROM address and compare with CSR address */
1744 for (i
= 0; i
< 6; i
++)
1745 promaddr
[i
] = inb(ioaddr
+ i
);
1747 if (memcmp(promaddr
, dev
->dev_addr
, 6)
1748 || !is_valid_ether_addr(dev
->dev_addr
)) {
1749 if (is_valid_ether_addr(promaddr
)) {
1750 if (pcnet32_debug
& NETIF_MSG_PROBE
) {
1751 printk(" warning: CSR address invalid,\n");
1753 " using instead PROM address of");
1755 memcpy(dev
->dev_addr
, promaddr
, 6);
1758 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
1760 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1761 if (!is_valid_ether_addr(dev
->perm_addr
))
1762 memset(dev
->dev_addr
, 0, sizeof(dev
->dev_addr
));
1764 if (pcnet32_debug
& NETIF_MSG_PROBE
) {
1765 printk(" %pM", dev
->dev_addr
);
1767 /* Version 0x2623 and 0x2624 */
1768 if (((chip_version
+ 1) & 0xfffe) == 0x2624) {
1769 i
= a
->read_csr(ioaddr
, 80) & 0x0C00; /* Check tx_start_pt */
1770 printk("\n" KERN_INFO
" tx_start_pt(0x%04x):", i
);
1773 printk(" 20 bytes,");
1776 printk(" 64 bytes,");
1779 printk(" 128 bytes,");
1782 printk("~220 bytes,");
1785 i
= a
->read_bcr(ioaddr
, 18); /* Check Burst/Bus control */
1786 printk(" BCR18(%x):", i
& 0xffff);
1788 printk("BurstWrEn ");
1790 printk("BurstRdEn ");
1795 i
= a
->read_bcr(ioaddr
, 25);
1796 printk("\n" KERN_INFO
" SRAMSIZE=0x%04x,", i
<< 8);
1797 i
= a
->read_bcr(ioaddr
, 26);
1798 printk(" SRAM_BND=0x%04x,", i
<< 8);
1799 i
= a
->read_bcr(ioaddr
, 27);
1805 dev
->base_addr
= ioaddr
;
1806 lp
= netdev_priv(dev
);
1807 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1808 if ((lp
->init_block
=
1809 pci_alloc_consistent(pdev
, sizeof(*lp
->init_block
), &lp
->init_dma_addr
)) == NULL
) {
1810 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1812 "Consistent memory allocation failed.\n");
1814 goto err_free_netdev
;
1820 spin_lock_init(&lp
->lock
);
1822 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1823 lp
->name
= chipname
;
1824 lp
->shared_irq
= shared
;
1825 lp
->tx_ring_size
= TX_RING_SIZE
; /* default tx ring size */
1826 lp
->rx_ring_size
= RX_RING_SIZE
; /* default rx ring size */
1827 lp
->tx_mod_mask
= lp
->tx_ring_size
- 1;
1828 lp
->rx_mod_mask
= lp
->rx_ring_size
- 1;
1829 lp
->tx_len_bits
= (PCNET32_LOG_TX_BUFFERS
<< 12);
1830 lp
->rx_len_bits
= (PCNET32_LOG_RX_BUFFERS
<< 4);
1831 lp
->mii_if
.full_duplex
= fdx
;
1832 lp
->mii_if
.phy_id_mask
= 0x1f;
1833 lp
->mii_if
.reg_num_mask
= 0x1f;
1834 lp
->dxsuflo
= dxsuflo
;
1836 lp
->chip_version
= chip_version
;
1837 lp
->msg_enable
= pcnet32_debug
;
1838 if ((cards_found
>= MAX_UNITS
)
1839 || (options
[cards_found
] > sizeof(options_mapping
)))
1840 lp
->options
= PCNET32_PORT_ASEL
;
1842 lp
->options
= options_mapping
[options
[cards_found
]];
1843 lp
->mii_if
.dev
= dev
;
1844 lp
->mii_if
.mdio_read
= mdio_read
;
1845 lp
->mii_if
.mdio_write
= mdio_write
;
1847 /* napi.weight is used in both the napi and non-napi cases */
1848 lp
->napi
.weight
= lp
->rx_ring_size
/ 2;
1850 netif_napi_add(dev
, &lp
->napi
, pcnet32_poll
, lp
->rx_ring_size
/ 2);
1852 if (fdx
&& !(lp
->options
& PCNET32_PORT_ASEL
) &&
1853 ((cards_found
>= MAX_UNITS
) || full_duplex
[cards_found
]))
1854 lp
->options
|= PCNET32_PORT_FD
;
1857 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1858 printk(KERN_ERR PFX
"No access methods\n");
1860 goto err_free_consistent
;
1864 /* prior to register_netdev, dev->name is not yet correct */
1865 if (pcnet32_alloc_ring(dev
, pci_name(lp
->pci_dev
))) {
1869 /* detect special T1/E1 WAN card by checking for MAC address */
1870 if (dev
->dev_addr
[0] == 0x00 && dev
->dev_addr
[1] == 0xe0
1871 && dev
->dev_addr
[2] == 0x75)
1872 lp
->options
= PCNET32_PORT_FD
| PCNET32_PORT_GPSI
;
1874 lp
->init_block
->mode
= cpu_to_le16(0x0003); /* Disable Rx and Tx. */
1875 lp
->init_block
->tlen_rlen
=
1876 cpu_to_le16(lp
->tx_len_bits
| lp
->rx_len_bits
);
1877 for (i
= 0; i
< 6; i
++)
1878 lp
->init_block
->phys_addr
[i
] = dev
->dev_addr
[i
];
1879 lp
->init_block
->filter
[0] = 0x00000000;
1880 lp
->init_block
->filter
[1] = 0x00000000;
1881 lp
->init_block
->rx_ring
= cpu_to_le32(lp
->rx_ring_dma_addr
);
1882 lp
->init_block
->tx_ring
= cpu_to_le32(lp
->tx_ring_dma_addr
);
1884 /* switch pcnet32 to 32bit mode */
1885 a
->write_bcr(ioaddr
, 20, 2);
1887 a
->write_csr(ioaddr
, 1, (lp
->init_dma_addr
& 0xffff));
1888 a
->write_csr(ioaddr
, 2, (lp
->init_dma_addr
>> 16));
1890 if (pdev
) { /* use the IRQ provided by PCI */
1891 dev
->irq
= pdev
->irq
;
1892 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1893 printk(" assigned IRQ %d.\n", dev
->irq
);
1895 unsigned long irq_mask
= probe_irq_on();
1898 * To auto-IRQ we enable the initialization-done and DMA error
1899 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1902 /* Trigger an initialization just for the interrupt. */
1903 a
->write_csr(ioaddr
, CSR0
, CSR0_INTEN
| CSR0_INIT
);
1906 dev
->irq
= probe_irq_off(irq_mask
);
1908 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1909 printk(", failed to detect IRQ line.\n");
1913 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1914 printk(", probed IRQ %d.\n", dev
->irq
);
1917 /* Set the mii phy_id so that we can query the link state */
1919 /* lp->phycount and lp->phymask are set to 0 by memset above */
1921 lp
->mii_if
.phy_id
= ((lp
->a
.read_bcr(ioaddr
, 33)) >> 5) & 0x1f;
1923 for (i
= 0; i
< PCNET32_MAX_PHYS
; i
++) {
1924 unsigned short id1
, id2
;
1926 id1
= mdio_read(dev
, i
, MII_PHYSID1
);
1929 id2
= mdio_read(dev
, i
, MII_PHYSID2
);
1932 if (i
== 31 && ((chip_version
+ 1) & 0xfffe) == 0x2624)
1933 continue; /* 79C971 & 79C972 have phantom phy at id 31 */
1935 lp
->phymask
|= (1 << i
);
1936 lp
->mii_if
.phy_id
= i
;
1937 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1938 printk(KERN_INFO PFX
1939 "Found PHY %04x:%04x at address %d.\n",
1942 lp
->a
.write_bcr(ioaddr
, 33, (lp
->mii_if
.phy_id
) << 5);
1943 if (lp
->phycount
> 1) {
1944 lp
->options
|= PCNET32_PORT_MII
;
1948 init_timer(&lp
->watchdog_timer
);
1949 lp
->watchdog_timer
.data
= (unsigned long)dev
;
1950 lp
->watchdog_timer
.function
= (void *)&pcnet32_watchdog
;
1952 /* The PCNET32-specific entries in the device structure. */
1953 dev
->netdev_ops
= &pcnet32_netdev_ops
;
1954 dev
->ethtool_ops
= &pcnet32_ethtool_ops
;
1955 dev
->watchdog_timeo
= (5 * HZ
);
1957 /* Fill in the generic fields of the device structure. */
1958 if (register_netdev(dev
))
1962 pci_set_drvdata(pdev
, dev
);
1964 lp
->next
= pcnet32_dev
;
1968 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1969 printk(KERN_INFO
"%s: registered as %s\n", dev
->name
, lp
->name
);
1972 /* enable LED writes */
1973 a
->write_bcr(ioaddr
, 2, a
->read_bcr(ioaddr
, 2) | 0x1000);
1978 pcnet32_free_ring(dev
);
1979 err_free_consistent
:
1980 pci_free_consistent(lp
->pci_dev
, sizeof(*lp
->init_block
),
1981 lp
->init_block
, lp
->init_dma_addr
);
1985 release_region(ioaddr
, PCNET32_TOTAL_SIZE
);
1989 /* if any allocation fails, caller must also call pcnet32_free_ring */
1990 static int pcnet32_alloc_ring(struct net_device
*dev
, const char *name
)
1992 struct pcnet32_private
*lp
= netdev_priv(dev
);
1994 lp
->tx_ring
= pci_alloc_consistent(lp
->pci_dev
,
1995 sizeof(struct pcnet32_tx_head
) *
1997 &lp
->tx_ring_dma_addr
);
1998 if (lp
->tx_ring
== NULL
) {
1999 if (netif_msg_drv(lp
))
2000 printk("\n" KERN_ERR PFX
2001 "%s: Consistent memory allocation failed.\n",
2006 lp
->rx_ring
= pci_alloc_consistent(lp
->pci_dev
,
2007 sizeof(struct pcnet32_rx_head
) *
2009 &lp
->rx_ring_dma_addr
);
2010 if (lp
->rx_ring
== NULL
) {
2011 if (netif_msg_drv(lp
))
2012 printk("\n" KERN_ERR PFX
2013 "%s: Consistent memory allocation failed.\n",
2018 lp
->tx_dma_addr
= kcalloc(lp
->tx_ring_size
, sizeof(dma_addr_t
),
2020 if (!lp
->tx_dma_addr
) {
2021 if (netif_msg_drv(lp
))
2022 printk("\n" KERN_ERR PFX
2023 "%s: Memory allocation failed.\n", name
);
2027 lp
->rx_dma_addr
= kcalloc(lp
->rx_ring_size
, sizeof(dma_addr_t
),
2029 if (!lp
->rx_dma_addr
) {
2030 if (netif_msg_drv(lp
))
2031 printk("\n" KERN_ERR PFX
2032 "%s: Memory allocation failed.\n", name
);
2036 lp
->tx_skbuff
= kcalloc(lp
->tx_ring_size
, sizeof(struct sk_buff
*),
2038 if (!lp
->tx_skbuff
) {
2039 if (netif_msg_drv(lp
))
2040 printk("\n" KERN_ERR PFX
2041 "%s: Memory allocation failed.\n", name
);
2045 lp
->rx_skbuff
= kcalloc(lp
->rx_ring_size
, sizeof(struct sk_buff
*),
2047 if (!lp
->rx_skbuff
) {
2048 if (netif_msg_drv(lp
))
2049 printk("\n" KERN_ERR PFX
2050 "%s: Memory allocation failed.\n", name
);
2057 static void pcnet32_free_ring(struct net_device
*dev
)
2059 struct pcnet32_private
*lp
= netdev_priv(dev
);
2061 kfree(lp
->tx_skbuff
);
2062 lp
->tx_skbuff
= NULL
;
2064 kfree(lp
->rx_skbuff
);
2065 lp
->rx_skbuff
= NULL
;
2067 kfree(lp
->tx_dma_addr
);
2068 lp
->tx_dma_addr
= NULL
;
2070 kfree(lp
->rx_dma_addr
);
2071 lp
->rx_dma_addr
= NULL
;
2074 pci_free_consistent(lp
->pci_dev
,
2075 sizeof(struct pcnet32_tx_head
) *
2076 lp
->tx_ring_size
, lp
->tx_ring
,
2077 lp
->tx_ring_dma_addr
);
2082 pci_free_consistent(lp
->pci_dev
,
2083 sizeof(struct pcnet32_rx_head
) *
2084 lp
->rx_ring_size
, lp
->rx_ring
,
2085 lp
->rx_ring_dma_addr
);
2090 static int pcnet32_open(struct net_device
*dev
)
2092 struct pcnet32_private
*lp
= netdev_priv(dev
);
2093 unsigned long ioaddr
= dev
->base_addr
;
2097 unsigned long flags
;
2099 if (request_irq(dev
->irq
, &pcnet32_interrupt
,
2100 lp
->shared_irq
? IRQF_SHARED
: 0, dev
->name
,
2105 spin_lock_irqsave(&lp
->lock
, flags
);
2106 /* Check for a valid station address */
2107 if (!is_valid_ether_addr(dev
->dev_addr
)) {
2112 /* Reset the PCNET32 */
2113 lp
->a
.reset(ioaddr
);
2115 /* switch pcnet32 to 32bit mode */
2116 lp
->a
.write_bcr(ioaddr
, 20, 2);
2118 if (netif_msg_ifup(lp
))
2120 "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
2121 dev
->name
, dev
->irq
, (u32
) (lp
->tx_ring_dma_addr
),
2122 (u32
) (lp
->rx_ring_dma_addr
),
2123 (u32
) (lp
->init_dma_addr
));
2125 /* set/reset autoselect bit */
2126 val
= lp
->a
.read_bcr(ioaddr
, 2) & ~2;
2127 if (lp
->options
& PCNET32_PORT_ASEL
)
2129 lp
->a
.write_bcr(ioaddr
, 2, val
);
2131 /* handle full duplex setting */
2132 if (lp
->mii_if
.full_duplex
) {
2133 val
= lp
->a
.read_bcr(ioaddr
, 9) & ~3;
2134 if (lp
->options
& PCNET32_PORT_FD
) {
2136 if (lp
->options
== (PCNET32_PORT_FD
| PCNET32_PORT_AUI
))
2138 } else if (lp
->options
& PCNET32_PORT_ASEL
) {
2139 /* workaround of xSeries250, turn on for 79C975 only */
2140 if (lp
->chip_version
== 0x2627)
2143 lp
->a
.write_bcr(ioaddr
, 9, val
);
2146 /* set/reset GPSI bit in test register */
2147 val
= lp
->a
.read_csr(ioaddr
, 124) & ~0x10;
2148 if ((lp
->options
& PCNET32_PORT_PORTSEL
) == PCNET32_PORT_GPSI
)
2150 lp
->a
.write_csr(ioaddr
, 124, val
);
2152 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
2153 if (lp
->pci_dev
->subsystem_vendor
== PCI_VENDOR_ID_AT
&&
2154 (lp
->pci_dev
->subsystem_device
== PCI_SUBDEVICE_ID_AT_2700FX
||
2155 lp
->pci_dev
->subsystem_device
== PCI_SUBDEVICE_ID_AT_2701FX
)) {
2156 if (lp
->options
& PCNET32_PORT_ASEL
) {
2157 lp
->options
= PCNET32_PORT_FD
| PCNET32_PORT_100
;
2158 if (netif_msg_link(lp
))
2160 "%s: Setting 100Mb-Full Duplex.\n",
2164 if (lp
->phycount
< 2) {
2166 * 24 Jun 2004 according AMD, in order to change the PHY,
2167 * DANAS (or DISPM for 79C976) must be set; then select the speed,
2168 * duplex, and/or enable auto negotiation, and clear DANAS
2170 if (lp
->mii
&& !(lp
->options
& PCNET32_PORT_ASEL
)) {
2171 lp
->a
.write_bcr(ioaddr
, 32,
2172 lp
->a
.read_bcr(ioaddr
, 32) | 0x0080);
2173 /* disable Auto Negotiation, set 10Mpbs, HD */
2174 val
= lp
->a
.read_bcr(ioaddr
, 32) & ~0xb8;
2175 if (lp
->options
& PCNET32_PORT_FD
)
2177 if (lp
->options
& PCNET32_PORT_100
)
2179 lp
->a
.write_bcr(ioaddr
, 32, val
);
2181 if (lp
->options
& PCNET32_PORT_ASEL
) {
2182 lp
->a
.write_bcr(ioaddr
, 32,
2183 lp
->a
.read_bcr(ioaddr
,
2185 /* enable auto negotiate, setup, disable fd */
2186 val
= lp
->a
.read_bcr(ioaddr
, 32) & ~0x98;
2188 lp
->a
.write_bcr(ioaddr
, 32, val
);
2195 struct ethtool_cmd ecmd
;
2198 * There is really no good other way to handle multiple PHYs
2199 * other than turning off all automatics
2201 val
= lp
->a
.read_bcr(ioaddr
, 2);
2202 lp
->a
.write_bcr(ioaddr
, 2, val
& ~2);
2203 val
= lp
->a
.read_bcr(ioaddr
, 32);
2204 lp
->a
.write_bcr(ioaddr
, 32, val
& ~(1 << 7)); /* stop MII manager */
2206 if (!(lp
->options
& PCNET32_PORT_ASEL
)) {
2208 ecmd
.port
= PORT_MII
;
2209 ecmd
.transceiver
= XCVR_INTERNAL
;
2210 ecmd
.autoneg
= AUTONEG_DISABLE
;
2213 options
& PCNET32_PORT_100
? SPEED_100
: SPEED_10
;
2214 bcr9
= lp
->a
.read_bcr(ioaddr
, 9);
2216 if (lp
->options
& PCNET32_PORT_FD
) {
2217 ecmd
.duplex
= DUPLEX_FULL
;
2220 ecmd
.duplex
= DUPLEX_HALF
;
2223 lp
->a
.write_bcr(ioaddr
, 9, bcr9
);
2226 for (i
= 0; i
< PCNET32_MAX_PHYS
; i
++) {
2227 if (lp
->phymask
& (1 << i
)) {
2228 /* isolate all but the first PHY */
2229 bmcr
= mdio_read(dev
, i
, MII_BMCR
);
2230 if (first_phy
== -1) {
2232 mdio_write(dev
, i
, MII_BMCR
,
2233 bmcr
& ~BMCR_ISOLATE
);
2235 mdio_write(dev
, i
, MII_BMCR
,
2236 bmcr
| BMCR_ISOLATE
);
2238 /* use mii_ethtool_sset to setup PHY */
2239 lp
->mii_if
.phy_id
= i
;
2240 ecmd
.phy_address
= i
;
2241 if (lp
->options
& PCNET32_PORT_ASEL
) {
2242 mii_ethtool_gset(&lp
->mii_if
, &ecmd
);
2243 ecmd
.autoneg
= AUTONEG_ENABLE
;
2245 mii_ethtool_sset(&lp
->mii_if
, &ecmd
);
2248 lp
->mii_if
.phy_id
= first_phy
;
2249 if (netif_msg_link(lp
))
2250 printk(KERN_INFO
"%s: Using PHY number %d.\n",
2251 dev
->name
, first_phy
);
2255 if (lp
->dxsuflo
) { /* Disable transmit stop on underflow */
2256 val
= lp
->a
.read_csr(ioaddr
, CSR3
);
2258 lp
->a
.write_csr(ioaddr
, CSR3
, val
);
2262 lp
->init_block
->mode
=
2263 cpu_to_le16((lp
->options
& PCNET32_PORT_PORTSEL
) << 7);
2264 pcnet32_load_multicast(dev
);
2266 if (pcnet32_init_ring(dev
)) {
2271 napi_enable(&lp
->napi
);
2273 /* Re-initialize the PCNET32, and start it when done. */
2274 lp
->a
.write_csr(ioaddr
, 1, (lp
->init_dma_addr
& 0xffff));
2275 lp
->a
.write_csr(ioaddr
, 2, (lp
->init_dma_addr
>> 16));
2277 lp
->a
.write_csr(ioaddr
, CSR4
, 0x0915); /* auto tx pad */
2278 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_INIT
);
2280 netif_start_queue(dev
);
2282 if (lp
->chip_version
>= PCNET32_79C970A
) {
2283 /* Print the link status and start the watchdog */
2284 pcnet32_check_media(dev
, 1);
2285 mod_timer(&lp
->watchdog_timer
, PCNET32_WATCHDOG_TIMEOUT
);
2290 if (lp
->a
.read_csr(ioaddr
, CSR0
) & CSR0_IDON
)
2293 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2294 * reports that doing so triggers a bug in the '974.
2296 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_NORMAL
);
2298 if (netif_msg_ifup(lp
))
2300 "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
2302 (u32
) (lp
->init_dma_addr
),
2303 lp
->a
.read_csr(ioaddr
, CSR0
));
2305 spin_unlock_irqrestore(&lp
->lock
, flags
);
2307 return 0; /* Always succeed */
2310 /* free any allocated skbuffs */
2311 pcnet32_purge_rx_ring(dev
);
2314 * Switch back to 16bit mode to avoid problems with dumb
2315 * DOS packet driver after a warm reboot
2317 lp
->a
.write_bcr(ioaddr
, 20, 4);
2320 spin_unlock_irqrestore(&lp
->lock
, flags
);
2321 free_irq(dev
->irq
, dev
);
2326 * The LANCE has been halted for one reason or another (busmaster memory
2327 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2328 * etc.). Modern LANCE variants always reload their ring-buffer
2329 * configuration when restarted, so we must reinitialize our ring
2330 * context before restarting. As part of this reinitialization,
2331 * find all packets still on the Tx ring and pretend that they had been
2332 * sent (in effect, drop the packets on the floor) - the higher-level
2333 * protocols will time out and retransmit. It'd be better to shuffle
2334 * these skbs to a temp list and then actually re-Tx them after
2335 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
2338 static void pcnet32_purge_tx_ring(struct net_device
*dev
)
2340 struct pcnet32_private
*lp
= netdev_priv(dev
);
2343 for (i
= 0; i
< lp
->tx_ring_size
; i
++) {
2344 lp
->tx_ring
[i
].status
= 0; /* CPU owns buffer */
2345 wmb(); /* Make sure adapter sees owner change */
2346 if (lp
->tx_skbuff
[i
]) {
2347 pci_unmap_single(lp
->pci_dev
, lp
->tx_dma_addr
[i
],
2348 lp
->tx_skbuff
[i
]->len
,
2350 dev_kfree_skb_any(lp
->tx_skbuff
[i
]);
2352 lp
->tx_skbuff
[i
] = NULL
;
2353 lp
->tx_dma_addr
[i
] = 0;
2357 /* Initialize the PCNET32 Rx and Tx rings. */
2358 static int pcnet32_init_ring(struct net_device
*dev
)
2360 struct pcnet32_private
*lp
= netdev_priv(dev
);
2364 lp
->cur_rx
= lp
->cur_tx
= 0;
2365 lp
->dirty_rx
= lp
->dirty_tx
= 0;
2367 for (i
= 0; i
< lp
->rx_ring_size
; i
++) {
2368 struct sk_buff
*rx_skbuff
= lp
->rx_skbuff
[i
];
2369 if (rx_skbuff
== NULL
) {
2371 (rx_skbuff
= lp
->rx_skbuff
[i
] =
2372 dev_alloc_skb(PKT_BUF_SKB
))) {
2373 /* there is not much, we can do at this point */
2374 if (netif_msg_drv(lp
))
2376 "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
2380 skb_reserve(rx_skbuff
, NET_IP_ALIGN
);
2384 if (lp
->rx_dma_addr
[i
] == 0)
2385 lp
->rx_dma_addr
[i
] =
2386 pci_map_single(lp
->pci_dev
, rx_skbuff
->data
,
2387 PKT_BUF_SIZE
, PCI_DMA_FROMDEVICE
);
2388 lp
->rx_ring
[i
].base
= cpu_to_le32(lp
->rx_dma_addr
[i
]);
2389 lp
->rx_ring
[i
].buf_length
= cpu_to_le16(NEG_BUF_SIZE
);
2390 wmb(); /* Make sure owner changes after all others are visible */
2391 lp
->rx_ring
[i
].status
= cpu_to_le16(0x8000);
2393 /* The Tx buffer address is filled in as needed, but we do need to clear
2394 * the upper ownership bit. */
2395 for (i
= 0; i
< lp
->tx_ring_size
; i
++) {
2396 lp
->tx_ring
[i
].status
= 0; /* CPU owns buffer */
2397 wmb(); /* Make sure adapter sees owner change */
2398 lp
->tx_ring
[i
].base
= 0;
2399 lp
->tx_dma_addr
[i
] = 0;
2402 lp
->init_block
->tlen_rlen
=
2403 cpu_to_le16(lp
->tx_len_bits
| lp
->rx_len_bits
);
2404 for (i
= 0; i
< 6; i
++)
2405 lp
->init_block
->phys_addr
[i
] = dev
->dev_addr
[i
];
2406 lp
->init_block
->rx_ring
= cpu_to_le32(lp
->rx_ring_dma_addr
);
2407 lp
->init_block
->tx_ring
= cpu_to_le32(lp
->tx_ring_dma_addr
);
2408 wmb(); /* Make sure all changes are visible */
2412 /* the pcnet32 has been issued a stop or reset. Wait for the stop bit
2413 * then flush the pending transmit operations, re-initialize the ring,
2414 * and tell the chip to initialize.
2416 static void pcnet32_restart(struct net_device
*dev
, unsigned int csr0_bits
)
2418 struct pcnet32_private
*lp
= netdev_priv(dev
);
2419 unsigned long ioaddr
= dev
->base_addr
;
2423 for (i
= 0; i
< 100; i
++)
2424 if (lp
->a
.read_csr(ioaddr
, CSR0
) & CSR0_STOP
)
2427 if (i
>= 100 && netif_msg_drv(lp
))
2429 "%s: pcnet32_restart timed out waiting for stop.\n",
2432 pcnet32_purge_tx_ring(dev
);
2433 if (pcnet32_init_ring(dev
))
2437 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_INIT
);
2440 if (lp
->a
.read_csr(ioaddr
, CSR0
) & CSR0_IDON
)
2443 lp
->a
.write_csr(ioaddr
, CSR0
, csr0_bits
);
2446 static void pcnet32_tx_timeout(struct net_device
*dev
)
2448 struct pcnet32_private
*lp
= netdev_priv(dev
);
2449 unsigned long ioaddr
= dev
->base_addr
, flags
;
2451 spin_lock_irqsave(&lp
->lock
, flags
);
2452 /* Transmitter timeout, serious problems. */
2453 if (pcnet32_debug
& NETIF_MSG_DRV
)
2455 "%s: transmit timed out, status %4.4x, resetting.\n",
2456 dev
->name
, lp
->a
.read_csr(ioaddr
, CSR0
));
2457 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_STOP
);
2458 dev
->stats
.tx_errors
++;
2459 if (netif_msg_tx_err(lp
)) {
2462 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2463 lp
->dirty_tx
, lp
->cur_tx
, lp
->tx_full
? " (full)" : "",
2465 for (i
= 0; i
< lp
->rx_ring_size
; i
++)
2466 printk("%s %08x %04x %08x %04x", i
& 1 ? "" : "\n ",
2467 le32_to_cpu(lp
->rx_ring
[i
].base
),
2468 (-le16_to_cpu(lp
->rx_ring
[i
].buf_length
)) &
2469 0xffff, le32_to_cpu(lp
->rx_ring
[i
].msg_length
),
2470 le16_to_cpu(lp
->rx_ring
[i
].status
));
2471 for (i
= 0; i
< lp
->tx_ring_size
; i
++)
2472 printk("%s %08x %04x %08x %04x", i
& 1 ? "" : "\n ",
2473 le32_to_cpu(lp
->tx_ring
[i
].base
),
2474 (-le16_to_cpu(lp
->tx_ring
[i
].length
)) & 0xffff,
2475 le32_to_cpu(lp
->tx_ring
[i
].misc
),
2476 le16_to_cpu(lp
->tx_ring
[i
].status
));
2479 pcnet32_restart(dev
, CSR0_NORMAL
);
2481 dev
->trans_start
= jiffies
;
2482 netif_wake_queue(dev
);
2484 spin_unlock_irqrestore(&lp
->lock
, flags
);
2487 static int pcnet32_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2489 struct pcnet32_private
*lp
= netdev_priv(dev
);
2490 unsigned long ioaddr
= dev
->base_addr
;
2493 unsigned long flags
;
2495 spin_lock_irqsave(&lp
->lock
, flags
);
2497 if (netif_msg_tx_queued(lp
)) {
2499 "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
2500 dev
->name
, lp
->a
.read_csr(ioaddr
, CSR0
));
2503 /* Default status -- will not enable Successful-TxDone
2504 * interrupt when that option is available to us.
2508 /* Fill in a Tx ring entry */
2510 /* Mask to ring buffer boundary. */
2511 entry
= lp
->cur_tx
& lp
->tx_mod_mask
;
2513 /* Caution: the write order is important here, set the status
2514 * with the "ownership" bits last. */
2516 lp
->tx_ring
[entry
].length
= cpu_to_le16(-skb
->len
);
2518 lp
->tx_ring
[entry
].misc
= 0x00000000;
2520 lp
->tx_skbuff
[entry
] = skb
;
2521 lp
->tx_dma_addr
[entry
] =
2522 pci_map_single(lp
->pci_dev
, skb
->data
, skb
->len
, PCI_DMA_TODEVICE
);
2523 lp
->tx_ring
[entry
].base
= cpu_to_le32(lp
->tx_dma_addr
[entry
]);
2524 wmb(); /* Make sure owner changes after all others are visible */
2525 lp
->tx_ring
[entry
].status
= cpu_to_le16(status
);
2528 dev
->stats
.tx_bytes
+= skb
->len
;
2530 /* Trigger an immediate send poll. */
2531 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_INTEN
| CSR0_TXPOLL
);
2533 dev
->trans_start
= jiffies
;
2535 if (lp
->tx_ring
[(entry
+ 1) & lp
->tx_mod_mask
].base
!= 0) {
2537 netif_stop_queue(dev
);
2539 spin_unlock_irqrestore(&lp
->lock
, flags
);
2543 /* The PCNET32 interrupt handler. */
2545 pcnet32_interrupt(int irq
, void *dev_id
)
2547 struct net_device
*dev
= dev_id
;
2548 struct pcnet32_private
*lp
;
2549 unsigned long ioaddr
;
2551 int boguscnt
= max_interrupt_work
;
2553 ioaddr
= dev
->base_addr
;
2554 lp
= netdev_priv(dev
);
2556 spin_lock(&lp
->lock
);
2558 csr0
= lp
->a
.read_csr(ioaddr
, CSR0
);
2559 while ((csr0
& 0x8f00) && --boguscnt
>= 0) {
2560 if (csr0
== 0xffff) {
2561 break; /* PCMCIA remove happened */
2563 /* Acknowledge all of the current interrupt sources ASAP. */
2564 lp
->a
.write_csr(ioaddr
, CSR0
, csr0
& ~0x004f);
2566 if (netif_msg_intr(lp
))
2568 "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
2569 dev
->name
, csr0
, lp
->a
.read_csr(ioaddr
, CSR0
));
2571 /* Log misc errors. */
2573 dev
->stats
.tx_errors
++; /* Tx babble. */
2574 if (csr0
& 0x1000) {
2576 * This happens when our receive ring is full. This
2577 * shouldn't be a problem as we will see normal rx
2578 * interrupts for the frames in the receive ring. But
2579 * there are some PCI chipsets (I can reproduce this
2580 * on SP3G with Intel saturn chipset) which have
2581 * sometimes problems and will fill up the receive
2582 * ring with error descriptors. In this situation we
2583 * don't get a rx interrupt, but a missed frame
2584 * interrupt sooner or later.
2586 dev
->stats
.rx_errors
++; /* Missed a Rx frame. */
2588 if (csr0
& 0x0800) {
2589 if (netif_msg_drv(lp
))
2591 "%s: Bus master arbitration failure, status %4.4x.\n",
2593 /* unlike for the lance, there is no restart needed */
2595 if (napi_schedule_prep(&lp
->napi
)) {
2597 /* set interrupt masks */
2598 val
= lp
->a
.read_csr(ioaddr
, CSR3
);
2600 lp
->a
.write_csr(ioaddr
, CSR3
, val
);
2602 __napi_schedule(&lp
->napi
);
2605 csr0
= lp
->a
.read_csr(ioaddr
, CSR0
);
2608 if (netif_msg_intr(lp
))
2609 printk(KERN_DEBUG
"%s: exiting interrupt, csr0=%#4.4x.\n",
2610 dev
->name
, lp
->a
.read_csr(ioaddr
, CSR0
));
2612 spin_unlock(&lp
->lock
);
2617 static int pcnet32_close(struct net_device
*dev
)
2619 unsigned long ioaddr
= dev
->base_addr
;
2620 struct pcnet32_private
*lp
= netdev_priv(dev
);
2621 unsigned long flags
;
2623 del_timer_sync(&lp
->watchdog_timer
);
2625 netif_stop_queue(dev
);
2626 napi_disable(&lp
->napi
);
2628 spin_lock_irqsave(&lp
->lock
, flags
);
2630 dev
->stats
.rx_missed_errors
= lp
->a
.read_csr(ioaddr
, 112);
2632 if (netif_msg_ifdown(lp
))
2634 "%s: Shutting down ethercard, status was %2.2x.\n",
2635 dev
->name
, lp
->a
.read_csr(ioaddr
, CSR0
));
2637 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2638 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_STOP
);
2641 * Switch back to 16bit mode to avoid problems with dumb
2642 * DOS packet driver after a warm reboot
2644 lp
->a
.write_bcr(ioaddr
, 20, 4);
2646 spin_unlock_irqrestore(&lp
->lock
, flags
);
2648 free_irq(dev
->irq
, dev
);
2650 spin_lock_irqsave(&lp
->lock
, flags
);
2652 pcnet32_purge_rx_ring(dev
);
2653 pcnet32_purge_tx_ring(dev
);
2655 spin_unlock_irqrestore(&lp
->lock
, flags
);
2660 static struct net_device_stats
*pcnet32_get_stats(struct net_device
*dev
)
2662 struct pcnet32_private
*lp
= netdev_priv(dev
);
2663 unsigned long ioaddr
= dev
->base_addr
;
2664 unsigned long flags
;
2666 spin_lock_irqsave(&lp
->lock
, flags
);
2667 dev
->stats
.rx_missed_errors
= lp
->a
.read_csr(ioaddr
, 112);
2668 spin_unlock_irqrestore(&lp
->lock
, flags
);
2673 /* taken from the sunlance driver, which it took from the depca driver */
2674 static void pcnet32_load_multicast(struct net_device
*dev
)
2676 struct pcnet32_private
*lp
= netdev_priv(dev
);
2677 volatile struct pcnet32_init_block
*ib
= lp
->init_block
;
2678 volatile __le16
*mcast_table
= (__le16
*)ib
->filter
;
2679 struct dev_mc_list
*dmi
= dev
->mc_list
;
2680 unsigned long ioaddr
= dev
->base_addr
;
2685 /* set all multicast bits */
2686 if (dev
->flags
& IFF_ALLMULTI
) {
2687 ib
->filter
[0] = cpu_to_le32(~0U);
2688 ib
->filter
[1] = cpu_to_le32(~0U);
2689 lp
->a
.write_csr(ioaddr
, PCNET32_MC_FILTER
, 0xffff);
2690 lp
->a
.write_csr(ioaddr
, PCNET32_MC_FILTER
+1, 0xffff);
2691 lp
->a
.write_csr(ioaddr
, PCNET32_MC_FILTER
+2, 0xffff);
2692 lp
->a
.write_csr(ioaddr
, PCNET32_MC_FILTER
+3, 0xffff);
2695 /* clear the multicast filter */
2700 for (i
= 0; i
< dev
->mc_count
; i
++) {
2701 addrs
= dmi
->dmi_addr
;
2704 /* multicast address? */
2708 crc
= ether_crc_le(6, addrs
);
2710 mcast_table
[crc
>> 4] |= cpu_to_le16(1 << (crc
& 0xf));
2712 for (i
= 0; i
< 4; i
++)
2713 lp
->a
.write_csr(ioaddr
, PCNET32_MC_FILTER
+ i
,
2714 le16_to_cpu(mcast_table
[i
]));
2719 * Set or clear the multicast filter for this adaptor.
2721 static void pcnet32_set_multicast_list(struct net_device
*dev
)
2723 unsigned long ioaddr
= dev
->base_addr
, flags
;
2724 struct pcnet32_private
*lp
= netdev_priv(dev
);
2725 int csr15
, suspended
;
2727 spin_lock_irqsave(&lp
->lock
, flags
);
2728 suspended
= pcnet32_suspend(dev
, &flags
, 0);
2729 csr15
= lp
->a
.read_csr(ioaddr
, CSR15
);
2730 if (dev
->flags
& IFF_PROMISC
) {
2731 /* Log any net taps. */
2732 if (netif_msg_hw(lp
))
2733 printk(KERN_INFO
"%s: Promiscuous mode enabled.\n",
2735 lp
->init_block
->mode
=
2736 cpu_to_le16(0x8000 | (lp
->options
& PCNET32_PORT_PORTSEL
) <<
2738 lp
->a
.write_csr(ioaddr
, CSR15
, csr15
| 0x8000);
2740 lp
->init_block
->mode
=
2741 cpu_to_le16((lp
->options
& PCNET32_PORT_PORTSEL
) << 7);
2742 lp
->a
.write_csr(ioaddr
, CSR15
, csr15
& 0x7fff);
2743 pcnet32_load_multicast(dev
);
2748 /* clear SUSPEND (SPND) - CSR5 bit 0 */
2749 csr5
= lp
->a
.read_csr(ioaddr
, CSR5
);
2750 lp
->a
.write_csr(ioaddr
, CSR5
, csr5
& (~CSR5_SUSPEND
));
2752 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_STOP
);
2753 pcnet32_restart(dev
, CSR0_NORMAL
);
2754 netif_wake_queue(dev
);
2757 spin_unlock_irqrestore(&lp
->lock
, flags
);
2760 /* This routine assumes that the lp->lock is held */
2761 static int mdio_read(struct net_device
*dev
, int phy_id
, int reg_num
)
2763 struct pcnet32_private
*lp
= netdev_priv(dev
);
2764 unsigned long ioaddr
= dev
->base_addr
;
2770 lp
->a
.write_bcr(ioaddr
, 33, ((phy_id
& 0x1f) << 5) | (reg_num
& 0x1f));
2771 val_out
= lp
->a
.read_bcr(ioaddr
, 34);
2776 /* This routine assumes that the lp->lock is held */
2777 static void mdio_write(struct net_device
*dev
, int phy_id
, int reg_num
, int val
)
2779 struct pcnet32_private
*lp
= netdev_priv(dev
);
2780 unsigned long ioaddr
= dev
->base_addr
;
2785 lp
->a
.write_bcr(ioaddr
, 33, ((phy_id
& 0x1f) << 5) | (reg_num
& 0x1f));
2786 lp
->a
.write_bcr(ioaddr
, 34, val
);
2789 static int pcnet32_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
2791 struct pcnet32_private
*lp
= netdev_priv(dev
);
2793 unsigned long flags
;
2795 /* SIOC[GS]MIIxxx ioctls */
2797 spin_lock_irqsave(&lp
->lock
, flags
);
2798 rc
= generic_mii_ioctl(&lp
->mii_if
, if_mii(rq
), cmd
, NULL
);
2799 spin_unlock_irqrestore(&lp
->lock
, flags
);
2807 static int pcnet32_check_otherphy(struct net_device
*dev
)
2809 struct pcnet32_private
*lp
= netdev_priv(dev
);
2810 struct mii_if_info mii
= lp
->mii_if
;
2814 for (i
= 0; i
< PCNET32_MAX_PHYS
; i
++) {
2815 if (i
== lp
->mii_if
.phy_id
)
2816 continue; /* skip active phy */
2817 if (lp
->phymask
& (1 << i
)) {
2819 if (mii_link_ok(&mii
)) {
2820 /* found PHY with active link */
2821 if (netif_msg_link(lp
))
2823 "%s: Using PHY number %d.\n",
2826 /* isolate inactive phy */
2828 mdio_read(dev
, lp
->mii_if
.phy_id
, MII_BMCR
);
2829 mdio_write(dev
, lp
->mii_if
.phy_id
, MII_BMCR
,
2830 bmcr
| BMCR_ISOLATE
);
2832 /* de-isolate new phy */
2833 bmcr
= mdio_read(dev
, i
, MII_BMCR
);
2834 mdio_write(dev
, i
, MII_BMCR
,
2835 bmcr
& ~BMCR_ISOLATE
);
2837 /* set new phy address */
2838 lp
->mii_if
.phy_id
= i
;
2847 * Show the status of the media. Similar to mii_check_media however it
2848 * correctly shows the link speed for all (tested) pcnet32 variants.
2849 * Devices with no mii just report link state without speed.
2851 * Caller is assumed to hold and release the lp->lock.
2854 static void pcnet32_check_media(struct net_device
*dev
, int verbose
)
2856 struct pcnet32_private
*lp
= netdev_priv(dev
);
2858 int prev_link
= netif_carrier_ok(dev
) ? 1 : 0;
2862 curr_link
= mii_link_ok(&lp
->mii_if
);
2864 ulong ioaddr
= dev
->base_addr
; /* card base I/O address */
2865 curr_link
= (lp
->a
.read_bcr(ioaddr
, 4) != 0xc0);
2868 if (prev_link
|| verbose
) {
2869 netif_carrier_off(dev
);
2870 if (netif_msg_link(lp
))
2871 printk(KERN_INFO
"%s: link down\n", dev
->name
);
2873 if (lp
->phycount
> 1) {
2874 curr_link
= pcnet32_check_otherphy(dev
);
2877 } else if (verbose
|| !prev_link
) {
2878 netif_carrier_on(dev
);
2880 if (netif_msg_link(lp
)) {
2881 struct ethtool_cmd ecmd
;
2882 mii_ethtool_gset(&lp
->mii_if
, &ecmd
);
2884 "%s: link up, %sMbps, %s-duplex\n",
2886 (ecmd
.speed
== SPEED_100
) ? "100" : "10",
2888 DUPLEX_FULL
) ? "full" : "half");
2890 bcr9
= lp
->a
.read_bcr(dev
->base_addr
, 9);
2891 if ((bcr9
& (1 << 0)) != lp
->mii_if
.full_duplex
) {
2892 if (lp
->mii_if
.full_duplex
)
2896 lp
->a
.write_bcr(dev
->base_addr
, 9, bcr9
);
2899 if (netif_msg_link(lp
))
2900 printk(KERN_INFO
"%s: link up\n", dev
->name
);
2906 * Check for loss of link and link establishment.
2907 * Can not use mii_check_media because it does nothing if mode is forced.
2910 static void pcnet32_watchdog(struct net_device
*dev
)
2912 struct pcnet32_private
*lp
= netdev_priv(dev
);
2913 unsigned long flags
;
2915 /* Print the link status if it has changed */
2916 spin_lock_irqsave(&lp
->lock
, flags
);
2917 pcnet32_check_media(dev
, 0);
2918 spin_unlock_irqrestore(&lp
->lock
, flags
);
2920 mod_timer(&lp
->watchdog_timer
, round_jiffies(PCNET32_WATCHDOG_TIMEOUT
));
2923 static int pcnet32_pm_suspend(struct pci_dev
*pdev
, pm_message_t state
)
2925 struct net_device
*dev
= pci_get_drvdata(pdev
);
2927 if (netif_running(dev
)) {
2928 netif_device_detach(dev
);
2931 pci_save_state(pdev
);
2932 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
2936 static int pcnet32_pm_resume(struct pci_dev
*pdev
)
2938 struct net_device
*dev
= pci_get_drvdata(pdev
);
2940 pci_set_power_state(pdev
, PCI_D0
);
2941 pci_restore_state(pdev
);
2943 if (netif_running(dev
)) {
2945 netif_device_attach(dev
);
2950 static void __devexit
pcnet32_remove_one(struct pci_dev
*pdev
)
2952 struct net_device
*dev
= pci_get_drvdata(pdev
);
2955 struct pcnet32_private
*lp
= netdev_priv(dev
);
2957 unregister_netdev(dev
);
2958 pcnet32_free_ring(dev
);
2959 release_region(dev
->base_addr
, PCNET32_TOTAL_SIZE
);
2960 pci_free_consistent(lp
->pci_dev
, sizeof(*lp
->init_block
),
2961 lp
->init_block
, lp
->init_dma_addr
);
2963 pci_disable_device(pdev
);
2964 pci_set_drvdata(pdev
, NULL
);
2968 static struct pci_driver pcnet32_driver
= {
2970 .probe
= pcnet32_probe_pci
,
2971 .remove
= __devexit_p(pcnet32_remove_one
),
2972 .id_table
= pcnet32_pci_tbl
,
2973 .suspend
= pcnet32_pm_suspend
,
2974 .resume
= pcnet32_pm_resume
,
2977 /* An additional parameter that may be passed in... */
2978 static int debug
= -1;
2979 static int tx_start_pt
= -1;
2980 static int pcnet32_have_pci
;
2982 module_param(debug
, int, 0);
2983 MODULE_PARM_DESC(debug
, DRV_NAME
" debug level");
2984 module_param(max_interrupt_work
, int, 0);
2985 MODULE_PARM_DESC(max_interrupt_work
,
2986 DRV_NAME
" maximum events handled per interrupt");
2987 module_param(rx_copybreak
, int, 0);
2988 MODULE_PARM_DESC(rx_copybreak
,
2989 DRV_NAME
" copy breakpoint for copy-only-tiny-frames");
2990 module_param(tx_start_pt
, int, 0);
2991 MODULE_PARM_DESC(tx_start_pt
, DRV_NAME
" transmit start point (0-3)");
2992 module_param(pcnet32vlb
, int, 0);
2993 MODULE_PARM_DESC(pcnet32vlb
, DRV_NAME
" Vesa local bus (VLB) support (0/1)");
2994 module_param_array(options
, int, NULL
, 0);
2995 MODULE_PARM_DESC(options
, DRV_NAME
" initial option setting(s) (0-15)");
2996 module_param_array(full_duplex
, int, NULL
, 0);
2997 MODULE_PARM_DESC(full_duplex
, DRV_NAME
" full duplex setting(s) (1)");
2998 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
2999 module_param_array(homepna
, int, NULL
, 0);
3000 MODULE_PARM_DESC(homepna
,
3002 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
3004 MODULE_AUTHOR("Thomas Bogendoerfer");
3005 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
3006 MODULE_LICENSE("GPL");
3008 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
3010 static int __init
pcnet32_init_module(void)
3012 printk(KERN_INFO
"%s", version
);
3014 pcnet32_debug
= netif_msg_init(debug
, PCNET32_MSG_DEFAULT
);
3016 if ((tx_start_pt
>= 0) && (tx_start_pt
<= 3))
3017 tx_start
= tx_start_pt
;
3019 /* find the PCI devices */
3020 if (!pci_register_driver(&pcnet32_driver
))
3021 pcnet32_have_pci
= 1;
3023 /* should we find any remaining VLbus devices ? */
3025 pcnet32_probe_vlbus(pcnet32_portlist
);
3027 if (cards_found
&& (pcnet32_debug
& NETIF_MSG_PROBE
))
3028 printk(KERN_INFO PFX
"%d cards_found.\n", cards_found
);
3030 return (pcnet32_have_pci
+ cards_found
) ? 0 : -ENODEV
;
3033 static void __exit
pcnet32_cleanup_module(void)
3035 struct net_device
*next_dev
;
3037 while (pcnet32_dev
) {
3038 struct pcnet32_private
*lp
= netdev_priv(pcnet32_dev
);
3039 next_dev
= lp
->next
;
3040 unregister_netdev(pcnet32_dev
);
3041 pcnet32_free_ring(pcnet32_dev
);
3042 release_region(pcnet32_dev
->base_addr
, PCNET32_TOTAL_SIZE
);
3043 pci_free_consistent(lp
->pci_dev
, sizeof(*lp
->init_block
),
3044 lp
->init_block
, lp
->init_dma_addr
);
3045 free_netdev(pcnet32_dev
);
3046 pcnet32_dev
= next_dev
;
3049 if (pcnet32_have_pci
)
3050 pci_unregister_driver(&pcnet32_driver
);
3053 module_init(pcnet32_init_module
);
3054 module_exit(pcnet32_cleanup_module
);