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[PATCH] radix-tree documentation cleanups
[linux-2.6/mini2440.git] / drivers / ide / pci / hpt366.c
blob940bdd4c5784bf80092bac207c75df2352f5c32b
1 /*
2 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
3 *
4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
5 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
6 * Portions Copyright (C) 2003 Red Hat Inc
7 *
8 * Thanks to HighPoint Technologies for their assistance, and hardware.
9 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
10 * donation of an ABit BP6 mainboard, processor, and memory acellerated
11 * development and support.
12 *
13 *
14 * Highpoint have their own driver (source except for the raid part)
15 * available from http://www.highpoint-tech.com/hpt3xx-opensource-v131.tgz
16 * This may be useful to anyone wanting to work on the mainstream hpt IDE.
17 *
18 * Note that final HPT370 support was done by force extraction of GPL.
19 *
20 * - add function for getting/setting power status of drive
21 * - the HPT370's state machine can get confused. reset it before each dma
22 * xfer to prevent that from happening.
23 * - reset state engine whenever we get an error.
24 * - check for busmaster state at end of dma.
25 * - use new highpoint timings.
26 * - detect bus speed using highpoint register.
27 * - use pll if we don't have a clock table. added a 66MHz table that's
28 * just 2x the 33MHz table.
29 * - removed turnaround. NOTE: we never want to switch between pll and
30 * pci clocks as the chip can glitch in those cases. the highpoint
31 * approved workaround slows everything down too much to be useful. in
32 * addition, we would have to serialize access to each chip.
33 * Adrian Sun <a.sun@sun.com>
34 *
35 * add drive timings for 66MHz PCI bus,
36 * fix ATA Cable signal detection, fix incorrect /proc info
37 * add /proc display for per-drive PIO/DMA/UDMA mode and
38 * per-channel ATA-33/66 Cable detect.
39 * Duncan Laurie <void@sun.com>
40 *
41 * fixup /proc output for multiple controllers
42 * Tim Hockin <thockin@sun.com>
43 *
44 * On hpt366:
45 * Reset the hpt366 on error, reset on dma
46 * Fix disabling Fast Interrupt hpt366.
47 * Mike Waychison <crlf@sun.com>
48 *
49 * Added support for 372N clocking and clock switching. The 372N needs
50 * different clocks on read/write. This requires overloading rw_disk and
51 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
52 * keeping me sane.
53 * Alan Cox <alan@redhat.com>
54 *
55 */
56
57
58 #include <linux/config.h>
59 #include <linux/types.h>
60 #include <linux/module.h>
61 #include <linux/kernel.h>
62 #include <linux/delay.h>
63 #include <linux/timer.h>
64 #include <linux/mm.h>
65 #include <linux/ioport.h>
66 #include <linux/blkdev.h>
67 #include <linux/hdreg.h>
68
69 #include <linux/interrupt.h>
70 #include <linux/pci.h>
71 #include <linux/init.h>
72 #include <linux/ide.h>
73
74 #include <asm/uaccess.h>
75 #include <asm/io.h>
76 #include <asm/irq.h>
77
78 /* various tuning parameters */
79 #define HPT_RESET_STATE_ENGINE
80 #undef HPT_DELAY_INTERRUPT
81 #undef HPT_SERIALIZE_IO
82
83 static const char *quirk_drives[] = {
84 "QUANTUM FIREBALLlct08 08",
85 "QUANTUM FIREBALLP KA6.4",
86 "QUANTUM FIREBALLP LM20.4",
87 "QUANTUM FIREBALLP LM20.5",
88 NULL
89 };
90
91 static const char *bad_ata100_5[] = {
92 "IBM-DTLA-307075",
93 "IBM-DTLA-307060",
94 "IBM-DTLA-307045",
95 "IBM-DTLA-307030",
96 "IBM-DTLA-307020",
97 "IBM-DTLA-307015",
98 "IBM-DTLA-305040",
99 "IBM-DTLA-305030",
100 "IBM-DTLA-305020",
101 "IC35L010AVER07-0",
102 "IC35L020AVER07-0",
103 "IC35L030AVER07-0",
104 "IC35L040AVER07-0",
105 "IC35L060AVER07-0",
106 "WDC AC310200R",
107 NULL
108 };
109
110 static const char *bad_ata66_4[] = {
111 "IBM-DTLA-307075",
112 "IBM-DTLA-307060",
113 "IBM-DTLA-307045",
114 "IBM-DTLA-307030",
115 "IBM-DTLA-307020",
116 "IBM-DTLA-307015",
117 "IBM-DTLA-305040",
118 "IBM-DTLA-305030",
119 "IBM-DTLA-305020",
120 "IC35L010AVER07-0",
121 "IC35L020AVER07-0",
122 "IC35L030AVER07-0",
123 "IC35L040AVER07-0",
124 "IC35L060AVER07-0",
125 "WDC AC310200R",
126 NULL
127 };
128
129 static const char *bad_ata66_3[] = {
130 "WDC AC310200R",
131 NULL
132 };
133
134 static const char *bad_ata33[] = {
135 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
136 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
137 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
138 "Maxtor 90510D4",
139 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
140 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
141 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
142 NULL
143 };
144
145 struct chipset_bus_clock_list_entry {
146 u8 xfer_speed;
147 unsigned int chipset_settings;
148 };
149
150 /* key for bus clock timings
151 * bit
152 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
153 * DMA. cycles = value + 1
154 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
155 * DMA. cycles = value + 1
156 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
157 * register access.
158 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
159 * register access.
160 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
161 * during task file register access.
162 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
163 * xfer.
164 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
165 * register access.
166 * 28 UDMA enable
167 * 29 DMA enable
168 * 30 PIO_MST enable. if set, the chip is in bus master mode during
169 * PIO.
170 * 31 FIFO enable.
171 */
172 static struct chipset_bus_clock_list_entry forty_base_hpt366[] = {
173 { XFER_UDMA_4, 0x900fd943 },
174 { XFER_UDMA_3, 0x900ad943 },
175 { XFER_UDMA_2, 0x900bd943 },
176 { XFER_UDMA_1, 0x9008d943 },
177 { XFER_UDMA_0, 0x9008d943 },
178
179 { XFER_MW_DMA_2, 0xa008d943 },
180 { XFER_MW_DMA_1, 0xa010d955 },
181 { XFER_MW_DMA_0, 0xa010d9fc },
182
183 { XFER_PIO_4, 0xc008d963 },
184 { XFER_PIO_3, 0xc010d974 },
185 { XFER_PIO_2, 0xc010d997 },
186 { XFER_PIO_1, 0xc010d9c7 },
187 { XFER_PIO_0, 0xc018d9d9 },
188 { 0, 0x0120d9d9 }
189 };
190
191 static struct chipset_bus_clock_list_entry thirty_three_base_hpt366[] = {
192 { XFER_UDMA_4, 0x90c9a731 },
193 { XFER_UDMA_3, 0x90cfa731 },
194 { XFER_UDMA_2, 0x90caa731 },
195 { XFER_UDMA_1, 0x90cba731 },
196 { XFER_UDMA_0, 0x90c8a731 },
197
198 { XFER_MW_DMA_2, 0xa0c8a731 },
199 { XFER_MW_DMA_1, 0xa0c8a732 }, /* 0xa0c8a733 */
200 { XFER_MW_DMA_0, 0xa0c8a797 },
201
202 { XFER_PIO_4, 0xc0c8a731 },
203 { XFER_PIO_3, 0xc0c8a742 },
204 { XFER_PIO_2, 0xc0d0a753 },
205 { XFER_PIO_1, 0xc0d0a7a3 }, /* 0xc0d0a793 */
206 { XFER_PIO_0, 0xc0d0a7aa }, /* 0xc0d0a7a7 */
207 { 0, 0x0120a7a7 }
208 };
209
210 static struct chipset_bus_clock_list_entry twenty_five_base_hpt366[] = {
211 { XFER_UDMA_4, 0x90c98521 },
212 { XFER_UDMA_3, 0x90cf8521 },
213 { XFER_UDMA_2, 0x90cf8521 },
214 { XFER_UDMA_1, 0x90cb8521 },
215 { XFER_UDMA_0, 0x90cb8521 },
216
217 { XFER_MW_DMA_2, 0xa0ca8521 },
218 { XFER_MW_DMA_1, 0xa0ca8532 },
219 { XFER_MW_DMA_0, 0xa0ca8575 },
220
221 { XFER_PIO_4, 0xc0ca8521 },
222 { XFER_PIO_3, 0xc0ca8532 },
223 { XFER_PIO_2, 0xc0ca8542 },
224 { XFER_PIO_1, 0xc0d08572 },
225 { XFER_PIO_0, 0xc0d08585 },
226 { 0, 0x01208585 }
227 };
228
229 /* from highpoint documentation. these are old values */
230 static struct chipset_bus_clock_list_entry thirty_three_base_hpt370[] = {
231 /* { XFER_UDMA_5, 0x1A85F442, 0x16454e31 }, */
232 { XFER_UDMA_5, 0x16454e31 },
233 { XFER_UDMA_4, 0x16454e31 },
234 { XFER_UDMA_3, 0x166d4e31 },
235 { XFER_UDMA_2, 0x16494e31 },
236 { XFER_UDMA_1, 0x164d4e31 },
237 { XFER_UDMA_0, 0x16514e31 },
238
239 { XFER_MW_DMA_2, 0x26514e21 },
240 { XFER_MW_DMA_1, 0x26514e33 },
241 { XFER_MW_DMA_0, 0x26514e97 },
242
243 { XFER_PIO_4, 0x06514e21 },
244 { XFER_PIO_3, 0x06514e22 },
245 { XFER_PIO_2, 0x06514e33 },
246 { XFER_PIO_1, 0x06914e43 },
247 { XFER_PIO_0, 0x06914e57 },
248 { 0, 0x06514e57 }
249 };
250
251 static struct chipset_bus_clock_list_entry sixty_six_base_hpt370[] = {
252 { XFER_UDMA_5, 0x14846231 },
253 { XFER_UDMA_4, 0x14886231 },
254 { XFER_UDMA_3, 0x148c6231 },
255 { XFER_UDMA_2, 0x148c6231 },
256 { XFER_UDMA_1, 0x14906231 },
257 { XFER_UDMA_0, 0x14986231 },
258
259 { XFER_MW_DMA_2, 0x26514e21 },
260 { XFER_MW_DMA_1, 0x26514e33 },
261 { XFER_MW_DMA_0, 0x26514e97 },
262
263 { XFER_PIO_4, 0x06514e21 },
264 { XFER_PIO_3, 0x06514e22 },
265 { XFER_PIO_2, 0x06514e33 },
266 { XFER_PIO_1, 0x06914e43 },
267 { XFER_PIO_0, 0x06914e57 },
268 { 0, 0x06514e57 }
269 };
270
271 /* these are the current (4 sep 2001) timings from highpoint */
272 static struct chipset_bus_clock_list_entry thirty_three_base_hpt370a[] = {
273 { XFER_UDMA_5, 0x12446231 },
274 { XFER_UDMA_4, 0x12446231 },
275 { XFER_UDMA_3, 0x126c6231 },
276 { XFER_UDMA_2, 0x12486231 },
277 { XFER_UDMA_1, 0x124c6233 },
278 { XFER_UDMA_0, 0x12506297 },
279
280 { XFER_MW_DMA_2, 0x22406c31 },
281 { XFER_MW_DMA_1, 0x22406c33 },
282 { XFER_MW_DMA_0, 0x22406c97 },
283
284 { XFER_PIO_4, 0x06414e31 },
285 { XFER_PIO_3, 0x06414e42 },
286 { XFER_PIO_2, 0x06414e53 },
287 { XFER_PIO_1, 0x06814e93 },
288 { XFER_PIO_0, 0x06814ea7 },
289 { 0, 0x06814ea7 }
290 };
291
292 /* 2x 33MHz timings */
293 static struct chipset_bus_clock_list_entry sixty_six_base_hpt370a[] = {
294 { XFER_UDMA_5, 0x1488e673 },
295 { XFER_UDMA_4, 0x1488e673 },
296 { XFER_UDMA_3, 0x1498e673 },
297 { XFER_UDMA_2, 0x1490e673 },
298 { XFER_UDMA_1, 0x1498e677 },
299 { XFER_UDMA_0, 0x14a0e73f },
300
301 { XFER_MW_DMA_2, 0x2480fa73 },
302 { XFER_MW_DMA_1, 0x2480fa77 },
303 { XFER_MW_DMA_0, 0x2480fb3f },
304
305 { XFER_PIO_4, 0x0c82be73 },
306 { XFER_PIO_3, 0x0c82be95 },
307 { XFER_PIO_2, 0x0c82beb7 },
308 { XFER_PIO_1, 0x0d02bf37 },
309 { XFER_PIO_0, 0x0d02bf5f },
310 { 0, 0x0d02bf5f }
311 };
312
313 static struct chipset_bus_clock_list_entry fifty_base_hpt370a[] = {
314 { XFER_UDMA_5, 0x12848242 },
315 { XFER_UDMA_4, 0x12ac8242 },
316 { XFER_UDMA_3, 0x128c8242 },
317 { XFER_UDMA_2, 0x120c8242 },
318 { XFER_UDMA_1, 0x12148254 },
319 { XFER_UDMA_0, 0x121882ea },
320
321 { XFER_MW_DMA_2, 0x22808242 },
322 { XFER_MW_DMA_1, 0x22808254 },
323 { XFER_MW_DMA_0, 0x228082ea },
324
325 { XFER_PIO_4, 0x0a81f442 },
326 { XFER_PIO_3, 0x0a81f443 },
327 { XFER_PIO_2, 0x0a81f454 },
328 { XFER_PIO_1, 0x0ac1f465 },
329 { XFER_PIO_0, 0x0ac1f48a },
330 { 0, 0x0ac1f48a }
331 };
332
333 static struct chipset_bus_clock_list_entry thirty_three_base_hpt372[] = {
334 { XFER_UDMA_6, 0x1c81dc62 },
335 { XFER_UDMA_5, 0x1c6ddc62 },
336 { XFER_UDMA_4, 0x1c8ddc62 },
337 { XFER_UDMA_3, 0x1c8edc62 }, /* checkme */
338 { XFER_UDMA_2, 0x1c91dc62 },
339 { XFER_UDMA_1, 0x1c9adc62 }, /* checkme */
340 { XFER_UDMA_0, 0x1c82dc62 }, /* checkme */
341
342 { XFER_MW_DMA_2, 0x2c829262 },
343 { XFER_MW_DMA_1, 0x2c829266 }, /* checkme */
344 { XFER_MW_DMA_0, 0x2c82922e }, /* checkme */
345
346 { XFER_PIO_4, 0x0c829c62 },
347 { XFER_PIO_3, 0x0c829c84 },
348 { XFER_PIO_2, 0x0c829ca6 },
349 { XFER_PIO_1, 0x0d029d26 },
350 { XFER_PIO_0, 0x0d029d5e },
351 { 0, 0x0d029d5e }
352 };
353
354 static struct chipset_bus_clock_list_entry fifty_base_hpt372[] = {
355 { XFER_UDMA_5, 0x12848242 },
356 { XFER_UDMA_4, 0x12ac8242 },
357 { XFER_UDMA_3, 0x128c8242 },
358 { XFER_UDMA_2, 0x120c8242 },
359 { XFER_UDMA_1, 0x12148254 },
360 { XFER_UDMA_0, 0x121882ea },
361
362 { XFER_MW_DMA_2, 0x22808242 },
363 { XFER_MW_DMA_1, 0x22808254 },
364 { XFER_MW_DMA_0, 0x228082ea },
365
366 { XFER_PIO_4, 0x0a81f442 },
367 { XFER_PIO_3, 0x0a81f443 },
368 { XFER_PIO_2, 0x0a81f454 },
369 { XFER_PIO_1, 0x0ac1f465 },
370 { XFER_PIO_0, 0x0ac1f48a },
371 { 0, 0x0a81f443 }
372 };
373
374 static struct chipset_bus_clock_list_entry sixty_six_base_hpt372[] = {
375 { XFER_UDMA_6, 0x1c869c62 },
376 { XFER_UDMA_5, 0x1cae9c62 },
377 { XFER_UDMA_4, 0x1c8a9c62 },
378 { XFER_UDMA_3, 0x1c8e9c62 },
379 { XFER_UDMA_2, 0x1c929c62 },
380 { XFER_UDMA_1, 0x1c9a9c62 },
381 { XFER_UDMA_0, 0x1c829c62 },
382
383 { XFER_MW_DMA_2, 0x2c829c62 },
384 { XFER_MW_DMA_1, 0x2c829c66 },
385 { XFER_MW_DMA_0, 0x2c829d2e },
386
387 { XFER_PIO_4, 0x0c829c62 },
388 { XFER_PIO_3, 0x0c829c84 },
389 { XFER_PIO_2, 0x0c829ca6 },
390 { XFER_PIO_1, 0x0d029d26 },
391 { XFER_PIO_0, 0x0d029d5e },
392 { 0, 0x0d029d26 }
393 };
394
395 static struct chipset_bus_clock_list_entry thirty_three_base_hpt374[] = {
396 { XFER_UDMA_6, 0x12808242 },
397 { XFER_UDMA_5, 0x12848242 },
398 { XFER_UDMA_4, 0x12ac8242 },
399 { XFER_UDMA_3, 0x128c8242 },
400 { XFER_UDMA_2, 0x120c8242 },
401 { XFER_UDMA_1, 0x12148254 },
402 { XFER_UDMA_0, 0x121882ea },
403
404 { XFER_MW_DMA_2, 0x22808242 },
405 { XFER_MW_DMA_1, 0x22808254 },
406 { XFER_MW_DMA_0, 0x228082ea },
407
408 { XFER_PIO_4, 0x0a81f442 },
409 { XFER_PIO_3, 0x0a81f443 },
410 { XFER_PIO_2, 0x0a81f454 },
411 { XFER_PIO_1, 0x0ac1f465 },
412 { XFER_PIO_0, 0x0ac1f48a },
413 { 0, 0x06814e93 }
414 };
415
416 /* FIXME: 50MHz timings for HPT374 */
417
418 #if 0
419 static struct chipset_bus_clock_list_entry sixty_six_base_hpt374[] = {
420 { XFER_UDMA_6, 0x12406231 }, /* checkme */
421 { XFER_UDMA_5, 0x12446231 }, /* 0x14846231 */
422 { XFER_UDMA_4, 0x16814ea7 }, /* 0x14886231 */
423 { XFER_UDMA_3, 0x16814ea7 }, /* 0x148c6231 */
424 { XFER_UDMA_2, 0x16814ea7 }, /* 0x148c6231 */
425 { XFER_UDMA_1, 0x16814ea7 }, /* 0x14906231 */
426 { XFER_UDMA_0, 0x16814ea7 }, /* 0x14986231 */
427 { XFER_MW_DMA_2, 0x16814ea7 }, /* 0x26514e21 */
428 { XFER_MW_DMA_1, 0x16814ea7 }, /* 0x26514e97 */
429 { XFER_MW_DMA_0, 0x16814ea7 }, /* 0x26514e97 */
430 { XFER_PIO_4, 0x06814ea7 }, /* 0x06514e21 */
431 { XFER_PIO_3, 0x06814ea7 }, /* 0x06514e22 */
432 { XFER_PIO_2, 0x06814ea7 }, /* 0x06514e33 */
433 { XFER_PIO_1, 0x06814ea7 }, /* 0x06914e43 */
434 { XFER_PIO_0, 0x06814ea7 }, /* 0x06914e57 */
435 { 0, 0x06814ea7 }
436 };
437 #endif
438
439 #define HPT366_DEBUG_DRIVE_INFO 0
440 #define HPT374_ALLOW_ATA133_6 0
441 #define HPT371_ALLOW_ATA133_6 0
442 #define HPT302_ALLOW_ATA133_6 0
443 #define HPT372_ALLOW_ATA133_6 1
444 #define HPT370_ALLOW_ATA100_5 1
445 #define HPT366_ALLOW_ATA66_4 1
446 #define HPT366_ALLOW_ATA66_3 1
447 #define HPT366_MAX_DEVS 8
448
449 #define F_LOW_PCI_33 0x23
450 #define F_LOW_PCI_40 0x29
451 #define F_LOW_PCI_50 0x2d
452 #define F_LOW_PCI_66 0x42
453
454 /*
455 * Hold all the highpoint quirks and revision information in one
456 * place.
457 */
458
459 struct hpt_info
460 {
461 u8 max_mode; /* Speeds allowed */
462 int revision; /* Chipset revision */
463 int flags; /* Chipset properties */
464 #define PLL_MODE 1
465 #define IS_372N 2
466 /* Speed table */
467 struct chipset_bus_clock_list_entry *speed;
468 };
469
470 /*
471 * This wants fixing so that we do everything not by classrev
472 * (which breaks on the newest chips) but by creating an
473 * enumeration of chip variants and using that
474 */
475
476 static __devinit u32 hpt_revision (struct pci_dev *dev)
477 {
478 u32 class_rev;
479 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
480 class_rev &= 0xff;
481
482 switch(dev->device) {
483 /* Remap new 372N onto 372 */
484 case PCI_DEVICE_ID_TTI_HPT372N:
485 class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
486 case PCI_DEVICE_ID_TTI_HPT374:
487 class_rev = PCI_DEVICE_ID_TTI_HPT374; break;
488 case PCI_DEVICE_ID_TTI_HPT371:
489 class_rev = PCI_DEVICE_ID_TTI_HPT371; break;
490 case PCI_DEVICE_ID_TTI_HPT302:
491 class_rev = PCI_DEVICE_ID_TTI_HPT302; break;
492 case PCI_DEVICE_ID_TTI_HPT372:
493 class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
494 default:
495 break;
496 }
497 return class_rev;
498 }
499
500 static int check_in_drive_lists(ide_drive_t *drive, const char **list);
501
502 static u8 hpt3xx_ratemask (ide_drive_t *drive)
503 {
504 ide_hwif_t *hwif = drive->hwif;
505 struct hpt_info *info = ide_get_hwifdata(hwif);
506 u8 mode = 0;
507
508 /* FIXME: TODO - move this to set info->mode once at boot */
509
510 if (info->revision >= 8) { /* HPT374 */
511 mode = (HPT374_ALLOW_ATA133_6) ? 4 : 3;
512 } else if (info->revision >= 7) { /* HPT371 */
513 mode = (HPT371_ALLOW_ATA133_6) ? 4 : 3;
514 } else if (info->revision >= 6) { /* HPT302 */
515 mode = (HPT302_ALLOW_ATA133_6) ? 4 : 3;
516 } else if (info->revision >= 5) { /* HPT372 */
517 mode = (HPT372_ALLOW_ATA133_6) ? 4 : 3;
518 } else if (info->revision >= 4) { /* HPT370A */
519 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
520 } else if (info->revision >= 3) { /* HPT370 */
521 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
522 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : mode;
523 } else { /* HPT366 and HPT368 */
524 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : 2;
525 }
526 if (!eighty_ninty_three(drive) && mode)
527 mode = min(mode, (u8)1);
528 return mode;
529 }
530
531 /*
532 * Note for the future; the SATA hpt37x we must set
533 * either PIO or UDMA modes 0,4,5
534 */
535
536 static u8 hpt3xx_ratefilter (ide_drive_t *drive, u8 speed)
537 {
538 ide_hwif_t *hwif = drive->hwif;
539 struct hpt_info *info = ide_get_hwifdata(hwif);
540 u8 mode = hpt3xx_ratemask(drive);
541
542 if (drive->media != ide_disk)
543 return min(speed, (u8)XFER_PIO_4);
544
545 switch(mode) {
546 case 0x04:
547 speed = min(speed, (u8)XFER_UDMA_6);
548 break;
549 case 0x03:
550 speed = min(speed, (u8)XFER_UDMA_5);
551 if (info->revision >= 5)
552 break;
553 if (check_in_drive_lists(drive, bad_ata100_5))
554 speed = min(speed, (u8)XFER_UDMA_4);
555 break;
556 case 0x02:
557 speed = min(speed, (u8)XFER_UDMA_4);
558 /*
559 * CHECK ME, Does this need to be set to 5 ??
560 */
561 if (info->revision >= 3)
562 break;
563 if ((check_in_drive_lists(drive, bad_ata66_4)) ||
564 (!(HPT366_ALLOW_ATA66_4)))
565 speed = min(speed, (u8)XFER_UDMA_3);
566 if ((check_in_drive_lists(drive, bad_ata66_3)) ||
567 (!(HPT366_ALLOW_ATA66_3)))
568 speed = min(speed, (u8)XFER_UDMA_2);
569 break;
570 case 0x01:
571 speed = min(speed, (u8)XFER_UDMA_2);
572 /*
573 * CHECK ME, Does this need to be set to 5 ??
574 */
575 if (info->revision >= 3)
576 break;
577 if (check_in_drive_lists(drive, bad_ata33))
578 speed = min(speed, (u8)XFER_MW_DMA_2);
579 break;
580 case 0x00:
581 default:
582 speed = min(speed, (u8)XFER_MW_DMA_2);
583 break;
584 }
585 return speed;
586 }
587
588 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
589 {
590 struct hd_driveid *id = drive->id;
591
592 if (quirk_drives == list) {
593 while (*list)
594 if (strstr(id->model, *list++))
595 return 1;
596 } else {
597 while (*list)
598 if (!strcmp(*list++,id->model))
599 return 1;
600 }
601 return 0;
602 }
603
604 static unsigned int pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
605 {
606 for ( ; chipset_table->xfer_speed ; chipset_table++)
607 if (chipset_table->xfer_speed == speed)
608 return chipset_table->chipset_settings;
609 return chipset_table->chipset_settings;
610 }
611
612 static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
613 {
614 ide_hwif_t *hwif = drive->hwif;
615 struct pci_dev *dev = hwif->pci_dev;
616 struct hpt_info *info = ide_get_hwifdata(hwif);
617 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
618 u8 regtime = (drive->select.b.unit & 0x01) ? 0x44 : 0x40;
619 u8 regfast = (hwif->channel) ? 0x55 : 0x51;
620 u8 drive_fast = 0;
621 u32 reg1 = 0, reg2 = 0;
622
623 /*
624 * Disable the "fast interrupt" prediction.
625 */
626 pci_read_config_byte(dev, regfast, &drive_fast);
627 if (drive_fast & 0x80)
628 pci_write_config_byte(dev, regfast, drive_fast & ~0x80);
629
630 reg2 = pci_bus_clock_list(speed, info->speed);
631
632 /*
633 * Disable on-chip PIO FIFO/buffer
634 * (to avoid problems handling I/O errors later)
635 */
636 pci_read_config_dword(dev, regtime, &reg1);
637 if (speed >= XFER_MW_DMA_0) {
638 reg2 = (reg2 & ~0xc0000000) | (reg1 & 0xc0000000);
639 } else {
640 reg2 = (reg2 & ~0x30070000) | (reg1 & 0x30070000);
641 }
642 reg2 &= ~0x80000000;
643
644 pci_write_config_dword(dev, regtime, reg2);
645
646 return ide_config_drive_speed(drive, speed);
647 }
648
649 static int hpt370_tune_chipset(ide_drive_t *drive, u8 xferspeed)
650 {
651 ide_hwif_t *hwif = drive->hwif;
652 struct pci_dev *dev = hwif->pci_dev;
653 struct hpt_info *info = ide_get_hwifdata(hwif);
654 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
655 u8 regfast = (drive->hwif->channel) ? 0x55 : 0x51;
656 u8 drive_pci = 0x40 + (drive->dn * 4);
657 u8 new_fast = 0, drive_fast = 0;
658 u32 list_conf = 0, drive_conf = 0;
659 u32 conf_mask = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
660
661 /*
662 * Disable the "fast interrupt" prediction.
663 * don't holdoff on interrupts. (== 0x01 despite what the docs say)
664 */
665 pci_read_config_byte(dev, regfast, &drive_fast);
666 new_fast = drive_fast;
667 if (new_fast & 0x02)
668 new_fast &= ~0x02;
669
670 #ifdef HPT_DELAY_INTERRUPT
671 if (new_fast & 0x01)
672 new_fast &= ~0x01;
673 #else
674 if ((new_fast & 0x01) == 0)
675 new_fast |= 0x01;
676 #endif
677 if (new_fast != drive_fast)
678 pci_write_config_byte(dev, regfast, new_fast);
679
680 list_conf = pci_bus_clock_list(speed, info->speed);
681
682 pci_read_config_dword(dev, drive_pci, &drive_conf);
683 list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
684
685 if (speed < XFER_MW_DMA_0)
686 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
687 pci_write_config_dword(dev, drive_pci, list_conf);
688
689 return ide_config_drive_speed(drive, speed);
690 }
691
692 static int hpt372_tune_chipset(ide_drive_t *drive, u8 xferspeed)
693 {
694 ide_hwif_t *hwif = drive->hwif;
695 struct pci_dev *dev = hwif->pci_dev;
696 struct hpt_info *info = ide_get_hwifdata(hwif);
697 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
698 u8 regfast = (drive->hwif->channel) ? 0x55 : 0x51;
699 u8 drive_fast = 0, drive_pci = 0x40 + (drive->dn * 4);
700 u32 list_conf = 0, drive_conf = 0;
701 u32 conf_mask = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
702
703 /*
704 * Disable the "fast interrupt" prediction.
705 * don't holdoff on interrupts. (== 0x01 despite what the docs say)
706 */
707 pci_read_config_byte(dev, regfast, &drive_fast);
708 drive_fast &= ~0x07;
709 pci_write_config_byte(dev, regfast, drive_fast);
710
711 list_conf = pci_bus_clock_list(speed, info->speed);
712 pci_read_config_dword(dev, drive_pci, &drive_conf);
713 list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
714 if (speed < XFER_MW_DMA_0)
715 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
716 pci_write_config_dword(dev, drive_pci, list_conf);
717
718 return ide_config_drive_speed(drive, speed);
719 }
720
721 static int hpt3xx_tune_chipset (ide_drive_t *drive, u8 speed)
722 {
723 ide_hwif_t *hwif = drive->hwif;
724 struct hpt_info *info = ide_get_hwifdata(hwif);
725
726 if (info->revision >= 8)
727 return hpt372_tune_chipset(drive, speed); /* not a typo */
728 else if (info->revision >= 5)
729 return hpt372_tune_chipset(drive, speed);
730 else if (info->revision >= 3)
731 return hpt370_tune_chipset(drive, speed);
732 else /* hpt368: hpt_minimum_revision(dev, 2) */
733 return hpt36x_tune_chipset(drive, speed);
734 }
735
736 static void hpt3xx_tune_drive (ide_drive_t *drive, u8 pio)
737 {
738 pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
739 (void) hpt3xx_tune_chipset(drive, (XFER_PIO_0 + pio));
740 }
741
742 /*
743 * This allows the configuration of ide_pci chipset registers
744 * for cards that learn about the drive's UDMA, DMA, PIO capabilities
745 * after the drive is reported by the OS. Initially for designed for
746 * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
747 *
748 * check_in_drive_lists(drive, bad_ata66_4)
749 * check_in_drive_lists(drive, bad_ata66_3)
750 * check_in_drive_lists(drive, bad_ata33)
751 *
752 */
753 static int config_chipset_for_dma (ide_drive_t *drive)
754 {
755 u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive));
756 ide_hwif_t *hwif = drive->hwif;
757 struct hpt_info *info = ide_get_hwifdata(hwif);
758
759 if (!speed)
760 return 0;
761
762 /* If we don't have any timings we can't do a lot */
763 if (info->speed == NULL)
764 return 0;
765
766 (void) hpt3xx_tune_chipset(drive, speed);
767 return ide_dma_enable(drive);
768 }
769
770 static int hpt3xx_quirkproc (ide_drive_t *drive)
771 {
772 return ((int) check_in_drive_lists(drive, quirk_drives));
773 }
774
775 static void hpt3xx_intrproc (ide_drive_t *drive)
776 {
777 ide_hwif_t *hwif = drive->hwif;
778
779 if (drive->quirk_list)
780 return;
781 /* drives in the quirk_list may not like intr setups/cleanups */
782 hwif->OUTB(drive->ctl|2, IDE_CONTROL_REG);
783 }
784
785 static void hpt3xx_maskproc (ide_drive_t *drive, int mask)
786 {
787 ide_hwif_t *hwif = drive->hwif;
788 struct hpt_info *info = ide_get_hwifdata(hwif);
789 struct pci_dev *dev = hwif->pci_dev;
790
791 if (drive->quirk_list) {
792 if (info->revision >= 3) {
793 u8 reg5a = 0;
794 pci_read_config_byte(dev, 0x5a, &reg5a);
795 if (((reg5a & 0x10) >> 4) != mask)
796 pci_write_config_byte(dev, 0x5a, mask ? (reg5a | 0x10) : (reg5a & ~0x10));
797 } else {
798 if (mask) {
799 disable_irq(hwif->irq);
800 } else {
801 enable_irq(hwif->irq);
802 }
803 }
804 } else {
805 if (IDE_CONTROL_REG)
806 hwif->OUTB(mask ? (drive->ctl | 2) :
807 (drive->ctl & ~2),
808 IDE_CONTROL_REG);
809 }
810 }
811
812 static int hpt366_config_drive_xfer_rate (ide_drive_t *drive)
813 {
814 ide_hwif_t *hwif = drive->hwif;
815 struct hd_driveid *id = drive->id;
816
817 drive->init_speed = 0;
818
819 if ((id->capability & 1) && drive->autodma) {
820
821 if (ide_use_dma(drive)) {
822 if (config_chipset_for_dma(drive))
823 return hwif->ide_dma_on(drive);
824 }
825
826 goto fast_ata_pio;
827
828 } else if ((id->capability & 8) || (id->field_valid & 2)) {
829 fast_ata_pio:
830 hpt3xx_tune_drive(drive, 5);
831 return hwif->ide_dma_off_quietly(drive);
832 }
833 /* IORDY not supported */
834 return 0;
835 }
836
837 /*
838 * This is specific to the HPT366 UDMA bios chipset
839 * by HighPoint|Triones Technologies, Inc.
840 */
841 static int hpt366_ide_dma_lostirq (ide_drive_t *drive)
842 {
843 struct pci_dev *dev = HWIF(drive)->pci_dev;
844 u8 reg50h = 0, reg52h = 0, reg5ah = 0;
845
846 pci_read_config_byte(dev, 0x50, &reg50h);
847 pci_read_config_byte(dev, 0x52, &reg52h);
848 pci_read_config_byte(dev, 0x5a, &reg5ah);
849 printk("%s: (%s) reg50h=0x%02x, reg52h=0x%02x, reg5ah=0x%02x\n",
850 drive->name, __FUNCTION__, reg50h, reg52h, reg5ah);
851 if (reg5ah & 0x10)
852 pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
853 return __ide_dma_lostirq(drive);
854 }
855
856 static void hpt370_clear_engine (ide_drive_t *drive)
857 {
858 u8 regstate = HWIF(drive)->channel ? 0x54 : 0x50;
859 pci_write_config_byte(HWIF(drive)->pci_dev, regstate, 0x37);
860 udelay(10);
861 }
862
863 static void hpt370_ide_dma_start(ide_drive_t *drive)
864 {
865 #ifdef HPT_RESET_STATE_ENGINE
866 hpt370_clear_engine(drive);
867 #endif
868 ide_dma_start(drive);
869 }
870
871 static int hpt370_ide_dma_end (ide_drive_t *drive)
872 {
873 ide_hwif_t *hwif = HWIF(drive);
874 u8 dma_stat = hwif->INB(hwif->dma_status);
875
876 if (dma_stat & 0x01) {
877 /* wait a little */
878 udelay(20);
879 dma_stat = hwif->INB(hwif->dma_status);
880 }
881 if ((dma_stat & 0x01) != 0)
882 /* fallthrough */
883 (void) HWIF(drive)->ide_dma_timeout(drive);
884
885 return __ide_dma_end(drive);
886 }
887
888 static void hpt370_lostirq_timeout (ide_drive_t *drive)
889 {
890 ide_hwif_t *hwif = HWIF(drive);
891 u8 bfifo = 0, reginfo = hwif->channel ? 0x56 : 0x52;
892 u8 dma_stat = 0, dma_cmd = 0;
893
894 pci_read_config_byte(HWIF(drive)->pci_dev, reginfo, &bfifo);
895 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo);
896 hpt370_clear_engine(drive);
897 /* get dma command mode */
898 dma_cmd = hwif->INB(hwif->dma_command);
899 /* stop dma */
900 hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
901 dma_stat = hwif->INB(hwif->dma_status);
902 /* clear errors */
903 hwif->OUTB(dma_stat | 0x6, hwif->dma_status);
904 }
905
906 static int hpt370_ide_dma_timeout (ide_drive_t *drive)
907 {
908 hpt370_lostirq_timeout(drive);
909 hpt370_clear_engine(drive);
910 return __ide_dma_timeout(drive);
911 }
912
913 static int hpt370_ide_dma_lostirq (ide_drive_t *drive)
914 {
915 hpt370_lostirq_timeout(drive);
916 hpt370_clear_engine(drive);
917 return __ide_dma_lostirq(drive);
918 }
919
920 /* returns 1 if DMA IRQ issued, 0 otherwise */
921 static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
922 {
923 ide_hwif_t *hwif = HWIF(drive);
924 u16 bfifo = 0;
925 u8 reginfo = hwif->channel ? 0x56 : 0x52;
926 u8 dma_stat;
927
928 pci_read_config_word(hwif->pci_dev, reginfo, &bfifo);
929 if (bfifo & 0x1FF) {
930 // printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
931 return 0;
932 }
933
934 dma_stat = hwif->INB(hwif->dma_status);
935 /* return 1 if INTR asserted */
936 if ((dma_stat & 4) == 4)
937 return 1;
938
939 if (!drive->waiting_for_dma)
940 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
941 drive->name, __FUNCTION__);
942 return 0;
943 }
944
945 static int hpt374_ide_dma_end (ide_drive_t *drive)
946 {
947 struct pci_dev *dev = HWIF(drive)->pci_dev;
948 ide_hwif_t *hwif = HWIF(drive);
949 u8 msc_stat = 0, mscreg = hwif->channel ? 0x54 : 0x50;
950 u8 bwsr_stat = 0, bwsr_mask = hwif->channel ? 0x02 : 0x01;
951
952 pci_read_config_byte(dev, 0x6a, &bwsr_stat);
953 pci_read_config_byte(dev, mscreg, &msc_stat);
954 if ((bwsr_stat & bwsr_mask) == bwsr_mask)
955 pci_write_config_byte(dev, mscreg, msc_stat|0x30);
956 return __ide_dma_end(drive);
957 }
958
959 /**
960 * hpt372n_set_clock - perform clock switching dance
961 * @drive: Drive to switch
962 * @mode: Switching mode (0x21 for write, 0x23 otherwise)
963 *
964 * Switch the DPLL clock on the HPT372N devices. This is a
965 * right mess.
966 */
967
968 static void hpt372n_set_clock(ide_drive_t *drive, int mode)
969 {
970 ide_hwif_t *hwif = HWIF(drive);
971
972 /* FIXME: should we check for DMA active and BUG() */
973 /* Tristate the bus */
974 outb(0x80, hwif->dma_base+0x73);
975 outb(0x80, hwif->dma_base+0x77);
976
977 /* Switch clock and reset channels */
978 outb(mode, hwif->dma_base+0x7B);
979 outb(0xC0, hwif->dma_base+0x79);
980
981 /* Reset state machines */
982 outb(0x37, hwif->dma_base+0x70);
983 outb(0x37, hwif->dma_base+0x74);
984
985 /* Complete reset */
986 outb(0x00, hwif->dma_base+0x79);
987
988 /* Reconnect channels to bus */
989 outb(0x00, hwif->dma_base+0x73);
990 outb(0x00, hwif->dma_base+0x77);
991 }
992
993 /**
994 * hpt372n_rw_disk - prepare for I/O
995 * @drive: drive for command
996 * @rq: block request structure
997 *
998 * This is called when a disk I/O is issued to the 372N.
999 * We need it because of the clock switching.
1000 */
1001
1002 static void hpt372n_rw_disk(ide_drive_t *drive, struct request *rq)
1003 {
1004 ide_hwif_t *hwif = drive->hwif;
1005 int wantclock;
1006
1007 wantclock = rq_data_dir(rq) ? 0x23 : 0x21;
1008
1009 if (hwif->config_data != wantclock) {
1010 hpt372n_set_clock(drive, wantclock);
1011 hwif->config_data = wantclock;
1012 }
1013 }
1014
1015 /*
1016 * Since SUN Cobalt is attempting to do this operation, I should disclose
1017 * this has been a long time ago Thu Jul 27 16:40:57 2000 was the patch date
1018 * HOTSWAP ATA Infrastructure.
1019 */
1020
1021 static void hpt3xx_reset (ide_drive_t *drive)
1022 {
1023 }
1024
1025 static int hpt3xx_tristate (ide_drive_t * drive, int state)
1026 {
1027 ide_hwif_t *hwif = HWIF(drive);
1028 struct pci_dev *dev = hwif->pci_dev;
1029 u8 reg59h = 0, reset = (hwif->channel) ? 0x80 : 0x40;
1030 u8 regXXh = 0, state_reg= (hwif->channel) ? 0x57 : 0x53;
1031
1032 pci_read_config_byte(dev, 0x59, &reg59h);
1033 pci_read_config_byte(dev, state_reg, &regXXh);
1034
1035 if (state) {
1036 (void) ide_do_reset(drive);
1037 pci_write_config_byte(dev, state_reg, regXXh|0x80);
1038 pci_write_config_byte(dev, 0x59, reg59h|reset);
1039 } else {
1040 pci_write_config_byte(dev, 0x59, reg59h & ~(reset));
1041 pci_write_config_byte(dev, state_reg, regXXh & ~(0x80));
1042 (void) ide_do_reset(drive);
1043 }
1044 return 0;
1045 }
1046
1047 /*
1048 * set/get power state for a drive.
1049 * turning the power off does the following things:
1050 * 1) soft-reset the drive
1051 * 2) tri-states the ide bus
1052 *
1053 * when we turn things back on, we need to re-initialize things.
1054 */
1055 #define TRISTATE_BIT 0x8000
1056 static int hpt370_busproc(ide_drive_t * drive, int state)
1057 {
1058 ide_hwif_t *hwif = drive->hwif;
1059 struct pci_dev *dev = hwif->pci_dev;
1060 u8 tristate = 0, resetmask = 0, bus_reg = 0;
1061 u16 tri_reg;
1062
1063 hwif->bus_state = state;
1064
1065 if (hwif->channel) {
1066 /* secondary channel */
1067 tristate = 0x56;
1068 resetmask = 0x80;
1069 } else {
1070 /* primary channel */
1071 tristate = 0x52;
1072 resetmask = 0x40;
1073 }
1074
1075 /* grab status */
1076 pci_read_config_word(dev, tristate, &tri_reg);
1077 pci_read_config_byte(dev, 0x59, &bus_reg);
1078
1079 /* set the state. we don't set it if we don't need to do so.
1080 * make sure that the drive knows that it has failed if it's off */
1081 switch (state) {
1082 case BUSSTATE_ON:
1083 hwif->drives[0].failures = 0;
1084 hwif->drives[1].failures = 0;
1085 if ((bus_reg & resetmask) == 0)
1086 return 0;
1087 tri_reg &= ~TRISTATE_BIT;
1088 bus_reg &= ~resetmask;
1089 break;
1090 case BUSSTATE_OFF:
1091 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
1092 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
1093 if ((tri_reg & TRISTATE_BIT) == 0 && (bus_reg & resetmask))
1094 return 0;
1095 tri_reg &= ~TRISTATE_BIT;
1096 bus_reg |= resetmask;
1097 break;
1098 case BUSSTATE_TRISTATE:
1099 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
1100 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
1101 if ((tri_reg & TRISTATE_BIT) && (bus_reg & resetmask))
1102 return 0;
1103 tri_reg |= TRISTATE_BIT;
1104 bus_reg |= resetmask;
1105 break;
1106 }
1107 pci_write_config_byte(dev, 0x59, bus_reg);
1108 pci_write_config_word(dev, tristate, tri_reg);
1109
1110 return 0;
1111 }
1112
1113 static void __devinit hpt366_clocking(ide_hwif_t *hwif)
1114 {
1115 u32 reg1 = 0;
1116 struct hpt_info *info = ide_get_hwifdata(hwif);
1117
1118 pci_read_config_dword(hwif->pci_dev, 0x40, &reg1);
1119
1120 /* detect bus speed by looking at control reg timing: */
1121 switch((reg1 >> 8) & 7) {
1122 case 5:
1123 info->speed = forty_base_hpt366;
1124 break;
1125 case 9:
1126 info->speed = twenty_five_base_hpt366;
1127 break;
1128 case 7:
1129 default:
1130 info->speed = thirty_three_base_hpt366;
1131 break;
1132 }
1133 }
1134
1135 static void __devinit hpt37x_clocking(ide_hwif_t *hwif)
1136 {
1137 struct hpt_info *info = ide_get_hwifdata(hwif);
1138 struct pci_dev *dev = hwif->pci_dev;
1139 int adjust, i;
1140 u16 freq;
1141 u32 pll;
1142 u8 reg5bh;
1143
1144 /*
1145 * default to pci clock. make sure MA15/16 are set to output
1146 * to prevent drives having problems with 40-pin cables. Needed
1147 * for some drives such as IBM-DTLA which will not enter ready
1148 * state on reset when PDIAG is a input.
1149 *
1150 * ToDo: should we set 0x21 when using PLL mode ?
1151 */
1152 pci_write_config_byte(dev, 0x5b, 0x23);
1153
1154 /*
1155 * set up the PLL. we need to adjust it so that it's stable.
1156 * freq = Tpll * 192 / Tpci
1157 *
1158 * Todo. For non x86 should probably check the dword is
1159 * set to 0xABCDExxx indicating the BIOS saved f_CNT
1160 */
1161 pci_read_config_word(dev, 0x78, &freq);
1162 freq &= 0x1FF;
1163
1164 /*
1165 * The 372N uses different PCI clock information and has
1166 * some other complications
1167 * On PCI33 timing we must clock switch
1168 * On PCI66 timing we must NOT use the PCI clock
1169 *
1170 * Currently we always set up the PLL for the 372N
1171 */
1172
1173 if(info->flags & IS_372N)
1174 {
1175 printk(KERN_INFO "hpt: HPT372N detected, using 372N timing.\n");
1176 if(freq < 0x55)
1177 pll = F_LOW_PCI_33;
1178 else if(freq < 0x70)
1179 pll = F_LOW_PCI_40;
1180 else if(freq < 0x7F)
1181 pll = F_LOW_PCI_50;
1182 else
1183 pll = F_LOW_PCI_66;
1184
1185 printk(KERN_INFO "FREQ: %d PLL: %d\n", freq, pll);
1186
1187 /* We always use the pll not the PCI clock on 372N */
1188 }
1189 else
1190 {
1191 if(freq < 0x9C)
1192 pll = F_LOW_PCI_33;
1193 else if(freq < 0xb0)
1194 pll = F_LOW_PCI_40;
1195 else if(freq <0xc8)
1196 pll = F_LOW_PCI_50;
1197 else
1198 pll = F_LOW_PCI_66;
1199
1200 if (pll == F_LOW_PCI_33) {
1201 if (info->revision >= 8)
1202 info->speed = thirty_three_base_hpt374;
1203 else if (info->revision >= 5)
1204 info->speed = thirty_three_base_hpt372;
1205 else if (info->revision >= 4)
1206 info->speed = thirty_three_base_hpt370a;
1207 else
1208 info->speed = thirty_three_base_hpt370;
1209 printk(KERN_DEBUG "HPT37X: using 33MHz PCI clock\n");
1210 } else if (pll == F_LOW_PCI_40) {
1211 /* Unsupported */
1212 } else if (pll == F_LOW_PCI_50) {
1213 if (info->revision >= 8)
1214 info->speed = fifty_base_hpt370a;
1215 else if (info->revision >= 5)
1216 info->speed = fifty_base_hpt372;
1217 else if (info->revision >= 4)
1218 info->speed = fifty_base_hpt370a;
1219 else
1220 info->speed = fifty_base_hpt370a;
1221 printk(KERN_DEBUG "HPT37X: using 50MHz PCI clock\n");
1222 } else {
1223 if (info->revision >= 8) {
1224 printk(KERN_ERR "HPT37x: 66MHz timings are not supported.\n");
1225 }
1226 else if (info->revision >= 5)
1227 info->speed = sixty_six_base_hpt372;
1228 else if (info->revision >= 4)
1229 info->speed = sixty_six_base_hpt370a;
1230 else
1231 info->speed = sixty_six_base_hpt370;
1232 printk(KERN_DEBUG "HPT37X: using 66MHz PCI clock\n");
1233 }
1234 }
1235
1236 /*
1237 * only try the pll if we don't have a table for the clock
1238 * speed that we're running at. NOTE: the internal PLL will
1239 * result in slow reads when using a 33MHz PCI clock. we also
1240 * don't like to use the PLL because it will cause glitches
1241 * on PRST/SRST when the HPT state engine gets reset.
1242 *
1243 * ToDo: Use 66MHz PLL when ATA133 devices are present on a
1244 * 372 device so we can get ATA133 support
1245 */
1246 if (info->speed)
1247 goto init_hpt37X_done;
1248
1249 info->flags |= PLL_MODE;
1250
1251 /*
1252 * FIXME: make this work correctly, esp with 372N as per
1253 * reference driver code.
1254 *
1255 * adjust PLL based upon PCI clock, enable it, and wait for
1256 * stabilization.
1257 */
1258 adjust = 0;
1259 freq = (pll < F_LOW_PCI_50) ? 2 : 4;
1260 while (adjust++ < 6) {
1261 pci_write_config_dword(dev, 0x5c, (freq + pll) << 16 |
1262 pll | 0x100);
1263
1264 /* wait for clock stabilization */
1265 for (i = 0; i < 0x50000; i++) {
1266 pci_read_config_byte(dev, 0x5b, &reg5bh);
1267 if (reg5bh & 0x80) {
1268 /* spin looking for the clock to destabilize */
1269 for (i = 0; i < 0x1000; ++i) {
1270 pci_read_config_byte(dev, 0x5b,
1271 &reg5bh);
1272 if ((reg5bh & 0x80) == 0)
1273 goto pll_recal;
1274 }
1275 pci_read_config_dword(dev, 0x5c, &pll);
1276 pci_write_config_dword(dev, 0x5c,
1277 pll & ~0x100);
1278 pci_write_config_byte(dev, 0x5b, 0x21);
1279 if (info->revision >= 8)
1280 info->speed = fifty_base_hpt370a;
1281 else if (info->revision >= 5)
1282 info->speed = fifty_base_hpt372;
1283 else if (info->revision >= 4)
1284 info->speed = fifty_base_hpt370a;
1285 else
1286 info->speed = fifty_base_hpt370a;
1287 printk("HPT37X: using 50MHz internal PLL\n");
1288 goto init_hpt37X_done;
1289 }
1290 }
1291 if (!pci_get_drvdata(dev)) {
1292 printk("No Clock Stabilization!!!\n");
1293 return;
1294 }
1295 pll_recal:
1296 if (adjust & 1)
1297 pll -= (adjust >> 1);
1298 else
1299 pll += (adjust >> 1);
1300 }
1301
1302 init_hpt37X_done:
1303 if (!info->speed)
1304 printk(KERN_ERR "HPT37X%s: unknown bus timing [%d %d].\n",
1305 (info->flags & IS_372N)?"N":"", pll, freq);
1306 /* reset state engine */
1307 pci_write_config_byte(dev, 0x50, 0x37);
1308 pci_write_config_byte(dev, 0x54, 0x37);
1309 udelay(100);
1310 }
1311
1312 static int __devinit init_hpt37x(struct pci_dev *dev)
1313 {
1314 u8 reg5ah;
1315
1316 pci_read_config_byte(dev, 0x5a, &reg5ah);
1317 /* interrupt force enable */
1318 pci_write_config_byte(dev, 0x5a, (reg5ah & ~0x10));
1319 return 0;
1320 }
1321
1322 static int __devinit init_hpt366(struct pci_dev *dev)
1323 {
1324 u32 reg1 = 0;
1325 u8 drive_fast = 0;
1326
1327 /*
1328 * Disable the "fast interrupt" prediction.
1329 */
1330 pci_read_config_byte(dev, 0x51, &drive_fast);
1331 if (drive_fast & 0x80)
1332 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
1333 pci_read_config_dword(dev, 0x40, &reg1);
1334
1335 return 0;
1336 }
1337
1338 static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
1339 {
1340 int ret = 0;
1341
1342 /*
1343 * FIXME: Not portable. Also, why do we enable the ROM in the first place?
1344 * We don't seem to be using it.
1345 */
1346 if (dev->resource[PCI_ROM_RESOURCE].start)
1347 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
1348 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
1349
1350 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1351 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1352 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1353 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1354
1355 if (hpt_revision(dev) >= 3)
1356 ret = init_hpt37x(dev);
1357 else
1358 ret = init_hpt366(dev);
1359
1360 if (ret)
1361 return ret;
1362
1363 return dev->irq;
1364 }
1365
1366 static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1367 {
1368 struct pci_dev *dev = hwif->pci_dev;
1369 struct hpt_info *info = ide_get_hwifdata(hwif);
1370 u8 ata66 = 0, regmask = (hwif->channel) ? 0x01 : 0x02;
1371
1372 hwif->tuneproc = &hpt3xx_tune_drive;
1373 hwif->speedproc = &hpt3xx_tune_chipset;
1374 hwif->quirkproc = &hpt3xx_quirkproc;
1375 hwif->intrproc = &hpt3xx_intrproc;
1376 hwif->maskproc = &hpt3xx_maskproc;
1377
1378 if(info->flags & IS_372N)
1379 hwif->rw_disk = &hpt372n_rw_disk;
1380
1381 /*
1382 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1383 * address lines to access an external eeprom. To read valid
1384 * cable detect state the pins must be enabled as inputs.
1385 */
1386 if (info->revision >= 8 && (PCI_FUNC(dev->devfn) & 1)) {
1387 /*
1388 * HPT374 PCI function 1
1389 * - set bit 15 of reg 0x52 to enable TCBLID as input
1390 * - set bit 15 of reg 0x56 to enable FCBLID as input
1391 */
1392 u16 mcr3, mcr6;
1393 pci_read_config_word(dev, 0x52, &mcr3);
1394 pci_read_config_word(dev, 0x56, &mcr6);
1395 pci_write_config_word(dev, 0x52, mcr3 | 0x8000);
1396 pci_write_config_word(dev, 0x56, mcr6 | 0x8000);
1397 /* now read cable id register */
1398 pci_read_config_byte(dev, 0x5a, &ata66);
1399 pci_write_config_word(dev, 0x52, mcr3);
1400 pci_write_config_word(dev, 0x56, mcr6);
1401 } else if (info->revision >= 3) {
1402 /*
1403 * HPT370/372 and 374 pcifn 0
1404 * - clear bit 0 of 0x5b to enable P/SCBLID as inputs
1405 */
1406 u8 scr2;
1407 pci_read_config_byte(dev, 0x5b, &scr2);
1408 pci_write_config_byte(dev, 0x5b, scr2 & ~1);
1409 /* now read cable id register */
1410 pci_read_config_byte(dev, 0x5a, &ata66);
1411 pci_write_config_byte(dev, 0x5b, scr2);
1412 } else {
1413 pci_read_config_byte(dev, 0x5a, &ata66);
1414 }
1415
1416 #ifdef DEBUG
1417 printk("HPT366: reg5ah=0x%02x ATA-%s Cable Port%d\n",
1418 ata66, (ata66 & regmask) ? "33" : "66",
1419 PCI_FUNC(hwif->pci_dev->devfn));
1420 #endif /* DEBUG */
1421
1422 #ifdef HPT_SERIALIZE_IO
1423 /* serialize access to this device */
1424 if (hwif->mate)
1425 hwif->serialized = hwif->mate->serialized = 1;
1426 #endif
1427
1428 if (info->revision >= 3) {
1429 u8 reg5ah = 0;
1430 pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
1431 /*
1432 * set up ioctl for power status.
1433 * note: power affects both
1434 * drives on each channel
1435 */
1436 hwif->resetproc = &hpt3xx_reset;
1437 hwif->busproc = &hpt370_busproc;
1438 } else if (info->revision >= 2) {
1439 hwif->resetproc = &hpt3xx_reset;
1440 hwif->busproc = &hpt3xx_tristate;
1441 } else {
1442 hwif->resetproc = &hpt3xx_reset;
1443 hwif->busproc = &hpt3xx_tristate;
1444 }
1445
1446 if (!hwif->dma_base) {
1447 hwif->drives[0].autotune = 1;
1448 hwif->drives[1].autotune = 1;
1449 return;
1450 }
1451
1452 hwif->ultra_mask = 0x7f;
1453 hwif->mwdma_mask = 0x07;
1454
1455 if (!(hwif->udma_four))
1456 hwif->udma_four = ((ata66 & regmask) ? 0 : 1);
1457 hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
1458
1459 if (info->revision >= 8) {
1460 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1461 hwif->ide_dma_end = &hpt374_ide_dma_end;
1462 } else if (info->revision >= 5) {
1463 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1464 hwif->ide_dma_end = &hpt374_ide_dma_end;
1465 } else if (info->revision >= 3) {
1466 hwif->dma_start = &hpt370_ide_dma_start;
1467 hwif->ide_dma_end = &hpt370_ide_dma_end;
1468 hwif->ide_dma_timeout = &hpt370_ide_dma_timeout;
1469 hwif->ide_dma_lostirq = &hpt370_ide_dma_lostirq;
1470 } else if (info->revision >= 2)
1471 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1472 else
1473 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1474
1475 if (!noautodma)
1476 hwif->autodma = 1;
1477 hwif->drives[0].autodma = hwif->autodma;
1478 hwif->drives[1].autodma = hwif->autodma;
1479 }
1480
1481 static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1482 {
1483 struct hpt_info *info = ide_get_hwifdata(hwif);
1484 u8 masterdma = 0, slavedma = 0;
1485 u8 dma_new = 0, dma_old = 0;
1486 u8 primary = hwif->channel ? 0x4b : 0x43;
1487 u8 secondary = hwif->channel ? 0x4f : 0x47;
1488 unsigned long flags;
1489
1490 if (!dmabase)
1491 return;
1492
1493 if(info->speed == NULL) {
1494 printk(KERN_WARNING "hpt: no known IDE timings, disabling DMA.\n");
1495 return;
1496 }
1497
1498 dma_old = hwif->INB(dmabase+2);
1499
1500 local_irq_save(flags);
1501
1502 dma_new = dma_old;
1503 pci_read_config_byte(hwif->pci_dev, primary, &masterdma);
1504 pci_read_config_byte(hwif->pci_dev, secondary, &slavedma);
1505
1506 if (masterdma & 0x30) dma_new |= 0x20;
1507 if (slavedma & 0x30) dma_new |= 0x40;
1508 if (dma_new != dma_old)
1509 hwif->OUTB(dma_new, dmabase+2);
1510
1511 local_irq_restore(flags);
1512
1513 ide_setup_dma(hwif, dmabase, 8);
1514 }
1515
1516 /*
1517 * We "borrow" this hook in order to set the data structures
1518 * up early enough before dma or init_hwif calls are made.
1519 */
1520
1521 static void __devinit init_iops_hpt366(ide_hwif_t *hwif)
1522 {
1523 struct hpt_info *info = kzalloc(sizeof(struct hpt_info), GFP_KERNEL);
1524 unsigned long dmabase = pci_resource_start(hwif->pci_dev, 4);
1525 u8 did, rid;
1526
1527 if(info == NULL) {
1528 printk(KERN_WARNING "hpt366: out of memory.\n");
1529 return;
1530 }
1531 ide_set_hwifdata(hwif, info);
1532
1533 if(dmabase) {
1534 did = inb(dmabase + 0x22);
1535 rid = inb(dmabase + 0x28);
1536
1537 if((did == 4 && rid == 6) || (did == 5 && rid > 1))
1538 info->flags |= IS_372N;
1539 }
1540
1541 info->revision = hpt_revision(hwif->pci_dev);
1542
1543 if (info->revision >= 3)
1544 hpt37x_clocking(hwif);
1545 else
1546 hpt366_clocking(hwif);
1547 }
1548
1549 static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1550 {
1551 struct pci_dev *findev = NULL;
1552
1553 if (PCI_FUNC(dev->devfn) & 1)
1554 return -ENODEV;
1555
1556 while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1557 if ((findev->vendor == dev->vendor) &&
1558 (findev->device == dev->device) &&
1559 ((findev->devfn - dev->devfn) == 1) &&
1560 (PCI_FUNC(findev->devfn) & 1)) {
1561 if (findev->irq != dev->irq) {
1562 /* FIXME: we need a core pci_set_interrupt() */
1563 findev->irq = dev->irq;
1564 printk(KERN_WARNING "%s: pci-config space interrupt "
1565 "fixed.\n", d->name);
1566 }
1567 return ide_setup_pci_devices(dev, findev, d);
1568 }
1569 }
1570 return ide_setup_pci_device(dev, d);
1571 }
1572
1573 static int __devinit init_setup_hpt37x(struct pci_dev *dev, ide_pci_device_t *d)
1574 {
1575 return ide_setup_pci_device(dev, d);
1576 }
1577
1578 static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1579 {
1580 struct pci_dev *findev = NULL;
1581 u8 pin1 = 0, pin2 = 0;
1582 unsigned int class_rev;
1583 char *chipset_names[] = {"HPT366", "HPT366", "HPT368",
1584 "HPT370", "HPT370A", "HPT372",
1585 "HPT372N" };
1586
1587 if (PCI_FUNC(dev->devfn) & 1)
1588 return -ENODEV;
1589
1590 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1591 class_rev &= 0xff;
1592
1593 if(dev->device == PCI_DEVICE_ID_TTI_HPT372N)
1594 class_rev = 6;
1595
1596 if(class_rev <= 6)
1597 d->name = chipset_names[class_rev];
1598
1599 switch(class_rev) {
1600 case 6:
1601 case 5:
1602 case 4:
1603 case 3:
1604 goto init_single;
1605 default:
1606 break;
1607 }
1608
1609 d->channels = 1;
1610
1611 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1612 while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1613 if ((findev->vendor == dev->vendor) &&
1614 (findev->device == dev->device) &&
1615 ((findev->devfn - dev->devfn) == 1) &&
1616 (PCI_FUNC(findev->devfn) & 1)) {
1617 pci_read_config_byte(findev, PCI_INTERRUPT_PIN, &pin2);
1618 if ((pin1 != pin2) && (dev->irq == findev->irq)) {
1619 d->bootable = ON_BOARD;
1620 printk("%s: onboard version of chipset, "
1621 "pin1=%d pin2=%d\n", d->name,
1622 pin1, pin2);
1623 }
1624 return ide_setup_pci_devices(dev, findev, d);
1625 }
1626 }
1627 init_single:
1628 return ide_setup_pci_device(dev, d);
1629 }
1630
1631 static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1632 { /* 0 */
1633 .name = "HPT366",
1634 .init_setup = init_setup_hpt366,
1635 .init_chipset = init_chipset_hpt366,
1636 .init_iops = init_iops_hpt366,
1637 .init_hwif = init_hwif_hpt366,
1638 .init_dma = init_dma_hpt366,
1639 .channels = 2,
1640 .autodma = AUTODMA,
1641 .bootable = OFF_BOARD,
1642 .extra = 240
1643 },{ /* 1 */
1644 .name = "HPT372A",
1645 .init_setup = init_setup_hpt37x,
1646 .init_chipset = init_chipset_hpt366,
1647 .init_iops = init_iops_hpt366,
1648 .init_hwif = init_hwif_hpt366,
1649 .init_dma = init_dma_hpt366,
1650 .channels = 2,
1651 .autodma = AUTODMA,
1652 .bootable = OFF_BOARD,
1653 },{ /* 2 */
1654 .name = "HPT302",
1655 .init_setup = init_setup_hpt37x,
1656 .init_chipset = init_chipset_hpt366,
1657 .init_iops = init_iops_hpt366,
1658 .init_hwif = init_hwif_hpt366,
1659 .init_dma = init_dma_hpt366,
1660 .channels = 2,
1661 .autodma = AUTODMA,
1662 .bootable = OFF_BOARD,
1663 },{ /* 3 */
1664 .name = "HPT371",
1665 .init_setup = init_setup_hpt37x,
1666 .init_chipset = init_chipset_hpt366,
1667 .init_iops = init_iops_hpt366,
1668 .init_hwif = init_hwif_hpt366,
1669 .init_dma = init_dma_hpt366,
1670 .channels = 2,
1671 .autodma = AUTODMA,
1672 .bootable = OFF_BOARD,
1673 },{ /* 4 */
1674 .name = "HPT374",
1675 .init_setup = init_setup_hpt374,
1676 .init_chipset = init_chipset_hpt366,
1677 .init_iops = init_iops_hpt366,
1678 .init_hwif = init_hwif_hpt366,
1679 .init_dma = init_dma_hpt366,
1680 .channels = 2, /* 4 */
1681 .autodma = AUTODMA,
1682 .bootable = OFF_BOARD,
1683 },{ /* 5 */
1684 .name = "HPT372N",
1685 .init_setup = init_setup_hpt37x,
1686 .init_chipset = init_chipset_hpt366,
1687 .init_iops = init_iops_hpt366,
1688 .init_hwif = init_hwif_hpt366,
1689 .init_dma = init_dma_hpt366,
1690 .channels = 2, /* 4 */
1691 .autodma = AUTODMA,
1692 .bootable = OFF_BOARD,
1693 }
1694 };
1695
1696 /**
1697 * hpt366_init_one - called when an HPT366 is found
1698 * @dev: the hpt366 device
1699 * @id: the matching pci id
1700 *
1701 * Called when the PCI registration layer (or the IDE initialization)
1702 * finds a device matching our IDE device tables.
1703 */
1704
1705 static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1706 {
1707 ide_pci_device_t *d = &hpt366_chipsets[id->driver_data];
1708
1709 return d->init_setup(dev, d);
1710 }
1711
1712 static struct pci_device_id hpt366_pci_tbl[] = {
1713 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1714 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1715 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1716 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1717 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1718 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
1719 { 0, },
1720 };
1721 MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1722
1723 static struct pci_driver driver = {
1724 .name = "HPT366_IDE",
1725 .id_table = hpt366_pci_tbl,
1726 .probe = hpt366_init_one,
1727 };
1728
1729 static int hpt366_ide_init(void)
1730 {
1731 return ide_pci_register_driver(&driver);
1732 }
1733
1734 module_init(hpt366_ide_init);
1735
1736 MODULE_AUTHOR("Andre Hedrick");
1737 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1738 MODULE_LICENSE("GPL");
Support for the Chinese Samsung S3C2440 based development boards