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[PATCH] radix-tree documentation cleanups
[linux-2.6/mini2440.git] / drivers / ide / pci / amd74xx.c
blob21965e5ef25e8c1c86bd59da0f40350d4f821702
1 /*
2 * Version 2.13
3 *
4 * AMD 755/756/766/8111 and nVidia nForce/2/2s/3/3s/CK804/MCP04
5 * IDE driver for Linux.
6 *
7 * Copyright (c) 2000-2002 Vojtech Pavlik
8 *
9 * Based on the work of:
10 * Andre Hedrick
11 */
12
13 /*
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License version 2 as published by
16 * the Free Software Foundation.
17 */
18
19 #include <linux/config.h>
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/ioport.h>
23 #include <linux/blkdev.h>
24 #include <linux/pci.h>
25 #include <linux/init.h>
26 #include <linux/ide.h>
27 #include <asm/io.h>
28
29 #include "ide-timing.h"
30
31 #define DISPLAY_AMD_TIMINGS
32
33 #define AMD_IDE_ENABLE (0x00 + amd_config->base)
34 #define AMD_IDE_CONFIG (0x01 + amd_config->base)
35 #define AMD_CABLE_DETECT (0x02 + amd_config->base)
36 #define AMD_DRIVE_TIMING (0x08 + amd_config->base)
37 #define AMD_8BIT_TIMING (0x0e + amd_config->base)
38 #define AMD_ADDRESS_SETUP (0x0c + amd_config->base)
39 #define AMD_UDMA_TIMING (0x10 + amd_config->base)
40
41 #define AMD_UDMA 0x07
42 #define AMD_UDMA_33 0x01
43 #define AMD_UDMA_66 0x02
44 #define AMD_UDMA_100 0x03
45 #define AMD_UDMA_133 0x04
46 #define AMD_CHECK_SWDMA 0x08
47 #define AMD_BAD_SWDMA 0x10
48 #define AMD_BAD_FIFO 0x20
49 #define AMD_CHECK_SERENADE 0x40
50
51 /*
52 * AMD SouthBridge chips.
53 */
54
55 static struct amd_ide_chip {
56 unsigned short id;
57 unsigned long base;
58 unsigned char flags;
59 } amd_ide_chips[] = {
60 { PCI_DEVICE_ID_AMD_COBRA_7401, 0x40, AMD_UDMA_33 | AMD_BAD_SWDMA },
61 { PCI_DEVICE_ID_AMD_VIPER_7409, 0x40, AMD_UDMA_66 | AMD_CHECK_SWDMA },
62 { PCI_DEVICE_ID_AMD_VIPER_7411, 0x40, AMD_UDMA_100 | AMD_BAD_FIFO },
63 { PCI_DEVICE_ID_AMD_OPUS_7441, 0x40, AMD_UDMA_100 },
64 { PCI_DEVICE_ID_AMD_8111_IDE, 0x40, AMD_UDMA_133 | AMD_CHECK_SERENADE },
65 { PCI_DEVICE_ID_NVIDIA_NFORCE_IDE, 0x50, AMD_UDMA_100 },
66 { PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE, 0x50, AMD_UDMA_133 },
67 { PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE, 0x50, AMD_UDMA_133 },
68 { PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA, 0x50, AMD_UDMA_133 },
69 { PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE, 0x50, AMD_UDMA_133 },
70 { PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE, 0x50, AMD_UDMA_133 },
71 { PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA, 0x50, AMD_UDMA_133 },
72 { PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2, 0x50, AMD_UDMA_133 },
73 { PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE, 0x50, AMD_UDMA_133 },
74 { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE, 0x50, AMD_UDMA_133 },
75 { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE, 0x50, AMD_UDMA_133 },
76 { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE, 0x50, AMD_UDMA_133 },
77 { PCI_DEVICE_ID_AMD_CS5536_IDE, 0x40, AMD_UDMA_100 },
78 { 0 }
79 };
80
81 static struct amd_ide_chip *amd_config;
82 static ide_pci_device_t *amd_chipset;
83 static unsigned int amd_80w;
84 static unsigned int amd_clock;
85
86 static char *amd_dma[] = { "MWDMA16", "UDMA33", "UDMA66", "UDMA100", "UDMA133" };
87 static unsigned char amd_cyc2udma[] = { 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 };
88
89 /*
90 * AMD /proc entry.
91 */
92
93 #ifdef CONFIG_PROC_FS
94
95 #include <linux/stat.h>
96 #include <linux/proc_fs.h>
97
98 static u8 amd74xx_proc;
99
100 static unsigned char amd_udma2cyc[] = { 4, 6, 8, 10, 3, 2, 1, 15 };
101 static unsigned long amd_base;
102 static struct pci_dev *bmide_dev;
103 extern int (*amd74xx_display_info)(char *, char **, off_t, int); /* ide-proc.c */
104
105 #define amd_print(format, arg...) p += sprintf(p, format "\n" , ## arg)
106 #define amd_print_drive(name, format, arg...)\
107 p += sprintf(p, name); for (i = 0; i < 4; i++) p += sprintf(p, format, ## arg); p += sprintf(p, "\n");
108
109 static int amd74xx_get_info(char *buffer, char **addr, off_t offset, int count)
110 {
111 int speed[4], cycle[4], setup[4], active[4], recover[4], den[4],
112 uen[4], udma[4], active8b[4], recover8b[4];
113 struct pci_dev *dev = bmide_dev;
114 unsigned int v, u, i;
115 unsigned short c, w;
116 unsigned char t;
117 int len;
118 char *p = buffer;
119
120 amd_print("----------AMD BusMastering IDE Configuration----------------");
121
122 amd_print("Driver Version: 2.13");
123 amd_print("South Bridge: %s", pci_name(bmide_dev));
124
125 pci_read_config_byte(dev, PCI_REVISION_ID, &t);
126 amd_print("Revision: IDE %#x", t);
127 amd_print("Highest DMA rate: %s", amd_dma[amd_config->flags & AMD_UDMA]);
128
129 amd_print("BM-DMA base: %#lx", amd_base);
130 amd_print("PCI clock: %d.%dMHz", amd_clock / 1000, amd_clock / 100 % 10);
131
132 amd_print("-----------------------Primary IDE-------Secondary IDE------");
133
134 pci_read_config_byte(dev, AMD_IDE_CONFIG, &t);
135 amd_print("Prefetch Buffer: %10s%20s", (t & 0x80) ? "yes" : "no", (t & 0x20) ? "yes" : "no");
136 amd_print("Post Write Buffer: %10s%20s", (t & 0x40) ? "yes" : "no", (t & 0x10) ? "yes" : "no");
137
138 pci_read_config_byte(dev, AMD_IDE_ENABLE, &t);
139 amd_print("Enabled: %10s%20s", (t & 0x02) ? "yes" : "no", (t & 0x01) ? "yes" : "no");
140
141 c = inb(amd_base + 0x02) | (inb(amd_base + 0x0a) << 8);
142 amd_print("Simplex only: %10s%20s", (c & 0x80) ? "yes" : "no", (c & 0x8000) ? "yes" : "no");
143
144 amd_print("Cable Type: %10s%20s", (amd_80w & 1) ? "80w" : "40w", (amd_80w & 2) ? "80w" : "40w");
145
146 if (!amd_clock)
147 return p - buffer;
148
149 amd_print("-------------------drive0----drive1----drive2----drive3-----");
150
151 pci_read_config_byte(dev, AMD_ADDRESS_SETUP, &t);
152 pci_read_config_dword(dev, AMD_DRIVE_TIMING, &v);
153 pci_read_config_word(dev, AMD_8BIT_TIMING, &w);
154 pci_read_config_dword(dev, AMD_UDMA_TIMING, &u);
155
156 for (i = 0; i < 4; i++) {
157 setup[i] = ((t >> ((3 - i) << 1)) & 0x3) + 1;
158 recover8b[i] = ((w >> ((1 - (i >> 1)) << 3)) & 0xf) + 1;
159 active8b[i] = ((w >> (((1 - (i >> 1)) << 3) + 4)) & 0xf) + 1;
160 active[i] = ((v >> (((3 - i) << 3) + 4)) & 0xf) + 1;
161 recover[i] = ((v >> ((3 - i) << 3)) & 0xf) + 1;
162
163 udma[i] = amd_udma2cyc[((u >> ((3 - i) << 3)) & 0x7)];
164 uen[i] = ((u >> ((3 - i) << 3)) & 0x40) ? 1 : 0;
165 den[i] = (c & ((i & 1) ? 0x40 : 0x20) << ((i & 2) << 2));
166
167 if (den[i] && uen[i] && udma[i] == 1) {
168 speed[i] = amd_clock * 3;
169 cycle[i] = 666666 / amd_clock;
170 continue;
171 }
172
173 if (den[i] && uen[i] && udma[i] == 15) {
174 speed[i] = amd_clock * 4;
175 cycle[i] = 500000 / amd_clock;
176 continue;
177 }
178
179 speed[i] = 4 * amd_clock / ((den[i] && uen[i]) ? udma[i] : (active[i] + recover[i]) * 2);
180 cycle[i] = 1000000 * ((den[i] && uen[i]) ? udma[i] : (active[i] + recover[i]) * 2) / amd_clock / 2;
181 }
182
183 amd_print_drive("Transfer Mode: ", "%10s", den[i] ? (uen[i] ? "UDMA" : "DMA") : "PIO");
184
185 amd_print_drive("Address Setup: ", "%8dns", 1000000 * setup[i] / amd_clock);
186 amd_print_drive("Cmd Active: ", "%8dns", 1000000 * active8b[i] / amd_clock);
187 amd_print_drive("Cmd Recovery: ", "%8dns", 1000000 * recover8b[i] / amd_clock);
188 amd_print_drive("Data Active: ", "%8dns", 1000000 * active[i] / amd_clock);
189 amd_print_drive("Data Recovery: ", "%8dns", 1000000 * recover[i] / amd_clock);
190 amd_print_drive("Cycle Time: ", "%8dns", cycle[i]);
191 amd_print_drive("Transfer Rate: ", "%4d.%dMB/s", speed[i] / 1000, speed[i] / 100 % 10);
192
193 /* hoping p - buffer is less than 4K... */
194 len = (p - buffer) - offset;
195 *addr = buffer + offset;
196
197 return len > count ? count : len;
198 }
199
200 #endif
201
202 /*
203 * amd_set_speed() writes timing values to the chipset registers
204 */
205
206 static void amd_set_speed(struct pci_dev *dev, unsigned char dn, struct ide_timing *timing)
207 {
208 unsigned char t;
209
210 pci_read_config_byte(dev, AMD_ADDRESS_SETUP, &t);
211 t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
212 pci_write_config_byte(dev, AMD_ADDRESS_SETUP, t);
213
214 pci_write_config_byte(dev, AMD_8BIT_TIMING + (1 - (dn >> 1)),
215 ((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1));
216
217 pci_write_config_byte(dev, AMD_DRIVE_TIMING + (3 - dn),
218 ((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1));
219
220 switch (amd_config->flags & AMD_UDMA) {
221 case AMD_UDMA_33: t = timing->udma ? (0xc0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
222 case AMD_UDMA_66: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 2, 10)]) : 0x03; break;
223 case AMD_UDMA_100: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 1, 10)]) : 0x03; break;
224 case AMD_UDMA_133: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 1, 15)]) : 0x03; break;
225 default: return;
226 }
227
228 pci_write_config_byte(dev, AMD_UDMA_TIMING + (3 - dn), t);
229 }
230
231 /*
232 * amd_set_drive() computes timing values configures the drive and
233 * the chipset to a desired transfer mode. It also can be called
234 * by upper layers.
235 */
236
237 static int amd_set_drive(ide_drive_t *drive, u8 speed)
238 {
239 ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1);
240 struct ide_timing t, p;
241 int T, UT;
242
243 if (speed != XFER_PIO_SLOW && speed != drive->current_speed)
244 if (ide_config_drive_speed(drive, speed))
245 printk(KERN_WARNING "ide%d: Drive %d didn't accept speed setting. Oh, well.\n",
246 drive->dn >> 1, drive->dn & 1);
247
248 T = 1000000000 / amd_clock;
249 UT = T / min_t(int, max_t(int, amd_config->flags & AMD_UDMA, 1), 2);
250
251 ide_timing_compute(drive, speed, &t, T, UT);
252
253 if (peer->present) {
254 ide_timing_compute(peer, peer->current_speed, &p, T, UT);
255 ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
256 }
257
258 if (speed == XFER_UDMA_5 && amd_clock <= 33333) t.udma = 1;
259 if (speed == XFER_UDMA_6 && amd_clock <= 33333) t.udma = 15;
260
261 amd_set_speed(HWIF(drive)->pci_dev, drive->dn, &t);
262
263 if (!drive->init_speed)
264 drive->init_speed = speed;
265 drive->current_speed = speed;
266
267 return 0;
268 }
269
270 /*
271 * amd74xx_tune_drive() is a callback from upper layers for
272 * PIO-only tuning.
273 */
274
275 static void amd74xx_tune_drive(ide_drive_t *drive, u8 pio)
276 {
277 if (pio == 255) {
278 amd_set_drive(drive, ide_find_best_mode(drive, XFER_PIO | XFER_EPIO));
279 return;
280 }
281
282 amd_set_drive(drive, XFER_PIO_0 + min_t(byte, pio, 5));
283 }
284
285 /*
286 * amd74xx_dmaproc() is a callback from upper layers that can do
287 * a lot, but we use it for DMA/PIO tuning only, delegating everything
288 * else to the default ide_dmaproc().
289 */
290
291 static int amd74xx_ide_dma_check(ide_drive_t *drive)
292 {
293 int w80 = HWIF(drive)->udma_four;
294
295 u8 speed = ide_find_best_mode(drive,
296 XFER_PIO | XFER_EPIO | XFER_MWDMA | XFER_UDMA |
297 ((amd_config->flags & AMD_BAD_SWDMA) ? 0 : XFER_SWDMA) |
298 (w80 && (amd_config->flags & AMD_UDMA) >= AMD_UDMA_66 ? XFER_UDMA_66 : 0) |
299 (w80 && (amd_config->flags & AMD_UDMA) >= AMD_UDMA_100 ? XFER_UDMA_100 : 0) |
300 (w80 && (amd_config->flags & AMD_UDMA) >= AMD_UDMA_133 ? XFER_UDMA_133 : 0));
301
302 amd_set_drive(drive, speed);
303
304 if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
305 return HWIF(drive)->ide_dma_on(drive);
306 return HWIF(drive)->ide_dma_off_quietly(drive);
307 }
308
309 /*
310 * The initialization callback. Here we determine the IDE chip type
311 * and initialize its drive independent registers.
312 */
313
314 static unsigned int __devinit init_chipset_amd74xx(struct pci_dev *dev, const char *name)
315 {
316 unsigned char t;
317 unsigned int u;
318 int i;
319
320 /*
321 * Check for bad SWDMA.
322 */
323
324 if (amd_config->flags & AMD_CHECK_SWDMA) {
325 pci_read_config_byte(dev, PCI_REVISION_ID, &t);
326 if (t <= 7)
327 amd_config->flags |= AMD_BAD_SWDMA;
328 }
329
330 /*
331 * Check 80-wire cable presence.
332 */
333
334 switch (amd_config->flags & AMD_UDMA) {
335
336 case AMD_UDMA_133:
337 case AMD_UDMA_100:
338 pci_read_config_byte(dev, AMD_CABLE_DETECT, &t);
339 pci_read_config_dword(dev, AMD_UDMA_TIMING, &u);
340 amd_80w = ((t & 0x3) ? 1 : 0) | ((t & 0xc) ? 2 : 0);
341 for (i = 24; i >= 0; i -= 8)
342 if (((u >> i) & 4) && !(amd_80w & (1 << (1 - (i >> 4))))) {
343 printk(KERN_WARNING "%s: BIOS didn't set cable bits correctly. Enabling workaround.\n",
344 amd_chipset->name);
345 amd_80w |= (1 << (1 - (i >> 4)));
346 }
347 break;
348
349 case AMD_UDMA_66:
350 pci_read_config_dword(dev, AMD_UDMA_TIMING, &u);
351 for (i = 24; i >= 0; i -= 8)
352 if ((u >> i) & 4)
353 amd_80w |= (1 << (1 - (i >> 4)));
354 break;
355 }
356
357 /*
358 * Take care of prefetch & postwrite.
359 */
360
361 pci_read_config_byte(dev, AMD_IDE_CONFIG, &t);
362 pci_write_config_byte(dev, AMD_IDE_CONFIG,
363 (amd_config->flags & AMD_BAD_FIFO) ? (t & 0x0f) : (t | 0xf0));
364
365 /*
366 * Take care of incorrectly wired Serenade mainboards.
367 */
368
369 if ((amd_config->flags & AMD_CHECK_SERENADE) &&
370 dev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
371 dev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
372 amd_config->flags = AMD_UDMA_100;
373
374 /*
375 * Determine the system bus clock.
376 */
377
378 amd_clock = system_bus_clock() * 1000;
379
380 switch (amd_clock) {
381 case 33000: amd_clock = 33333; break;
382 case 37000: amd_clock = 37500; break;
383 case 41000: amd_clock = 41666; break;
384 }
385
386 if (amd_clock < 20000 || amd_clock > 50000) {
387 printk(KERN_WARNING "%s: User given PCI clock speed impossible (%d), using 33 MHz instead.\n",
388 amd_chipset->name, amd_clock);
389 printk(KERN_WARNING "%s: Use ide0=ata66 if you want to assume 80-wire cable\n",
390 amd_chipset->name);
391 amd_clock = 33333;
392 }
393
394 /*
395 * Print the boot message.
396 */
397
398 pci_read_config_byte(dev, PCI_REVISION_ID, &t);
399 printk(KERN_INFO "%s: %s (rev %02x) %s controller\n",
400 amd_chipset->name, pci_name(dev), t, amd_dma[amd_config->flags & AMD_UDMA]);
401
402 /*
403 * Register /proc/ide/amd74xx entry
404 */
405
406 #if defined(DISPLAY_AMD_TIMINGS) && defined(CONFIG_PROC_FS)
407 if (!amd74xx_proc) {
408 amd_base = pci_resource_start(dev, 4);
409 bmide_dev = dev;
410 ide_pci_create_host_proc("amd74xx", amd74xx_get_info);
411 amd74xx_proc = 1;
412 }
413 #endif /* DISPLAY_AMD_TIMINGS && CONFIG_PROC_FS */
414
415 return dev->irq;
416 }
417
418 static void __devinit init_hwif_amd74xx(ide_hwif_t *hwif)
419 {
420 int i;
421
422 if (hwif->irq == 0) /* 0 is bogus but will do for now */
423 hwif->irq = pci_get_legacy_ide_irq(hwif->pci_dev, hwif->channel);
424
425 hwif->autodma = 0;
426
427 hwif->tuneproc = &amd74xx_tune_drive;
428 hwif->speedproc = &amd_set_drive;
429
430 for (i = 0; i < 2; i++) {
431 hwif->drives[i].io_32bit = 1;
432 hwif->drives[i].unmask = 1;
433 hwif->drives[i].autotune = 1;
434 hwif->drives[i].dn = hwif->channel * 2 + i;
435 }
436
437 if (!hwif->dma_base)
438 return;
439
440 hwif->atapi_dma = 1;
441 hwif->ultra_mask = 0x7f;
442 hwif->mwdma_mask = 0x07;
443 hwif->swdma_mask = 0x07;
444
445 if (!hwif->udma_four)
446 hwif->udma_four = (amd_80w >> hwif->channel) & 1;
447 hwif->ide_dma_check = &amd74xx_ide_dma_check;
448 if (!noautodma)
449 hwif->autodma = 1;
450 hwif->drives[0].autodma = hwif->autodma;
451 hwif->drives[1].autodma = hwif->autodma;
452 }
453
454 #define DECLARE_AMD_DEV(name_str) \
455 { \
456 .name = name_str, \
457 .init_chipset = init_chipset_amd74xx, \
458 .init_hwif = init_hwif_amd74xx, \
459 .channels = 2, \
460 .autodma = AUTODMA, \
461 .enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, \
462 .bootable = ON_BOARD, \
463 }
464
465 #define DECLARE_NV_DEV(name_str) \
466 { \
467 .name = name_str, \
468 .init_chipset = init_chipset_amd74xx, \
469 .init_hwif = init_hwif_amd74xx, \
470 .channels = 2, \
471 .autodma = AUTODMA, \
472 .enablebits = {{0x50,0x02,0x02}, {0x50,0x01,0x01}}, \
473 .bootable = ON_BOARD, \
474 }
475
476 static ide_pci_device_t amd74xx_chipsets[] __devinitdata = {
477 /* 0 */ DECLARE_AMD_DEV("AMD7401"),
478 /* 1 */ DECLARE_AMD_DEV("AMD7409"),
479 /* 2 */ DECLARE_AMD_DEV("AMD7411"),
480 /* 3 */ DECLARE_AMD_DEV("AMD7441"),
481 /* 4 */ DECLARE_AMD_DEV("AMD8111"),
482
483 /* 5 */ DECLARE_NV_DEV("NFORCE"),
484 /* 6 */ DECLARE_NV_DEV("NFORCE2"),
485 /* 7 */ DECLARE_NV_DEV("NFORCE2-U400R"),
486 /* 8 */ DECLARE_NV_DEV("NFORCE2-U400R-SATA"),
487 /* 9 */ DECLARE_NV_DEV("NFORCE3-150"),
488 /* 10 */ DECLARE_NV_DEV("NFORCE3-250"),
489 /* 11 */ DECLARE_NV_DEV("NFORCE3-250-SATA"),
490 /* 12 */ DECLARE_NV_DEV("NFORCE3-250-SATA2"),
491 /* 13 */ DECLARE_NV_DEV("NFORCE-CK804"),
492 /* 14 */ DECLARE_NV_DEV("NFORCE-MCP04"),
493 /* 15 */ DECLARE_NV_DEV("NFORCE-MCP51"),
494 /* 16 */ DECLARE_NV_DEV("NFORCE-MCP55"),
495 /* 17 */ DECLARE_AMD_DEV("AMD5536"),
496 };
497
498 static int __devinit amd74xx_probe(struct pci_dev *dev, const struct pci_device_id *id)
499 {
500 amd_chipset = amd74xx_chipsets + id->driver_data;
501 amd_config = amd_ide_chips + id->driver_data;
502 if (dev->device != amd_config->id) {
503 printk(KERN_ERR "%s: assertion 0x%02x == 0x%02x failed !\n",
504 pci_name(dev), dev->device, amd_config->id);
505 return -ENODEV;
506 }
507 return ide_setup_pci_device(dev, amd_chipset);
508 }
509
510 static struct pci_device_id amd74xx_pci_tbl[] = {
511 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_COBRA_7401, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
512 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7409, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
513 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
514 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_OPUS_7441, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
515 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
516 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 },
517 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6 },
518 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7 },
519 #ifdef CONFIG_BLK_DEV_IDE_SATA
520 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
521 #endif
522 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9 },
523 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10 },
524 #ifdef CONFIG_BLK_DEV_IDE_SATA
525 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11 },
526 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12 },
527 #endif
528 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 13 },
529 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 14 },
530 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 15 },
531 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 16 },
532 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 17 },
533 { 0, },
534 };
535 MODULE_DEVICE_TABLE(pci, amd74xx_pci_tbl);
536
537 static struct pci_driver driver = {
538 .name = "AMD_IDE",
539 .id_table = amd74xx_pci_tbl,
540 .probe = amd74xx_probe,
541 };
542
543 static int amd74xx_ide_init(void)
544 {
545 return ide_pci_register_driver(&driver);
546 }
547
548 module_init(amd74xx_ide_init);
549
550 MODULE_AUTHOR("Vojtech Pavlik");
551 MODULE_DESCRIPTION("AMD PCI IDE driver");
552 MODULE_LICENSE("GPL");
Support for the Chinese Samsung S3C2440 based development boards