1 #include <linux/interrupt.h>
2 #include <linux/dmar.h>
3 #include <linux/spinlock.h>
4 #include <linux/jiffies.h>
7 #include <asm/io_apic.h>
9 #include <linux/intel-iommu.h>
10 #include "intr_remapping.h"
12 static struct ioapic_scope ir_ioapic
[MAX_IO_APICS
];
13 static int ir_ioapic_num
;
14 int intr_remapping_enabled
;
17 struct intel_iommu
*iommu
;
23 #ifdef CONFIG_SPARSE_IRQ
24 static struct irq_2_iommu
*get_one_free_irq_2_iommu(int cpu
)
26 struct irq_2_iommu
*iommu
;
29 node
= cpu_to_node(cpu
);
31 iommu
= kzalloc_node(sizeof(*iommu
), GFP_ATOMIC
, node
);
32 printk(KERN_DEBUG
"alloc irq_2_iommu on cpu %d node %d\n", cpu
, node
);
37 static struct irq_2_iommu
*irq_2_iommu(unsigned int irq
)
39 struct irq_desc
*desc
;
41 desc
= irq_to_desc(irq
);
43 if (WARN_ON_ONCE(!desc
))
46 return desc
->irq_2_iommu
;
49 static struct irq_2_iommu
*irq_2_iommu_alloc_cpu(unsigned int irq
, int cpu
)
51 struct irq_desc
*desc
;
52 struct irq_2_iommu
*irq_iommu
;
55 * alloc irq desc if not allocated already.
57 desc
= irq_to_desc_alloc_cpu(irq
, cpu
);
59 printk(KERN_INFO
"can not get irq_desc for %d\n", irq
);
63 irq_iommu
= desc
->irq_2_iommu
;
66 desc
->irq_2_iommu
= get_one_free_irq_2_iommu(cpu
);
68 return desc
->irq_2_iommu
;
71 static struct irq_2_iommu
*irq_2_iommu_alloc(unsigned int irq
)
73 return irq_2_iommu_alloc_cpu(irq
, boot_cpu_id
);
76 #else /* !CONFIG_SPARSE_IRQ */
78 static struct irq_2_iommu irq_2_iommuX
[NR_IRQS
];
80 static struct irq_2_iommu
*irq_2_iommu(unsigned int irq
)
83 return &irq_2_iommuX
[irq
];
87 static struct irq_2_iommu
*irq_2_iommu_alloc(unsigned int irq
)
89 return irq_2_iommu(irq
);
93 static DEFINE_SPINLOCK(irq_2_ir_lock
);
95 static struct irq_2_iommu
*valid_irq_2_iommu(unsigned int irq
)
97 struct irq_2_iommu
*irq_iommu
;
99 irq_iommu
= irq_2_iommu(irq
);
104 if (!irq_iommu
->iommu
)
110 int irq_remapped(int irq
)
112 return valid_irq_2_iommu(irq
) != NULL
;
115 int get_irte(int irq
, struct irte
*entry
)
118 struct irq_2_iommu
*irq_iommu
;
123 spin_lock(&irq_2_ir_lock
);
124 irq_iommu
= valid_irq_2_iommu(irq
);
126 spin_unlock(&irq_2_ir_lock
);
130 index
= irq_iommu
->irte_index
+ irq_iommu
->sub_handle
;
131 *entry
= *(irq_iommu
->iommu
->ir_table
->base
+ index
);
133 spin_unlock(&irq_2_ir_lock
);
137 int alloc_irte(struct intel_iommu
*iommu
, int irq
, u16 count
)
139 struct ir_table
*table
= iommu
->ir_table
;
140 struct irq_2_iommu
*irq_iommu
;
141 u16 index
, start_index
;
142 unsigned int mask
= 0;
148 #ifndef CONFIG_SPARSE_IRQ
149 /* protect irq_2_iommu_alloc later */
155 * start the IRTE search from index 0.
157 index
= start_index
= 0;
160 count
= __roundup_pow_of_two(count
);
164 if (mask
> ecap_max_handle_mask(iommu
->ecap
)) {
166 "Requested mask %x exceeds the max invalidation handle"
167 " mask value %Lx\n", mask
,
168 ecap_max_handle_mask(iommu
->ecap
));
172 spin_lock(&irq_2_ir_lock
);
174 for (i
= index
; i
< index
+ count
; i
++)
175 if (table
->base
[i
].present
)
177 /* empty index found */
178 if (i
== index
+ count
)
181 index
= (index
+ count
) % INTR_REMAP_TABLE_ENTRIES
;
183 if (index
== start_index
) {
184 spin_unlock(&irq_2_ir_lock
);
185 printk(KERN_ERR
"can't allocate an IRTE\n");
190 for (i
= index
; i
< index
+ count
; i
++)
191 table
->base
[i
].present
= 1;
193 irq_iommu
= irq_2_iommu_alloc(irq
);
195 spin_unlock(&irq_2_ir_lock
);
196 printk(KERN_ERR
"can't allocate irq_2_iommu\n");
200 irq_iommu
->iommu
= iommu
;
201 irq_iommu
->irte_index
= index
;
202 irq_iommu
->sub_handle
= 0;
203 irq_iommu
->irte_mask
= mask
;
205 spin_unlock(&irq_2_ir_lock
);
210 static void qi_flush_iec(struct intel_iommu
*iommu
, int index
, int mask
)
214 desc
.low
= QI_IEC_IIDEX(index
) | QI_IEC_TYPE
| QI_IEC_IM(mask
)
218 qi_submit_sync(&desc
, iommu
);
221 int map_irq_to_irte_handle(int irq
, u16
*sub_handle
)
224 struct irq_2_iommu
*irq_iommu
;
226 spin_lock(&irq_2_ir_lock
);
227 irq_iommu
= valid_irq_2_iommu(irq
);
229 spin_unlock(&irq_2_ir_lock
);
233 *sub_handle
= irq_iommu
->sub_handle
;
234 index
= irq_iommu
->irte_index
;
235 spin_unlock(&irq_2_ir_lock
);
239 int set_irte_irq(int irq
, struct intel_iommu
*iommu
, u16 index
, u16 subhandle
)
241 struct irq_2_iommu
*irq_iommu
;
243 spin_lock(&irq_2_ir_lock
);
245 irq_iommu
= irq_2_iommu_alloc(irq
);
248 spin_unlock(&irq_2_ir_lock
);
249 printk(KERN_ERR
"can't allocate irq_2_iommu\n");
253 irq_iommu
->iommu
= iommu
;
254 irq_iommu
->irte_index
= index
;
255 irq_iommu
->sub_handle
= subhandle
;
256 irq_iommu
->irte_mask
= 0;
258 spin_unlock(&irq_2_ir_lock
);
263 int clear_irte_irq(int irq
, struct intel_iommu
*iommu
, u16 index
)
265 struct irq_2_iommu
*irq_iommu
;
267 spin_lock(&irq_2_ir_lock
);
268 irq_iommu
= valid_irq_2_iommu(irq
);
270 spin_unlock(&irq_2_ir_lock
);
274 irq_iommu
->iommu
= NULL
;
275 irq_iommu
->irte_index
= 0;
276 irq_iommu
->sub_handle
= 0;
277 irq_2_iommu(irq
)->irte_mask
= 0;
279 spin_unlock(&irq_2_ir_lock
);
284 int modify_irte(int irq
, struct irte
*irte_modified
)
288 struct intel_iommu
*iommu
;
289 struct irq_2_iommu
*irq_iommu
;
291 spin_lock(&irq_2_ir_lock
);
292 irq_iommu
= valid_irq_2_iommu(irq
);
294 spin_unlock(&irq_2_ir_lock
);
298 iommu
= irq_iommu
->iommu
;
300 index
= irq_iommu
->irte_index
+ irq_iommu
->sub_handle
;
301 irte
= &iommu
->ir_table
->base
[index
];
303 set_64bit((unsigned long *)irte
, irte_modified
->low
| (1 << 1));
304 __iommu_flush_cache(iommu
, irte
, sizeof(*irte
));
306 qi_flush_iec(iommu
, index
, 0);
308 spin_unlock(&irq_2_ir_lock
);
312 int flush_irte(int irq
)
315 struct intel_iommu
*iommu
;
316 struct irq_2_iommu
*irq_iommu
;
318 spin_lock(&irq_2_ir_lock
);
319 irq_iommu
= valid_irq_2_iommu(irq
);
321 spin_unlock(&irq_2_ir_lock
);
325 iommu
= irq_iommu
->iommu
;
327 index
= irq_iommu
->irte_index
+ irq_iommu
->sub_handle
;
329 qi_flush_iec(iommu
, index
, irq_iommu
->irte_mask
);
330 spin_unlock(&irq_2_ir_lock
);
335 struct intel_iommu
*map_ioapic_to_ir(int apic
)
339 for (i
= 0; i
< MAX_IO_APICS
; i
++)
340 if (ir_ioapic
[i
].id
== apic
)
341 return ir_ioapic
[i
].iommu
;
345 struct intel_iommu
*map_dev_to_ir(struct pci_dev
*dev
)
347 struct dmar_drhd_unit
*drhd
;
349 drhd
= dmar_find_matched_drhd_unit(dev
);
356 int free_irte(int irq
)
360 struct intel_iommu
*iommu
;
361 struct irq_2_iommu
*irq_iommu
;
363 spin_lock(&irq_2_ir_lock
);
364 irq_iommu
= valid_irq_2_iommu(irq
);
366 spin_unlock(&irq_2_ir_lock
);
370 iommu
= irq_iommu
->iommu
;
372 index
= irq_iommu
->irte_index
+ irq_iommu
->sub_handle
;
373 irte
= &iommu
->ir_table
->base
[index
];
375 if (!irq_iommu
->sub_handle
) {
376 for (i
= 0; i
< (1 << irq_iommu
->irte_mask
); i
++)
377 set_64bit((unsigned long *)irte
, 0);
378 qi_flush_iec(iommu
, index
, irq_iommu
->irte_mask
);
381 irq_iommu
->iommu
= NULL
;
382 irq_iommu
->irte_index
= 0;
383 irq_iommu
->sub_handle
= 0;
384 irq_iommu
->irte_mask
= 0;
386 spin_unlock(&irq_2_ir_lock
);
391 static void iommu_set_intr_remapping(struct intel_iommu
*iommu
, int mode
)
397 addr
= virt_to_phys((void *)iommu
->ir_table
->base
);
399 spin_lock_irqsave(&iommu
->register_lock
, flags
);
401 dmar_writeq(iommu
->reg
+ DMAR_IRTA_REG
,
402 (addr
) | IR_X2APIC_MODE(mode
) | INTR_REMAP_TABLE_REG_SIZE
);
404 /* Set interrupt-remapping table pointer */
405 cmd
= iommu
->gcmd
| DMA_GCMD_SIRTP
;
406 writel(cmd
, iommu
->reg
+ DMAR_GCMD_REG
);
408 IOMMU_WAIT_OP(iommu
, DMAR_GSTS_REG
,
409 readl
, (sts
& DMA_GSTS_IRTPS
), sts
);
410 spin_unlock_irqrestore(&iommu
->register_lock
, flags
);
413 * global invalidation of interrupt entry cache before enabling
414 * interrupt-remapping.
416 qi_global_iec(iommu
);
418 spin_lock_irqsave(&iommu
->register_lock
, flags
);
420 /* Enable interrupt-remapping */
421 cmd
= iommu
->gcmd
| DMA_GCMD_IRE
;
422 iommu
->gcmd
|= DMA_GCMD_IRE
;
423 writel(cmd
, iommu
->reg
+ DMAR_GCMD_REG
);
425 IOMMU_WAIT_OP(iommu
, DMAR_GSTS_REG
,
426 readl
, (sts
& DMA_GSTS_IRES
), sts
);
428 spin_unlock_irqrestore(&iommu
->register_lock
, flags
);
432 static int setup_intr_remapping(struct intel_iommu
*iommu
, int mode
)
434 struct ir_table
*ir_table
;
437 ir_table
= iommu
->ir_table
= kzalloc(sizeof(struct ir_table
),
440 if (!iommu
->ir_table
)
443 pages
= alloc_pages(GFP_KERNEL
| __GFP_ZERO
, INTR_REMAP_PAGE_ORDER
);
446 printk(KERN_ERR
"failed to allocate pages of order %d\n",
447 INTR_REMAP_PAGE_ORDER
);
448 kfree(iommu
->ir_table
);
452 ir_table
->base
= page_address(pages
);
454 iommu_set_intr_remapping(iommu
, mode
);
458 int __init
enable_intr_remapping(int eim
)
460 struct dmar_drhd_unit
*drhd
;
464 * check for the Interrupt-remapping support
466 for_each_drhd_unit(drhd
) {
467 struct intel_iommu
*iommu
= drhd
->iommu
;
469 if (!ecap_ir_support(iommu
->ecap
))
472 if (eim
&& !ecap_eim_support(iommu
->ecap
)) {
473 printk(KERN_INFO
"DRHD %Lx: EIM not supported by DRHD, "
474 " ecap %Lx\n", drhd
->reg_base_addr
, iommu
->ecap
);
480 * Enable queued invalidation for all the DRHD's.
482 for_each_drhd_unit(drhd
) {
484 struct intel_iommu
*iommu
= drhd
->iommu
;
485 ret
= dmar_enable_qi(iommu
);
488 printk(KERN_ERR
"DRHD %Lx: failed to enable queued, "
489 " invalidation, ecap %Lx, ret %d\n",
490 drhd
->reg_base_addr
, iommu
->ecap
, ret
);
496 * Setup Interrupt-remapping for all the DRHD's now.
498 for_each_drhd_unit(drhd
) {
499 struct intel_iommu
*iommu
= drhd
->iommu
;
501 if (!ecap_ir_support(iommu
->ecap
))
504 if (setup_intr_remapping(iommu
, eim
))
513 intr_remapping_enabled
= 1;
519 * handle error condition gracefully here!
524 static int ir_parse_ioapic_scope(struct acpi_dmar_header
*header
,
525 struct intel_iommu
*iommu
)
527 struct acpi_dmar_hardware_unit
*drhd
;
528 struct acpi_dmar_device_scope
*scope
;
531 drhd
= (struct acpi_dmar_hardware_unit
*)header
;
533 start
= (void *)(drhd
+ 1);
534 end
= ((void *)drhd
) + header
->length
;
536 while (start
< end
) {
538 if (scope
->entry_type
== ACPI_DMAR_SCOPE_TYPE_IOAPIC
) {
539 if (ir_ioapic_num
== MAX_IO_APICS
) {
540 printk(KERN_WARNING
"Exceeded Max IO APICS\n");
544 printk(KERN_INFO
"IOAPIC id %d under DRHD base"
545 " 0x%Lx\n", scope
->enumeration_id
,
548 ir_ioapic
[ir_ioapic_num
].iommu
= iommu
;
549 ir_ioapic
[ir_ioapic_num
].id
= scope
->enumeration_id
;
552 start
+= scope
->length
;
559 * Finds the assocaition between IOAPIC's and its Interrupt-remapping
562 int __init
parse_ioapics_under_ir(void)
564 struct dmar_drhd_unit
*drhd
;
565 int ir_supported
= 0;
567 for_each_drhd_unit(drhd
) {
568 struct intel_iommu
*iommu
= drhd
->iommu
;
570 if (ecap_ir_support(iommu
->ecap
)) {
571 if (ir_parse_ioapic_scope(drhd
->hdr
, iommu
))
578 if (ir_supported
&& ir_ioapic_num
!= nr_ioapics
) {
580 "Not all IO-APIC's listed under remapping hardware\n");