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1 Booting the Linux/ppc kernel without Open Firmware
2 --------------------------------------------------
4 (c) 2005 Benjamin Herrenschmidt <benh at kernel.crashing.org>,
5 IBM Corp.
6 (c) 2005 Becky Bruce <becky.bruce at freescale.com>,
7 Freescale Semiconductor, FSL SOC and 32-bit additions
8 (c) 2006 MontaVista Software, Inc.
9 Flash chip node definition
11 Table of Contents
12 =================
14 I - Introduction
15 1) Entry point for arch/powerpc
16 2) Board support
18 II - The DT block format
19 1) Header
20 2) Device tree generalities
21 3) Device tree "structure" block
22 4) Device tree "strings" block
24 III - Required content of the device tree
25 1) Note about cells and address representation
26 2) Note about "compatible" properties
27 3) Note about "name" properties
28 4) Note about node and property names and character set
29 5) Required nodes and properties
30 a) The root node
31 b) The /cpus node
32 c) The /cpus/* nodes
33 d) the /memory node(s)
34 e) The /chosen node
35 f) the /soc<SOCname> node
37 IV - "dtc", the device tree compiler
39 V - Recommendations for a bootloader
41 VI - System-on-a-chip devices and nodes
42 1) Defining child nodes of an SOC
43 2) Representing devices without a current OF specification
44 a) PHY nodes
45 b) Interrupt controllers
46 c) CFI or JEDEC memory-mapped NOR flash
47 d) 4xx/Axon EMAC ethernet nodes
48 e) Xilinx IP cores
49 f) USB EHCI controllers
50 g) MDIO on GPIOs
51 h) SPI busses
53 VII - Marvell Discovery mv64[345]6x System Controller chips
54 1) The /system-controller node
55 2) Child nodes of /system-controller
56 a) Marvell Discovery MDIO bus
57 b) Marvell Discovery ethernet controller
58 c) Marvell Discovery PHY nodes
59 d) Marvell Discovery SDMA nodes
60 e) Marvell Discovery BRG nodes
61 f) Marvell Discovery CUNIT nodes
62 g) Marvell Discovery MPSCROUTING nodes
63 h) Marvell Discovery MPSCINTR nodes
64 i) Marvell Discovery MPSC nodes
65 j) Marvell Discovery Watch Dog Timer nodes
66 k) Marvell Discovery I2C nodes
67 l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes
68 m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes
69 n) Marvell Discovery GPP (General Purpose Pins) nodes
70 o) Marvell Discovery PCI host bridge node
71 p) Marvell Discovery CPU Error nodes
72 q) Marvell Discovery SRAM Controller nodes
73 r) Marvell Discovery PCI Error Handler nodes
74 s) Marvell Discovery Memory Controller nodes
76 VIII - Specifying interrupt information for devices
77 1) interrupts property
78 2) interrupt-parent property
79 3) OpenPIC Interrupt Controllers
80 4) ISA Interrupt Controllers
82 IX - Specifying GPIO information for devices
83 1) gpios property
84 2) gpio-controller nodes
86 X - Specifying device power management information (sleep property)
88 Appendix A - Sample SOC node for MPC8540
91 Revision Information
92 ====================
94 May 18, 2005: Rev 0.1 - Initial draft, no chapter III yet.
96 May 19, 2005: Rev 0.2 - Add chapter III and bits & pieces here or
97 clarifies the fact that a lot of things are
98 optional, the kernel only requires a very
99 small device tree, though it is encouraged
100 to provide an as complete one as possible.
102 May 24, 2005: Rev 0.3 - Precise that DT block has to be in RAM
103 - Misc fixes
104 - Define version 3 and new format version 16
105 for the DT block (version 16 needs kernel
106 patches, will be fwd separately).
107 String block now has a size, and full path
108 is replaced by unit name for more
109 compactness.
110 linux,phandle is made optional, only nodes
111 that are referenced by other nodes need it.
112 "name" property is now automatically
113 deduced from the unit name
115 June 1, 2005: Rev 0.4 - Correct confusion between OF_DT_END and
116 OF_DT_END_NODE in structure definition.
117 - Change version 16 format to always align
118 property data to 4 bytes. Since tokens are
119 already aligned, that means no specific
120 required alignment between property size
121 and property data. The old style variable
122 alignment would make it impossible to do
123 "simple" insertion of properties using
124 memmove (thanks Milton for
125 noticing). Updated kernel patch as well
126 - Correct a few more alignment constraints
127 - Add a chapter about the device-tree
128 compiler and the textural representation of
129 the tree that can be "compiled" by dtc.
131 November 21, 2005: Rev 0.5
132 - Additions/generalizations for 32-bit
133 - Changed to reflect the new arch/powerpc
134 structure
135 - Added chapter VI
138 ToDo:
139 - Add some definitions of interrupt tree (simple/complex)
140 - Add some definitions for PCI host bridges
141 - Add some common address format examples
142 - Add definitions for standard properties and "compatible"
143 names for cells that are not already defined by the existing
144 OF spec.
145 - Compare FSL SOC use of PCI to standard and make sure no new
146 node definition required.
147 - Add more information about node definitions for SOC devices
148 that currently have no standard, like the FSL CPM.
151 I - Introduction
152 ================
154 During the recent development of the Linux/ppc64 kernel, and more
155 specifically, the addition of new platform types outside of the old
156 IBM pSeries/iSeries pair, it was decided to enforce some strict rules
157 regarding the kernel entry and bootloader <-> kernel interfaces, in
158 order to avoid the degeneration that had become the ppc32 kernel entry
159 point and the way a new platform should be added to the kernel. The
160 legacy iSeries platform breaks those rules as it predates this scheme,
161 but no new board support will be accepted in the main tree that
162 doesn't follows them properly. In addition, since the advent of the
163 arch/powerpc merged architecture for ppc32 and ppc64, new 32-bit
164 platforms and 32-bit platforms which move into arch/powerpc will be
165 required to use these rules as well.
167 The main requirement that will be defined in more detail below is
168 the presence of a device-tree whose format is defined after Open
169 Firmware specification. However, in order to make life easier
170 to embedded board vendors, the kernel doesn't require the device-tree
171 to represent every device in the system and only requires some nodes
172 and properties to be present. This will be described in detail in
173 section III, but, for example, the kernel does not require you to
174 create a node for every PCI device in the system. It is a requirement
175 to have a node for PCI host bridges in order to provide interrupt
176 routing informations and memory/IO ranges, among others. It is also
177 recommended to define nodes for on chip devices and other busses that
178 don't specifically fit in an existing OF specification. This creates a
179 great flexibility in the way the kernel can then probe those and match
180 drivers to device, without having to hard code all sorts of tables. It
181 also makes it more flexible for board vendors to do minor hardware
182 upgrades without significantly impacting the kernel code or cluttering
183 it with special cases.
186 1) Entry point for arch/powerpc
187 -------------------------------
189 There is one and one single entry point to the kernel, at the start
190 of the kernel image. That entry point supports two calling
191 conventions:
193 a) Boot from Open Firmware. If your firmware is compatible
194 with Open Firmware (IEEE 1275) or provides an OF compatible
195 client interface API (support for "interpret" callback of
196 forth words isn't required), you can enter the kernel with:
198 r5 : OF callback pointer as defined by IEEE 1275
199 bindings to powerpc. Only the 32-bit client interface
200 is currently supported
202 r3, r4 : address & length of an initrd if any or 0
204 The MMU is either on or off; the kernel will run the
205 trampoline located in arch/powerpc/kernel/prom_init.c to
206 extract the device-tree and other information from open
207 firmware and build a flattened device-tree as described
208 in b). prom_init() will then re-enter the kernel using
209 the second method. This trampoline code runs in the
210 context of the firmware, which is supposed to handle all
211 exceptions during that time.
213 b) Direct entry with a flattened device-tree block. This entry
214 point is called by a) after the OF trampoline and can also be
215 called directly by a bootloader that does not support the Open
216 Firmware client interface. It is also used by "kexec" to
217 implement "hot" booting of a new kernel from a previous
218 running one. This method is what I will describe in more
219 details in this document, as method a) is simply standard Open
220 Firmware, and thus should be implemented according to the
221 various standard documents defining it and its binding to the
222 PowerPC platform. The entry point definition then becomes:
224 r3 : physical pointer to the device-tree block
225 (defined in chapter II) in RAM
227 r4 : physical pointer to the kernel itself. This is
228 used by the assembly code to properly disable the MMU
229 in case you are entering the kernel with MMU enabled
230 and a non-1:1 mapping.
232 r5 : NULL (as to differentiate with method a)
234 Note about SMP entry: Either your firmware puts your other
235 CPUs in some sleep loop or spin loop in ROM where you can get
236 them out via a soft reset or some other means, in which case
237 you don't need to care, or you'll have to enter the kernel
238 with all CPUs. The way to do that with method b) will be
239 described in a later revision of this document.
242 2) Board support
243 ----------------
245 64-bit kernels:
247 Board supports (platforms) are not exclusive config options. An
248 arbitrary set of board supports can be built in a single kernel
249 image. The kernel will "know" what set of functions to use for a
250 given platform based on the content of the device-tree. Thus, you
251 should:
253 a) add your platform support as a _boolean_ option in
254 arch/powerpc/Kconfig, following the example of PPC_PSERIES,
255 PPC_PMAC and PPC_MAPLE. The later is probably a good
256 example of a board support to start from.
258 b) create your main platform file as
259 "arch/powerpc/platforms/myplatform/myboard_setup.c" and add it
260 to the Makefile under the condition of your CONFIG_
261 option. This file will define a structure of type "ppc_md"
262 containing the various callbacks that the generic code will
263 use to get to your platform specific code
265 c) Add a reference to your "ppc_md" structure in the
266 "machines" table in arch/powerpc/kernel/setup_64.c if you are
267 a 64-bit platform.
269 d) request and get assigned a platform number (see PLATFORM_*
270 constants in arch/powerpc/include/asm/processor.h
272 32-bit embedded kernels:
274 Currently, board support is essentially an exclusive config option.
275 The kernel is configured for a single platform. Part of the reason
276 for this is to keep kernels on embedded systems small and efficient;
277 part of this is due to the fact the code is already that way. In the
278 future, a kernel may support multiple platforms, but only if the
279 platforms feature the same core architecture. A single kernel build
280 cannot support both configurations with Book E and configurations
281 with classic Powerpc architectures.
283 32-bit embedded platforms that are moved into arch/powerpc using a
284 flattened device tree should adopt the merged tree practice of
285 setting ppc_md up dynamically, even though the kernel is currently
286 built with support for only a single platform at a time. This allows
287 unification of the setup code, and will make it easier to go to a
288 multiple-platform-support model in the future.
290 NOTE: I believe the above will be true once Ben's done with the merge
291 of the boot sequences.... someone speak up if this is wrong!
293 To add a 32-bit embedded platform support, follow the instructions
294 for 64-bit platforms above, with the exception that the Kconfig
295 option should be set up such that the kernel builds exclusively for
296 the platform selected. The processor type for the platform should
297 enable another config option to select the specific board
298 supported.
300 NOTE: If Ben doesn't merge the setup files, may need to change this to
301 point to setup_32.c
304 I will describe later the boot process and various callbacks that
305 your platform should implement.
308 II - The DT block format
309 ========================
312 This chapter defines the actual format of the flattened device-tree
313 passed to the kernel. The actual content of it and kernel requirements
314 are described later. You can find example of code manipulating that
315 format in various places, including arch/powerpc/kernel/prom_init.c
316 which will generate a flattened device-tree from the Open Firmware
317 representation, or the fs2dt utility which is part of the kexec tools
318 which will generate one from a filesystem representation. It is
319 expected that a bootloader like uboot provides a bit more support,
320 that will be discussed later as well.
322 Note: The block has to be in main memory. It has to be accessible in
323 both real mode and virtual mode with no mapping other than main
324 memory. If you are writing a simple flash bootloader, it should copy
325 the block to RAM before passing it to the kernel.
328 1) Header
329 ---------
331 The kernel is entered with r3 pointing to an area of memory that is
332 roughly described in arch/powerpc/include/asm/prom.h by the structure
333 boot_param_header:
335 struct boot_param_header {
336 u32 magic; /* magic word OF_DT_HEADER */
337 u32 totalsize; /* total size of DT block */
338 u32 off_dt_struct; /* offset to structure */
339 u32 off_dt_strings; /* offset to strings */
340 u32 off_mem_rsvmap; /* offset to memory reserve map
341 */
342 u32 version; /* format version */
343 u32 last_comp_version; /* last compatible version */
345 /* version 2 fields below */
346 u32 boot_cpuid_phys; /* Which physical CPU id we're
347 booting on */
348 /* version 3 fields below */
349 u32 size_dt_strings; /* size of the strings block */
351 /* version 17 fields below */
352 u32 size_dt_struct; /* size of the DT structure block */
353 };
355 Along with the constants:
357 /* Definitions used by the flattened device tree */
358 #define OF_DT_HEADER 0xd00dfeed /* 4: version,
359 4: total size */
360 #define OF_DT_BEGIN_NODE 0x1 /* Start node: full name
361 */
362 #define OF_DT_END_NODE 0x2 /* End node */
363 #define OF_DT_PROP 0x3 /* Property: name off,
364 size, content */
365 #define OF_DT_END 0x9
367 All values in this header are in big endian format, the various
368 fields in this header are defined more precisely below. All
369 "offset" values are in bytes from the start of the header; that is
370 from the value of r3.
372 - magic
374 This is a magic value that "marks" the beginning of the
375 device-tree block header. It contains the value 0xd00dfeed and is
376 defined by the constant OF_DT_HEADER
378 - totalsize
380 This is the total size of the DT block including the header. The
381 "DT" block should enclose all data structures defined in this
382 chapter (who are pointed to by offsets in this header). That is,
383 the device-tree structure, strings, and the memory reserve map.
385 - off_dt_struct
387 This is an offset from the beginning of the header to the start
388 of the "structure" part the device tree. (see 2) device tree)
390 - off_dt_strings
392 This is an offset from the beginning of the header to the start
393 of the "strings" part of the device-tree
395 - off_mem_rsvmap
397 This is an offset from the beginning of the header to the start
398 of the reserved memory map. This map is a list of pairs of 64-
399 bit integers. Each pair is a physical address and a size. The
400 list is terminated by an entry of size 0. This map provides the
401 kernel with a list of physical memory areas that are "reserved"
402 and thus not to be used for memory allocations, especially during
403 early initialization. The kernel needs to allocate memory during
404 boot for things like un-flattening the device-tree, allocating an
405 MMU hash table, etc... Those allocations must be done in such a
406 way to avoid overriding critical things like, on Open Firmware
407 capable machines, the RTAS instance, or on some pSeries, the TCE
408 tables used for the iommu. Typically, the reserve map should
409 contain _at least_ this DT block itself (header,total_size). If
410 you are passing an initrd to the kernel, you should reserve it as
411 well. You do not need to reserve the kernel image itself. The map
412 should be 64-bit aligned.
414 - version
416 This is the version of this structure. Version 1 stops
417 here. Version 2 adds an additional field boot_cpuid_phys.
418 Version 3 adds the size of the strings block, allowing the kernel
419 to reallocate it easily at boot and free up the unused flattened
420 structure after expansion. Version 16 introduces a new more
421 "compact" format for the tree itself that is however not backward
422 compatible. Version 17 adds an additional field, size_dt_struct,
423 allowing it to be reallocated or moved more easily (this is
424 particularly useful for bootloaders which need to make
425 adjustments to a device tree based on probed information). You
426 should always generate a structure of the highest version defined
427 at the time of your implementation. Currently that is version 17,
428 unless you explicitly aim at being backward compatible.
430 - last_comp_version
432 Last compatible version. This indicates down to what version of
433 the DT block you are backward compatible. For example, version 2
434 is backward compatible with version 1 (that is, a kernel build
435 for version 1 will be able to boot with a version 2 format). You
436 should put a 1 in this field if you generate a device tree of
437 version 1 to 3, or 16 if you generate a tree of version 16 or 17
438 using the new unit name format.
440 - boot_cpuid_phys
442 This field only exist on version 2 headers. It indicate which
443 physical CPU ID is calling the kernel entry point. This is used,
444 among others, by kexec. If you are on an SMP system, this value
445 should match the content of the "reg" property of the CPU node in
446 the device-tree corresponding to the CPU calling the kernel entry
447 point (see further chapters for more informations on the required
448 device-tree contents)
450 - size_dt_strings
452 This field only exists on version 3 and later headers. It
453 gives the size of the "strings" section of the device tree (which
454 starts at the offset given by off_dt_strings).
456 - size_dt_struct
458 This field only exists on version 17 and later headers. It gives
459 the size of the "structure" section of the device tree (which
460 starts at the offset given by off_dt_struct).
462 So the typical layout of a DT block (though the various parts don't
463 need to be in that order) looks like this (addresses go from top to
464 bottom):
467 ------------------------------
468 r3 -> | struct boot_param_header |
469 ------------------------------
470 | (alignment gap) (*) |
471 ------------------------------
472 | memory reserve map |
473 ------------------------------
474 | (alignment gap) |
475 ------------------------------
476 | |
477 | device-tree structure |
478 | |
479 ------------------------------
480 | (alignment gap) |
481 ------------------------------
482 | |
483 | device-tree strings |
484 | |
485 -----> ------------------------------
486 |
487 |
488 --- (r3 + totalsize)
490 (*) The alignment gaps are not necessarily present; their presence
491 and size are dependent on the various alignment requirements of
492 the individual data blocks.
495 2) Device tree generalities
496 ---------------------------
498 This device-tree itself is separated in two different blocks, a
499 structure block and a strings block. Both need to be aligned to a 4
500 byte boundary.
502 First, let's quickly describe the device-tree concept before detailing
503 the storage format. This chapter does _not_ describe the detail of the
504 required types of nodes & properties for the kernel, this is done
505 later in chapter III.
507 The device-tree layout is strongly inherited from the definition of
508 the Open Firmware IEEE 1275 device-tree. It's basically a tree of
509 nodes, each node having two or more named properties. A property can
510 have a value or not.
512 It is a tree, so each node has one and only one parent except for the
513 root node who has no parent.
515 A node has 2 names. The actual node name is generally contained in a
516 property of type "name" in the node property list whose value is a
517 zero terminated string and is mandatory for version 1 to 3 of the
518 format definition (as it is in Open Firmware). Version 16 makes it
519 optional as it can generate it from the unit name defined below.
521 There is also a "unit name" that is used to differentiate nodes with
522 the same name at the same level, it is usually made of the node
523 names, the "@" sign, and a "unit address", which definition is
524 specific to the bus type the node sits on.
526 The unit name doesn't exist as a property per-se but is included in
527 the device-tree structure. It is typically used to represent "path" in
528 the device-tree. More details about the actual format of these will be
529 below.
531 The kernel powerpc generic code does not make any formal use of the
532 unit address (though some board support code may do) so the only real
533 requirement here for the unit address is to ensure uniqueness of
534 the node unit name at a given level of the tree. Nodes with no notion
535 of address and no possible sibling of the same name (like /memory or
536 /cpus) may omit the unit address in the context of this specification,
537 or use the "@0" default unit address. The unit name is used to define
538 a node "full path", which is the concatenation of all parent node
539 unit names separated with "/".
541 The root node doesn't have a defined name, and isn't required to have
542 a name property either if you are using version 3 or earlier of the
543 format. It also has no unit address (no @ symbol followed by a unit
544 address). The root node unit name is thus an empty string. The full
545 path to the root node is "/".
547 Every node which actually represents an actual device (that is, a node
548 which isn't only a virtual "container" for more nodes, like "/cpus"
549 is) is also required to have a "device_type" property indicating the
550 type of node .
552 Finally, every node that can be referenced from a property in another
553 node is required to have a "linux,phandle" property. Real open
554 firmware implementations provide a unique "phandle" value for every
555 node that the "prom_init()" trampoline code turns into
556 "linux,phandle" properties. However, this is made optional if the
557 flattened device tree is used directly. An example of a node
558 referencing another node via "phandle" is when laying out the
559 interrupt tree which will be described in a further version of this
560 document.
562 This "linux, phandle" property is a 32-bit value that uniquely
563 identifies a node. You are free to use whatever values or system of
564 values, internal pointers, or whatever to generate these, the only
565 requirement is that every node for which you provide that property has
566 a unique value for it.
568 Here is an example of a simple device-tree. In this example, an "o"
569 designates a node followed by the node unit name. Properties are
570 presented with their name followed by their content. "content"
571 represents an ASCII string (zero terminated) value, while <content>
572 represents a 32-bit hexadecimal value. The various nodes in this
573 example will be discussed in a later chapter. At this point, it is
574 only meant to give you a idea of what a device-tree looks like. I have
575 purposefully kept the "name" and "linux,phandle" properties which
576 aren't necessary in order to give you a better idea of what the tree
577 looks like in practice.
579 / o device-tree
580 |- name = "device-tree"
581 |- model = "MyBoardName"
582 |- compatible = "MyBoardFamilyName"
583 |- #address-cells = <2>
584 |- #size-cells = <2>
585 |- linux,phandle = <0>
586 |
587 o cpus
588 | | - name = "cpus"
589 | | - linux,phandle = <1>
590 | | - #address-cells = <1>
591 | | - #size-cells = <0>
592 | |
593 | o PowerPC,970@0
594 | |- name = "PowerPC,970"
595 | |- device_type = "cpu"
596 | |- reg = <0>
597 | |- clock-frequency = <5f5e1000>
598 | |- 64-bit
599 | |- linux,phandle = <2>
600 |
601 o memory@0
602 | |- name = "memory"
603 | |- device_type = "memory"
604 | |- reg = <00000000 00000000 00000000 20000000>
605 | |- linux,phandle = <3>
606 |
607 o chosen
608 |- name = "chosen"
609 |- bootargs = "root=/dev/sda2"
610 |- linux,phandle = <4>
612 This tree is almost a minimal tree. It pretty much contains the
613 minimal set of required nodes and properties to boot a linux kernel;
614 that is, some basic model informations at the root, the CPUs, and the
615 physical memory layout. It also includes misc information passed
616 through /chosen, like in this example, the platform type (mandatory)
617 and the kernel command line arguments (optional).
619 The /cpus/PowerPC,970@0/64-bit property is an example of a
620 property without a value. All other properties have a value. The
621 significance of the #address-cells and #size-cells properties will be
622 explained in chapter IV which defines precisely the required nodes and
623 properties and their content.
626 3) Device tree "structure" block
628 The structure of the device tree is a linearized tree structure. The
629 "OF_DT_BEGIN_NODE" token starts a new node, and the "OF_DT_END_NODE"
630 ends that node definition. Child nodes are simply defined before
631 "OF_DT_END_NODE" (that is nodes within the node). A 'token' is a 32
632 bit value. The tree has to be "finished" with a OF_DT_END token
634 Here's the basic structure of a single node:
636 * token OF_DT_BEGIN_NODE (that is 0x00000001)
637 * for version 1 to 3, this is the node full path as a zero
638 terminated string, starting with "/". For version 16 and later,
639 this is the node unit name only (or an empty string for the
640 root node)
641 * [align gap to next 4 bytes boundary]
642 * for each property:
643 * token OF_DT_PROP (that is 0x00000003)
644 * 32-bit value of property value size in bytes (or 0 if no
645 value)
646 * 32-bit value of offset in string block of property name
647 * property value data if any
648 * [align gap to next 4 bytes boundary]
649 * [child nodes if any]
650 * token OF_DT_END_NODE (that is 0x00000002)
652 So the node content can be summarized as a start token, a full path,
653 a list of properties, a list of child nodes, and an end token. Every
654 child node is a full node structure itself as defined above.
656 NOTE: The above definition requires that all property definitions for
657 a particular node MUST precede any subnode definitions for that node.
658 Although the structure would not be ambiguous if properties and
659 subnodes were intermingled, the kernel parser requires that the
660 properties come first (up until at least 2.6.22). Any tools
661 manipulating a flattened tree must take care to preserve this
662 constraint.
664 4) Device tree "strings" block
666 In order to save space, property names, which are generally redundant,
667 are stored separately in the "strings" block. This block is simply the
668 whole bunch of zero terminated strings for all property names
669 concatenated together. The device-tree property definitions in the
670 structure block will contain offset values from the beginning of the
671 strings block.
674 III - Required content of the device tree
675 =========================================
677 WARNING: All "linux,*" properties defined in this document apply only
678 to a flattened device-tree. If your platform uses a real
679 implementation of Open Firmware or an implementation compatible with
680 the Open Firmware client interface, those properties will be created
681 by the trampoline code in the kernel's prom_init() file. For example,
682 that's where you'll have to add code to detect your board model and
683 set the platform number. However, when using the flattened device-tree
684 entry point, there is no prom_init() pass, and thus you have to
685 provide those properties yourself.
688 1) Note about cells and address representation
689 ----------------------------------------------
691 The general rule is documented in the various Open Firmware
692 documentations. If you choose to describe a bus with the device-tree
693 and there exist an OF bus binding, then you should follow the
694 specification. However, the kernel does not require every single
695 device or bus to be described by the device tree.
697 In general, the format of an address for a device is defined by the
698 parent bus type, based on the #address-cells and #size-cells
699 properties. Note that the parent's parent definitions of #address-cells
700 and #size-cells are not inherited so every node with children must specify
701 them. The kernel requires the root node to have those properties defining
702 addresses format for devices directly mapped on the processor bus.
704 Those 2 properties define 'cells' for representing an address and a
705 size. A "cell" is a 32-bit number. For example, if both contain 2
706 like the example tree given above, then an address and a size are both
707 composed of 2 cells, and each is a 64-bit number (cells are
708 concatenated and expected to be in big endian format). Another example
709 is the way Apple firmware defines them, with 2 cells for an address
710 and one cell for a size. Most 32-bit implementations should define
711 #address-cells and #size-cells to 1, which represents a 32-bit value.
712 Some 32-bit processors allow for physical addresses greater than 32
713 bits; these processors should define #address-cells as 2.
715 "reg" properties are always a tuple of the type "address size" where
716 the number of cells of address and size is specified by the bus
717 #address-cells and #size-cells. When a bus supports various address
718 spaces and other flags relative to a given address allocation (like
719 prefetchable, etc...) those flags are usually added to the top level
720 bits of the physical address. For example, a PCI physical address is
721 made of 3 cells, the bottom two containing the actual address itself
722 while the top cell contains address space indication, flags, and pci
723 bus & device numbers.
725 For busses that support dynamic allocation, it's the accepted practice
726 to then not provide the address in "reg" (keep it 0) though while
727 providing a flag indicating the address is dynamically allocated, and
728 then, to provide a separate "assigned-addresses" property that
729 contains the fully allocated addresses. See the PCI OF bindings for
730 details.
732 In general, a simple bus with no address space bits and no dynamic
733 allocation is preferred if it reflects your hardware, as the existing
734 kernel address parsing functions will work out of the box. If you
735 define a bus type with a more complex address format, including things
736 like address space bits, you'll have to add a bus translator to the
737 prom_parse.c file of the recent kernels for your bus type.
739 The "reg" property only defines addresses and sizes (if #size-cells is
740 non-0) within a given bus. In order to translate addresses upward
741 (that is into parent bus addresses, and possibly into CPU physical
742 addresses), all busses must contain a "ranges" property. If the
743 "ranges" property is missing at a given level, it's assumed that
744 translation isn't possible, i.e., the registers are not visible on the
745 parent bus. The format of the "ranges" property for a bus is a list
746 of:
748 bus address, parent bus address, size
750 "bus address" is in the format of the bus this bus node is defining,
751 that is, for a PCI bridge, it would be a PCI address. Thus, (bus
752 address, size) defines a range of addresses for child devices. "parent
753 bus address" is in the format of the parent bus of this bus. For
754 example, for a PCI host controller, that would be a CPU address. For a
755 PCI<->ISA bridge, that would be a PCI address. It defines the base
756 address in the parent bus where the beginning of that range is mapped.
758 For a new 64-bit powerpc board, I recommend either the 2/2 format or
759 Apple's 2/1 format which is slightly more compact since sizes usually
760 fit in a single 32-bit word. New 32-bit powerpc boards should use a
761 1/1 format, unless the processor supports physical addresses greater
762 than 32-bits, in which case a 2/1 format is recommended.
764 Alternatively, the "ranges" property may be empty, indicating that the
765 registers are visible on the parent bus using an identity mapping
766 translation. In other words, the parent bus address space is the same
767 as the child bus address space.
769 2) Note about "compatible" properties
770 -------------------------------------
772 These properties are optional, but recommended in devices and the root
773 node. The format of a "compatible" property is a list of concatenated
774 zero terminated strings. They allow a device to express its
775 compatibility with a family of similar devices, in some cases,
776 allowing a single driver to match against several devices regardless
777 of their actual names.
779 3) Note about "name" properties
780 -------------------------------
782 While earlier users of Open Firmware like OldWorld macintoshes tended
783 to use the actual device name for the "name" property, it's nowadays
784 considered a good practice to use a name that is closer to the device
785 class (often equal to device_type). For example, nowadays, ethernet
786 controllers are named "ethernet", an additional "model" property
787 defining precisely the chip type/model, and "compatible" property
788 defining the family in case a single driver can driver more than one
789 of these chips. However, the kernel doesn't generally put any
790 restriction on the "name" property; it is simply considered good
791 practice to follow the standard and its evolutions as closely as
792 possible.
794 Note also that the new format version 16 makes the "name" property
795 optional. If it's absent for a node, then the node's unit name is then
796 used to reconstruct the name. That is, the part of the unit name
797 before the "@" sign is used (or the entire unit name if no "@" sign
798 is present).
800 4) Note about node and property names and character set
801 -------------------------------------------------------
803 While open firmware provides more flexible usage of 8859-1, this
804 specification enforces more strict rules. Nodes and properties should
805 be comprised only of ASCII characters 'a' to 'z', '0' to
806 '9', ',', '.', '_', '+', '#', '?', and '-'. Node names additionally
807 allow uppercase characters 'A' to 'Z' (property names should be
808 lowercase. The fact that vendors like Apple don't respect this rule is
809 irrelevant here). Additionally, node and property names should always
810 begin with a character in the range 'a' to 'z' (or 'A' to 'Z' for node
811 names).
813 The maximum number of characters for both nodes and property names
814 is 31. In the case of node names, this is only the leftmost part of
815 a unit name (the pure "name" property), it doesn't include the unit
816 address which can extend beyond that limit.
819 5) Required nodes and properties
820 --------------------------------
821 These are all that are currently required. However, it is strongly
822 recommended that you expose PCI host bridges as documented in the
823 PCI binding to open firmware, and your interrupt tree as documented
824 in OF interrupt tree specification.
826 a) The root node
828 The root node requires some properties to be present:
830 - model : this is your board name/model
831 - #address-cells : address representation for "root" devices
832 - #size-cells: the size representation for "root" devices
833 - device_type : This property shouldn't be necessary. However, if
834 you decide to create a device_type for your root node, make sure it
835 is _not_ "chrp" unless your platform is a pSeries or PAPR compliant
836 one for 64-bit, or a CHRP-type machine for 32-bit as this will
837 matched by the kernel this way.
839 Additionally, some recommended properties are:
841 - compatible : the board "family" generally finds its way here,
842 for example, if you have 2 board models with a similar layout,
843 that typically get driven by the same platform code in the
844 kernel, you would use a different "model" property but put a
845 value in "compatible". The kernel doesn't directly use that
846 value but it is generally useful.
848 The root node is also generally where you add additional properties
849 specific to your board like the serial number if any, that sort of
850 thing. It is recommended that if you add any "custom" property whose
851 name may clash with standard defined ones, you prefix them with your
852 vendor name and a comma.
854 b) The /cpus node
856 This node is the parent of all individual CPU nodes. It doesn't
857 have any specific requirements, though it's generally good practice
858 to have at least:
860 #address-cells = <00000001>
861 #size-cells = <00000000>
863 This defines that the "address" for a CPU is a single cell, and has
864 no meaningful size. This is not necessary but the kernel will assume
865 that format when reading the "reg" properties of a CPU node, see
866 below
868 c) The /cpus/* nodes
870 So under /cpus, you are supposed to create a node for every CPU on
871 the machine. There is no specific restriction on the name of the
872 CPU, though It's common practice to call it PowerPC,<name>. For
873 example, Apple uses PowerPC,G5 while IBM uses PowerPC,970FX.
875 Required properties:
877 - device_type : has to be "cpu"
878 - reg : This is the physical CPU number, it's a single 32-bit cell
879 and is also used as-is as the unit number for constructing the
880 unit name in the full path. For example, with 2 CPUs, you would
881 have the full path:
882 /cpus/PowerPC,970FX@0
883 /cpus/PowerPC,970FX@1
884 (unit addresses do not require leading zeroes)
885 - d-cache-block-size : one cell, L1 data cache block size in bytes (*)
886 - i-cache-block-size : one cell, L1 instruction cache block size in
887 bytes
888 - d-cache-size : one cell, size of L1 data cache in bytes
889 - i-cache-size : one cell, size of L1 instruction cache in bytes
891 (*) The cache "block" size is the size on which the cache management
892 instructions operate. Historically, this document used the cache
893 "line" size here which is incorrect. The kernel will prefer the cache
894 block size and will fallback to cache line size for backward
895 compatibility.
897 Recommended properties:
899 - timebase-frequency : a cell indicating the frequency of the
900 timebase in Hz. This is not directly used by the generic code,
901 but you are welcome to copy/paste the pSeries code for setting
902 the kernel timebase/decrementer calibration based on this
903 value.
904 - clock-frequency : a cell indicating the CPU core clock frequency
905 in Hz. A new property will be defined for 64-bit values, but if
906 your frequency is < 4Ghz, one cell is enough. Here as well as
907 for the above, the common code doesn't use that property, but
908 you are welcome to re-use the pSeries or Maple one. A future
909 kernel version might provide a common function for this.
910 - d-cache-line-size : one cell, L1 data cache line size in bytes
911 if different from the block size
912 - i-cache-line-size : one cell, L1 instruction cache line size in
913 bytes if different from the block size
915 You are welcome to add any property you find relevant to your board,
916 like some information about the mechanism used to soft-reset the
917 CPUs. For example, Apple puts the GPIO number for CPU soft reset
918 lines in there as a "soft-reset" property since they start secondary
919 CPUs by soft-resetting them.
922 d) the /memory node(s)
924 To define the physical memory layout of your board, you should
925 create one or more memory node(s). You can either create a single
926 node with all memory ranges in its reg property, or you can create
927 several nodes, as you wish. The unit address (@ part) used for the
928 full path is the address of the first range of memory defined by a
929 given node. If you use a single memory node, this will typically be
930 @0.
932 Required properties:
934 - device_type : has to be "memory"
935 - reg : This property contains all the physical memory ranges of
936 your board. It's a list of addresses/sizes concatenated
937 together, with the number of cells of each defined by the
938 #address-cells and #size-cells of the root node. For example,
939 with both of these properties being 2 like in the example given
940 earlier, a 970 based machine with 6Gb of RAM could typically
941 have a "reg" property here that looks like:
943 00000000 00000000 00000000 80000000
944 00000001 00000000 00000001 00000000
946 That is a range starting at 0 of 0x80000000 bytes and a range
947 starting at 0x100000000 and of 0x100000000 bytes. You can see
948 that there is no memory covering the IO hole between 2Gb and
949 4Gb. Some vendors prefer splitting those ranges into smaller
950 segments, but the kernel doesn't care.
952 e) The /chosen node
954 This node is a bit "special". Normally, that's where open firmware
955 puts some variable environment information, like the arguments, or
956 the default input/output devices.
958 This specification makes a few of these mandatory, but also defines
959 some linux-specific properties that would be normally constructed by
960 the prom_init() trampoline when booting with an OF client interface,
961 but that you have to provide yourself when using the flattened format.
963 Recommended properties:
965 - bootargs : This zero-terminated string is passed as the kernel
966 command line
967 - linux,stdout-path : This is the full path to your standard
968 console device if any. Typically, if you have serial devices on
969 your board, you may want to put the full path to the one set as
970 the default console in the firmware here, for the kernel to pick
971 it up as its own default console. If you look at the function
972 set_preferred_console() in arch/ppc64/kernel/setup.c, you'll see
973 that the kernel tries to find out the default console and has
974 knowledge of various types like 8250 serial ports. You may want
975 to extend this function to add your own.
977 Note that u-boot creates and fills in the chosen node for platforms
978 that use it.
980 (Note: a practice that is now obsolete was to include a property
981 under /chosen called interrupt-controller which had a phandle value
982 that pointed to the main interrupt controller)
984 f) the /soc<SOCname> node
986 This node is used to represent a system-on-a-chip (SOC) and must be
987 present if the processor is a SOC. The top-level soc node contains
988 information that is global to all devices on the SOC. The node name
989 should contain a unit address for the SOC, which is the base address
990 of the memory-mapped register set for the SOC. The name of an soc
991 node should start with "soc", and the remainder of the name should
992 represent the part number for the soc. For example, the MPC8540's
993 soc node would be called "soc8540".
995 Required properties:
997 - device_type : Should be "soc"
998 - ranges : Should be defined as specified in 1) to describe the
999 translation of SOC addresses for memory mapped SOC registers.
1000 - bus-frequency: Contains the bus frequency for the SOC node.
1001 Typically, the value of this field is filled in by the boot
1002 loader.
1005 Recommended properties:
1007 - reg : This property defines the address and size of the
1008 memory-mapped registers that are used for the SOC node itself.
1009 It does not include the child device registers - these will be
1010 defined inside each child node. The address specified in the
1011 "reg" property should match the unit address of the SOC node.
1012 - #address-cells : Address representation for "soc" devices. The
1013 format of this field may vary depending on whether or not the
1014 device registers are memory mapped. For memory mapped
1015 registers, this field represents the number of cells needed to
1016 represent the address of the registers. For SOCs that do not
1017 use MMIO, a special address format should be defined that
1018 contains enough cells to represent the required information.
1019 See 1) above for more details on defining #address-cells.
1020 - #size-cells : Size representation for "soc" devices
1021 - #interrupt-cells : Defines the width of cells used to represent
1022 interrupts. Typically this value is <2>, which includes a
1023 32-bit number that represents the interrupt number, and a
1024 32-bit number that represents the interrupt sense and level.
1025 This field is only needed if the SOC contains an interrupt
1026 controller.
1028 The SOC node may contain child nodes for each SOC device that the
1029 platform uses. Nodes should not be created for devices which exist
1030 on the SOC but are not used by a particular platform. See chapter VI
1031 for more information on how to specify devices that are part of a SOC.
1033 Example SOC node for the MPC8540:
1035 soc8540@e0000000 {
1036 #address-cells = <1>;
1037 #size-cells = <1>;
1038 #interrupt-cells = <2>;
1039 device_type = "soc";
1040 ranges = <00000000 e0000000 00100000>
1041 reg = <e0000000 00003000>;
1042 bus-frequency = <0>;
1043 }
1047 IV - "dtc", the device tree compiler
1048 ====================================
1051 dtc source code can be found at
1052 <http://ozlabs.org/~dgibson/dtc/dtc.tar.gz>
1054 WARNING: This version is still in early development stage; the
1055 resulting device-tree "blobs" have not yet been validated with the
1056 kernel. The current generated bloc lacks a useful reserve map (it will
1057 be fixed to generate an empty one, it's up to the bootloader to fill
1058 it up) among others. The error handling needs work, bugs are lurking,
1059 etc...
1061 dtc basically takes a device-tree in a given format and outputs a
1062 device-tree in another format. The currently supported formats are:
1064 Input formats:
1065 -------------
1067 - "dtb": "blob" format, that is a flattened device-tree block
1068 with
1069 header all in a binary blob.
1070 - "dts": "source" format. This is a text file containing a
1071 "source" for a device-tree. The format is defined later in this
1072 chapter.
1073 - "fs" format. This is a representation equivalent to the
1074 output of /proc/device-tree, that is nodes are directories and
1075 properties are files
1077 Output formats:
1078 ---------------
1080 - "dtb": "blob" format
1081 - "dts": "source" format
1082 - "asm": assembly language file. This is a file that can be
1083 sourced by gas to generate a device-tree "blob". That file can
1084 then simply be added to your Makefile. Additionally, the
1085 assembly file exports some symbols that can be used.
1088 The syntax of the dtc tool is
1090 dtc [-I <input-format>] [-O <output-format>]
1091 [-o output-filename] [-V output_version] input_filename
1094 The "output_version" defines what version of the "blob" format will be
1095 generated. Supported versions are 1,2,3 and 16. The default is
1096 currently version 3 but that may change in the future to version 16.
1098 Additionally, dtc performs various sanity checks on the tree, like the
1099 uniqueness of linux, phandle properties, validity of strings, etc...
1101 The format of the .dts "source" file is "C" like, supports C and C++
1102 style comments.
1104 / {
1105 }
1107 The above is the "device-tree" definition. It's the only statement
1108 supported currently at the toplevel.
1110 / {
1111 property1 = "string_value"; /* define a property containing a 0
1112 * terminated string
1113 */
1115 property2 = <1234abcd>; /* define a property containing a
1116 * numerical 32-bit value (hexadecimal)
1117 */
1119 property3 = <12345678 12345678 deadbeef>;
1120 /* define a property containing 3
1121 * numerical 32-bit values (cells) in
1122 * hexadecimal
1123 */
1124 property4 = [0a 0b 0c 0d de ea ad be ef];
1125 /* define a property whose content is
1126 * an arbitrary array of bytes
1127 */
1129 childnode@addresss { /* define a child node named "childnode"
1130 * whose unit name is "childnode at
1131 * address"
1132 */
1134 childprop = "hello\n"; /* define a property "childprop" of
1135 * childnode (in this case, a string)
1136 */
1137 };
1138 };
1140 Nodes can contain other nodes etc... thus defining the hierarchical
1141 structure of the tree.
1143 Strings support common escape sequences from C: "\n", "\t", "\r",
1144 "\(octal value)", "\x(hex value)".
1146 It is also suggested that you pipe your source file through cpp (gcc
1147 preprocessor) so you can use #include's, #define for constants, etc...
1149 Finally, various options are planned but not yet implemented, like
1150 automatic generation of phandles, labels (exported to the asm file so
1151 you can point to a property content and change it easily from whatever
1152 you link the device-tree with), label or path instead of numeric value
1153 in some cells to "point" to a node (replaced by a phandle at compile
1154 time), export of reserve map address to the asm file, ability to
1155 specify reserve map content at compile time, etc...
1157 We may provide a .h include file with common definitions of that
1158 proves useful for some properties (like building PCI properties or
1159 interrupt maps) though it may be better to add a notion of struct
1160 definitions to the compiler...
1163 V - Recommendations for a bootloader
1164 ====================================
1167 Here are some various ideas/recommendations that have been proposed
1168 while all this has been defined and implemented.
1170 - The bootloader may want to be able to use the device-tree itself
1171 and may want to manipulate it (to add/edit some properties,
1172 like physical memory size or kernel arguments). At this point, 2
1173 choices can be made. Either the bootloader works directly on the
1174 flattened format, or the bootloader has its own internal tree
1175 representation with pointers (similar to the kernel one) and
1176 re-flattens the tree when booting the kernel. The former is a bit
1177 more difficult to edit/modify, the later requires probably a bit
1178 more code to handle the tree structure. Note that the structure
1179 format has been designed so it's relatively easy to "insert"
1180 properties or nodes or delete them by just memmoving things
1181 around. It contains no internal offsets or pointers for this
1182 purpose.
1184 - An example of code for iterating nodes & retrieving properties
1185 directly from the flattened tree format can be found in the kernel
1186 file arch/ppc64/kernel/prom.c, look at scan_flat_dt() function,
1187 its usage in early_init_devtree(), and the corresponding various
1188 early_init_dt_scan_*() callbacks. That code can be re-used in a
1189 GPL bootloader, and as the author of that code, I would be happy
1190 to discuss possible free licensing to any vendor who wishes to
1191 integrate all or part of this code into a non-GPL bootloader.
1195 VI - System-on-a-chip devices and nodes
1196 =======================================
1198 Many companies are now starting to develop system-on-a-chip
1199 processors, where the processor core (CPU) and many peripheral devices
1200 exist on a single piece of silicon. For these SOCs, an SOC node
1201 should be used that defines child nodes for the devices that make
1202 up the SOC. While platforms are not required to use this model in
1203 order to boot the kernel, it is highly encouraged that all SOC
1204 implementations define as complete a flat-device-tree as possible to
1205 describe the devices on the SOC. This will allow for the
1206 genericization of much of the kernel code.
1209 1) Defining child nodes of an SOC
1210 ---------------------------------
1212 Each device that is part of an SOC may have its own node entry inside
1213 the SOC node. For each device that is included in the SOC, the unit
1214 address property represents the address offset for this device's
1215 memory-mapped registers in the parent's address space. The parent's
1216 address space is defined by the "ranges" property in the top-level soc
1217 node. The "reg" property for each node that exists directly under the
1218 SOC node should contain the address mapping from the child address space
1219 to the parent SOC address space and the size of the device's
1220 memory-mapped register file.
1222 For many devices that may exist inside an SOC, there are predefined
1223 specifications for the format of the device tree node. All SOC child
1224 nodes should follow these specifications, except where noted in this
1225 document.
1227 See appendix A for an example partial SOC node definition for the
1228 MPC8540.
1231 2) Representing devices without a current OF specification
1232 ----------------------------------------------------------
1234 Currently, there are many devices on SOCs that do not have a standard
1235 representation pre-defined as part of the open firmware
1236 specifications, mainly because the boards that contain these SOCs are
1237 not currently booted using open firmware. This section contains
1238 descriptions for the SOC devices for which new nodes have been
1239 defined; this list will expand as more and more SOC-containing
1240 platforms are moved over to use the flattened-device-tree model.
1242 a) PHY nodes
1244 Required properties:
1246 - device_type : Should be "ethernet-phy"
1247 - interrupts : <a b> where a is the interrupt number and b is a
1248 field that represents an encoding of the sense and level
1249 information for the interrupt. This should be encoded based on
1250 the information in section 2) depending on the type of interrupt
1251 controller you have.
1252 - interrupt-parent : the phandle for the interrupt controller that
1253 services interrupts for this device.
1254 - reg : The ID number for the phy, usually a small integer
1255 - linux,phandle : phandle for this node; likely referenced by an
1256 ethernet controller node.
1259 Example:
1261 ethernet-phy@0 {
1262 linux,phandle = <2452000>
1263 interrupt-parent = <40000>;
1264 interrupts = <35 1>;
1265 reg = <0>;
1266 device_type = "ethernet-phy";
1267 };
1270 b) Interrupt controllers
1272 Some SOC devices contain interrupt controllers that are different
1273 from the standard Open PIC specification. The SOC device nodes for
1274 these types of controllers should be specified just like a standard
1275 OpenPIC controller. Sense and level information should be encoded
1276 as specified in section 2) of this chapter for each device that
1277 specifies an interrupt.
1279 Example :
1281 pic@40000 {
1282 linux,phandle = <40000>;
1283 interrupt-controller;
1284 #address-cells = <0>;
1285 reg = <40000 40000>;
1286 compatible = "chrp,open-pic";
1287 device_type = "open-pic";
1288 };
1290 c) CFI or JEDEC memory-mapped NOR flash
1292 Flash chips (Memory Technology Devices) are often used for solid state
1293 file systems on embedded devices.
1295 - compatible : should contain the specific model of flash chip(s)
1296 used, if known, followed by either "cfi-flash" or "jedec-flash"
1297 - reg : Address range of the flash chip
1298 - bank-width : Width (in bytes) of the flash bank. Equal to the
1299 device width times the number of interleaved chips.
1300 - device-width : (optional) Width of a single flash chip. If
1301 omitted, assumed to be equal to 'bank-width'.
1302 - #address-cells, #size-cells : Must be present if the flash has
1303 sub-nodes representing partitions (see below). In this case
1304 both #address-cells and #size-cells must be equal to 1.
1306 For JEDEC compatible devices, the following additional properties
1307 are defined:
1309 - vendor-id : Contains the flash chip's vendor id (1 byte).
1310 - device-id : Contains the flash chip's device id (1 byte).
1312 In addition to the information on the flash bank itself, the
1313 device tree may optionally contain additional information
1314 describing partitions of the flash address space. This can be
1315 used on platforms which have strong conventions about which
1316 portions of the flash are used for what purposes, but which don't
1317 use an on-flash partition table such as RedBoot.
1319 Each partition is represented as a sub-node of the flash device.
1320 Each node's name represents the name of the corresponding
1321 partition of the flash device.
1323 Flash partitions
1324 - reg : The partition's offset and size within the flash bank.
1325 - label : (optional) The label / name for this flash partition.
1326 If omitted, the label is taken from the node name (excluding
1327 the unit address).
1328 - read-only : (optional) This parameter, if present, is a hint to
1329 Linux that this flash partition should only be mounted
1330 read-only. This is usually used for flash partitions
1331 containing early-boot firmware images or data which should not
1332 be clobbered.
1334 Example:
1336 flash@ff000000 {
1337 compatible = "amd,am29lv128ml", "cfi-flash";
1338 reg = <ff000000 01000000>;
1339 bank-width = <4>;
1340 device-width = <1>;
1341 #address-cells = <1>;
1342 #size-cells = <1>;
1343 fs@0 {
1344 label = "fs";
1345 reg = <0 f80000>;
1346 };
1347 firmware@f80000 {
1348 label ="firmware";
1349 reg = <f80000 80000>;
1350 read-only;
1351 };
1352 };
1354 d) 4xx/Axon EMAC ethernet nodes
1356 The EMAC ethernet controller in IBM and AMCC 4xx chips, and also
1357 the Axon bridge. To operate this needs to interact with a ths
1358 special McMAL DMA controller, and sometimes an RGMII or ZMII
1359 interface. In addition to the nodes and properties described
1360 below, the node for the OPB bus on which the EMAC sits must have a
1361 correct clock-frequency property.
1363 i) The EMAC node itself
1365 Required properties:
1366 - device_type : "network"
1368 - compatible : compatible list, contains 2 entries, first is
1369 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
1370 405gp, Axon) and second is either "ibm,emac" or
1371 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
1372 "ibm,emac4"
1373 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
1374 - interrupt-parent : optional, if needed for interrupt mapping
1375 - reg : <registers mapping>
1376 - local-mac-address : 6 bytes, MAC address
1377 - mal-device : phandle of the associated McMAL node
1378 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
1379 with this EMAC
1380 - mal-rx-channel : 1 cell, index of the rx channel on McMAL associated
1381 with this EMAC
1382 - cell-index : 1 cell, hardware index of the EMAC cell on a given
1383 ASIC (typically 0x0 and 0x1 for EMAC0 and EMAC1 on
1384 each Axon chip)
1385 - max-frame-size : 1 cell, maximum frame size supported in bytes
1386 - rx-fifo-size : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec
1387 operations.
1388 For Axon, 2048
1389 - tx-fifo-size : 1 cell, Tx fifo size in bytes for 10 and 100 Mb/sec
1390 operations.
1391 For Axon, 2048.
1392 - fifo-entry-size : 1 cell, size of a fifo entry (used to calculate
1393 thresholds).
1394 For Axon, 0x00000010
1395 - mal-burst-size : 1 cell, MAL burst size (used to calculate thresholds)
1396 in bytes.
1397 For Axon, 0x00000100 (I think ...)
1398 - phy-mode : string, mode of operations of the PHY interface.
1399 Supported values are: "mii", "rmii", "smii", "rgmii",
1400 "tbi", "gmii", rtbi", "sgmii".
1401 For Axon on CAB, it is "rgmii"
1402 - mdio-device : 1 cell, required iff using shared MDIO registers
1403 (440EP). phandle of the EMAC to use to drive the
1404 MDIO lines for the PHY used by this EMAC.
1405 - zmii-device : 1 cell, required iff connected to a ZMII. phandle of
1406 the ZMII device node
1407 - zmii-channel : 1 cell, required iff connected to a ZMII. Which ZMII
1408 channel or 0xffffffff if ZMII is only used for MDIO.
1409 - rgmii-device : 1 cell, required iff connected to an RGMII. phandle
1410 of the RGMII device node.
1411 For Axon: phandle of plb5/plb4/opb/rgmii
1412 - rgmii-channel : 1 cell, required iff connected to an RGMII. Which
1413 RGMII channel is used by this EMAC.
1414 Fox Axon: present, whatever value is appropriate for each
1415 EMAC, that is the content of the current (bogus) "phy-port"
1416 property.
1418 Optional properties:
1419 - phy-address : 1 cell, optional, MDIO address of the PHY. If absent,
1420 a search is performed.
1421 - phy-map : 1 cell, optional, bitmap of addresses to probe the PHY
1422 for, used if phy-address is absent. bit 0x00000001 is
1423 MDIO address 0.
1424 For Axon it can be absent, thouugh my current driver
1425 doesn't handle phy-address yet so for now, keep
1426 0x00ffffff in it.
1427 - rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec
1428 operations (if absent the value is the same as
1429 rx-fifo-size). For Axon, either absent or 2048.
1430 - tx-fifo-size-gige : 1 cell, Tx fifo size in bytes for 1000 Mb/sec
1431 operations (if absent the value is the same as
1432 tx-fifo-size). For Axon, either absent or 2048.
1433 - tah-device : 1 cell, optional. If connected to a TAH engine for
1434 offload, phandle of the TAH device node.
1435 - tah-channel : 1 cell, optional. If appropriate, channel used on the
1436 TAH engine.
1438 Example:
1440 EMAC0: ethernet@40000800 {
1441 device_type = "network";
1442 compatible = "ibm,emac-440gp", "ibm,emac";
1443 interrupt-parent = <&UIC1>;
1444 interrupts = <1c 4 1d 4>;
1445 reg = <40000800 70>;
1446 local-mac-address = [00 04 AC E3 1B 1E];
1447 mal-device = <&MAL0>;
1448 mal-tx-channel = <0 1>;
1449 mal-rx-channel = <0>;
1450 cell-index = <0>;
1451 max-frame-size = <5dc>;
1452 rx-fifo-size = <1000>;
1453 tx-fifo-size = <800>;
1454 phy-mode = "rmii";
1455 phy-map = <00000001>;
1456 zmii-device = <&ZMII0>;
1457 zmii-channel = <0>;
1458 };
1460 ii) McMAL node
1462 Required properties:
1463 - device_type : "dma-controller"
1464 - compatible : compatible list, containing 2 entries, first is
1465 "ibm,mcmal-CHIP" where CHIP is the host ASIC (like
1466 emac) and the second is either "ibm,mcmal" or
1467 "ibm,mcmal2".
1468 For Axon, "ibm,mcmal-axon","ibm,mcmal2"
1469 - interrupts : <interrupt mapping for the MAL interrupts sources:
1470 5 sources: tx_eob, rx_eob, serr, txde, rxde>.
1471 For Axon: This is _different_ from the current
1472 firmware. We use the "delayed" interrupts for txeob
1473 and rxeob. Thus we end up with mapping those 5 MPIC
1474 interrupts, all level positive sensitive: 10, 11, 32,
1475 33, 34 (in decimal)
1476 - dcr-reg : < DCR registers range >
1477 - dcr-parent : if needed for dcr-reg
1478 - num-tx-chans : 1 cell, number of Tx channels
1479 - num-rx-chans : 1 cell, number of Rx channels
1481 iii) ZMII node
1483 Required properties:
1484 - compatible : compatible list, containing 2 entries, first is
1485 "ibm,zmii-CHIP" where CHIP is the host ASIC (like
1486 EMAC) and the second is "ibm,zmii".
1487 For Axon, there is no ZMII node.
1488 - reg : <registers mapping>
1490 iv) RGMII node
1492 Required properties:
1493 - compatible : compatible list, containing 2 entries, first is
1494 "ibm,rgmii-CHIP" where CHIP is the host ASIC (like
1495 EMAC) and the second is "ibm,rgmii".
1496 For Axon, "ibm,rgmii-axon","ibm,rgmii"
1497 - reg : <registers mapping>
1498 - revision : as provided by the RGMII new version register if
1499 available.
1500 For Axon: 0x0000012a
1502 e) Xilinx IP cores
1504 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
1505 in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
1506 of standard device types (network, serial, etc.) and miscellanious
1507 devices (gpio, LCD, spi, etc). Also, since these devices are
1508 implemented within the fpga fabric every instance of the device can be
1509 synthesised with different options that change the behaviour.
1511 Each IP-core has a set of parameters which the FPGA designer can use to
1512 control how the core is synthesized. Historically, the EDK tool would
1513 extract the device parameters relevant to device drivers and copy them
1514 into an 'xparameters.h' in the form of #define symbols. This tells the
1515 device drivers how the IP cores are configured, but it requres the kernel
1516 to be recompiled every time the FPGA bitstream is resynthesized.
1518 The new approach is to export the parameters into the device tree and
1519 generate a new device tree each time the FPGA bitstream changes. The
1520 parameters which used to be exported as #defines will now become
1521 properties of the device node. In general, device nodes for IP-cores
1522 will take the following form:
1524 (name): (generic-name)@(base-address) {
1525 compatible = "xlnx,(ip-core-name)-(HW_VER)"
1526 [, (list of compatible devices), ...];
1527 reg = <(baseaddr) (size)>;
1528 interrupt-parent = <&interrupt-controller-phandle>;
1529 interrupts = < ... >;
1530 xlnx,(parameter1) = "(string-value)";
1531 xlnx,(parameter2) = <(int-value)>;
1532 };
1534 (generic-name): an open firmware-style name that describes the
1535 generic class of device. Preferably, this is one word, such
1536 as 'serial' or 'ethernet'.
1537 (ip-core-name): the name of the ip block (given after the BEGIN
1538 directive in system.mhs). Should be in lowercase
1539 and all underscores '_' converted to dashes '-'.
1540 (name): is derived from the "PARAMETER INSTANCE" value.
1541 (parameter#): C_* parameters from system.mhs. The C_ prefix is
1542 dropped from the parameter name, the name is converted
1543 to lowercase and all underscore '_' characters are
1544 converted to dashes '-'.
1545 (baseaddr): the baseaddr parameter value (often named C_BASEADDR).
1546 (HW_VER): from the HW_VER parameter.
1547 (size): the address range size (often C_HIGHADDR - C_BASEADDR + 1).
1549 Typically, the compatible list will include the exact IP core version
1550 followed by an older IP core version which implements the same
1551 interface or any other device with the same interface.
1553 'reg', 'interrupt-parent' and 'interrupts' are all optional properties.
1555 For example, the following block from system.mhs:
1557 BEGIN opb_uartlite
1558 PARAMETER INSTANCE = opb_uartlite_0
1559 PARAMETER HW_VER = 1.00.b
1560 PARAMETER C_BAUDRATE = 115200
1561 PARAMETER C_DATA_BITS = 8
1562 PARAMETER C_ODD_PARITY = 0
1563 PARAMETER C_USE_PARITY = 0
1564 PARAMETER C_CLK_FREQ = 50000000
1565 PARAMETER C_BASEADDR = 0xEC100000
1566 PARAMETER C_HIGHADDR = 0xEC10FFFF
1567 BUS_INTERFACE SOPB = opb_7
1568 PORT OPB_Clk = CLK_50MHz
1569 PORT Interrupt = opb_uartlite_0_Interrupt
1570 PORT RX = opb_uartlite_0_RX
1571 PORT TX = opb_uartlite_0_TX
1572 PORT OPB_Rst = sys_bus_reset_0
1573 END
1575 becomes the following device tree node:
1577 opb_uartlite_0: serial@ec100000 {
1578 device_type = "serial";
1579 compatible = "xlnx,opb-uartlite-1.00.b";
1580 reg = <ec100000 10000>;
1581 interrupt-parent = <&opb_intc_0>;
1582 interrupts = <1 0>; // got this from the opb_intc parameters
1583 current-speed = <d#115200>; // standard serial device prop
1584 clock-frequency = <d#50000000>; // standard serial device prop
1585 xlnx,data-bits = <8>;
1586 xlnx,odd-parity = <0>;
1587 xlnx,use-parity = <0>;
1588 };
1590 Some IP cores actually implement 2 or more logical devices. In
1591 this case, the device should still describe the whole IP core with
1592 a single node and add a child node for each logical device. The
1593 ranges property can be used to translate from parent IP-core to the
1594 registers of each device. In addition, the parent node should be
1595 compatible with the bus type 'xlnx,compound', and should contain
1596 #address-cells and #size-cells, as with any other bus. (Note: this
1597 makes the assumption that both logical devices have the same bus
1598 binding. If this is not true, then separate nodes should be used
1599 for each logical device). The 'cell-index' property can be used to
1600 enumerate logical devices within an IP core. For example, the
1601 following is the system.mhs entry for the dual ps2 controller found
1602 on the ml403 reference design.
1604 BEGIN opb_ps2_dual_ref
1605 PARAMETER INSTANCE = opb_ps2_dual_ref_0
1606 PARAMETER HW_VER = 1.00.a
1607 PARAMETER C_BASEADDR = 0xA9000000
1608 PARAMETER C_HIGHADDR = 0xA9001FFF
1609 BUS_INTERFACE SOPB = opb_v20_0
1610 PORT Sys_Intr1 = ps2_1_intr
1611 PORT Sys_Intr2 = ps2_2_intr
1612 PORT Clkin1 = ps2_clk_rx_1
1613 PORT Clkin2 = ps2_clk_rx_2
1614 PORT Clkpd1 = ps2_clk_tx_1
1615 PORT Clkpd2 = ps2_clk_tx_2
1616 PORT Rx1 = ps2_d_rx_1
1617 PORT Rx2 = ps2_d_rx_2
1618 PORT Txpd1 = ps2_d_tx_1
1619 PORT Txpd2 = ps2_d_tx_2
1620 END
1622 It would result in the following device tree nodes:
1624 opb_ps2_dual_ref_0: opb-ps2-dual-ref@a9000000 {
1625 #address-cells = <1>;
1626 #size-cells = <1>;
1627 compatible = "xlnx,compound";
1628 ranges = <0 a9000000 2000>;
1629 // If this device had extra parameters, then they would
1630 // go here.
1631 ps2@0 {
1632 compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
1633 reg = <0 40>;
1634 interrupt-parent = <&opb_intc_0>;
1635 interrupts = <3 0>;
1636 cell-index = <0>;
1637 };
1638 ps2@1000 {
1639 compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
1640 reg = <1000 40>;
1641 interrupt-parent = <&opb_intc_0>;
1642 interrupts = <3 0>;
1643 cell-index = <0>;
1644 };
1645 };
1647 Also, the system.mhs file defines bus attachments from the processor
1648 to the devices. The device tree structure should reflect the bus
1649 attachments. Again an example; this system.mhs fragment:
1651 BEGIN ppc405_virtex4
1652 PARAMETER INSTANCE = ppc405_0
1653 PARAMETER HW_VER = 1.01.a
1654 BUS_INTERFACE DPLB = plb_v34_0
1655 BUS_INTERFACE IPLB = plb_v34_0
1656 END
1658 BEGIN opb_intc
1659 PARAMETER INSTANCE = opb_intc_0
1660 PARAMETER HW_VER = 1.00.c
1661 PARAMETER C_BASEADDR = 0xD1000FC0
1662 PARAMETER C_HIGHADDR = 0xD1000FDF
1663 BUS_INTERFACE SOPB = opb_v20_0
1664 END
1666 BEGIN opb_uart16550
1667 PARAMETER INSTANCE = opb_uart16550_0
1668 PARAMETER HW_VER = 1.00.d
1669 PARAMETER C_BASEADDR = 0xa0000000
1670 PARAMETER C_HIGHADDR = 0xa0001FFF
1671 BUS_INTERFACE SOPB = opb_v20_0
1672 END
1674 BEGIN plb_v34
1675 PARAMETER INSTANCE = plb_v34_0
1676 PARAMETER HW_VER = 1.02.a
1677 END
1679 BEGIN plb_bram_if_cntlr
1680 PARAMETER INSTANCE = plb_bram_if_cntlr_0
1681 PARAMETER HW_VER = 1.00.b
1682 PARAMETER C_BASEADDR = 0xFFFF0000
1683 PARAMETER C_HIGHADDR = 0xFFFFFFFF
1684 BUS_INTERFACE SPLB = plb_v34_0
1685 END
1687 BEGIN plb2opb_bridge
1688 PARAMETER INSTANCE = plb2opb_bridge_0
1689 PARAMETER HW_VER = 1.01.a
1690 PARAMETER C_RNG0_BASEADDR = 0x20000000
1691 PARAMETER C_RNG0_HIGHADDR = 0x3FFFFFFF
1692 PARAMETER C_RNG1_BASEADDR = 0x60000000
1693 PARAMETER C_RNG1_HIGHADDR = 0x7FFFFFFF
1694 PARAMETER C_RNG2_BASEADDR = 0x80000000
1695 PARAMETER C_RNG2_HIGHADDR = 0xBFFFFFFF
1696 PARAMETER C_RNG3_BASEADDR = 0xC0000000
1697 PARAMETER C_RNG3_HIGHADDR = 0xDFFFFFFF
1698 BUS_INTERFACE SPLB = plb_v34_0
1699 BUS_INTERFACE MOPB = opb_v20_0
1700 END
1702 Gives this device tree (some properties removed for clarity):
1704 plb@0 {
1705 #address-cells = <1>;
1706 #size-cells = <1>;
1707 compatible = "xlnx,plb-v34-1.02.a";
1708 device_type = "ibm,plb";
1709 ranges; // 1:1 translation
1711 plb_bram_if_cntrl_0: bram@ffff0000 {
1712 reg = <ffff0000 10000>;
1713 }
1715 opb@20000000 {
1716 #address-cells = <1>;
1717 #size-cells = <1>;
1718 ranges = <20000000 20000000 20000000
1719 60000000 60000000 20000000
1720 80000000 80000000 40000000
1721 c0000000 c0000000 20000000>;
1723 opb_uart16550_0: serial@a0000000 {
1724 reg = <a00000000 2000>;
1725 };
1727 opb_intc_0: interrupt-controller@d1000fc0 {
1728 reg = <d1000fc0 20>;
1729 };
1730 };
1731 };
1733 That covers the general approach to binding xilinx IP cores into the
1734 device tree. The following are bindings for specific devices:
1736 i) Xilinx ML300 Framebuffer
1738 Simple framebuffer device from the ML300 reference design (also on the
1739 ML403 reference design as well as others).
1741 Optional properties:
1742 - resolution = <xres yres> : pixel resolution of framebuffer. Some
1743 implementations use a different resolution.
1744 Default is <d#640 d#480>
1745 - virt-resolution = <xvirt yvirt> : Size of framebuffer in memory.
1746 Default is <d#1024 d#480>.
1747 - rotate-display (empty) : rotate display 180 degrees.
1749 ii) Xilinx SystemACE
1751 The Xilinx SystemACE device is used to program FPGAs from an FPGA
1752 bitstream stored on a CF card. It can also be used as a generic CF
1753 interface device.
1755 Optional properties:
1756 - 8-bit (empty) : Set this property for SystemACE in 8 bit mode
1758 iii) Xilinx EMAC and Xilinx TEMAC
1760 Xilinx Ethernet devices. In addition to general xilinx properties
1761 listed above, nodes for these devices should include a phy-handle
1762 property, and may include other common network device properties
1763 like local-mac-address.
1765 iv) Xilinx Uartlite
1767 Xilinx uartlite devices are simple fixed speed serial ports.
1769 Required properties:
1770 - current-speed : Baud rate of uartlite
1772 v) Xilinx hwicap
1774 Xilinx hwicap devices provide access to the configuration logic
1775 of the FPGA through the Internal Configuration Access Port
1776 (ICAP). The ICAP enables partial reconfiguration of the FPGA,
1777 readback of the configuration information, and some control over
1778 'warm boots' of the FPGA fabric.
1780 Required properties:
1781 - xlnx,family : The family of the FPGA, necessary since the
1782 capabilities of the underlying ICAP hardware
1783 differ between different families. May be
1784 'virtex2p', 'virtex4', or 'virtex5'.
1786 vi) Xilinx Uart 16550
1788 Xilinx UART 16550 devices are very similar to the NS16550 but with
1789 different register spacing and an offset from the base address.
1791 Required properties:
1792 - clock-frequency : Frequency of the clock input
1793 - reg-offset : A value of 3 is required
1794 - reg-shift : A value of 2 is required
1796 f) USB EHCI controllers
1798 Required properties:
1799 - compatible : should be "usb-ehci".
1800 - reg : should contain at least address and length of the standard EHCI
1801 register set for the device. Optional platform-dependent registers
1802 (debug-port or other) can be also specified here, but only after
1803 definition of standard EHCI registers.
1804 - interrupts : one EHCI interrupt should be described here.
1805 If device registers are implemented in big endian mode, the device
1806 node should have "big-endian-regs" property.
1807 If controller implementation operates with big endian descriptors,
1808 "big-endian-desc" property should be specified.
1809 If both big endian registers and descriptors are used by the controller
1810 implementation, "big-endian" property can be specified instead of having
1811 both "big-endian-regs" and "big-endian-desc".
1813 Example (Sequoia 440EPx):
1814 ehci@e0000300 {
1815 compatible = "ibm,usb-ehci-440epx", "usb-ehci";
1816 interrupt-parent = <&UIC0>;
1817 interrupts = <1a 4>;
1818 reg = <0 e0000300 90 0 e0000390 70>;
1819 big-endian;
1820 };
1822 g) MDIO on GPIOs
1824 Currently defined compatibles:
1825 - virtual,gpio-mdio
1827 MDC and MDIO lines connected to GPIO controllers are listed in the
1828 gpios property as described in section VIII.1 in the following order:
1830 MDC, MDIO.
1832 Example:
1834 mdio {
1835 compatible = "virtual,mdio-gpio";
1836 #address-cells = <1>;
1837 #size-cells = <0>;
1838 gpios = <&qe_pio_a 11
1839 &qe_pio_c 6>;
1840 };
1842 h) SPI (Serial Peripheral Interface) busses
1844 SPI busses can be described with a node for the SPI master device
1845 and a set of child nodes for each SPI slave on the bus. For this
1846 discussion, it is assumed that the system's SPI controller is in
1847 SPI master mode. This binding does not describe SPI controllers
1848 in slave mode.
1850 The SPI master node requires the following properties:
1851 - #address-cells - number of cells required to define a chip select
1852 address on the SPI bus.
1853 - #size-cells - should be zero.
1854 - compatible - name of SPI bus controller following generic names
1855 recommended practice.
1856 No other properties are required in the SPI bus node. It is assumed
1857 that a driver for an SPI bus device will understand that it is an SPI bus.
1858 However, the binding does not attempt to define the specific method for
1859 assigning chip select numbers. Since SPI chip select configuration is
1860 flexible and non-standardized, it is left out of this binding with the
1861 assumption that board specific platform code will be used to manage
1862 chip selects. Individual drivers can define additional properties to
1863 support describing the chip select layout.
1865 SPI slave nodes must be children of the SPI master node and can
1866 contain the following properties.
1867 - reg - (required) chip select address of device.
1868 - compatible - (required) name of SPI device following generic names
1869 recommended practice
1870 - spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz
1871 - spi-cpol - (optional) Empty property indicating device requires
1872 inverse clock polarity (CPOL) mode
1873 - spi-cpha - (optional) Empty property indicating device requires
1874 shifted clock phase (CPHA) mode
1875 - spi-cs-high - (optional) Empty property indicating device requires
1876 chip select active high
1878 SPI example for an MPC5200 SPI bus:
1879 spi@f00 {
1880 #address-cells = <1>;
1881 #size-cells = <0>;
1882 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
1883 reg = <0xf00 0x20>;
1884 interrupts = <2 13 0 2 14 0>;
1885 interrupt-parent = <&mpc5200_pic>;
1887 ethernet-switch@0 {
1888 compatible = "micrel,ks8995m";
1889 spi-max-frequency = <1000000>;
1890 reg = <0>;
1891 };
1893 codec@1 {
1894 compatible = "ti,tlv320aic26";
1895 spi-max-frequency = <100000>;
1896 reg = <1>;
1897 };
1898 };
1900 VII - Marvell Discovery mv64[345]6x System Controller chips
1901 ===========================================================
1903 The Marvell mv64[345]60 series of system controller chips contain
1904 many of the peripherals needed to implement a complete computer
1905 system. In this section, we define device tree nodes to describe
1906 the system controller chip itself and each of the peripherals
1907 which it contains. Compatible string values for each node are
1908 prefixed with the string "marvell,", for Marvell Technology Group Ltd.
1910 1) The /system-controller node
1912 This node is used to represent the system-controller and must be
1913 present when the system uses a system controller chip. The top-level
1914 system-controller node contains information that is global to all
1915 devices within the system controller chip. The node name begins
1916 with "system-controller" followed by the unit address, which is
1917 the base address of the memory-mapped register set for the system
1918 controller chip.
1920 Required properties:
1922 - ranges : Describes the translation of system controller addresses
1923 for memory mapped registers.
1924 - clock-frequency: Contains the main clock frequency for the system
1925 controller chip.
1926 - reg : This property defines the address and size of the
1927 memory-mapped registers contained within the system controller
1928 chip. The address specified in the "reg" property should match
1929 the unit address of the system-controller node.
1930 - #address-cells : Address representation for system controller
1931 devices. This field represents the number of cells needed to
1932 represent the address of the memory-mapped registers of devices
1933 within the system controller chip.
1934 - #size-cells : Size representation for for the memory-mapped
1935 registers within the system controller chip.
1936 - #interrupt-cells : Defines the width of cells used to represent
1937 interrupts.
1939 Optional properties:
1941 - model : The specific model of the system controller chip. Such
1942 as, "mv64360", "mv64460", or "mv64560".
1943 - compatible : A string identifying the compatibility identifiers
1944 of the system controller chip.
1946 The system-controller node contains child nodes for each system
1947 controller device that the platform uses. Nodes should not be created
1948 for devices which exist on the system controller chip but are not used
1950 Example Marvell Discovery mv64360 system-controller node:
1952 system-controller@f1000000 { /* Marvell Discovery mv64360 */
1953 #address-cells = <1>;
1954 #size-cells = <1>;
1955 model = "mv64360"; /* Default */
1956 compatible = "marvell,mv64360";
1957 clock-frequency = <133333333>;
1958 reg = <0xf1000000 0x10000>;
1959 virtual-reg = <0xf1000000>;
1960 ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */
1961 0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */
1962 0xa0000000 0xa0000000 0x4000000 /* User FLASH */
1963 0x00000000 0xf1000000 0x0010000 /* Bridge's regs */
1964 0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */
1966 [ child node definitions... ]
1967 }
1969 2) Child nodes of /system-controller
1971 a) Marvell Discovery MDIO bus
1973 The MDIO is a bus to which the PHY devices are connected. For each
1974 device that exists on this bus, a child node should be created. See
1975 the definition of the PHY node below for an example of how to define
1976 a PHY.
1978 Required properties:
1979 - #address-cells : Should be <1>
1980 - #size-cells : Should be <0>
1981 - device_type : Should be "mdio"
1982 - compatible : Should be "marvell,mv64360-mdio"
1984 Example:
1986 mdio {
1987 #address-cells = <1>;
1988 #size-cells = <0>;
1989 device_type = "mdio";
1990 compatible = "marvell,mv64360-mdio";
1992 ethernet-phy@0 {
1993 ......
1994 };
1995 };
1998 b) Marvell Discovery ethernet controller
2000 The Discover ethernet controller is described with two levels
2001 of nodes. The first level describes an ethernet silicon block
2002 and the second level describes up to 3 ethernet nodes within
2003 that block. The reason for the multiple levels is that the
2004 registers for the node are interleaved within a single set
2005 of registers. The "ethernet-block" level describes the
2006 shared register set, and the "ethernet" nodes describe ethernet
2007 port-specific properties.
2009 Ethernet block node
2011 Required properties:
2012 - #address-cells : <1>
2013 - #size-cells : <0>
2014 - compatible : "marvell,mv64360-eth-block"
2015 - reg : Offset and length of the register set for this block
2017 Example Discovery Ethernet block node:
2018 ethernet-block@2000 {
2019 #address-cells = <1>;
2020 #size-cells = <0>;
2021 compatible = "marvell,mv64360-eth-block";
2022 reg = <0x2000 0x2000>;
2023 ethernet@0 {
2024 .......
2025 };
2026 };
2028 Ethernet port node
2030 Required properties:
2031 - device_type : Should be "network".
2032 - compatible : Should be "marvell,mv64360-eth".
2033 - reg : Should be <0>, <1>, or <2>, according to which registers
2034 within the silicon block the device uses.
2035 - interrupts : <a> where a is the interrupt number for the port.
2036 - interrupt-parent : the phandle for the interrupt controller
2037 that services interrupts for this device.
2038 - phy : the phandle for the PHY connected to this ethernet
2039 controller.
2040 - local-mac-address : 6 bytes, MAC address
2042 Example Discovery Ethernet port node:
2043 ethernet@0 {
2044 device_type = "network";
2045 compatible = "marvell,mv64360-eth";
2046 reg = <0>;
2047 interrupts = <32>;
2048 interrupt-parent = <&PIC>;
2049 phy = <&PHY0>;
2050 local-mac-address = [ 00 00 00 00 00 00 ];
2051 };
2055 c) Marvell Discovery PHY nodes
2057 Required properties:
2058 - device_type : Should be "ethernet-phy"
2059 - interrupts : <a> where a is the interrupt number for this phy.
2060 - interrupt-parent : the phandle for the interrupt controller that
2061 services interrupts for this device.
2062 - reg : The ID number for the phy, usually a small integer
2064 Example Discovery PHY node:
2065 ethernet-phy@1 {
2066 device_type = "ethernet-phy";
2067 compatible = "broadcom,bcm5421";
2068 interrupts = <76>; /* GPP 12 */
2069 interrupt-parent = <&PIC>;
2070 reg = <1>;
2071 };
2074 d) Marvell Discovery SDMA nodes
2076 Represent DMA hardware associated with the MPSC (multiprotocol
2077 serial controllers).
2079 Required properties:
2080 - compatible : "marvell,mv64360-sdma"
2081 - reg : Offset and length of the register set for this device
2082 - interrupts : <a> where a is the interrupt number for the DMA
2083 device.
2084 - interrupt-parent : the phandle for the interrupt controller
2085 that services interrupts for this device.
2087 Example Discovery SDMA node:
2088 sdma@4000 {
2089 compatible = "marvell,mv64360-sdma";
2090 reg = <0x4000 0xc18>;
2091 virtual-reg = <0xf1004000>;
2092 interrupts = <36>;
2093 interrupt-parent = <&PIC>;
2094 };
2097 e) Marvell Discovery BRG nodes
2099 Represent baud rate generator hardware associated with the MPSC
2100 (multiprotocol serial controllers).
2102 Required properties:
2103 - compatible : "marvell,mv64360-brg"
2104 - reg : Offset and length of the register set for this device
2105 - clock-src : A value from 0 to 15 which selects the clock
2106 source for the baud rate generator. This value corresponds
2107 to the CLKS value in the BRGx configuration register. See
2108 the mv64x60 User's Manual.
2109 - clock-frequence : The frequency (in Hz) of the baud rate
2110 generator's input clock.
2111 - current-speed : The current speed setting (presumably by
2112 firmware) of the baud rate generator.
2114 Example Discovery BRG node:
2115 brg@b200 {
2116 compatible = "marvell,mv64360-brg";
2117 reg = <0xb200 0x8>;
2118 clock-src = <8>;
2119 clock-frequency = <133333333>;
2120 current-speed = <9600>;
2121 };
2124 f) Marvell Discovery CUNIT nodes
2126 Represent the Serial Communications Unit device hardware.
2128 Required properties:
2129 - reg : Offset and length of the register set for this device
2131 Example Discovery CUNIT node:
2132 cunit@f200 {
2133 reg = <0xf200 0x200>;
2134 };
2137 g) Marvell Discovery MPSCROUTING nodes
2139 Represent the Discovery's MPSC routing hardware
2141 Required properties:
2142 - reg : Offset and length of the register set for this device
2144 Example Discovery CUNIT node:
2145 mpscrouting@b500 {
2146 reg = <0xb400 0xc>;
2147 };
2150 h) Marvell Discovery MPSCINTR nodes
2152 Represent the Discovery's MPSC DMA interrupt hardware registers
2153 (SDMA cause and mask registers).
2155 Required properties:
2156 - reg : Offset and length of the register set for this device
2158 Example Discovery MPSCINTR node:
2159 mpsintr@b800 {
2160 reg = <0xb800 0x100>;
2161 };
2164 i) Marvell Discovery MPSC nodes
2166 Represent the Discovery's MPSC (Multiprotocol Serial Controller)
2167 serial port.
2169 Required properties:
2170 - device_type : "serial"
2171 - compatible : "marvell,mv64360-mpsc"
2172 - reg : Offset and length of the register set for this device
2173 - sdma : the phandle for the SDMA node used by this port
2174 - brg : the phandle for the BRG node used by this port
2175 - cunit : the phandle for the CUNIT node used by this port
2176 - mpscrouting : the phandle for the MPSCROUTING node used by this port
2177 - mpscintr : the phandle for the MPSCINTR node used by this port
2178 - cell-index : the hardware index of this cell in the MPSC core
2179 - max_idle : value needed for MPSC CHR3 (Maximum Frame Length)
2180 register
2181 - interrupts : <a> where a is the interrupt number for the MPSC.
2182 - interrupt-parent : the phandle for the interrupt controller
2183 that services interrupts for this device.
2185 Example Discovery MPSCINTR node:
2186 mpsc@8000 {
2187 device_type = "serial";
2188 compatible = "marvell,mv64360-mpsc";
2189 reg = <0x8000 0x38>;
2190 virtual-reg = <0xf1008000>;
2191 sdma = <&SDMA0>;
2192 brg = <&BRG0>;
2193 cunit = <&CUNIT>;
2194 mpscrouting = <&MPSCROUTING>;
2195 mpscintr = <&MPSCINTR>;
2196 cell-index = <0>;
2197 max_idle = <40>;
2198 interrupts = <40>;
2199 interrupt-parent = <&PIC>;
2200 };
2203 j) Marvell Discovery Watch Dog Timer nodes
2205 Represent the Discovery's watchdog timer hardware
2207 Required properties:
2208 - compatible : "marvell,mv64360-wdt"
2209 - reg : Offset and length of the register set for this device
2211 Example Discovery Watch Dog Timer node:
2212 wdt@b410 {
2213 compatible = "marvell,mv64360-wdt";
2214 reg = <0xb410 0x8>;
2215 };
2218 k) Marvell Discovery I2C nodes
2220 Represent the Discovery's I2C hardware
2222 Required properties:
2223 - device_type : "i2c"
2224 - compatible : "marvell,mv64360-i2c"
2225 - reg : Offset and length of the register set for this device
2226 - interrupts : <a> where a is the interrupt number for the I2C.
2227 - interrupt-parent : the phandle for the interrupt controller
2228 that services interrupts for this device.
2230 Example Discovery I2C node:
2231 compatible = "marvell,mv64360-i2c";
2232 reg = <0xc000 0x20>;
2233 virtual-reg = <0xf100c000>;
2234 interrupts = <37>;
2235 interrupt-parent = <&PIC>;
2236 };
2239 l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes
2241 Represent the Discovery's PIC hardware
2243 Required properties:
2244 - #interrupt-cells : <1>
2245 - #address-cells : <0>
2246 - compatible : "marvell,mv64360-pic"
2247 - reg : Offset and length of the register set for this device
2248 - interrupt-controller
2250 Example Discovery PIC node:
2251 pic {
2252 #interrupt-cells = <1>;
2253 #address-cells = <0>;
2254 compatible = "marvell,mv64360-pic";
2255 reg = <0x0 0x88>;
2256 interrupt-controller;
2257 };
2260 m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes
2262 Represent the Discovery's MPP hardware
2264 Required properties:
2265 - compatible : "marvell,mv64360-mpp"
2266 - reg : Offset and length of the register set for this device
2268 Example Discovery MPP node:
2269 mpp@f000 {
2270 compatible = "marvell,mv64360-mpp";
2271 reg = <0xf000 0x10>;
2272 };
2275 n) Marvell Discovery GPP (General Purpose Pins) nodes
2277 Represent the Discovery's GPP hardware
2279 Required properties:
2280 - compatible : "marvell,mv64360-gpp"
2281 - reg : Offset and length of the register set for this device
2283 Example Discovery GPP node:
2284 gpp@f000 {
2285 compatible = "marvell,mv64360-gpp";
2286 reg = <0xf100 0x20>;
2287 };
2290 o) Marvell Discovery PCI host bridge node
2292 Represents the Discovery's PCI host bridge device. The properties
2293 for this node conform to Rev 2.1 of the PCI Bus Binding to IEEE
2294 1275-1994. A typical value for the compatible property is
2295 "marvell,mv64360-pci".
2297 Example Discovery PCI host bridge node
2298 pci@80000000 {
2299 #address-cells = <3>;
2300 #size-cells = <2>;
2301 #interrupt-cells = <1>;
2302 device_type = "pci";
2303 compatible = "marvell,mv64360-pci";
2304 reg = <0xcf8 0x8>;
2305 ranges = <0x01000000 0x0 0x0
2306 0x88000000 0x0 0x01000000
2307 0x02000000 0x0 0x80000000
2308 0x80000000 0x0 0x08000000>;
2309 bus-range = <0 255>;
2310 clock-frequency = <66000000>;
2311 interrupt-parent = <&PIC>;
2312 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
2313 interrupt-map = <
2314 /* IDSEL 0x0a */
2315 0x5000 0 0 1 &PIC 80
2316 0x5000 0 0 2 &PIC 81
2317 0x5000 0 0 3 &PIC 91
2318 0x5000 0 0 4 &PIC 93
2320 /* IDSEL 0x0b */
2321 0x5800 0 0 1 &PIC 91
2322 0x5800 0 0 2 &PIC 93
2323 0x5800 0 0 3 &PIC 80
2324 0x5800 0 0 4 &PIC 81
2326 /* IDSEL 0x0c */
2327 0x6000 0 0 1 &PIC 91
2328 0x6000 0 0 2 &PIC 93
2329 0x6000 0 0 3 &PIC 80
2330 0x6000 0 0 4 &PIC 81
2332 /* IDSEL 0x0d */
2333 0x6800 0 0 1 &PIC 93
2334 0x6800 0 0 2 &PIC 80
2335 0x6800 0 0 3 &PIC 81
2336 0x6800 0 0 4 &PIC 91
2337 >;
2338 };
2341 p) Marvell Discovery CPU Error nodes
2343 Represent the Discovery's CPU error handler device.
2345 Required properties:
2346 - compatible : "marvell,mv64360-cpu-error"
2347 - reg : Offset and length of the register set for this device
2348 - interrupts : the interrupt number for this device
2349 - interrupt-parent : the phandle for the interrupt controller
2350 that services interrupts for this device.
2352 Example Discovery CPU Error node:
2353 cpu-error@0070 {
2354 compatible = "marvell,mv64360-cpu-error";
2355 reg = <0x70 0x10 0x128 0x28>;
2356 interrupts = <3>;
2357 interrupt-parent = <&PIC>;
2358 };
2361 q) Marvell Discovery SRAM Controller nodes
2363 Represent the Discovery's SRAM controller device.
2365 Required properties:
2366 - compatible : "marvell,mv64360-sram-ctrl"
2367 - reg : Offset and length of the register set for this device
2368 - interrupts : the interrupt number for this device
2369 - interrupt-parent : the phandle for the interrupt controller
2370 that services interrupts for this device.
2372 Example Discovery SRAM Controller node:
2373 sram-ctrl@0380 {
2374 compatible = "marvell,mv64360-sram-ctrl";
2375 reg = <0x380 0x80>;
2376 interrupts = <13>;
2377 interrupt-parent = <&PIC>;
2378 };
2381 r) Marvell Discovery PCI Error Handler nodes
2383 Represent the Discovery's PCI error handler device.
2385 Required properties:
2386 - compatible : "marvell,mv64360-pci-error"
2387 - reg : Offset and length of the register set for this device
2388 - interrupts : the interrupt number for this device
2389 - interrupt-parent : the phandle for the interrupt controller
2390 that services interrupts for this device.
2392 Example Discovery PCI Error Handler node:
2393 pci-error@1d40 {
2394 compatible = "marvell,mv64360-pci-error";
2395 reg = <0x1d40 0x40 0xc28 0x4>;
2396 interrupts = <12>;
2397 interrupt-parent = <&PIC>;
2398 };
2401 s) Marvell Discovery Memory Controller nodes
2403 Represent the Discovery's memory controller device.
2405 Required properties:
2406 - compatible : "marvell,mv64360-mem-ctrl"
2407 - reg : Offset and length of the register set for this device
2408 - interrupts : the interrupt number for this device
2409 - interrupt-parent : the phandle for the interrupt controller
2410 that services interrupts for this device.
2412 Example Discovery Memory Controller node:
2413 mem-ctrl@1400 {
2414 compatible = "marvell,mv64360-mem-ctrl";
2415 reg = <0x1400 0x60>;
2416 interrupts = <17>;
2417 interrupt-parent = <&PIC>;
2418 };
2421 VIII - Specifying interrupt information for devices
2422 ===================================================
2424 The device tree represents the busses and devices of a hardware
2425 system in a form similar to the physical bus topology of the
2426 hardware.
2428 In addition, a logical 'interrupt tree' exists which represents the
2429 hierarchy and routing of interrupts in the hardware.
2431 The interrupt tree model is fully described in the
2432 document "Open Firmware Recommended Practice: Interrupt
2433 Mapping Version 0.9". The document is available at:
2434 <http://playground.sun.com/1275/practice>.
2436 1) interrupts property
2437 ----------------------
2439 Devices that generate interrupts to a single interrupt controller
2440 should use the conventional OF representation described in the
2441 OF interrupt mapping documentation.
2443 Each device which generates interrupts must have an 'interrupt'
2444 property. The interrupt property value is an arbitrary number of
2445 of 'interrupt specifier' values which describe the interrupt or
2446 interrupts for the device.
2448 The encoding of an interrupt specifier is determined by the
2449 interrupt domain in which the device is located in the
2450 interrupt tree. The root of an interrupt domain specifies in
2451 its #interrupt-cells property the number of 32-bit cells
2452 required to encode an interrupt specifier. See the OF interrupt
2453 mapping documentation for a detailed description of domains.
2455 For example, the binding for the OpenPIC interrupt controller
2456 specifies an #interrupt-cells value of 2 to encode the interrupt
2457 number and level/sense information. All interrupt children in an
2458 OpenPIC interrupt domain use 2 cells per interrupt in their interrupts
2459 property.
2461 The PCI bus binding specifies a #interrupt-cell value of 1 to encode
2462 which interrupt pin (INTA,INTB,INTC,INTD) is used.
2464 2) interrupt-parent property
2465 ----------------------------
2467 The interrupt-parent property is specified to define an explicit
2468 link between a device node and its interrupt parent in
2469 the interrupt tree. The value of interrupt-parent is the
2470 phandle of the parent node.
2472 If the interrupt-parent property is not defined for a node, it's
2473 interrupt parent is assumed to be an ancestor in the node's
2474 _device tree_ hierarchy.
2476 3) OpenPIC Interrupt Controllers
2477 --------------------------------
2479 OpenPIC interrupt controllers require 2 cells to encode
2480 interrupt information. The first cell defines the interrupt
2481 number. The second cell defines the sense and level
2482 information.
2484 Sense and level information should be encoded as follows:
2486 0 = low to high edge sensitive type enabled
2487 1 = active low level sensitive type enabled
2488 2 = active high level sensitive type enabled
2489 3 = high to low edge sensitive type enabled
2491 4) ISA Interrupt Controllers
2492 ----------------------------
2494 ISA PIC interrupt controllers require 2 cells to encode
2495 interrupt information. The first cell defines the interrupt
2496 number. The second cell defines the sense and level
2497 information.
2499 ISA PIC interrupt controllers should adhere to the ISA PIC
2500 encodings listed below:
2502 0 = active low level sensitive type enabled
2503 1 = active high level sensitive type enabled
2504 2 = high to low edge sensitive type enabled
2505 3 = low to high edge sensitive type enabled
2507 IX - Specifying GPIO information for devices
2508 ============================================
2510 1) gpios property
2511 -----------------
2513 Nodes that makes use of GPIOs should define them using `gpios' property,
2514 format of which is: <&gpio-controller1-phandle gpio1-specifier
2515 &gpio-controller2-phandle gpio2-specifier
2516 0 /* holes are permitted, means no GPIO 3 */
2517 &gpio-controller4-phandle gpio4-specifier
2518 ...>;
2520 Note that gpio-specifier length is controller dependent.
2522 gpio-specifier may encode: bank, pin position inside the bank,
2523 whether pin is open-drain and whether pin is logically inverted.
2525 Example of the node using GPIOs:
2527 node {
2528 gpios = <&qe_pio_e 18 0>;
2529 };
2531 In this example gpio-specifier is "18 0" and encodes GPIO pin number,
2532 and empty GPIO flags as accepted by the "qe_pio_e" gpio-controller.
2534 2) gpio-controller nodes
2535 ------------------------
2537 Every GPIO controller node must have #gpio-cells property defined,
2538 this information will be used to translate gpio-specifiers.
2540 Example of two SOC GPIO banks defined as gpio-controller nodes:
2542 qe_pio_a: gpio-controller@1400 {
2543 #gpio-cells = <2>;
2544 compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank";
2545 reg = <0x1400 0x18>;
2546 gpio-controller;
2547 };
2549 qe_pio_e: gpio-controller@1460 {
2550 #gpio-cells = <2>;
2551 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
2552 reg = <0x1460 0x18>;
2553 gpio-controller;
2554 };
2556 X - Specifying Device Power Management Information (sleep property)
2557 ===================================================================
2559 Devices on SOCs often have mechanisms for placing devices into low-power
2560 states that are decoupled from the devices' own register blocks. Sometimes,
2561 this information is more complicated than a cell-index property can
2562 reasonably describe. Thus, each device controlled in such a manner
2563 may contain a "sleep" property which describes these connections.
2565 The sleep property consists of one or more sleep resources, each of
2566 which consists of a phandle to a sleep controller, followed by a
2567 controller-specific sleep specifier of zero or more cells.
2569 The semantics of what type of low power modes are possible are defined
2570 by the sleep controller. Some examples of the types of low power modes
2571 that may be supported are:
2573 - Dynamic: The device may be disabled or enabled at any time.
2574 - System Suspend: The device may request to be disabled or remain
2575 awake during system suspend, but will not be disabled until then.
2576 - Permanent: The device is disabled permanently (until the next hard
2577 reset).
2579 Some devices may share a clock domain with each other, such that they should
2580 only be suspended when none of the devices are in use. Where reasonable,
2581 such nodes should be placed on a virtual bus, where the bus has the sleep
2582 property. If the clock domain is shared among devices that cannot be
2583 reasonably grouped in this manner, then create a virtual sleep controller
2584 (similar to an interrupt nexus, except that defining a standardized
2585 sleep-map should wait until its necessity is demonstrated).
2587 Appendix A - Sample SOC node for MPC8540
2588 ========================================
2590 soc@e0000000 {
2591 #address-cells = <1>;
2592 #size-cells = <1>;
2593 compatible = "fsl,mpc8540-ccsr", "simple-bus";
2594 device_type = "soc";
2595 ranges = <0x00000000 0xe0000000 0x00100000>
2596 bus-frequency = <0>;
2597 interrupt-parent = <&pic>;
2599 ethernet@24000 {
2600 #address-cells = <1>;
2601 #size-cells = <1>;
2602 device_type = "network";
2603 model = "TSEC";
2604 compatible = "gianfar", "simple-bus";
2605 reg = <0x24000 0x1000>;
2606 local-mac-address = [ 00 E0 0C 00 73 00 ];
2607 interrupts = <29 2 30 2 34 2>;
2608 phy-handle = <&phy0>;
2609 sleep = <&pmc 00000080>;
2610 ranges;
2612 mdio@24520 {
2613 reg = <0x24520 0x20>;
2614 compatible = "fsl,gianfar-mdio";
2616 phy0: ethernet-phy@0 {
2617 interrupts = <5 1>;
2618 reg = <0>;
2619 device_type = "ethernet-phy";
2620 };
2622 phy1: ethernet-phy@1 {
2623 interrupts = <5 1>;
2624 reg = <1>;
2625 device_type = "ethernet-phy";
2626 };
2628 phy3: ethernet-phy@3 {
2629 interrupts = <7 1>;
2630 reg = <3>;
2631 device_type = "ethernet-phy";
2632 };
2633 };
2634 };
2636 ethernet@25000 {
2637 device_type = "network";
2638 model = "TSEC";
2639 compatible = "gianfar";
2640 reg = <0x25000 0x1000>;
2641 local-mac-address = [ 00 E0 0C 00 73 01 ];
2642 interrupts = <13 2 14 2 18 2>;
2643 phy-handle = <&phy1>;
2644 sleep = <&pmc 00000040>;
2645 };
2647 ethernet@26000 {
2648 device_type = "network";
2649 model = "FEC";
2650 compatible = "gianfar";
2651 reg = <0x26000 0x1000>;
2652 local-mac-address = [ 00 E0 0C 00 73 02 ];
2653 interrupts = <41 2>;
2654 phy-handle = <&phy3>;
2655 sleep = <&pmc 00000020>;
2656 };
2658 serial@4500 {
2659 #address-cells = <1>;
2660 #size-cells = <1>;
2661 compatible = "fsl,mpc8540-duart", "simple-bus";
2662 sleep = <&pmc 00000002>;
2663 ranges;
2665 serial@4500 {
2666 device_type = "serial";
2667 compatible = "ns16550";
2668 reg = <0x4500 0x100>;
2669 clock-frequency = <0>;
2670 interrupts = <42 2>;
2671 };
2673 serial@4600 {
2674 device_type = "serial";
2675 compatible = "ns16550";
2676 reg = <0x4600 0x100>;
2677 clock-frequency = <0>;
2678 interrupts = <42 2>;
2679 };
2680 };
2682 pic: pic@40000 {
2683 interrupt-controller;
2684 #address-cells = <0>;
2685 #interrupt-cells = <2>;
2686 reg = <0x40000 0x40000>;
2687 compatible = "chrp,open-pic";
2688 device_type = "open-pic";
2689 };
2691 i2c@3000 {
2692 interrupts = <43 2>;
2693 reg = <0x3000 0x100>;
2694 compatible = "fsl-i2c";
2695 dfsrr;
2696 sleep = <&pmc 00000004>;
2697 };
2699 pmc: power@e0070 {
2700 compatible = "fsl,mpc8540-pmc", "fsl,mpc8548-pmc";
2701 reg = <0xe0070 0x20>;
2702 };
2703 };