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Merge git://git.kernel.org/pub/scm/linux/kernel/git/sam/kbuild-fixes
[linux-2.6/mini2440.git] / drivers / net / tg3.c
blob26aa37aa531f9d851716074f64cf0976e9f3f590
1 /*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2007 Broadcom Corporation.
8 *
9 * Firmware is:
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
16 */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
38 #include <linux/ip.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43
44 #include <net/checksum.h>
45 #include <net/ip.h>
46
47 #include <asm/system.h>
48 #include <asm/io.h>
49 #include <asm/byteorder.h>
50 #include <asm/uaccess.h>
51
52 #ifdef CONFIG_SPARC
53 #include <asm/idprom.h>
54 #include <asm/prom.h>
55 #endif
56
57 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
58 #define TG3_VLAN_TAG_USED 1
59 #else
60 #define TG3_VLAN_TAG_USED 0
61 #endif
62
63 #define TG3_TSO_SUPPORT 1
64
65 #include "tg3.h"
66
67 #define DRV_MODULE_NAME "tg3"
68 #define PFX DRV_MODULE_NAME ": "
69 #define DRV_MODULE_VERSION "3.93"
70 #define DRV_MODULE_RELDATE "May 22, 2008"
71
72 #define TG3_DEF_MAC_MODE 0
73 #define TG3_DEF_RX_MODE 0
74 #define TG3_DEF_TX_MODE 0
75 #define TG3_DEF_MSG_ENABLE \
76 (NETIF_MSG_DRV | \
77 NETIF_MSG_PROBE | \
78 NETIF_MSG_LINK | \
79 NETIF_MSG_TIMER | \
80 NETIF_MSG_IFDOWN | \
81 NETIF_MSG_IFUP | \
82 NETIF_MSG_RX_ERR | \
83 NETIF_MSG_TX_ERR)
84
85 /* length of time before we decide the hardware is borked,
86 * and dev->tx_timeout() should be called to fix the problem
87 */
88 #define TG3_TX_TIMEOUT (5 * HZ)
89
90 /* hardware minimum and maximum for a single frame's data payload */
91 #define TG3_MIN_MTU 60
92 #define TG3_MAX_MTU(tp) \
93 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
94
95 /* These numbers seem to be hard coded in the NIC firmware somehow.
96 * You can't change the ring sizes, but you can change where you place
97 * them in the NIC onboard memory.
98 */
99 #define TG3_RX_RING_SIZE 512
100 #define TG3_DEF_RX_RING_PENDING 200
101 #define TG3_RX_JUMBO_RING_SIZE 256
102 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
103
104 /* Do not place this n-ring entries value into the tp struct itself,
105 * we really want to expose these constants to GCC so that modulo et
106 * al. operations are done with shifts and masks instead of with
107 * hw multiply/modulo instructions. Another solution would be to
108 * replace things like '% foo' with '& (foo - 1)'.
109 */
110 #define TG3_RX_RCB_RING_SIZE(tp) \
111 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
112
113 #define TG3_TX_RING_SIZE 512
114 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
115
116 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
117 TG3_RX_RING_SIZE)
118 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_JUMBO_RING_SIZE)
120 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_RCB_RING_SIZE(tp))
122 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
123 TG3_TX_RING_SIZE)
124 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
125
126 #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
127 #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
128
129 /* minimum number of free TX descriptors required to wake up TX process */
130 #define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
131
132 /* number of ETHTOOL_GSTATS u64's */
133 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
134
135 #define TG3_NUM_TEST 6
136
137 static char version[] __devinitdata =
138 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
139
140 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
141 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
142 MODULE_LICENSE("GPL");
143 MODULE_VERSION(DRV_MODULE_VERSION);
144
145 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
146 module_param(tg3_debug, int, 0);
147 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
148
149 static struct pci_device_id tg3_pci_tbl[] = {
150 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
151 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
152 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
153 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
154 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
155 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
156 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
157 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
158 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
159 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
160 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
161 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
209 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
210 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
211 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
212 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
213 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
214 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
215 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
216 {}
217 };
218
219 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
220
221 static const struct {
222 const char string[ETH_GSTRING_LEN];
223 } ethtool_stats_keys[TG3_NUM_STATS] = {
224 { "rx_octets" },
225 { "rx_fragments" },
226 { "rx_ucast_packets" },
227 { "rx_mcast_packets" },
228 { "rx_bcast_packets" },
229 { "rx_fcs_errors" },
230 { "rx_align_errors" },
231 { "rx_xon_pause_rcvd" },
232 { "rx_xoff_pause_rcvd" },
233 { "rx_mac_ctrl_rcvd" },
234 { "rx_xoff_entered" },
235 { "rx_frame_too_long_errors" },
236 { "rx_jabbers" },
237 { "rx_undersize_packets" },
238 { "rx_in_length_errors" },
239 { "rx_out_length_errors" },
240 { "rx_64_or_less_octet_packets" },
241 { "rx_65_to_127_octet_packets" },
242 { "rx_128_to_255_octet_packets" },
243 { "rx_256_to_511_octet_packets" },
244 { "rx_512_to_1023_octet_packets" },
245 { "rx_1024_to_1522_octet_packets" },
246 { "rx_1523_to_2047_octet_packets" },
247 { "rx_2048_to_4095_octet_packets" },
248 { "rx_4096_to_8191_octet_packets" },
249 { "rx_8192_to_9022_octet_packets" },
250
251 { "tx_octets" },
252 { "tx_collisions" },
253
254 { "tx_xon_sent" },
255 { "tx_xoff_sent" },
256 { "tx_flow_control" },
257 { "tx_mac_errors" },
258 { "tx_single_collisions" },
259 { "tx_mult_collisions" },
260 { "tx_deferred" },
261 { "tx_excessive_collisions" },
262 { "tx_late_collisions" },
263 { "tx_collide_2times" },
264 { "tx_collide_3times" },
265 { "tx_collide_4times" },
266 { "tx_collide_5times" },
267 { "tx_collide_6times" },
268 { "tx_collide_7times" },
269 { "tx_collide_8times" },
270 { "tx_collide_9times" },
271 { "tx_collide_10times" },
272 { "tx_collide_11times" },
273 { "tx_collide_12times" },
274 { "tx_collide_13times" },
275 { "tx_collide_14times" },
276 { "tx_collide_15times" },
277 { "tx_ucast_packets" },
278 { "tx_mcast_packets" },
279 { "tx_bcast_packets" },
280 { "tx_carrier_sense_errors" },
281 { "tx_discards" },
282 { "tx_errors" },
283
284 { "dma_writeq_full" },
285 { "dma_write_prioq_full" },
286 { "rxbds_empty" },
287 { "rx_discards" },
288 { "rx_errors" },
289 { "rx_threshold_hit" },
290
291 { "dma_readq_full" },
292 { "dma_read_prioq_full" },
293 { "tx_comp_queue_full" },
294
295 { "ring_set_send_prod_index" },
296 { "ring_status_update" },
297 { "nic_irqs" },
298 { "nic_avoided_irqs" },
299 { "nic_tx_threshold_hit" }
300 };
301
302 static const struct {
303 const char string[ETH_GSTRING_LEN];
304 } ethtool_test_keys[TG3_NUM_TEST] = {
305 { "nvram test (online) " },
306 { "link test (online) " },
307 { "register test (offline)" },
308 { "memory test (offline)" },
309 { "loopback test (offline)" },
310 { "interrupt test (offline)" },
311 };
312
313 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
314 {
315 writel(val, tp->regs + off);
316 }
317
318 static u32 tg3_read32(struct tg3 *tp, u32 off)
319 {
320 return (readl(tp->regs + off));
321 }
322
323 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
324 {
325 writel(val, tp->aperegs + off);
326 }
327
328 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
329 {
330 return (readl(tp->aperegs + off));
331 }
332
333 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
334 {
335 unsigned long flags;
336
337 spin_lock_irqsave(&tp->indirect_lock, flags);
338 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
339 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
340 spin_unlock_irqrestore(&tp->indirect_lock, flags);
341 }
342
343 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
344 {
345 writel(val, tp->regs + off);
346 readl(tp->regs + off);
347 }
348
349 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
350 {
351 unsigned long flags;
352 u32 val;
353
354 spin_lock_irqsave(&tp->indirect_lock, flags);
355 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
356 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
357 spin_unlock_irqrestore(&tp->indirect_lock, flags);
358 return val;
359 }
360
361 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
362 {
363 unsigned long flags;
364
365 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
366 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
367 TG3_64BIT_REG_LOW, val);
368 return;
369 }
370 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
371 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
372 TG3_64BIT_REG_LOW, val);
373 return;
374 }
375
376 spin_lock_irqsave(&tp->indirect_lock, flags);
377 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
378 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
379 spin_unlock_irqrestore(&tp->indirect_lock, flags);
380
381 /* In indirect mode when disabling interrupts, we also need
382 * to clear the interrupt bit in the GRC local ctrl register.
383 */
384 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
385 (val == 0x1)) {
386 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
387 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
388 }
389 }
390
391 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
392 {
393 unsigned long flags;
394 u32 val;
395
396 spin_lock_irqsave(&tp->indirect_lock, flags);
397 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
398 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
399 spin_unlock_irqrestore(&tp->indirect_lock, flags);
400 return val;
401 }
402
403 /* usec_wait specifies the wait time in usec when writing to certain registers
404 * where it is unsafe to read back the register without some delay.
405 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
406 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
407 */
408 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
409 {
410 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
411 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
412 /* Non-posted methods */
413 tp->write32(tp, off, val);
414 else {
415 /* Posted method */
416 tg3_write32(tp, off, val);
417 if (usec_wait)
418 udelay(usec_wait);
419 tp->read32(tp, off);
420 }
421 /* Wait again after the read for the posted method to guarantee that
422 * the wait time is met.
423 */
424 if (usec_wait)
425 udelay(usec_wait);
426 }
427
428 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
429 {
430 tp->write32_mbox(tp, off, val);
431 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
432 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
433 tp->read32_mbox(tp, off);
434 }
435
436 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
437 {
438 void __iomem *mbox = tp->regs + off;
439 writel(val, mbox);
440 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
441 writel(val, mbox);
442 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
443 readl(mbox);
444 }
445
446 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
447 {
448 return (readl(tp->regs + off + GRCMBOX_BASE));
449 }
450
451 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
452 {
453 writel(val, tp->regs + off + GRCMBOX_BASE);
454 }
455
456 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
457 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
458 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
459 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
460 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
461
462 #define tw32(reg,val) tp->write32(tp, reg, val)
463 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
464 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
465 #define tr32(reg) tp->read32(tp, reg)
466
467 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
468 {
469 unsigned long flags;
470
471 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
472 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
473 return;
474
475 spin_lock_irqsave(&tp->indirect_lock, flags);
476 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
477 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
478 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
479
480 /* Always leave this as zero. */
481 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
482 } else {
483 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
484 tw32_f(TG3PCI_MEM_WIN_DATA, val);
485
486 /* Always leave this as zero. */
487 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
488 }
489 spin_unlock_irqrestore(&tp->indirect_lock, flags);
490 }
491
492 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
493 {
494 unsigned long flags;
495
496 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
497 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
498 *val = 0;
499 return;
500 }
501
502 spin_lock_irqsave(&tp->indirect_lock, flags);
503 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
504 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
505 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
506
507 /* Always leave this as zero. */
508 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
509 } else {
510 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
511 *val = tr32(TG3PCI_MEM_WIN_DATA);
512
513 /* Always leave this as zero. */
514 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
515 }
516 spin_unlock_irqrestore(&tp->indirect_lock, flags);
517 }
518
519 static void tg3_ape_lock_init(struct tg3 *tp)
520 {
521 int i;
522
523 /* Make sure the driver hasn't any stale locks. */
524 for (i = 0; i < 8; i++)
525 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
526 APE_LOCK_GRANT_DRIVER);
527 }
528
529 static int tg3_ape_lock(struct tg3 *tp, int locknum)
530 {
531 int i, off;
532 int ret = 0;
533 u32 status;
534
535 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
536 return 0;
537
538 switch (locknum) {
539 case TG3_APE_LOCK_MEM:
540 break;
541 default:
542 return -EINVAL;
543 }
544
545 off = 4 * locknum;
546
547 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
548
549 /* Wait for up to 1 millisecond to acquire lock. */
550 for (i = 0; i < 100; i++) {
551 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
552 if (status == APE_LOCK_GRANT_DRIVER)
553 break;
554 udelay(10);
555 }
556
557 if (status != APE_LOCK_GRANT_DRIVER) {
558 /* Revoke the lock request. */
559 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
560 APE_LOCK_GRANT_DRIVER);
561
562 ret = -EBUSY;
563 }
564
565 return ret;
566 }
567
568 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
569 {
570 int off;
571
572 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
573 return;
574
575 switch (locknum) {
576 case TG3_APE_LOCK_MEM:
577 break;
578 default:
579 return;
580 }
581
582 off = 4 * locknum;
583 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
584 }
585
586 static void tg3_disable_ints(struct tg3 *tp)
587 {
588 tw32(TG3PCI_MISC_HOST_CTRL,
589 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
590 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
591 }
592
593 static inline void tg3_cond_int(struct tg3 *tp)
594 {
595 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
596 (tp->hw_status->status & SD_STATUS_UPDATED))
597 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
598 else
599 tw32(HOSTCC_MODE, tp->coalesce_mode |
600 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
601 }
602
603 static void tg3_enable_ints(struct tg3 *tp)
604 {
605 tp->irq_sync = 0;
606 wmb();
607
608 tw32(TG3PCI_MISC_HOST_CTRL,
609 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
610 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
611 (tp->last_tag << 24));
612 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
613 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
614 (tp->last_tag << 24));
615 tg3_cond_int(tp);
616 }
617
618 static inline unsigned int tg3_has_work(struct tg3 *tp)
619 {
620 struct tg3_hw_status *sblk = tp->hw_status;
621 unsigned int work_exists = 0;
622
623 /* check for phy events */
624 if (!(tp->tg3_flags &
625 (TG3_FLAG_USE_LINKCHG_REG |
626 TG3_FLAG_POLL_SERDES))) {
627 if (sblk->status & SD_STATUS_LINK_CHG)
628 work_exists = 1;
629 }
630 /* check for RX/TX work to do */
631 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
632 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
633 work_exists = 1;
634
635 return work_exists;
636 }
637
638 /* tg3_restart_ints
639 * similar to tg3_enable_ints, but it accurately determines whether there
640 * is new work pending and can return without flushing the PIO write
641 * which reenables interrupts
642 */
643 static void tg3_restart_ints(struct tg3 *tp)
644 {
645 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
646 tp->last_tag << 24);
647 mmiowb();
648
649 /* When doing tagged status, this work check is unnecessary.
650 * The last_tag we write above tells the chip which piece of
651 * work we've completed.
652 */
653 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
654 tg3_has_work(tp))
655 tw32(HOSTCC_MODE, tp->coalesce_mode |
656 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
657 }
658
659 static inline void tg3_netif_stop(struct tg3 *tp)
660 {
661 tp->dev->trans_start = jiffies; /* prevent tx timeout */
662 napi_disable(&tp->napi);
663 netif_tx_disable(tp->dev);
664 }
665
666 static inline void tg3_netif_start(struct tg3 *tp)
667 {
668 netif_wake_queue(tp->dev);
669 /* NOTE: unconditional netif_wake_queue is only appropriate
670 * so long as all callers are assured to have free tx slots
671 * (such as after tg3_init_hw)
672 */
673 napi_enable(&tp->napi);
674 tp->hw_status->status |= SD_STATUS_UPDATED;
675 tg3_enable_ints(tp);
676 }
677
678 static void tg3_switch_clocks(struct tg3 *tp)
679 {
680 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
681 u32 orig_clock_ctrl;
682
683 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
684 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
685 return;
686
687 orig_clock_ctrl = clock_ctrl;
688 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
689 CLOCK_CTRL_CLKRUN_OENABLE |
690 0x1f);
691 tp->pci_clock_ctrl = clock_ctrl;
692
693 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
694 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
695 tw32_wait_f(TG3PCI_CLOCK_CTRL,
696 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
697 }
698 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
699 tw32_wait_f(TG3PCI_CLOCK_CTRL,
700 clock_ctrl |
701 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
702 40);
703 tw32_wait_f(TG3PCI_CLOCK_CTRL,
704 clock_ctrl | (CLOCK_CTRL_ALTCLK),
705 40);
706 }
707 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
708 }
709
710 #define PHY_BUSY_LOOPS 5000
711
712 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
713 {
714 u32 frame_val;
715 unsigned int loops;
716 int ret;
717
718 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
719 tw32_f(MAC_MI_MODE,
720 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
721 udelay(80);
722 }
723
724 *val = 0x0;
725
726 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
727 MI_COM_PHY_ADDR_MASK);
728 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
729 MI_COM_REG_ADDR_MASK);
730 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
731
732 tw32_f(MAC_MI_COM, frame_val);
733
734 loops = PHY_BUSY_LOOPS;
735 while (loops != 0) {
736 udelay(10);
737 frame_val = tr32(MAC_MI_COM);
738
739 if ((frame_val & MI_COM_BUSY) == 0) {
740 udelay(5);
741 frame_val = tr32(MAC_MI_COM);
742 break;
743 }
744 loops -= 1;
745 }
746
747 ret = -EBUSY;
748 if (loops != 0) {
749 *val = frame_val & MI_COM_DATA_MASK;
750 ret = 0;
751 }
752
753 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
754 tw32_f(MAC_MI_MODE, tp->mi_mode);
755 udelay(80);
756 }
757
758 return ret;
759 }
760
761 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
762 {
763 u32 frame_val;
764 unsigned int loops;
765 int ret;
766
767 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
768 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
769 return 0;
770
771 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
772 tw32_f(MAC_MI_MODE,
773 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
774 udelay(80);
775 }
776
777 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
778 MI_COM_PHY_ADDR_MASK);
779 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
780 MI_COM_REG_ADDR_MASK);
781 frame_val |= (val & MI_COM_DATA_MASK);
782 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
783
784 tw32_f(MAC_MI_COM, frame_val);
785
786 loops = PHY_BUSY_LOOPS;
787 while (loops != 0) {
788 udelay(10);
789 frame_val = tr32(MAC_MI_COM);
790 if ((frame_val & MI_COM_BUSY) == 0) {
791 udelay(5);
792 frame_val = tr32(MAC_MI_COM);
793 break;
794 }
795 loops -= 1;
796 }
797
798 ret = -EBUSY;
799 if (loops != 0)
800 ret = 0;
801
802 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
803 tw32_f(MAC_MI_MODE, tp->mi_mode);
804 udelay(80);
805 }
806
807 return ret;
808 }
809
810 static int tg3_bmcr_reset(struct tg3 *tp)
811 {
812 u32 phy_control;
813 int limit, err;
814
815 /* OK, reset it, and poll the BMCR_RESET bit until it
816 * clears or we time out.
817 */
818 phy_control = BMCR_RESET;
819 err = tg3_writephy(tp, MII_BMCR, phy_control);
820 if (err != 0)
821 return -EBUSY;
822
823 limit = 5000;
824 while (limit--) {
825 err = tg3_readphy(tp, MII_BMCR, &phy_control);
826 if (err != 0)
827 return -EBUSY;
828
829 if ((phy_control & BMCR_RESET) == 0) {
830 udelay(40);
831 break;
832 }
833 udelay(10);
834 }
835 if (limit <= 0)
836 return -EBUSY;
837
838 return 0;
839 }
840
841 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
842 {
843 struct tg3 *tp = (struct tg3 *)bp->priv;
844 u32 val;
845
846 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
847 return -EAGAIN;
848
849 if (tg3_readphy(tp, reg, &val))
850 return -EIO;
851
852 return val;
853 }
854
855 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
856 {
857 struct tg3 *tp = (struct tg3 *)bp->priv;
858
859 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
860 return -EAGAIN;
861
862 if (tg3_writephy(tp, reg, val))
863 return -EIO;
864
865 return 0;
866 }
867
868 static int tg3_mdio_reset(struct mii_bus *bp)
869 {
870 return 0;
871 }
872
873 static void tg3_mdio_config(struct tg3 *tp)
874 {
875 u32 val;
876
877 if (tp->mdio_bus.phy_map[PHY_ADDR]->interface !=
878 PHY_INTERFACE_MODE_RGMII)
879 return;
880
881 val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC |
882 MAC_PHYCFG1_RGMII_SND_STAT_EN);
883 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
884 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
885 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
886 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
887 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
888 }
889 tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV);
890
891 val = tr32(MAC_PHYCFG2) & ~(MAC_PHYCFG2_INBAND_ENABLE);
892 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
893 val |= MAC_PHYCFG2_INBAND_ENABLE;
894 tw32(MAC_PHYCFG2, val);
895
896 val = tr32(MAC_EXT_RGMII_MODE);
897 val &= ~(MAC_RGMII_MODE_RX_INT_B |
898 MAC_RGMII_MODE_RX_QUALITY |
899 MAC_RGMII_MODE_RX_ACTIVITY |
900 MAC_RGMII_MODE_RX_ENG_DET |
901 MAC_RGMII_MODE_TX_ENABLE |
902 MAC_RGMII_MODE_TX_LOWPWR |
903 MAC_RGMII_MODE_TX_RESET);
904 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
905 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
906 val |= MAC_RGMII_MODE_RX_INT_B |
907 MAC_RGMII_MODE_RX_QUALITY |
908 MAC_RGMII_MODE_RX_ACTIVITY |
909 MAC_RGMII_MODE_RX_ENG_DET;
910 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
911 val |= MAC_RGMII_MODE_TX_ENABLE |
912 MAC_RGMII_MODE_TX_LOWPWR |
913 MAC_RGMII_MODE_TX_RESET;
914 }
915 tw32(MAC_EXT_RGMII_MODE, val);
916 }
917
918 static void tg3_mdio_start(struct tg3 *tp)
919 {
920 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
921 mutex_lock(&tp->mdio_bus.mdio_lock);
922 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
923 mutex_unlock(&tp->mdio_bus.mdio_lock);
924 }
925
926 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
927 tw32_f(MAC_MI_MODE, tp->mi_mode);
928 udelay(80);
929
930 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED)
931 tg3_mdio_config(tp);
932 }
933
934 static void tg3_mdio_stop(struct tg3 *tp)
935 {
936 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
937 mutex_lock(&tp->mdio_bus.mdio_lock);
938 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
939 mutex_unlock(&tp->mdio_bus.mdio_lock);
940 }
941 }
942
943 static int tg3_mdio_init(struct tg3 *tp)
944 {
945 int i;
946 u32 reg;
947 struct phy_device *phydev;
948 struct mii_bus *mdio_bus = &tp->mdio_bus;
949
950 tg3_mdio_start(tp);
951
952 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
953 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
954 return 0;
955
956 memset(mdio_bus, 0, sizeof(*mdio_bus));
957
958 mdio_bus->name = "tg3 mdio bus";
959 snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%x",
960 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
961 mdio_bus->priv = tp;
962 mdio_bus->dev = &tp->pdev->dev;
963 mdio_bus->read = &tg3_mdio_read;
964 mdio_bus->write = &tg3_mdio_write;
965 mdio_bus->reset = &tg3_mdio_reset;
966 mdio_bus->phy_mask = ~(1 << PHY_ADDR);
967 mdio_bus->irq = &tp->mdio_irq[0];
968
969 for (i = 0; i < PHY_MAX_ADDR; i++)
970 mdio_bus->irq[i] = PHY_POLL;
971
972 /* The bus registration will look for all the PHYs on the mdio bus.
973 * Unfortunately, it does not ensure the PHY is powered up before
974 * accessing the PHY ID registers. A chip reset is the
975 * quickest way to bring the device back to an operational state..
976 */
977 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
978 tg3_bmcr_reset(tp);
979
980 i = mdiobus_register(mdio_bus);
981 if (i) {
982 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
983 tp->dev->name, i);
984 return i;
985 }
986
987 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
988
989 phydev = tp->mdio_bus.phy_map[PHY_ADDR];
990
991 switch (phydev->phy_id) {
992 case TG3_PHY_ID_BCM50610:
993 phydev->interface = PHY_INTERFACE_MODE_RGMII;
994 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
995 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
996 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
997 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
998 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
999 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1000 break;
1001 case TG3_PHY_ID_BCMAC131:
1002 phydev->interface = PHY_INTERFACE_MODE_MII;
1003 break;
1004 }
1005
1006 tg3_mdio_config(tp);
1007
1008 return 0;
1009 }
1010
1011 static void tg3_mdio_fini(struct tg3 *tp)
1012 {
1013 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1014 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1015 mdiobus_unregister(&tp->mdio_bus);
1016 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1017 }
1018 }
1019
1020 /* tp->lock is held. */
1021 static void tg3_wait_for_event_ack(struct tg3 *tp)
1022 {
1023 int i;
1024
1025 /* Wait for up to 2.5 milliseconds */
1026 for (i = 0; i < 250000; i++) {
1027 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1028 break;
1029 udelay(10);
1030 }
1031 }
1032
1033 /* tp->lock is held. */
1034 static void tg3_ump_link_report(struct tg3 *tp)
1035 {
1036 u32 reg;
1037 u32 val;
1038
1039 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1040 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1041 return;
1042
1043 tg3_wait_for_event_ack(tp);
1044
1045 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1046
1047 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1048
1049 val = 0;
1050 if (!tg3_readphy(tp, MII_BMCR, &reg))
1051 val = reg << 16;
1052 if (!tg3_readphy(tp, MII_BMSR, &reg))
1053 val |= (reg & 0xffff);
1054 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1055
1056 val = 0;
1057 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1058 val = reg << 16;
1059 if (!tg3_readphy(tp, MII_LPA, &reg))
1060 val |= (reg & 0xffff);
1061 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1062
1063 val = 0;
1064 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1065 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1066 val = reg << 16;
1067 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1068 val |= (reg & 0xffff);
1069 }
1070 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1071
1072 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1073 val = reg << 16;
1074 else
1075 val = 0;
1076 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1077
1078 val = tr32(GRC_RX_CPU_EVENT);
1079 val |= GRC_RX_CPU_DRIVER_EVENT;
1080 tw32_f(GRC_RX_CPU_EVENT, val);
1081 }
1082
1083 static void tg3_link_report(struct tg3 *tp)
1084 {
1085 if (!netif_carrier_ok(tp->dev)) {
1086 if (netif_msg_link(tp))
1087 printk(KERN_INFO PFX "%s: Link is down.\n",
1088 tp->dev->name);
1089 tg3_ump_link_report(tp);
1090 } else if (netif_msg_link(tp)) {
1091 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1092 tp->dev->name,
1093 (tp->link_config.active_speed == SPEED_1000 ?
1094 1000 :
1095 (tp->link_config.active_speed == SPEED_100 ?
1096 100 : 10)),
1097 (tp->link_config.active_duplex == DUPLEX_FULL ?
1098 "full" : "half"));
1099
1100 printk(KERN_INFO PFX
1101 "%s: Flow control is %s for TX and %s for RX.\n",
1102 tp->dev->name,
1103 (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX) ?
1104 "on" : "off",
1105 (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX) ?
1106 "on" : "off");
1107 tg3_ump_link_report(tp);
1108 }
1109 }
1110
1111 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1112 {
1113 u16 miireg;
1114
1115 if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1116 miireg = ADVERTISE_PAUSE_CAP;
1117 else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1118 miireg = ADVERTISE_PAUSE_ASYM;
1119 else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1120 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1121 else
1122 miireg = 0;
1123
1124 return miireg;
1125 }
1126
1127 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1128 {
1129 u16 miireg;
1130
1131 if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1132 miireg = ADVERTISE_1000XPAUSE;
1133 else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1134 miireg = ADVERTISE_1000XPSE_ASYM;
1135 else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1136 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1137 else
1138 miireg = 0;
1139
1140 return miireg;
1141 }
1142
1143 static u8 tg3_resolve_flowctrl_1000T(u16 lcladv, u16 rmtadv)
1144 {
1145 u8 cap = 0;
1146
1147 if (lcladv & ADVERTISE_PAUSE_CAP) {
1148 if (lcladv & ADVERTISE_PAUSE_ASYM) {
1149 if (rmtadv & LPA_PAUSE_CAP)
1150 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1151 else if (rmtadv & LPA_PAUSE_ASYM)
1152 cap = TG3_FLOW_CTRL_RX;
1153 } else {
1154 if (rmtadv & LPA_PAUSE_CAP)
1155 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1156 }
1157 } else if (lcladv & ADVERTISE_PAUSE_ASYM) {
1158 if ((rmtadv & LPA_PAUSE_CAP) && (rmtadv & LPA_PAUSE_ASYM))
1159 cap = TG3_FLOW_CTRL_TX;
1160 }
1161
1162 return cap;
1163 }
1164
1165 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1166 {
1167 u8 cap = 0;
1168
1169 if (lcladv & ADVERTISE_1000XPAUSE) {
1170 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1171 if (rmtadv & LPA_1000XPAUSE)
1172 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1173 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1174 cap = TG3_FLOW_CTRL_RX;
1175 } else {
1176 if (rmtadv & LPA_1000XPAUSE)
1177 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1178 }
1179 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1180 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1181 cap = TG3_FLOW_CTRL_TX;
1182 }
1183
1184 return cap;
1185 }
1186
1187 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1188 {
1189 u8 autoneg;
1190 u8 flowctrl = 0;
1191 u32 old_rx_mode = tp->rx_mode;
1192 u32 old_tx_mode = tp->tx_mode;
1193
1194 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1195 autoneg = tp->mdio_bus.phy_map[PHY_ADDR]->autoneg;
1196 else
1197 autoneg = tp->link_config.autoneg;
1198
1199 if (autoneg == AUTONEG_ENABLE &&
1200 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1201 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1202 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1203 else
1204 flowctrl = tg3_resolve_flowctrl_1000T(lcladv, rmtadv);
1205 } else
1206 flowctrl = tp->link_config.flowctrl;
1207
1208 tp->link_config.active_flowctrl = flowctrl;
1209
1210 if (flowctrl & TG3_FLOW_CTRL_RX)
1211 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1212 else
1213 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1214
1215 if (old_rx_mode != tp->rx_mode)
1216 tw32_f(MAC_RX_MODE, tp->rx_mode);
1217
1218 if (flowctrl & TG3_FLOW_CTRL_TX)
1219 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1220 else
1221 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1222
1223 if (old_tx_mode != tp->tx_mode)
1224 tw32_f(MAC_TX_MODE, tp->tx_mode);
1225 }
1226
1227 static void tg3_adjust_link(struct net_device *dev)
1228 {
1229 u8 oldflowctrl, linkmesg = 0;
1230 u32 mac_mode, lcl_adv, rmt_adv;
1231 struct tg3 *tp = netdev_priv(dev);
1232 struct phy_device *phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1233
1234 spin_lock(&tp->lock);
1235
1236 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1237 MAC_MODE_HALF_DUPLEX);
1238
1239 oldflowctrl = tp->link_config.active_flowctrl;
1240
1241 if (phydev->link) {
1242 lcl_adv = 0;
1243 rmt_adv = 0;
1244
1245 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1246 mac_mode |= MAC_MODE_PORT_MODE_MII;
1247 else
1248 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1249
1250 if (phydev->duplex == DUPLEX_HALF)
1251 mac_mode |= MAC_MODE_HALF_DUPLEX;
1252 else {
1253 lcl_adv = tg3_advert_flowctrl_1000T(
1254 tp->link_config.flowctrl);
1255
1256 if (phydev->pause)
1257 rmt_adv = LPA_PAUSE_CAP;
1258 if (phydev->asym_pause)
1259 rmt_adv |= LPA_PAUSE_ASYM;
1260 }
1261
1262 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1263 } else
1264 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1265
1266 if (mac_mode != tp->mac_mode) {
1267 tp->mac_mode = mac_mode;
1268 tw32_f(MAC_MODE, tp->mac_mode);
1269 udelay(40);
1270 }
1271
1272 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1273 tw32(MAC_TX_LENGTHS,
1274 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1275 (6 << TX_LENGTHS_IPG_SHIFT) |
1276 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1277 else
1278 tw32(MAC_TX_LENGTHS,
1279 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1280 (6 << TX_LENGTHS_IPG_SHIFT) |
1281 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1282
1283 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1284 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1285 phydev->speed != tp->link_config.active_speed ||
1286 phydev->duplex != tp->link_config.active_duplex ||
1287 oldflowctrl != tp->link_config.active_flowctrl)
1288 linkmesg = 1;
1289
1290 tp->link_config.active_speed = phydev->speed;
1291 tp->link_config.active_duplex = phydev->duplex;
1292
1293 spin_unlock(&tp->lock);
1294
1295 if (linkmesg)
1296 tg3_link_report(tp);
1297 }
1298
1299 static int tg3_phy_init(struct tg3 *tp)
1300 {
1301 struct phy_device *phydev;
1302
1303 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1304 return 0;
1305
1306 /* Bring the PHY back to a known state. */
1307 tg3_bmcr_reset(tp);
1308
1309 phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1310
1311 /* Attach the MAC to the PHY. */
1312 phydev = phy_connect(tp->dev, phydev->dev.bus_id, tg3_adjust_link,
1313 phydev->dev_flags, phydev->interface);
1314 if (IS_ERR(phydev)) {
1315 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1316 return PTR_ERR(phydev);
1317 }
1318
1319 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1320
1321 /* Mask with MAC supported features. */
1322 phydev->supported &= (PHY_GBIT_FEATURES |
1323 SUPPORTED_Pause |
1324 SUPPORTED_Asym_Pause);
1325
1326 phydev->advertising = phydev->supported;
1327
1328 printk(KERN_INFO
1329 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
1330 tp->dev->name, phydev->drv->name, phydev->dev.bus_id);
1331
1332 return 0;
1333 }
1334
1335 static void tg3_phy_start(struct tg3 *tp)
1336 {
1337 struct phy_device *phydev;
1338
1339 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1340 return;
1341
1342 phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1343
1344 if (tp->link_config.phy_is_low_power) {
1345 tp->link_config.phy_is_low_power = 0;
1346 phydev->speed = tp->link_config.orig_speed;
1347 phydev->duplex = tp->link_config.orig_duplex;
1348 phydev->autoneg = tp->link_config.orig_autoneg;
1349 phydev->advertising = tp->link_config.orig_advertising;
1350 }
1351
1352 phy_start(phydev);
1353
1354 phy_start_aneg(phydev);
1355 }
1356
1357 static void tg3_phy_stop(struct tg3 *tp)
1358 {
1359 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1360 return;
1361
1362 phy_stop(tp->mdio_bus.phy_map[PHY_ADDR]);
1363 }
1364
1365 static void tg3_phy_fini(struct tg3 *tp)
1366 {
1367 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1368 phy_disconnect(tp->mdio_bus.phy_map[PHY_ADDR]);
1369 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1370 }
1371 }
1372
1373 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1374 {
1375 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1376 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1377 }
1378
1379 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1380 {
1381 u32 phy;
1382
1383 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1384 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1385 return;
1386
1387 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1388 u32 ephy;
1389
1390 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
1391 tg3_writephy(tp, MII_TG3_EPHY_TEST,
1392 ephy | MII_TG3_EPHY_SHADOW_EN);
1393 if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
1394 if (enable)
1395 phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
1396 else
1397 phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
1398 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
1399 }
1400 tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
1401 }
1402 } else {
1403 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1404 MII_TG3_AUXCTL_SHDWSEL_MISC;
1405 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1406 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1407 if (enable)
1408 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1409 else
1410 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1411 phy |= MII_TG3_AUXCTL_MISC_WREN;
1412 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1413 }
1414 }
1415 }
1416
1417 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1418 {
1419 u32 val;
1420
1421 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1422 return;
1423
1424 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1425 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1426 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1427 (val | (1 << 15) | (1 << 4)));
1428 }
1429
1430 static void tg3_phy_apply_otp(struct tg3 *tp)
1431 {
1432 u32 otp, phy;
1433
1434 if (!tp->phy_otp)
1435 return;
1436
1437 otp = tp->phy_otp;
1438
1439 /* Enable SM_DSP clock and tx 6dB coding. */
1440 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1441 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1442 MII_TG3_AUXCTL_ACTL_TX_6DB;
1443 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1444
1445 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1446 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1447 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1448
1449 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1450 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1451 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1452
1453 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1454 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1455 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1456
1457 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1458 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1459
1460 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1461 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1462
1463 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1464 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1465 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1466
1467 /* Turn off SM_DSP clock. */
1468 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1469 MII_TG3_AUXCTL_ACTL_TX_6DB;
1470 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1471 }
1472
1473 static int tg3_wait_macro_done(struct tg3 *tp)
1474 {
1475 int limit = 100;
1476
1477 while (limit--) {
1478 u32 tmp32;
1479
1480 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1481 if ((tmp32 & 0x1000) == 0)
1482 break;
1483 }
1484 }
1485 if (limit <= 0)
1486 return -EBUSY;
1487
1488 return 0;
1489 }
1490
1491 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1492 {
1493 static const u32 test_pat[4][6] = {
1494 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1495 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1496 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1497 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1498 };
1499 int chan;
1500
1501 for (chan = 0; chan < 4; chan++) {
1502 int i;
1503
1504 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1505 (chan * 0x2000) | 0x0200);
1506 tg3_writephy(tp, 0x16, 0x0002);
1507
1508 for (i = 0; i < 6; i++)
1509 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1510 test_pat[chan][i]);
1511
1512 tg3_writephy(tp, 0x16, 0x0202);
1513 if (tg3_wait_macro_done(tp)) {
1514 *resetp = 1;
1515 return -EBUSY;
1516 }
1517
1518 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1519 (chan * 0x2000) | 0x0200);
1520 tg3_writephy(tp, 0x16, 0x0082);
1521 if (tg3_wait_macro_done(tp)) {
1522 *resetp = 1;
1523 return -EBUSY;
1524 }
1525
1526 tg3_writephy(tp, 0x16, 0x0802);
1527 if (tg3_wait_macro_done(tp)) {
1528 *resetp = 1;
1529 return -EBUSY;
1530 }
1531
1532 for (i = 0; i < 6; i += 2) {
1533 u32 low, high;
1534
1535 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1536 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1537 tg3_wait_macro_done(tp)) {
1538 *resetp = 1;
1539 return -EBUSY;
1540 }
1541 low &= 0x7fff;
1542 high &= 0x000f;
1543 if (low != test_pat[chan][i] ||
1544 high != test_pat[chan][i+1]) {
1545 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1546 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1547 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1548
1549 return -EBUSY;
1550 }
1551 }
1552 }
1553
1554 return 0;
1555 }
1556
1557 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1558 {
1559 int chan;
1560
1561 for (chan = 0; chan < 4; chan++) {
1562 int i;
1563
1564 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1565 (chan * 0x2000) | 0x0200);
1566 tg3_writephy(tp, 0x16, 0x0002);
1567 for (i = 0; i < 6; i++)
1568 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1569 tg3_writephy(tp, 0x16, 0x0202);
1570 if (tg3_wait_macro_done(tp))
1571 return -EBUSY;
1572 }
1573
1574 return 0;
1575 }
1576
1577 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1578 {
1579 u32 reg32, phy9_orig;
1580 int retries, do_phy_reset, err;
1581
1582 retries = 10;
1583 do_phy_reset = 1;
1584 do {
1585 if (do_phy_reset) {
1586 err = tg3_bmcr_reset(tp);
1587 if (err)
1588 return err;
1589 do_phy_reset = 0;
1590 }
1591
1592 /* Disable transmitter and interrupt. */
1593 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1594 continue;
1595
1596 reg32 |= 0x3000;
1597 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1598
1599 /* Set full-duplex, 1000 mbps. */
1600 tg3_writephy(tp, MII_BMCR,
1601 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1602
1603 /* Set to master mode. */
1604 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1605 continue;
1606
1607 tg3_writephy(tp, MII_TG3_CTRL,
1608 (MII_TG3_CTRL_AS_MASTER |
1609 MII_TG3_CTRL_ENABLE_AS_MASTER));
1610
1611 /* Enable SM_DSP_CLOCK and 6dB. */
1612 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1613
1614 /* Block the PHY control access. */
1615 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1616 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1617
1618 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1619 if (!err)
1620 break;
1621 } while (--retries);
1622
1623 err = tg3_phy_reset_chanpat(tp);
1624 if (err)
1625 return err;
1626
1627 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1628 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1629
1630 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1631 tg3_writephy(tp, 0x16, 0x0000);
1632
1633 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1634 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1635 /* Set Extended packet length bit for jumbo frames */
1636 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1637 }
1638 else {
1639 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1640 }
1641
1642 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1643
1644 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1645 reg32 &= ~0x3000;
1646 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1647 } else if (!err)
1648 err = -EBUSY;
1649
1650 return err;
1651 }
1652
1653 /* This will reset the tigon3 PHY if there is no valid
1654 * link unless the FORCE argument is non-zero.
1655 */
1656 static int tg3_phy_reset(struct tg3 *tp)
1657 {
1658 u32 cpmuctrl;
1659 u32 phy_status;
1660 int err;
1661
1662 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1663 u32 val;
1664
1665 val = tr32(GRC_MISC_CFG);
1666 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1667 udelay(40);
1668 }
1669 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1670 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1671 if (err != 0)
1672 return -EBUSY;
1673
1674 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1675 netif_carrier_off(tp->dev);
1676 tg3_link_report(tp);
1677 }
1678
1679 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1680 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1681 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1682 err = tg3_phy_reset_5703_4_5(tp);
1683 if (err)
1684 return err;
1685 goto out;
1686 }
1687
1688 cpmuctrl = 0;
1689 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1690 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1691 cpmuctrl = tr32(TG3_CPMU_CTRL);
1692 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1693 tw32(TG3_CPMU_CTRL,
1694 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1695 }
1696
1697 err = tg3_bmcr_reset(tp);
1698 if (err)
1699 return err;
1700
1701 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1702 u32 phy;
1703
1704 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1705 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1706
1707 tw32(TG3_CPMU_CTRL, cpmuctrl);
1708 }
1709
1710 if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
1711 u32 val;
1712
1713 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1714 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1715 CPMU_LSPD_1000MB_MACCLK_12_5) {
1716 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1717 udelay(40);
1718 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1719 }
1720
1721 /* Disable GPHY autopowerdown. */
1722 tg3_writephy(tp, MII_TG3_MISC_SHDW,
1723 MII_TG3_MISC_SHDW_WREN |
1724 MII_TG3_MISC_SHDW_APD_SEL |
1725 MII_TG3_MISC_SHDW_APD_WKTM_84MS);
1726 }
1727
1728 tg3_phy_apply_otp(tp);
1729
1730 out:
1731 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1732 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1733 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1734 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1735 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1736 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1737 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1738 }
1739 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1740 tg3_writephy(tp, 0x1c, 0x8d68);
1741 tg3_writephy(tp, 0x1c, 0x8d68);
1742 }
1743 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1744 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1745 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1746 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1747 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1748 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1749 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1750 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1751 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1752 }
1753 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1754 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1755 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1756 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1757 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1758 tg3_writephy(tp, MII_TG3_TEST1,
1759 MII_TG3_TEST1_TRIM_EN | 0x4);
1760 } else
1761 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1762 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1763 }
1764 /* Set Extended packet length bit (bit 14) on all chips that */
1765 /* support jumbo frames */
1766 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1767 /* Cannot do read-modify-write on 5401 */
1768 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1769 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1770 u32 phy_reg;
1771
1772 /* Set bit 14 with read-modify-write to preserve other bits */
1773 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1774 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1775 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1776 }
1777
1778 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1779 * jumbo frames transmission.
1780 */
1781 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1782 u32 phy_reg;
1783
1784 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1785 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1786 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1787 }
1788
1789 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1790 /* adjust output voltage */
1791 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1792 }
1793
1794 tg3_phy_toggle_automdix(tp, 1);
1795 tg3_phy_set_wirespeed(tp);
1796 return 0;
1797 }
1798
1799 static void tg3_frob_aux_power(struct tg3 *tp)
1800 {
1801 struct tg3 *tp_peer = tp;
1802
1803 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1804 return;
1805
1806 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1807 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1808 struct net_device *dev_peer;
1809
1810 dev_peer = pci_get_drvdata(tp->pdev_peer);
1811 /* remove_one() may have been run on the peer. */
1812 if (!dev_peer)
1813 tp_peer = tp;
1814 else
1815 tp_peer = netdev_priv(dev_peer);
1816 }
1817
1818 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1819 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1820 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1821 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1822 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1823 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1824 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1825 (GRC_LCLCTRL_GPIO_OE0 |
1826 GRC_LCLCTRL_GPIO_OE1 |
1827 GRC_LCLCTRL_GPIO_OE2 |
1828 GRC_LCLCTRL_GPIO_OUTPUT0 |
1829 GRC_LCLCTRL_GPIO_OUTPUT1),
1830 100);
1831 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
1832 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1833 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1834 GRC_LCLCTRL_GPIO_OE1 |
1835 GRC_LCLCTRL_GPIO_OE2 |
1836 GRC_LCLCTRL_GPIO_OUTPUT0 |
1837 GRC_LCLCTRL_GPIO_OUTPUT1 |
1838 tp->grc_local_ctrl;
1839 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1840
1841 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
1842 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1843
1844 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
1845 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1846 } else {
1847 u32 no_gpio2;
1848 u32 grc_local_ctrl = 0;
1849
1850 if (tp_peer != tp &&
1851 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1852 return;
1853
1854 /* Workaround to prevent overdrawing Amps. */
1855 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1856 ASIC_REV_5714) {
1857 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1858 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1859 grc_local_ctrl, 100);
1860 }
1861
1862 /* On 5753 and variants, GPIO2 cannot be used. */
1863 no_gpio2 = tp->nic_sram_data_cfg &
1864 NIC_SRAM_DATA_CFG_NO_GPIO2;
1865
1866 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1867 GRC_LCLCTRL_GPIO_OE1 |
1868 GRC_LCLCTRL_GPIO_OE2 |
1869 GRC_LCLCTRL_GPIO_OUTPUT1 |
1870 GRC_LCLCTRL_GPIO_OUTPUT2;
1871 if (no_gpio2) {
1872 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1873 GRC_LCLCTRL_GPIO_OUTPUT2);
1874 }
1875 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1876 grc_local_ctrl, 100);
1877
1878 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1879
1880 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1881 grc_local_ctrl, 100);
1882
1883 if (!no_gpio2) {
1884 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1885 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1886 grc_local_ctrl, 100);
1887 }
1888 }
1889 } else {
1890 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1891 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1892 if (tp_peer != tp &&
1893 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1894 return;
1895
1896 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1897 (GRC_LCLCTRL_GPIO_OE1 |
1898 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1899
1900 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1901 GRC_LCLCTRL_GPIO_OE1, 100);
1902
1903 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1904 (GRC_LCLCTRL_GPIO_OE1 |
1905 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1906 }
1907 }
1908 }
1909
1910 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
1911 {
1912 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
1913 return 1;
1914 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
1915 if (speed != SPEED_10)
1916 return 1;
1917 } else if (speed == SPEED_10)
1918 return 1;
1919
1920 return 0;
1921 }
1922
1923 static int tg3_setup_phy(struct tg3 *, int);
1924
1925 #define RESET_KIND_SHUTDOWN 0
1926 #define RESET_KIND_INIT 1
1927 #define RESET_KIND_SUSPEND 2
1928
1929 static void tg3_write_sig_post_reset(struct tg3 *, int);
1930 static int tg3_halt_cpu(struct tg3 *, u32);
1931 static int tg3_nvram_lock(struct tg3 *);
1932 static void tg3_nvram_unlock(struct tg3 *);
1933
1934 static void tg3_power_down_phy(struct tg3 *tp)
1935 {
1936 u32 val;
1937
1938 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1939 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1940 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1941 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1942
1943 sg_dig_ctrl |=
1944 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1945 tw32(SG_DIG_CTRL, sg_dig_ctrl);
1946 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1947 }
1948 return;
1949 }
1950
1951 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1952 tg3_bmcr_reset(tp);
1953 val = tr32(GRC_MISC_CFG);
1954 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1955 udelay(40);
1956 return;
1957 } else if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
1958 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1959 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1960 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1961 }
1962
1963 /* The PHY should not be powered down on some chips because
1964 * of bugs.
1965 */
1966 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1967 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1968 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1969 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1970 return;
1971
1972 if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
1973 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1974 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1975 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
1976 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1977 }
1978
1979 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1980 }
1981
1982 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1983 {
1984 u32 misc_host_ctrl;
1985
1986 /* Make sure register accesses (indirect or otherwise)
1987 * will function correctly.
1988 */
1989 pci_write_config_dword(tp->pdev,
1990 TG3PCI_MISC_HOST_CTRL,
1991 tp->misc_host_ctrl);
1992
1993 switch (state) {
1994 case PCI_D0:
1995 pci_enable_wake(tp->pdev, state, false);
1996 pci_set_power_state(tp->pdev, PCI_D0);
1997
1998 /* Switch out of Vaux if it is a NIC */
1999 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2000 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2001
2002 return 0;
2003
2004 case PCI_D1:
2005 case PCI_D2:
2006 case PCI_D3hot:
2007 break;
2008
2009 default:
2010 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2011 tp->dev->name, state);
2012 return -EINVAL;
2013 }
2014 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2015 tw32(TG3PCI_MISC_HOST_CTRL,
2016 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2017
2018 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2019 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2020 !tp->link_config.phy_is_low_power) {
2021 struct phy_device *phydev;
2022 u32 advertising;
2023
2024 phydev = tp->mdio_bus.phy_map[PHY_ADDR];
2025
2026 tp->link_config.phy_is_low_power = 1;
2027
2028 tp->link_config.orig_speed = phydev->speed;
2029 tp->link_config.orig_duplex = phydev->duplex;
2030 tp->link_config.orig_autoneg = phydev->autoneg;
2031 tp->link_config.orig_advertising = phydev->advertising;
2032
2033 advertising = ADVERTISED_TP |
2034 ADVERTISED_Pause |
2035 ADVERTISED_Autoneg |
2036 ADVERTISED_10baseT_Half;
2037
2038 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2039 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
2040 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2041 advertising |=
2042 ADVERTISED_100baseT_Half |
2043 ADVERTISED_100baseT_Full |
2044 ADVERTISED_10baseT_Full;
2045 else
2046 advertising |= ADVERTISED_10baseT_Full;
2047 }
2048
2049 phydev->advertising = advertising;
2050
2051 phy_start_aneg(phydev);
2052 }
2053 } else {
2054 if (tp->link_config.phy_is_low_power == 0) {
2055 tp->link_config.phy_is_low_power = 1;
2056 tp->link_config.orig_speed = tp->link_config.speed;
2057 tp->link_config.orig_duplex = tp->link_config.duplex;
2058 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2059 }
2060
2061 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2062 tp->link_config.speed = SPEED_10;
2063 tp->link_config.duplex = DUPLEX_HALF;
2064 tp->link_config.autoneg = AUTONEG_ENABLE;
2065 tg3_setup_phy(tp, 0);
2066 }
2067 }
2068
2069 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2070 u32 val;
2071
2072 val = tr32(GRC_VCPU_EXT_CTRL);
2073 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2074 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2075 int i;
2076 u32 val;
2077
2078 for (i = 0; i < 200; i++) {
2079 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2080 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2081 break;
2082 msleep(1);
2083 }
2084 }
2085 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2086 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2087 WOL_DRV_STATE_SHUTDOWN |
2088 WOL_DRV_WOL |
2089 WOL_SET_MAGIC_PKT);
2090
2091 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
2092 u32 mac_mode;
2093
2094 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2095 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
2096 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2097 udelay(40);
2098 }
2099
2100 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2101 mac_mode = MAC_MODE_PORT_MODE_GMII;
2102 else
2103 mac_mode = MAC_MODE_PORT_MODE_MII;
2104
2105 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2106 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2107 ASIC_REV_5700) {
2108 u32 speed = (tp->tg3_flags &
2109 TG3_FLAG_WOL_SPEED_100MB) ?
2110 SPEED_100 : SPEED_10;
2111 if (tg3_5700_link_polarity(tp, speed))
2112 mac_mode |= MAC_MODE_LINK_POLARITY;
2113 else
2114 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2115 }
2116 } else {
2117 mac_mode = MAC_MODE_PORT_MODE_TBI;
2118 }
2119
2120 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2121 tw32(MAC_LED_CTRL, tp->led_ctrl);
2122
2123 if (pci_pme_capable(tp->pdev, state) &&
2124 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE))
2125 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2126
2127 tw32_f(MAC_MODE, mac_mode);
2128 udelay(100);
2129
2130 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2131 udelay(10);
2132 }
2133
2134 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2135 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2136 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2137 u32 base_val;
2138
2139 base_val = tp->pci_clock_ctrl;
2140 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2141 CLOCK_CTRL_TXCLK_DISABLE);
2142
2143 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2144 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2145 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2146 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2147 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2148 /* do nothing */
2149 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2150 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2151 u32 newbits1, newbits2;
2152
2153 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2154 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2155 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2156 CLOCK_CTRL_TXCLK_DISABLE |
2157 CLOCK_CTRL_ALTCLK);
2158 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2159 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2160 newbits1 = CLOCK_CTRL_625_CORE;
2161 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2162 } else {
2163 newbits1 = CLOCK_CTRL_ALTCLK;
2164 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2165 }
2166
2167 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2168 40);
2169
2170 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2171 40);
2172
2173 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2174 u32 newbits3;
2175
2176 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2177 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2178 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2179 CLOCK_CTRL_TXCLK_DISABLE |
2180 CLOCK_CTRL_44MHZ_CORE);
2181 } else {
2182 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2183 }
2184
2185 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2186 tp->pci_clock_ctrl | newbits3, 40);
2187 }
2188 }
2189
2190 if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
2191 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
2192 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
2193 tg3_power_down_phy(tp);
2194
2195 tg3_frob_aux_power(tp);
2196
2197 /* Workaround for unstable PLL clock */
2198 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2199 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2200 u32 val = tr32(0x7d00);
2201
2202 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2203 tw32(0x7d00, val);
2204 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2205 int err;
2206
2207 err = tg3_nvram_lock(tp);
2208 tg3_halt_cpu(tp, RX_CPU_BASE);
2209 if (!err)
2210 tg3_nvram_unlock(tp);
2211 }
2212 }
2213
2214 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2215
2216 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
2217 pci_enable_wake(tp->pdev, state, true);
2218
2219 /* Finally, set the new power state. */
2220 pci_set_power_state(tp->pdev, state);
2221
2222 return 0;
2223 }
2224
2225 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2226 {
2227 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2228 case MII_TG3_AUX_STAT_10HALF:
2229 *speed = SPEED_10;
2230 *duplex = DUPLEX_HALF;
2231 break;
2232
2233 case MII_TG3_AUX_STAT_10FULL:
2234 *speed = SPEED_10;
2235 *duplex = DUPLEX_FULL;
2236 break;
2237
2238 case MII_TG3_AUX_STAT_100HALF:
2239 *speed = SPEED_100;
2240 *duplex = DUPLEX_HALF;
2241 break;
2242
2243 case MII_TG3_AUX_STAT_100FULL:
2244 *speed = SPEED_100;
2245 *duplex = DUPLEX_FULL;
2246 break;
2247
2248 case MII_TG3_AUX_STAT_1000HALF:
2249 *speed = SPEED_1000;
2250 *duplex = DUPLEX_HALF;
2251 break;
2252
2253 case MII_TG3_AUX_STAT_1000FULL:
2254 *speed = SPEED_1000;
2255 *duplex = DUPLEX_FULL;
2256 break;
2257
2258 default:
2259 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2260 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2261 SPEED_10;
2262 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2263 DUPLEX_HALF;
2264 break;
2265 }
2266 *speed = SPEED_INVALID;
2267 *duplex = DUPLEX_INVALID;
2268 break;
2269 }
2270 }
2271
2272 static void tg3_phy_copper_begin(struct tg3 *tp)
2273 {
2274 u32 new_adv;
2275 int i;
2276
2277 if (tp->link_config.phy_is_low_power) {
2278 /* Entering low power mode. Disable gigabit and
2279 * 100baseT advertisements.
2280 */
2281 tg3_writephy(tp, MII_TG3_CTRL, 0);
2282
2283 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2284 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2285 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2286 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2287
2288 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2289 } else if (tp->link_config.speed == SPEED_INVALID) {
2290 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2291 tp->link_config.advertising &=
2292 ~(ADVERTISED_1000baseT_Half |
2293 ADVERTISED_1000baseT_Full);
2294
2295 new_adv = ADVERTISE_CSMA;
2296 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2297 new_adv |= ADVERTISE_10HALF;
2298 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2299 new_adv |= ADVERTISE_10FULL;
2300 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2301 new_adv |= ADVERTISE_100HALF;
2302 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2303 new_adv |= ADVERTISE_100FULL;
2304
2305 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2306
2307 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2308
2309 if (tp->link_config.advertising &
2310 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2311 new_adv = 0;
2312 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2313 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2314 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2315 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2316 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2317 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2318 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2319 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2320 MII_TG3_CTRL_ENABLE_AS_MASTER);
2321 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2322 } else {
2323 tg3_writephy(tp, MII_TG3_CTRL, 0);
2324 }
2325 } else {
2326 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2327 new_adv |= ADVERTISE_CSMA;
2328
2329 /* Asking for a specific link mode. */
2330 if (tp->link_config.speed == SPEED_1000) {
2331 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2332
2333 if (tp->link_config.duplex == DUPLEX_FULL)
2334 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2335 else
2336 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2337 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2338 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2339 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2340 MII_TG3_CTRL_ENABLE_AS_MASTER);
2341 } else {
2342 if (tp->link_config.speed == SPEED_100) {
2343 if (tp->link_config.duplex == DUPLEX_FULL)
2344 new_adv |= ADVERTISE_100FULL;
2345 else
2346 new_adv |= ADVERTISE_100HALF;
2347 } else {
2348 if (tp->link_config.duplex == DUPLEX_FULL)
2349 new_adv |= ADVERTISE_10FULL;
2350 else
2351 new_adv |= ADVERTISE_10HALF;
2352 }
2353 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2354
2355 new_adv = 0;
2356 }
2357
2358 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2359 }
2360
2361 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2362 tp->link_config.speed != SPEED_INVALID) {
2363 u32 bmcr, orig_bmcr;
2364
2365 tp->link_config.active_speed = tp->link_config.speed;
2366 tp->link_config.active_duplex = tp->link_config.duplex;
2367
2368 bmcr = 0;
2369 switch (tp->link_config.speed) {
2370 default:
2371 case SPEED_10:
2372 break;
2373
2374 case SPEED_100:
2375 bmcr |= BMCR_SPEED100;
2376 break;
2377
2378 case SPEED_1000:
2379 bmcr |= TG3_BMCR_SPEED1000;
2380 break;
2381 }
2382
2383 if (tp->link_config.duplex == DUPLEX_FULL)
2384 bmcr |= BMCR_FULLDPLX;
2385
2386 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2387 (bmcr != orig_bmcr)) {
2388 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2389 for (i = 0; i < 1500; i++) {
2390 u32 tmp;
2391
2392 udelay(10);
2393 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2394 tg3_readphy(tp, MII_BMSR, &tmp))
2395 continue;
2396 if (!(tmp & BMSR_LSTATUS)) {
2397 udelay(40);
2398 break;
2399 }
2400 }
2401 tg3_writephy(tp, MII_BMCR, bmcr);
2402 udelay(40);
2403 }
2404 } else {
2405 tg3_writephy(tp, MII_BMCR,
2406 BMCR_ANENABLE | BMCR_ANRESTART);
2407 }
2408 }
2409
2410 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2411 {
2412 int err;
2413
2414 /* Turn off tap power management. */
2415 /* Set Extended packet length bit */
2416 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2417
2418 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2419 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2420
2421 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2422 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2423
2424 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2425 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2426
2427 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2428 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2429
2430 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2431 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2432
2433 udelay(40);
2434
2435 return err;
2436 }
2437
2438 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2439 {
2440 u32 adv_reg, all_mask = 0;
2441
2442 if (mask & ADVERTISED_10baseT_Half)
2443 all_mask |= ADVERTISE_10HALF;
2444 if (mask & ADVERTISED_10baseT_Full)
2445 all_mask |= ADVERTISE_10FULL;
2446 if (mask & ADVERTISED_100baseT_Half)
2447 all_mask |= ADVERTISE_100HALF;
2448 if (mask & ADVERTISED_100baseT_Full)
2449 all_mask |= ADVERTISE_100FULL;
2450
2451 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2452 return 0;
2453
2454 if ((adv_reg & all_mask) != all_mask)
2455 return 0;
2456 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2457 u32 tg3_ctrl;
2458
2459 all_mask = 0;
2460 if (mask & ADVERTISED_1000baseT_Half)
2461 all_mask |= ADVERTISE_1000HALF;
2462 if (mask & ADVERTISED_1000baseT_Full)
2463 all_mask |= ADVERTISE_1000FULL;
2464
2465 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2466 return 0;
2467
2468 if ((tg3_ctrl & all_mask) != all_mask)
2469 return 0;
2470 }
2471 return 1;
2472 }
2473
2474 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2475 {
2476 u32 curadv, reqadv;
2477
2478 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2479 return 1;
2480
2481 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2482 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2483
2484 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2485 if (curadv != reqadv)
2486 return 0;
2487
2488 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2489 tg3_readphy(tp, MII_LPA, rmtadv);
2490 } else {
2491 /* Reprogram the advertisement register, even if it
2492 * does not affect the current link. If the link
2493 * gets renegotiated in the future, we can save an
2494 * additional renegotiation cycle by advertising
2495 * it correctly in the first place.
2496 */
2497 if (curadv != reqadv) {
2498 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2499 ADVERTISE_PAUSE_ASYM);
2500 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2501 }
2502 }
2503
2504 return 1;
2505 }
2506
2507 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2508 {
2509 int current_link_up;
2510 u32 bmsr, dummy;
2511 u32 lcl_adv, rmt_adv;
2512 u16 current_speed;
2513 u8 current_duplex;
2514 int i, err;
2515
2516 tw32(MAC_EVENT, 0);
2517
2518 tw32_f(MAC_STATUS,
2519 (MAC_STATUS_SYNC_CHANGED |
2520 MAC_STATUS_CFG_CHANGED |
2521 MAC_STATUS_MI_COMPLETION |
2522 MAC_STATUS_LNKSTATE_CHANGED));
2523 udelay(40);
2524
2525 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2526 tw32_f(MAC_MI_MODE,
2527 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2528 udelay(80);
2529 }
2530
2531 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2532
2533 /* Some third-party PHYs need to be reset on link going
2534 * down.
2535 */
2536 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2537 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2538 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2539 netif_carrier_ok(tp->dev)) {
2540 tg3_readphy(tp, MII_BMSR, &bmsr);
2541 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2542 !(bmsr & BMSR_LSTATUS))
2543 force_reset = 1;
2544 }
2545 if (force_reset)
2546 tg3_phy_reset(tp);
2547
2548 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2549 tg3_readphy(tp, MII_BMSR, &bmsr);
2550 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2551 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2552 bmsr = 0;
2553
2554 if (!(bmsr & BMSR_LSTATUS)) {
2555 err = tg3_init_5401phy_dsp(tp);
2556 if (err)
2557 return err;
2558
2559 tg3_readphy(tp, MII_BMSR, &bmsr);
2560 for (i = 0; i < 1000; i++) {
2561 udelay(10);
2562 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2563 (bmsr & BMSR_LSTATUS)) {
2564 udelay(40);
2565 break;
2566 }
2567 }
2568
2569 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2570 !(bmsr & BMSR_LSTATUS) &&
2571 tp->link_config.active_speed == SPEED_1000) {
2572 err = tg3_phy_reset(tp);
2573 if (!err)
2574 err = tg3_init_5401phy_dsp(tp);
2575 if (err)
2576 return err;
2577 }
2578 }
2579 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2580 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2581 /* 5701 {A0,B0} CRC bug workaround */
2582 tg3_writephy(tp, 0x15, 0x0a75);
2583 tg3_writephy(tp, 0x1c, 0x8c68);
2584 tg3_writephy(tp, 0x1c, 0x8d68);
2585 tg3_writephy(tp, 0x1c, 0x8c68);
2586 }
2587
2588 /* Clear pending interrupts... */
2589 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2590 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2591
2592 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2593 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
2594 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
2595 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2596
2597 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2598 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2599 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
2600 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2601 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
2602 else
2603 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
2604 }
2605
2606 current_link_up = 0;
2607 current_speed = SPEED_INVALID;
2608 current_duplex = DUPLEX_INVALID;
2609
2610 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
2611 u32 val;
2612
2613 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
2614 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
2615 if (!(val & (1 << 10))) {
2616 val |= (1 << 10);
2617 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2618 goto relink;
2619 }
2620 }
2621
2622 bmsr = 0;
2623 for (i = 0; i < 100; i++) {
2624 tg3_readphy(tp, MII_BMSR, &bmsr);
2625 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2626 (bmsr & BMSR_LSTATUS))
2627 break;
2628 udelay(40);
2629 }
2630
2631 if (bmsr & BMSR_LSTATUS) {
2632 u32 aux_stat, bmcr;
2633
2634 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
2635 for (i = 0; i < 2000; i++) {
2636 udelay(10);
2637 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
2638 aux_stat)
2639 break;
2640 }
2641
2642 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
2643 &current_speed,
2644 &current_duplex);
2645
2646 bmcr = 0;
2647 for (i = 0; i < 200; i++) {
2648 tg3_readphy(tp, MII_BMCR, &bmcr);
2649 if (tg3_readphy(tp, MII_BMCR, &bmcr))
2650 continue;
2651 if (bmcr && bmcr != 0x7fff)
2652 break;
2653 udelay(10);
2654 }
2655
2656 lcl_adv = 0;
2657 rmt_adv = 0;
2658
2659 tp->link_config.active_speed = current_speed;
2660 tp->link_config.active_duplex = current_duplex;
2661
2662 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2663 if ((bmcr & BMCR_ANENABLE) &&
2664 tg3_copper_is_advertising_all(tp,
2665 tp->link_config.advertising)) {
2666 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
2667 &rmt_adv))
2668 current_link_up = 1;
2669 }
2670 } else {
2671 if (!(bmcr & BMCR_ANENABLE) &&
2672 tp->link_config.speed == current_speed &&
2673 tp->link_config.duplex == current_duplex &&
2674 tp->link_config.flowctrl ==
2675 tp->link_config.active_flowctrl) {
2676 current_link_up = 1;
2677 }
2678 }
2679
2680 if (current_link_up == 1 &&
2681 tp->link_config.active_duplex == DUPLEX_FULL)
2682 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2683 }
2684
2685 relink:
2686 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
2687 u32 tmp;
2688
2689 tg3_phy_copper_begin(tp);
2690
2691 tg3_readphy(tp, MII_BMSR, &tmp);
2692 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
2693 (tmp & BMSR_LSTATUS))
2694 current_link_up = 1;
2695 }
2696
2697 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2698 if (current_link_up == 1) {
2699 if (tp->link_config.active_speed == SPEED_100 ||
2700 tp->link_config.active_speed == SPEED_10)
2701 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2702 else
2703 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2704 } else
2705 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2706
2707 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2708 if (tp->link_config.active_duplex == DUPLEX_HALF)
2709 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2710
2711 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
2712 if (current_link_up == 1 &&
2713 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
2714 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2715 else
2716 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2717 }
2718
2719 /* ??? Without this setting Netgear GA302T PHY does not
2720 * ??? send/receive packets...
2721 */
2722 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2723 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2724 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2725 tw32_f(MAC_MI_MODE, tp->mi_mode);
2726 udelay(80);
2727 }
2728
2729 tw32_f(MAC_MODE, tp->mac_mode);
2730 udelay(40);
2731
2732 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2733 /* Polled via timer. */
2734 tw32_f(MAC_EVENT, 0);
2735 } else {
2736 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2737 }
2738 udelay(40);
2739
2740 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2741 current_link_up == 1 &&
2742 tp->link_config.active_speed == SPEED_1000 &&
2743 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2744 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2745 udelay(120);
2746 tw32_f(MAC_STATUS,
2747 (MAC_STATUS_SYNC_CHANGED |
2748 MAC_STATUS_CFG_CHANGED));
2749 udelay(40);
2750 tg3_write_mem(tp,
2751 NIC_SRAM_FIRMWARE_MBOX,
2752 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2753 }
2754
2755 if (current_link_up != netif_carrier_ok(tp->dev)) {
2756 if (current_link_up)
2757 netif_carrier_on(tp->dev);
2758 else
2759 netif_carrier_off(tp->dev);
2760 tg3_link_report(tp);
2761 }
2762
2763 return 0;
2764 }
2765
2766 struct tg3_fiber_aneginfo {
2767 int state;
2768 #define ANEG_STATE_UNKNOWN 0
2769 #define ANEG_STATE_AN_ENABLE 1
2770 #define ANEG_STATE_RESTART_INIT 2
2771 #define ANEG_STATE_RESTART 3
2772 #define ANEG_STATE_DISABLE_LINK_OK 4
2773 #define ANEG_STATE_ABILITY_DETECT_INIT 5
2774 #define ANEG_STATE_ABILITY_DETECT 6
2775 #define ANEG_STATE_ACK_DETECT_INIT 7
2776 #define ANEG_STATE_ACK_DETECT 8
2777 #define ANEG_STATE_COMPLETE_ACK_INIT 9
2778 #define ANEG_STATE_COMPLETE_ACK 10
2779 #define ANEG_STATE_IDLE_DETECT_INIT 11
2780 #define ANEG_STATE_IDLE_DETECT 12
2781 #define ANEG_STATE_LINK_OK 13
2782 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
2783 #define ANEG_STATE_NEXT_PAGE_WAIT 15
2784
2785 u32 flags;
2786 #define MR_AN_ENABLE 0x00000001
2787 #define MR_RESTART_AN 0x00000002
2788 #define MR_AN_COMPLETE 0x00000004
2789 #define MR_PAGE_RX 0x00000008
2790 #define MR_NP_LOADED 0x00000010
2791 #define MR_TOGGLE_TX 0x00000020
2792 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
2793 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
2794 #define MR_LP_ADV_SYM_PAUSE 0x00000100
2795 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
2796 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2797 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2798 #define MR_LP_ADV_NEXT_PAGE 0x00001000
2799 #define MR_TOGGLE_RX 0x00002000
2800 #define MR_NP_RX 0x00004000
2801
2802 #define MR_LINK_OK 0x80000000
2803
2804 unsigned long link_time, cur_time;
2805
2806 u32 ability_match_cfg;
2807 int ability_match_count;
2808
2809 char ability_match, idle_match, ack_match;
2810
2811 u32 txconfig, rxconfig;
2812 #define ANEG_CFG_NP 0x00000080
2813 #define ANEG_CFG_ACK 0x00000040
2814 #define ANEG_CFG_RF2 0x00000020
2815 #define ANEG_CFG_RF1 0x00000010
2816 #define ANEG_CFG_PS2 0x00000001
2817 #define ANEG_CFG_PS1 0x00008000
2818 #define ANEG_CFG_HD 0x00004000
2819 #define ANEG_CFG_FD 0x00002000
2820 #define ANEG_CFG_INVAL 0x00001f06
2821
2822 };
2823 #define ANEG_OK 0
2824 #define ANEG_DONE 1
2825 #define ANEG_TIMER_ENAB 2
2826 #define ANEG_FAILED -1
2827
2828 #define ANEG_STATE_SETTLE_TIME 10000
2829
2830 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2831 struct tg3_fiber_aneginfo *ap)
2832 {
2833 u16 flowctrl;
2834 unsigned long delta;
2835 u32 rx_cfg_reg;
2836 int ret;
2837
2838 if (ap->state == ANEG_STATE_UNKNOWN) {
2839 ap->rxconfig = 0;
2840 ap->link_time = 0;
2841 ap->cur_time = 0;
2842 ap->ability_match_cfg = 0;
2843 ap->ability_match_count = 0;
2844 ap->ability_match = 0;
2845 ap->idle_match = 0;
2846 ap->ack_match = 0;
2847 }
2848 ap->cur_time++;
2849
2850 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2851 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2852
2853 if (rx_cfg_reg != ap->ability_match_cfg) {
2854 ap->ability_match_cfg = rx_cfg_reg;
2855 ap->ability_match = 0;
2856 ap->ability_match_count = 0;
2857 } else {
2858 if (++ap->ability_match_count > 1) {
2859 ap->ability_match = 1;
2860 ap->ability_match_cfg = rx_cfg_reg;
2861 }
2862 }
2863 if (rx_cfg_reg & ANEG_CFG_ACK)
2864 ap->ack_match = 1;
2865 else
2866 ap->ack_match = 0;
2867
2868 ap->idle_match = 0;
2869 } else {
2870 ap->idle_match = 1;
2871 ap->ability_match_cfg = 0;
2872 ap->ability_match_count = 0;
2873 ap->ability_match = 0;
2874 ap->ack_match = 0;
2875
2876 rx_cfg_reg = 0;
2877 }
2878
2879 ap->rxconfig = rx_cfg_reg;
2880 ret = ANEG_OK;
2881
2882 switch(ap->state) {
2883 case ANEG_STATE_UNKNOWN:
2884 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2885 ap->state = ANEG_STATE_AN_ENABLE;
2886
2887 /* fallthru */
2888 case ANEG_STATE_AN_ENABLE:
2889 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2890 if (ap->flags & MR_AN_ENABLE) {
2891 ap->link_time = 0;
2892 ap->cur_time = 0;
2893 ap->ability_match_cfg = 0;
2894 ap->ability_match_count = 0;
2895 ap->ability_match = 0;
2896 ap->idle_match = 0;
2897 ap->ack_match = 0;
2898
2899 ap->state = ANEG_STATE_RESTART_INIT;
2900 } else {
2901 ap->state = ANEG_STATE_DISABLE_LINK_OK;
2902 }
2903 break;
2904
2905 case ANEG_STATE_RESTART_INIT:
2906 ap->link_time = ap->cur_time;
2907 ap->flags &= ~(MR_NP_LOADED);
2908 ap->txconfig = 0;
2909 tw32(MAC_TX_AUTO_NEG, 0);
2910 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2911 tw32_f(MAC_MODE, tp->mac_mode);
2912 udelay(40);
2913
2914 ret = ANEG_TIMER_ENAB;
2915 ap->state = ANEG_STATE_RESTART;
2916
2917 /* fallthru */
2918 case ANEG_STATE_RESTART:
2919 delta = ap->cur_time - ap->link_time;
2920 if (delta > ANEG_STATE_SETTLE_TIME) {
2921 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2922 } else {
2923 ret = ANEG_TIMER_ENAB;
2924 }
2925 break;
2926
2927 case ANEG_STATE_DISABLE_LINK_OK:
2928 ret = ANEG_DONE;
2929 break;
2930
2931 case ANEG_STATE_ABILITY_DETECT_INIT:
2932 ap->flags &= ~(MR_TOGGLE_TX);
2933 ap->txconfig = ANEG_CFG_FD;
2934 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
2935 if (flowctrl & ADVERTISE_1000XPAUSE)
2936 ap->txconfig |= ANEG_CFG_PS1;
2937 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
2938 ap->txconfig |= ANEG_CFG_PS2;
2939 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2940 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2941 tw32_f(MAC_MODE, tp->mac_mode);
2942 udelay(40);
2943
2944 ap->state = ANEG_STATE_ABILITY_DETECT;
2945 break;
2946
2947 case ANEG_STATE_ABILITY_DETECT:
2948 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2949 ap->state = ANEG_STATE_ACK_DETECT_INIT;
2950 }
2951 break;
2952
2953 case ANEG_STATE_ACK_DETECT_INIT:
2954 ap->txconfig |= ANEG_CFG_ACK;
2955 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2956 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2957 tw32_f(MAC_MODE, tp->mac_mode);
2958 udelay(40);
2959
2960 ap->state = ANEG_STATE_ACK_DETECT;
2961
2962 /* fallthru */
2963 case ANEG_STATE_ACK_DETECT:
2964 if (ap->ack_match != 0) {
2965 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2966 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2967 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2968 } else {
2969 ap->state = ANEG_STATE_AN_ENABLE;
2970 }
2971 } else if (ap->ability_match != 0 &&
2972 ap->rxconfig == 0) {
2973 ap->state = ANEG_STATE_AN_ENABLE;
2974 }
2975 break;
2976
2977 case ANEG_STATE_COMPLETE_ACK_INIT:
2978 if (ap->rxconfig & ANEG_CFG_INVAL) {
2979 ret = ANEG_FAILED;
2980 break;
2981 }
2982 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2983 MR_LP_ADV_HALF_DUPLEX |
2984 MR_LP_ADV_SYM_PAUSE |
2985 MR_LP_ADV_ASYM_PAUSE |
2986 MR_LP_ADV_REMOTE_FAULT1 |
2987 MR_LP_ADV_REMOTE_FAULT2 |
2988 MR_LP_ADV_NEXT_PAGE |
2989 MR_TOGGLE_RX |
2990 MR_NP_RX);
2991 if (ap->rxconfig & ANEG_CFG_FD)
2992 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2993 if (ap->rxconfig & ANEG_CFG_HD)
2994 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2995 if (ap->rxconfig & ANEG_CFG_PS1)
2996 ap->flags |= MR_LP_ADV_SYM_PAUSE;
2997 if (ap->rxconfig & ANEG_CFG_PS2)
2998 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2999 if (ap->rxconfig & ANEG_CFG_RF1)
3000 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3001 if (ap->rxconfig & ANEG_CFG_RF2)
3002 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3003 if (ap->rxconfig & ANEG_CFG_NP)
3004 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3005
3006 ap->link_time = ap->cur_time;
3007
3008 ap->flags ^= (MR_TOGGLE_TX);
3009 if (ap->rxconfig & 0x0008)
3010 ap->flags |= MR_TOGGLE_RX;
3011 if (ap->rxconfig & ANEG_CFG_NP)
3012 ap->flags |= MR_NP_RX;
3013 ap->flags |= MR_PAGE_RX;
3014
3015 ap->state = ANEG_STATE_COMPLETE_ACK;
3016 ret = ANEG_TIMER_ENAB;
3017 break;
3018
3019 case ANEG_STATE_COMPLETE_ACK:
3020 if (ap->ability_match != 0 &&
3021 ap->rxconfig == 0) {
3022 ap->state = ANEG_STATE_AN_ENABLE;
3023 break;
3024 }
3025 delta = ap->cur_time - ap->link_time;
3026 if (delta > ANEG_STATE_SETTLE_TIME) {
3027 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3028 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3029 } else {
3030 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3031 !(ap->flags & MR_NP_RX)) {
3032 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3033 } else {
3034 ret = ANEG_FAILED;
3035 }
3036 }
3037 }
3038 break;
3039
3040 case ANEG_STATE_IDLE_DETECT_INIT:
3041 ap->link_time = ap->cur_time;
3042 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3043 tw32_f(MAC_MODE, tp->mac_mode);
3044 udelay(40);
3045
3046 ap->state = ANEG_STATE_IDLE_DETECT;
3047 ret = ANEG_TIMER_ENAB;
3048 break;
3049
3050 case ANEG_STATE_IDLE_DETECT:
3051 if (ap->ability_match != 0 &&
3052 ap->rxconfig == 0) {
3053 ap->state = ANEG_STATE_AN_ENABLE;
3054 break;
3055 }
3056 delta = ap->cur_time - ap->link_time;
3057 if (delta > ANEG_STATE_SETTLE_TIME) {
3058 /* XXX another gem from the Broadcom driver :( */
3059 ap->state = ANEG_STATE_LINK_OK;
3060 }
3061 break;
3062
3063 case ANEG_STATE_LINK_OK:
3064 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3065 ret = ANEG_DONE;
3066 break;
3067
3068 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3069 /* ??? unimplemented */
3070 break;
3071
3072 case ANEG_STATE_NEXT_PAGE_WAIT:
3073 /* ??? unimplemented */
3074 break;
3075
3076 default:
3077 ret = ANEG_FAILED;
3078 break;
3079 }
3080
3081 return ret;
3082 }
3083
3084 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3085 {
3086 int res = 0;
3087 struct tg3_fiber_aneginfo aninfo;
3088 int status = ANEG_FAILED;
3089 unsigned int tick;
3090 u32 tmp;
3091
3092 tw32_f(MAC_TX_AUTO_NEG, 0);
3093
3094 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3095 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3096 udelay(40);
3097
3098 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3099 udelay(40);
3100
3101 memset(&aninfo, 0, sizeof(aninfo));
3102 aninfo.flags |= MR_AN_ENABLE;
3103 aninfo.state = ANEG_STATE_UNKNOWN;
3104 aninfo.cur_time = 0;
3105 tick = 0;
3106 while (++tick < 195000) {
3107 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3108 if (status == ANEG_DONE || status == ANEG_FAILED)
3109 break;
3110
3111 udelay(1);
3112 }
3113
3114 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3115 tw32_f(MAC_MODE, tp->mac_mode);
3116 udelay(40);
3117
3118 *txflags = aninfo.txconfig;
3119 *rxflags = aninfo.flags;
3120
3121 if (status == ANEG_DONE &&
3122 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3123 MR_LP_ADV_FULL_DUPLEX)))
3124 res = 1;
3125
3126 return res;
3127 }
3128
3129 static void tg3_init_bcm8002(struct tg3 *tp)
3130 {
3131 u32 mac_status = tr32(MAC_STATUS);
3132 int i;
3133
3134 /* Reset when initting first time or we have a link. */
3135 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3136 !(mac_status & MAC_STATUS_PCS_SYNCED))
3137 return;
3138
3139 /* Set PLL lock range. */
3140 tg3_writephy(tp, 0x16, 0x8007);
3141
3142 /* SW reset */
3143 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3144
3145 /* Wait for reset to complete. */
3146 /* XXX schedule_timeout() ... */
3147 for (i = 0; i < 500; i++)
3148 udelay(10);
3149
3150 /* Config mode; select PMA/Ch 1 regs. */
3151 tg3_writephy(tp, 0x10, 0x8411);
3152
3153 /* Enable auto-lock and comdet, select txclk for tx. */
3154 tg3_writephy(tp, 0x11, 0x0a10);
3155
3156 tg3_writephy(tp, 0x18, 0x00a0);
3157 tg3_writephy(tp, 0x16, 0x41ff);
3158
3159 /* Assert and deassert POR. */
3160 tg3_writephy(tp, 0x13, 0x0400);
3161 udelay(40);
3162 tg3_writephy(tp, 0x13, 0x0000);
3163
3164 tg3_writephy(tp, 0x11, 0x0a50);
3165 udelay(40);
3166 tg3_writephy(tp, 0x11, 0x0a10);
3167
3168 /* Wait for signal to stabilize */
3169 /* XXX schedule_timeout() ... */
3170 for (i = 0; i < 15000; i++)
3171 udelay(10);
3172
3173 /* Deselect the channel register so we can read the PHYID
3174 * later.
3175 */
3176 tg3_writephy(tp, 0x10, 0x8011);
3177 }
3178
3179 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3180 {
3181 u16 flowctrl;
3182 u32 sg_dig_ctrl, sg_dig_status;
3183 u32 serdes_cfg, expected_sg_dig_ctrl;
3184 int workaround, port_a;
3185 int current_link_up;
3186
3187 serdes_cfg = 0;
3188 expected_sg_dig_ctrl = 0;
3189 workaround = 0;
3190 port_a = 1;
3191 current_link_up = 0;
3192
3193 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3194 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3195 workaround = 1;
3196 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3197 port_a = 0;
3198
3199 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3200 /* preserve bits 20-23 for voltage regulator */
3201 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3202 }
3203
3204 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3205
3206 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3207 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3208 if (workaround) {
3209 u32 val = serdes_cfg;
3210
3211 if (port_a)
3212 val |= 0xc010000;
3213 else
3214 val |= 0x4010000;
3215 tw32_f(MAC_SERDES_CFG, val);
3216 }
3217
3218 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3219 }
3220 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3221 tg3_setup_flow_control(tp, 0, 0);
3222 current_link_up = 1;
3223 }
3224 goto out;
3225 }
3226
3227 /* Want auto-negotiation. */
3228 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3229
3230 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3231 if (flowctrl & ADVERTISE_1000XPAUSE)
3232 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3233 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3234 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3235
3236 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3237 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3238 tp->serdes_counter &&
3239 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3240 MAC_STATUS_RCVD_CFG)) ==
3241 MAC_STATUS_PCS_SYNCED)) {
3242 tp->serdes_counter--;
3243 current_link_up = 1;
3244 goto out;
3245 }
3246 restart_autoneg:
3247 if (workaround)
3248 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3249 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3250 udelay(5);
3251 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3252
3253 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3254 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3255 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3256 MAC_STATUS_SIGNAL_DET)) {
3257 sg_dig_status = tr32(SG_DIG_STATUS);
3258 mac_status = tr32(MAC_STATUS);
3259
3260 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3261 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3262 u32 local_adv = 0, remote_adv = 0;
3263
3264 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3265 local_adv |= ADVERTISE_1000XPAUSE;
3266 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3267 local_adv |= ADVERTISE_1000XPSE_ASYM;
3268
3269 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3270 remote_adv |= LPA_1000XPAUSE;
3271 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3272 remote_adv |= LPA_1000XPAUSE_ASYM;
3273
3274 tg3_setup_flow_control(tp, local_adv, remote_adv);
3275 current_link_up = 1;
3276 tp->serdes_counter = 0;
3277 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3278 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3279 if (tp->serdes_counter)
3280 tp->serdes_counter--;
3281 else {
3282 if (workaround) {
3283 u32 val = serdes_cfg;
3284
3285 if (port_a)
3286 val |= 0xc010000;
3287 else
3288 val |= 0x4010000;
3289
3290 tw32_f(MAC_SERDES_CFG, val);
3291 }
3292
3293 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3294 udelay(40);
3295
3296 /* Link parallel detection - link is up */
3297 /* only if we have PCS_SYNC and not */
3298 /* receiving config code words */
3299 mac_status = tr32(MAC_STATUS);
3300 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3301 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3302 tg3_setup_flow_control(tp, 0, 0);
3303 current_link_up = 1;
3304 tp->tg3_flags2 |=
3305 TG3_FLG2_PARALLEL_DETECT;
3306 tp->serdes_counter =
3307 SERDES_PARALLEL_DET_TIMEOUT;
3308 } else
3309 goto restart_autoneg;
3310 }
3311 }
3312 } else {
3313 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3314 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3315 }
3316
3317 out:
3318 return current_link_up;
3319 }
3320
3321 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3322 {
3323 int current_link_up = 0;
3324
3325 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3326 goto out;
3327
3328 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3329 u32 txflags, rxflags;
3330 int i;
3331
3332 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3333 u32 local_adv = 0, remote_adv = 0;
3334
3335 if (txflags & ANEG_CFG_PS1)
3336 local_adv |= ADVERTISE_1000XPAUSE;
3337 if (txflags & ANEG_CFG_PS2)
3338 local_adv |= ADVERTISE_1000XPSE_ASYM;
3339
3340 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3341 remote_adv |= LPA_1000XPAUSE;
3342 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3343 remote_adv |= LPA_1000XPAUSE_ASYM;
3344
3345 tg3_setup_flow_control(tp, local_adv, remote_adv);
3346
3347 current_link_up = 1;
3348 }
3349 for (i = 0; i < 30; i++) {
3350 udelay(20);
3351 tw32_f(MAC_STATUS,
3352 (MAC_STATUS_SYNC_CHANGED |
3353 MAC_STATUS_CFG_CHANGED));
3354 udelay(40);
3355 if ((tr32(MAC_STATUS) &
3356 (MAC_STATUS_SYNC_CHANGED |
3357 MAC_STATUS_CFG_CHANGED)) == 0)
3358 break;
3359 }
3360
3361 mac_status = tr32(MAC_STATUS);
3362 if (current_link_up == 0 &&
3363 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3364 !(mac_status & MAC_STATUS_RCVD_CFG))
3365 current_link_up = 1;
3366 } else {
3367 tg3_setup_flow_control(tp, 0, 0);
3368
3369 /* Forcing 1000FD link up. */
3370 current_link_up = 1;
3371
3372 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3373 udelay(40);
3374
3375 tw32_f(MAC_MODE, tp->mac_mode);
3376 udelay(40);
3377 }
3378
3379 out:
3380 return current_link_up;
3381 }
3382
3383 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3384 {
3385 u32 orig_pause_cfg;
3386 u16 orig_active_speed;
3387 u8 orig_active_duplex;
3388 u32 mac_status;
3389 int current_link_up;
3390 int i;
3391
3392 orig_pause_cfg = tp->link_config.active_flowctrl;
3393 orig_active_speed = tp->link_config.active_speed;
3394 orig_active_duplex = tp->link_config.active_duplex;
3395
3396 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3397 netif_carrier_ok(tp->dev) &&
3398 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3399 mac_status = tr32(MAC_STATUS);
3400 mac_status &= (MAC_STATUS_PCS_SYNCED |
3401 MAC_STATUS_SIGNAL_DET |
3402 MAC_STATUS_CFG_CHANGED |
3403 MAC_STATUS_RCVD_CFG);
3404 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3405 MAC_STATUS_SIGNAL_DET)) {
3406 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3407 MAC_STATUS_CFG_CHANGED));
3408 return 0;
3409 }
3410 }
3411
3412 tw32_f(MAC_TX_AUTO_NEG, 0);
3413
3414 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3415 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3416 tw32_f(MAC_MODE, tp->mac_mode);
3417 udelay(40);
3418
3419 if (tp->phy_id == PHY_ID_BCM8002)
3420 tg3_init_bcm8002(tp);
3421
3422 /* Enable link change event even when serdes polling. */
3423 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3424 udelay(40);
3425
3426 current_link_up = 0;
3427 mac_status = tr32(MAC_STATUS);
3428
3429 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3430 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3431 else
3432 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3433
3434 tp->hw_status->status =
3435 (SD_STATUS_UPDATED |
3436 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3437
3438 for (i = 0; i < 100; i++) {
3439 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3440 MAC_STATUS_CFG_CHANGED));
3441 udelay(5);
3442 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3443 MAC_STATUS_CFG_CHANGED |
3444 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3445 break;
3446 }
3447
3448 mac_status = tr32(MAC_STATUS);
3449 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3450 current_link_up = 0;
3451 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3452 tp->serdes_counter == 0) {
3453 tw32_f(MAC_MODE, (tp->mac_mode |
3454 MAC_MODE_SEND_CONFIGS));
3455 udelay(1);
3456 tw32_f(MAC_MODE, tp->mac_mode);
3457 }
3458 }
3459
3460 if (current_link_up == 1) {
3461 tp->link_config.active_speed = SPEED_1000;
3462 tp->link_config.active_duplex = DUPLEX_FULL;
3463 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3464 LED_CTRL_LNKLED_OVERRIDE |
3465 LED_CTRL_1000MBPS_ON));
3466 } else {
3467 tp->link_config.active_speed = SPEED_INVALID;
3468 tp->link_config.active_duplex = DUPLEX_INVALID;
3469 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3470 LED_CTRL_LNKLED_OVERRIDE |
3471 LED_CTRL_TRAFFIC_OVERRIDE));
3472 }
3473
3474 if (current_link_up != netif_carrier_ok(tp->dev)) {
3475 if (current_link_up)
3476 netif_carrier_on(tp->dev);
3477 else
3478 netif_carrier_off(tp->dev);
3479 tg3_link_report(tp);
3480 } else {
3481 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3482 if (orig_pause_cfg != now_pause_cfg ||
3483 orig_active_speed != tp->link_config.active_speed ||
3484 orig_active_duplex != tp->link_config.active_duplex)
3485 tg3_link_report(tp);
3486 }
3487
3488 return 0;
3489 }
3490
3491 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3492 {
3493 int current_link_up, err = 0;
3494 u32 bmsr, bmcr;
3495 u16 current_speed;
3496 u8 current_duplex;
3497 u32 local_adv, remote_adv;
3498
3499 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3500 tw32_f(MAC_MODE, tp->mac_mode);
3501 udelay(40);
3502
3503 tw32(MAC_EVENT, 0);
3504
3505 tw32_f(MAC_STATUS,
3506 (MAC_STATUS_SYNC_CHANGED |
3507 MAC_STATUS_CFG_CHANGED |
3508 MAC_STATUS_MI_COMPLETION |
3509 MAC_STATUS_LNKSTATE_CHANGED));
3510 udelay(40);
3511
3512 if (force_reset)
3513 tg3_phy_reset(tp);
3514
3515 current_link_up = 0;
3516 current_speed = SPEED_INVALID;
3517 current_duplex = DUPLEX_INVALID;
3518
3519 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3520 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3521 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3522 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3523 bmsr |= BMSR_LSTATUS;
3524 else
3525 bmsr &= ~BMSR_LSTATUS;
3526 }
3527
3528 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3529
3530 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
3531 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3532 /* do nothing, just check for link up at the end */
3533 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3534 u32 adv, new_adv;
3535
3536 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3537 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3538 ADVERTISE_1000XPAUSE |
3539 ADVERTISE_1000XPSE_ASYM |
3540 ADVERTISE_SLCT);
3541
3542 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3543
3544 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3545 new_adv |= ADVERTISE_1000XHALF;
3546 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3547 new_adv |= ADVERTISE_1000XFULL;
3548
3549 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3550 tg3_writephy(tp, MII_ADVERTISE, new_adv);
3551 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3552 tg3_writephy(tp, MII_BMCR, bmcr);
3553
3554 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3555 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
3556 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3557
3558 return err;
3559 }
3560 } else {
3561 u32 new_bmcr;
3562
3563 bmcr &= ~BMCR_SPEED1000;
3564 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3565
3566 if (tp->link_config.duplex == DUPLEX_FULL)
3567 new_bmcr |= BMCR_FULLDPLX;
3568
3569 if (new_bmcr != bmcr) {
3570 /* BMCR_SPEED1000 is a reserved bit that needs
3571 * to be set on write.
3572 */
3573 new_bmcr |= BMCR_SPEED1000;
3574
3575 /* Force a linkdown */
3576 if (netif_carrier_ok(tp->dev)) {
3577 u32 adv;
3578
3579 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3580 adv &= ~(ADVERTISE_1000XFULL |
3581 ADVERTISE_1000XHALF |
3582 ADVERTISE_SLCT);
3583 tg3_writephy(tp, MII_ADVERTISE, adv);
3584 tg3_writephy(tp, MII_BMCR, bmcr |
3585 BMCR_ANRESTART |
3586 BMCR_ANENABLE);
3587 udelay(10);
3588 netif_carrier_off(tp->dev);
3589 }
3590 tg3_writephy(tp, MII_BMCR, new_bmcr);
3591 bmcr = new_bmcr;
3592 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3593 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3594 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3595 ASIC_REV_5714) {
3596 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3597 bmsr |= BMSR_LSTATUS;
3598 else
3599 bmsr &= ~BMSR_LSTATUS;
3600 }
3601 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3602 }
3603 }
3604
3605 if (bmsr & BMSR_LSTATUS) {
3606 current_speed = SPEED_1000;
3607 current_link_up = 1;
3608 if (bmcr & BMCR_FULLDPLX)
3609 current_duplex = DUPLEX_FULL;
3610 else
3611 current_duplex = DUPLEX_HALF;
3612
3613 local_adv = 0;
3614 remote_adv = 0;
3615
3616 if (bmcr & BMCR_ANENABLE) {
3617 u32 common;
3618
3619 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
3620 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
3621 common = local_adv & remote_adv;
3622 if (common & (ADVERTISE_1000XHALF |
3623 ADVERTISE_1000XFULL)) {
3624 if (common & ADVERTISE_1000XFULL)
3625 current_duplex = DUPLEX_FULL;
3626 else
3627 current_duplex = DUPLEX_HALF;
3628 }
3629 else
3630 current_link_up = 0;
3631 }
3632 }
3633
3634 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
3635 tg3_setup_flow_control(tp, local_adv, remote_adv);
3636
3637 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3638 if (tp->link_config.active_duplex == DUPLEX_HALF)
3639 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3640
3641 tw32_f(MAC_MODE, tp->mac_mode);
3642 udelay(40);
3643
3644 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3645
3646 tp->link_config.active_speed = current_speed;
3647 tp->link_config.active_duplex = current_duplex;
3648
3649 if (current_link_up != netif_carrier_ok(tp->dev)) {
3650 if (current_link_up)
3651 netif_carrier_on(tp->dev);
3652 else {
3653 netif_carrier_off(tp->dev);
3654 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3655 }
3656 tg3_link_report(tp);
3657 }
3658 return err;
3659 }
3660
3661 static void tg3_serdes_parallel_detect(struct tg3 *tp)
3662 {
3663 if (tp->serdes_counter) {
3664 /* Give autoneg time to complete. */
3665 tp->serdes_counter--;
3666 return;
3667 }
3668 if (!netif_carrier_ok(tp->dev) &&
3669 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
3670 u32 bmcr;
3671
3672 tg3_readphy(tp, MII_BMCR, &bmcr);
3673 if (bmcr & BMCR_ANENABLE) {
3674 u32 phy1, phy2;
3675
3676 /* Select shadow register 0x1f */
3677 tg3_writephy(tp, 0x1c, 0x7c00);
3678 tg3_readphy(tp, 0x1c, &phy1);
3679
3680 /* Select expansion interrupt status register */
3681 tg3_writephy(tp, 0x17, 0x0f01);
3682 tg3_readphy(tp, 0x15, &phy2);
3683 tg3_readphy(tp, 0x15, &phy2);
3684
3685 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
3686 /* We have signal detect and not receiving
3687 * config code words, link is up by parallel
3688 * detection.
3689 */
3690
3691 bmcr &= ~BMCR_ANENABLE;
3692 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
3693 tg3_writephy(tp, MII_BMCR, bmcr);
3694 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
3695 }
3696 }
3697 }
3698 else if (netif_carrier_ok(tp->dev) &&
3699 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
3700 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3701 u32 phy2;
3702
3703 /* Select expansion interrupt status register */
3704 tg3_writephy(tp, 0x17, 0x0f01);
3705 tg3_readphy(tp, 0x15, &phy2);
3706 if (phy2 & 0x20) {
3707 u32 bmcr;
3708
3709 /* Config code words received, turn on autoneg. */
3710 tg3_readphy(tp, MII_BMCR, &bmcr);
3711 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
3712
3713 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3714
3715 }
3716 }
3717 }
3718
3719 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3720 {
3721 int err;
3722
3723 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3724 err = tg3_setup_fiber_phy(tp, force_reset);
3725 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
3726 err = tg3_setup_fiber_mii_phy(tp, force_reset);
3727 } else {
3728 err = tg3_setup_copper_phy(tp, force_reset);
3729 }
3730
3731 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
3732 tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
3733 u32 val, scale;
3734
3735 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
3736 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
3737 scale = 65;
3738 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
3739 scale = 6;
3740 else
3741 scale = 12;
3742
3743 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
3744 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
3745 tw32(GRC_MISC_CFG, val);
3746 }
3747
3748 if (tp->link_config.active_speed == SPEED_1000 &&
3749 tp->link_config.active_duplex == DUPLEX_HALF)
3750 tw32(MAC_TX_LENGTHS,
3751 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3752 (6 << TX_LENGTHS_IPG_SHIFT) |
3753 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3754 else
3755 tw32(MAC_TX_LENGTHS,
3756 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3757 (6 << TX_LENGTHS_IPG_SHIFT) |
3758 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3759
3760 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3761 if (netif_carrier_ok(tp->dev)) {
3762 tw32(HOSTCC_STAT_COAL_TICKS,
3763 tp->coal.stats_block_coalesce_usecs);
3764 } else {
3765 tw32(HOSTCC_STAT_COAL_TICKS, 0);
3766 }
3767 }
3768
3769 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3770 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3771 if (!netif_carrier_ok(tp->dev))
3772 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3773 tp->pwrmgmt_thresh;
3774 else
3775 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3776 tw32(PCIE_PWR_MGMT_THRESH, val);
3777 }
3778
3779 return err;
3780 }
3781
3782 /* This is called whenever we suspect that the system chipset is re-
3783 * ordering the sequence of MMIO to the tx send mailbox. The symptom
3784 * is bogus tx completions. We try to recover by setting the
3785 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3786 * in the workqueue.
3787 */
3788 static void tg3_tx_recover(struct tg3 *tp)
3789 {
3790 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3791 tp->write32_tx_mbox == tg3_write_indirect_mbox);
3792
3793 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3794 "mapped I/O cycles to the network device, attempting to "
3795 "recover. Please report the problem to the driver maintainer "
3796 "and include system chipset information.\n", tp->dev->name);
3797
3798 spin_lock(&tp->lock);
3799 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3800 spin_unlock(&tp->lock);
3801 }
3802
3803 static inline u32 tg3_tx_avail(struct tg3 *tp)
3804 {
3805 smp_mb();
3806 return (tp->tx_pending -
3807 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3808 }
3809
3810 /* Tigon3 never reports partial packet sends. So we do not
3811 * need special logic to handle SKBs that have not had all
3812 * of their frags sent yet, like SunGEM does.
3813 */
3814 static void tg3_tx(struct tg3 *tp)
3815 {
3816 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3817 u32 sw_idx = tp->tx_cons;
3818
3819 while (sw_idx != hw_idx) {
3820 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3821 struct sk_buff *skb = ri->skb;
3822 int i, tx_bug = 0;
3823
3824 if (unlikely(skb == NULL)) {
3825 tg3_tx_recover(tp);
3826 return;
3827 }
3828
3829 pci_unmap_single(tp->pdev,
3830 pci_unmap_addr(ri, mapping),
3831 skb_headlen(skb),
3832 PCI_DMA_TODEVICE);
3833
3834 ri->skb = NULL;
3835
3836 sw_idx = NEXT_TX(sw_idx);
3837
3838 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3839 ri = &tp->tx_buffers[sw_idx];
3840 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3841 tx_bug = 1;
3842
3843 pci_unmap_page(tp->pdev,
3844 pci_unmap_addr(ri, mapping),
3845 skb_shinfo(skb)->frags[i].size,
3846 PCI_DMA_TODEVICE);
3847
3848 sw_idx = NEXT_TX(sw_idx);
3849 }
3850
3851 dev_kfree_skb(skb);
3852
3853 if (unlikely(tx_bug)) {
3854 tg3_tx_recover(tp);
3855 return;
3856 }
3857 }
3858
3859 tp->tx_cons = sw_idx;
3860
3861 /* Need to make the tx_cons update visible to tg3_start_xmit()
3862 * before checking for netif_queue_stopped(). Without the
3863 * memory barrier, there is a small possibility that tg3_start_xmit()
3864 * will miss it and cause the queue to be stopped forever.
3865 */
3866 smp_mb();
3867
3868 if (unlikely(netif_queue_stopped(tp->dev) &&
3869 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3870 netif_tx_lock(tp->dev);
3871 if (netif_queue_stopped(tp->dev) &&
3872 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3873 netif_wake_queue(tp->dev);
3874 netif_tx_unlock(tp->dev);
3875 }
3876 }
3877
3878 /* Returns size of skb allocated or < 0 on error.
3879 *
3880 * We only need to fill in the address because the other members
3881 * of the RX descriptor are invariant, see tg3_init_rings.
3882 *
3883 * Note the purposeful assymetry of cpu vs. chip accesses. For
3884 * posting buffers we only dirty the first cache line of the RX
3885 * descriptor (containing the address). Whereas for the RX status
3886 * buffers the cpu only reads the last cacheline of the RX descriptor
3887 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3888 */
3889 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3890 int src_idx, u32 dest_idx_unmasked)
3891 {
3892 struct tg3_rx_buffer_desc *desc;
3893 struct ring_info *map, *src_map;
3894 struct sk_buff *skb;
3895 dma_addr_t mapping;
3896 int skb_size, dest_idx;
3897
3898 src_map = NULL;
3899 switch (opaque_key) {
3900 case RXD_OPAQUE_RING_STD:
3901 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3902 desc = &tp->rx_std[dest_idx];
3903 map = &tp->rx_std_buffers[dest_idx];
3904 if (src_idx >= 0)
3905 src_map = &tp->rx_std_buffers[src_idx];
3906 skb_size = tp->rx_pkt_buf_sz;
3907 break;
3908
3909 case RXD_OPAQUE_RING_JUMBO:
3910 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3911 desc = &tp->rx_jumbo[dest_idx];
3912 map = &tp->rx_jumbo_buffers[dest_idx];
3913 if (src_idx >= 0)
3914 src_map = &tp->rx_jumbo_buffers[src_idx];
3915 skb_size = RX_JUMBO_PKT_BUF_SZ;
3916 break;
3917
3918 default:
3919 return -EINVAL;
3920 }
3921
3922 /* Do not overwrite any of the map or rp information
3923 * until we are sure we can commit to a new buffer.
3924 *
3925 * Callers depend upon this behavior and assume that
3926 * we leave everything unchanged if we fail.
3927 */
3928 skb = netdev_alloc_skb(tp->dev, skb_size);
3929 if (skb == NULL)
3930 return -ENOMEM;
3931
3932 skb_reserve(skb, tp->rx_offset);
3933
3934 mapping = pci_map_single(tp->pdev, skb->data,
3935 skb_size - tp->rx_offset,
3936 PCI_DMA_FROMDEVICE);
3937
3938 map->skb = skb;
3939 pci_unmap_addr_set(map, mapping, mapping);
3940
3941 if (src_map != NULL)
3942 src_map->skb = NULL;
3943
3944 desc->addr_hi = ((u64)mapping >> 32);
3945 desc->addr_lo = ((u64)mapping & 0xffffffff);
3946
3947 return skb_size;
3948 }
3949
3950 /* We only need to move over in the address because the other
3951 * members of the RX descriptor are invariant. See notes above
3952 * tg3_alloc_rx_skb for full details.
3953 */
3954 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3955 int src_idx, u32 dest_idx_unmasked)
3956 {
3957 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3958 struct ring_info *src_map, *dest_map;
3959 int dest_idx;
3960
3961 switch (opaque_key) {
3962 case RXD_OPAQUE_RING_STD:
3963 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3964 dest_desc = &tp->rx_std[dest_idx];
3965 dest_map = &tp->rx_std_buffers[dest_idx];
3966 src_desc = &tp->rx_std[src_idx];
3967 src_map = &tp->rx_std_buffers[src_idx];
3968 break;
3969
3970 case RXD_OPAQUE_RING_JUMBO:
3971 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3972 dest_desc = &tp->rx_jumbo[dest_idx];
3973 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3974 src_desc = &tp->rx_jumbo[src_idx];
3975 src_map = &tp->rx_jumbo_buffers[src_idx];
3976 break;
3977
3978 default:
3979 return;
3980 }
3981
3982 dest_map->skb = src_map->skb;
3983 pci_unmap_addr_set(dest_map, mapping,
3984 pci_unmap_addr(src_map, mapping));
3985 dest_desc->addr_hi = src_desc->addr_hi;
3986 dest_desc->addr_lo = src_desc->addr_lo;
3987
3988 src_map->skb = NULL;
3989 }
3990
3991 #if TG3_VLAN_TAG_USED
3992 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3993 {
3994 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3995 }
3996 #endif
3997
3998 /* The RX ring scheme is composed of multiple rings which post fresh
3999 * buffers to the chip, and one special ring the chip uses to report
4000 * status back to the host.
4001 *
4002 * The special ring reports the status of received packets to the
4003 * host. The chip does not write into the original descriptor the
4004 * RX buffer was obtained from. The chip simply takes the original
4005 * descriptor as provided by the host, updates the status and length
4006 * field, then writes this into the next status ring entry.
4007 *
4008 * Each ring the host uses to post buffers to the chip is described
4009 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4010 * it is first placed into the on-chip ram. When the packet's length
4011 * is known, it walks down the TG3_BDINFO entries to select the ring.
4012 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4013 * which is within the range of the new packet's length is chosen.
4014 *
4015 * The "separate ring for rx status" scheme may sound queer, but it makes
4016 * sense from a cache coherency perspective. If only the host writes
4017 * to the buffer post rings, and only the chip writes to the rx status
4018 * rings, then cache lines never move beyond shared-modified state.
4019 * If both the host and chip were to write into the same ring, cache line
4020 * eviction could occur since both entities want it in an exclusive state.
4021 */
4022 static int tg3_rx(struct tg3 *tp, int budget)
4023 {
4024 u32 work_mask, rx_std_posted = 0;
4025 u32 sw_idx = tp->rx_rcb_ptr;
4026 u16 hw_idx;
4027 int received;
4028
4029 hw_idx = tp->hw_status->idx[0].rx_producer;
4030 /*
4031 * We need to order the read of hw_idx and the read of
4032 * the opaque cookie.
4033 */
4034 rmb();
4035 work_mask = 0;
4036 received = 0;
4037 while (sw_idx != hw_idx && budget > 0) {
4038 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4039 unsigned int len;
4040 struct sk_buff *skb;
4041 dma_addr_t dma_addr;
4042 u32 opaque_key, desc_idx, *post_ptr;
4043
4044 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4045 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4046 if (opaque_key == RXD_OPAQUE_RING_STD) {
4047 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
4048 mapping);
4049 skb = tp->rx_std_buffers[desc_idx].skb;
4050 post_ptr = &tp->rx_std_ptr;
4051 rx_std_posted++;
4052 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4053 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
4054 mapping);
4055 skb = tp->rx_jumbo_buffers[desc_idx].skb;
4056 post_ptr = &tp->rx_jumbo_ptr;
4057 }
4058 else {
4059 goto next_pkt_nopost;
4060 }
4061
4062 work_mask |= opaque_key;
4063
4064 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4065 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4066 drop_it:
4067 tg3_recycle_rx(tp, opaque_key,
4068 desc_idx, *post_ptr);
4069 drop_it_no_recycle:
4070 /* Other statistics kept track of by card. */
4071 tp->net_stats.rx_dropped++;
4072 goto next_pkt;
4073 }
4074
4075 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
4076
4077 if (len > RX_COPY_THRESHOLD
4078 && tp->rx_offset == 2
4079 /* rx_offset != 2 iff this is a 5701 card running
4080 * in PCI-X mode [see tg3_get_invariants()] */
4081 ) {
4082 int skb_size;
4083
4084 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4085 desc_idx, *post_ptr);
4086 if (skb_size < 0)
4087 goto drop_it;
4088
4089 pci_unmap_single(tp->pdev, dma_addr,
4090 skb_size - tp->rx_offset,
4091 PCI_DMA_FROMDEVICE);
4092
4093 skb_put(skb, len);
4094 } else {
4095 struct sk_buff *copy_skb;
4096
4097 tg3_recycle_rx(tp, opaque_key,
4098 desc_idx, *post_ptr);
4099
4100 copy_skb = netdev_alloc_skb(tp->dev, len + 2);
4101 if (copy_skb == NULL)
4102 goto drop_it_no_recycle;
4103
4104 skb_reserve(copy_skb, 2);
4105 skb_put(copy_skb, len);
4106 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4107 skb_copy_from_linear_data(skb, copy_skb->data, len);
4108 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4109
4110 /* We'll reuse the original ring buffer. */
4111 skb = copy_skb;
4112 }
4113
4114 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4115 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4116 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4117 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4118 skb->ip_summed = CHECKSUM_UNNECESSARY;
4119 else
4120 skb->ip_summed = CHECKSUM_NONE;
4121
4122 skb->protocol = eth_type_trans(skb, tp->dev);
4123 #if TG3_VLAN_TAG_USED
4124 if (tp->vlgrp != NULL &&
4125 desc->type_flags & RXD_FLAG_VLAN) {
4126 tg3_vlan_rx(tp, skb,
4127 desc->err_vlan & RXD_VLAN_MASK);
4128 } else
4129 #endif
4130 netif_receive_skb(skb);
4131
4132 tp->dev->last_rx = jiffies;
4133 received++;
4134 budget--;
4135
4136 next_pkt:
4137 (*post_ptr)++;
4138
4139 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4140 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4141
4142 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4143 TG3_64BIT_REG_LOW, idx);
4144 work_mask &= ~RXD_OPAQUE_RING_STD;
4145 rx_std_posted = 0;
4146 }
4147 next_pkt_nopost:
4148 sw_idx++;
4149 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4150
4151 /* Refresh hw_idx to see if there is new work */
4152 if (sw_idx == hw_idx) {
4153 hw_idx = tp->hw_status->idx[0].rx_producer;
4154 rmb();
4155 }
4156 }
4157
4158 /* ACK the status ring. */
4159 tp->rx_rcb_ptr = sw_idx;
4160 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
4161
4162 /* Refill RX ring(s). */
4163 if (work_mask & RXD_OPAQUE_RING_STD) {
4164 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
4165 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4166 sw_idx);
4167 }
4168 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4169 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
4170 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4171 sw_idx);
4172 }
4173 mmiowb();
4174
4175 return received;
4176 }
4177
4178 static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
4179 {
4180 struct tg3_hw_status *sblk = tp->hw_status;
4181
4182 /* handle link change and other phy events */
4183 if (!(tp->tg3_flags &
4184 (TG3_FLAG_USE_LINKCHG_REG |
4185 TG3_FLAG_POLL_SERDES))) {
4186 if (sblk->status & SD_STATUS_LINK_CHG) {
4187 sblk->status = SD_STATUS_UPDATED |
4188 (sblk->status & ~SD_STATUS_LINK_CHG);
4189 spin_lock(&tp->lock);
4190 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4191 tw32_f(MAC_STATUS,
4192 (MAC_STATUS_SYNC_CHANGED |
4193 MAC_STATUS_CFG_CHANGED |
4194 MAC_STATUS_MI_COMPLETION |
4195 MAC_STATUS_LNKSTATE_CHANGED));
4196 udelay(40);
4197 } else
4198 tg3_setup_phy(tp, 0);
4199 spin_unlock(&tp->lock);
4200 }
4201 }
4202
4203 /* run TX completion thread */
4204 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
4205 tg3_tx(tp);
4206 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4207 return work_done;
4208 }
4209
4210 /* run RX thread, within the bounds set by NAPI.
4211 * All RX "locking" is done by ensuring outside
4212 * code synchronizes with tg3->napi.poll()
4213 */
4214 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
4215 work_done += tg3_rx(tp, budget - work_done);
4216
4217 return work_done;
4218 }
4219
4220 static int tg3_poll(struct napi_struct *napi, int budget)
4221 {
4222 struct tg3 *tp = container_of(napi, struct tg3, napi);
4223 int work_done = 0;
4224 struct tg3_hw_status *sblk = tp->hw_status;
4225
4226 while (1) {
4227 work_done = tg3_poll_work(tp, work_done, budget);
4228
4229 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4230 goto tx_recovery;
4231
4232 if (unlikely(work_done >= budget))
4233 break;
4234
4235 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4236 /* tp->last_tag is used in tg3_restart_ints() below
4237 * to tell the hw how much work has been processed,
4238 * so we must read it before checking for more work.
4239 */
4240 tp->last_tag = sblk->status_tag;
4241 rmb();
4242 } else
4243 sblk->status &= ~SD_STATUS_UPDATED;
4244
4245 if (likely(!tg3_has_work(tp))) {
4246 netif_rx_complete(tp->dev, napi);
4247 tg3_restart_ints(tp);
4248 break;
4249 }
4250 }
4251
4252 return work_done;
4253
4254 tx_recovery:
4255 /* work_done is guaranteed to be less than budget. */
4256 netif_rx_complete(tp->dev, napi);
4257 schedule_work(&tp->reset_task);
4258 return work_done;
4259 }
4260
4261 static void tg3_irq_quiesce(struct tg3 *tp)
4262 {
4263 BUG_ON(tp->irq_sync);
4264
4265 tp->irq_sync = 1;
4266 smp_mb();
4267
4268 synchronize_irq(tp->pdev->irq);
4269 }
4270
4271 static inline int tg3_irq_sync(struct tg3 *tp)
4272 {
4273 return tp->irq_sync;
4274 }
4275
4276 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4277 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4278 * with as well. Most of the time, this is not necessary except when
4279 * shutting down the device.
4280 */
4281 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4282 {
4283 spin_lock_bh(&tp->lock);
4284 if (irq_sync)
4285 tg3_irq_quiesce(tp);
4286 }
4287
4288 static inline void tg3_full_unlock(struct tg3 *tp)
4289 {
4290 spin_unlock_bh(&tp->lock);
4291 }
4292
4293 /* One-shot MSI handler - Chip automatically disables interrupt
4294 * after sending MSI so driver doesn't have to do it.
4295 */
4296 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4297 {
4298 struct net_device *dev = dev_id;
4299 struct tg3 *tp = netdev_priv(dev);
4300
4301 prefetch(tp->hw_status);
4302 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4303
4304 if (likely(!tg3_irq_sync(tp)))
4305 netif_rx_schedule(dev, &tp->napi);
4306
4307 return IRQ_HANDLED;
4308 }
4309
4310 /* MSI ISR - No need to check for interrupt sharing and no need to
4311 * flush status block and interrupt mailbox. PCI ordering rules
4312 * guarantee that MSI will arrive after the status block.
4313 */
4314 static irqreturn_t tg3_msi(int irq, void *dev_id)
4315 {
4316 struct net_device *dev = dev_id;
4317 struct tg3 *tp = netdev_priv(dev);
4318
4319 prefetch(tp->hw_status);
4320 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4321 /*
4322 * Writing any value to intr-mbox-0 clears PCI INTA# and
4323 * chip-internal interrupt pending events.
4324 * Writing non-zero to intr-mbox-0 additional tells the
4325 * NIC to stop sending us irqs, engaging "in-intr-handler"
4326 * event coalescing.
4327 */
4328 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4329 if (likely(!tg3_irq_sync(tp)))
4330 netif_rx_schedule(dev, &tp->napi);
4331
4332 return IRQ_RETVAL(1);
4333 }
4334
4335 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4336 {
4337 struct net_device *dev = dev_id;
4338 struct tg3 *tp = netdev_priv(dev);
4339 struct tg3_hw_status *sblk = tp->hw_status;
4340 unsigned int handled = 1;
4341
4342 /* In INTx mode, it is possible for the interrupt to arrive at
4343 * the CPU before the status block posted prior to the interrupt.
4344 * Reading the PCI State register will confirm whether the
4345 * interrupt is ours and will flush the status block.
4346 */
4347 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4348 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4349 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4350 handled = 0;
4351 goto out;
4352 }
4353 }
4354
4355 /*
4356 * Writing any value to intr-mbox-0 clears PCI INTA# and
4357 * chip-internal interrupt pending events.
4358 * Writing non-zero to intr-mbox-0 additional tells the
4359 * NIC to stop sending us irqs, engaging "in-intr-handler"
4360 * event coalescing.
4361 *
4362 * Flush the mailbox to de-assert the IRQ immediately to prevent
4363 * spurious interrupts. The flush impacts performance but
4364 * excessive spurious interrupts can be worse in some cases.
4365 */
4366 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4367 if (tg3_irq_sync(tp))
4368 goto out;
4369 sblk->status &= ~SD_STATUS_UPDATED;
4370 if (likely(tg3_has_work(tp))) {
4371 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4372 netif_rx_schedule(dev, &tp->napi);
4373 } else {
4374 /* No work, shared interrupt perhaps? re-enable
4375 * interrupts, and flush that PCI write
4376 */
4377 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4378 0x00000000);
4379 }
4380 out:
4381 return IRQ_RETVAL(handled);
4382 }
4383
4384 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4385 {
4386 struct net_device *dev = dev_id;
4387 struct tg3 *tp = netdev_priv(dev);
4388 struct tg3_hw_status *sblk = tp->hw_status;
4389 unsigned int handled = 1;
4390
4391 /* In INTx mode, it is possible for the interrupt to arrive at
4392 * the CPU before the status block posted prior to the interrupt.
4393 * Reading the PCI State register will confirm whether the
4394 * interrupt is ours and will flush the status block.
4395 */
4396 if (unlikely(sblk->status_tag == tp->last_tag)) {
4397 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4398 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4399 handled = 0;
4400 goto out;
4401 }
4402 }
4403
4404 /*
4405 * writing any value to intr-mbox-0 clears PCI INTA# and
4406 * chip-internal interrupt pending events.
4407 * writing non-zero to intr-mbox-0 additional tells the
4408 * NIC to stop sending us irqs, engaging "in-intr-handler"
4409 * event coalescing.
4410 *
4411 * Flush the mailbox to de-assert the IRQ immediately to prevent
4412 * spurious interrupts. The flush impacts performance but
4413 * excessive spurious interrupts can be worse in some cases.
4414 */
4415 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4416 if (tg3_irq_sync(tp))
4417 goto out;
4418 if (netif_rx_schedule_prep(dev, &tp->napi)) {
4419 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4420 /* Update last_tag to mark that this status has been
4421 * seen. Because interrupt may be shared, we may be
4422 * racing with tg3_poll(), so only update last_tag
4423 * if tg3_poll() is not scheduled.
4424 */
4425 tp->last_tag = sblk->status_tag;
4426 __netif_rx_schedule(dev, &tp->napi);
4427 }
4428 out:
4429 return IRQ_RETVAL(handled);
4430 }
4431
4432 /* ISR for interrupt test */
4433 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4434 {
4435 struct net_device *dev = dev_id;
4436 struct tg3 *tp = netdev_priv(dev);
4437 struct tg3_hw_status *sblk = tp->hw_status;
4438
4439 if ((sblk->status & SD_STATUS_UPDATED) ||
4440 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4441 tg3_disable_ints(tp);
4442 return IRQ_RETVAL(1);
4443 }
4444 return IRQ_RETVAL(0);
4445 }
4446
4447 static int tg3_init_hw(struct tg3 *, int);
4448 static int tg3_halt(struct tg3 *, int, int);
4449
4450 /* Restart hardware after configuration changes, self-test, etc.
4451 * Invoked with tp->lock held.
4452 */
4453 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4454 __releases(tp->lock)
4455 __acquires(tp->lock)
4456 {
4457 int err;
4458
4459 err = tg3_init_hw(tp, reset_phy);
4460 if (err) {
4461 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4462 "aborting.\n", tp->dev->name);
4463 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4464 tg3_full_unlock(tp);
4465 del_timer_sync(&tp->timer);
4466 tp->irq_sync = 0;
4467 napi_enable(&tp->napi);
4468 dev_close(tp->dev);
4469 tg3_full_lock(tp, 0);
4470 }
4471 return err;
4472 }
4473
4474 #ifdef CONFIG_NET_POLL_CONTROLLER
4475 static void tg3_poll_controller(struct net_device *dev)
4476 {
4477 struct tg3 *tp = netdev_priv(dev);
4478
4479 tg3_interrupt(tp->pdev->irq, dev);
4480 }
4481 #endif
4482
4483 static void tg3_reset_task(struct work_struct *work)
4484 {
4485 struct tg3 *tp = container_of(work, struct tg3, reset_task);
4486 int err;
4487 unsigned int restart_timer;
4488
4489 tg3_full_lock(tp, 0);
4490
4491 if (!netif_running(tp->dev)) {
4492 tg3_full_unlock(tp);
4493 return;
4494 }
4495
4496 tg3_full_unlock(tp);
4497
4498 tg3_phy_stop(tp);
4499
4500 tg3_netif_stop(tp);
4501
4502 tg3_full_lock(tp, 1);
4503
4504 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4505 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4506
4507 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4508 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4509 tp->write32_rx_mbox = tg3_write_flush_reg32;
4510 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4511 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4512 }
4513
4514 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4515 err = tg3_init_hw(tp, 1);
4516 if (err)
4517 goto out;
4518
4519 tg3_netif_start(tp);
4520
4521 if (restart_timer)
4522 mod_timer(&tp->timer, jiffies + 1);
4523
4524 out:
4525 tg3_full_unlock(tp);
4526
4527 if (!err)
4528 tg3_phy_start(tp);
4529 }
4530
4531 static void tg3_dump_short_state(struct tg3 *tp)
4532 {
4533 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4534 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4535 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4536 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4537 }
4538
4539 static void tg3_tx_timeout(struct net_device *dev)
4540 {
4541 struct tg3 *tp = netdev_priv(dev);
4542
4543 if (netif_msg_tx_err(tp)) {
4544 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4545 dev->name);
4546 tg3_dump_short_state(tp);
4547 }
4548
4549 schedule_work(&tp->reset_task);
4550 }
4551
4552 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4553 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4554 {
4555 u32 base = (u32) mapping & 0xffffffff;
4556
4557 return ((base > 0xffffdcc0) &&
4558 (base + len + 8 < base));
4559 }
4560
4561 /* Test for DMA addresses > 40-bit */
4562 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4563 int len)
4564 {
4565 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
4566 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
4567 return (((u64) mapping + len) > DMA_40BIT_MASK);
4568 return 0;
4569 #else
4570 return 0;
4571 #endif
4572 }
4573
4574 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
4575
4576 /* Workaround 4GB and 40-bit hardware DMA bugs. */
4577 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
4578 u32 last_plus_one, u32 *start,
4579 u32 base_flags, u32 mss)
4580 {
4581 struct sk_buff *new_skb;
4582 dma_addr_t new_addr = 0;
4583 u32 entry = *start;
4584 int i, ret = 0;
4585
4586 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
4587 new_skb = skb_copy(skb, GFP_ATOMIC);
4588 else {
4589 int more_headroom = 4 - ((unsigned long)skb->data & 3);
4590
4591 new_skb = skb_copy_expand(skb,
4592 skb_headroom(skb) + more_headroom,
4593 skb_tailroom(skb), GFP_ATOMIC);
4594 }
4595
4596 if (!new_skb) {
4597 ret = -1;
4598 } else {
4599 /* New SKB is guaranteed to be linear. */
4600 entry = *start;
4601 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
4602 PCI_DMA_TODEVICE);
4603 /* Make sure new skb does not cross any 4G boundaries.
4604 * Drop the packet if it does.
4605 */
4606 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
4607 ret = -1;
4608 dev_kfree_skb(new_skb);
4609 new_skb = NULL;
4610 } else {
4611 tg3_set_txd(tp, entry, new_addr, new_skb->len,
4612 base_flags, 1 | (mss << 1));
4613 *start = NEXT_TX(entry);
4614 }
4615 }
4616
4617 /* Now clean up the sw ring entries. */
4618 i = 0;
4619 while (entry != last_plus_one) {
4620 int len;
4621
4622 if (i == 0)
4623 len = skb_headlen(skb);
4624 else
4625 len = skb_shinfo(skb)->frags[i-1].size;
4626 pci_unmap_single(tp->pdev,
4627 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
4628 len, PCI_DMA_TODEVICE);
4629 if (i == 0) {
4630 tp->tx_buffers[entry].skb = new_skb;
4631 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
4632 } else {
4633 tp->tx_buffers[entry].skb = NULL;
4634 }
4635 entry = NEXT_TX(entry);
4636 i++;
4637 }
4638
4639 dev_kfree_skb(skb);
4640
4641 return ret;
4642 }
4643
4644 static void tg3_set_txd(struct tg3 *tp, int entry,
4645 dma_addr_t mapping, int len, u32 flags,
4646 u32 mss_and_is_end)
4647 {
4648 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
4649 int is_end = (mss_and_is_end & 0x1);
4650 u32 mss = (mss_and_is_end >> 1);
4651 u32 vlan_tag = 0;
4652
4653 if (is_end)
4654 flags |= TXD_FLAG_END;
4655 if (flags & TXD_FLAG_VLAN) {
4656 vlan_tag = flags >> 16;
4657 flags &= 0xffff;
4658 }
4659 vlan_tag |= (mss << TXD_MSS_SHIFT);
4660
4661 txd->addr_hi = ((u64) mapping >> 32);
4662 txd->addr_lo = ((u64) mapping & 0xffffffff);
4663 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
4664 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
4665 }
4666
4667 /* hard_start_xmit for devices that don't have any bugs and
4668 * support TG3_FLG2_HW_TSO_2 only.
4669 */
4670 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
4671 {
4672 struct tg3 *tp = netdev_priv(dev);
4673 dma_addr_t mapping;
4674 u32 len, entry, base_flags, mss;
4675
4676 len = skb_headlen(skb);
4677
4678 /* We are running in BH disabled context with netif_tx_lock
4679 * and TX reclaim runs via tp->napi.poll inside of a software
4680 * interrupt. Furthermore, IRQ processing runs lockless so we have
4681 * no IRQ context deadlocks to worry about either. Rejoice!
4682 */
4683 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4684 if (!netif_queue_stopped(dev)) {
4685 netif_stop_queue(dev);
4686
4687 /* This is a hard error, log it. */
4688 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4689 "queue awake!\n", dev->name);
4690 }
4691 return NETDEV_TX_BUSY;
4692 }
4693
4694 entry = tp->tx_prod;
4695 base_flags = 0;
4696 mss = 0;
4697 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4698 int tcp_opt_len, ip_tcp_len;
4699
4700 if (skb_header_cloned(skb) &&
4701 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4702 dev_kfree_skb(skb);
4703 goto out_unlock;
4704 }
4705
4706 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
4707 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
4708 else {
4709 struct iphdr *iph = ip_hdr(skb);
4710
4711 tcp_opt_len = tcp_optlen(skb);
4712 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4713
4714 iph->check = 0;
4715 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
4716 mss |= (ip_tcp_len + tcp_opt_len) << 9;
4717 }
4718
4719 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4720 TXD_FLAG_CPU_POST_DMA);
4721
4722 tcp_hdr(skb)->check = 0;
4723
4724 }
4725 else if (skb->ip_summed == CHECKSUM_PARTIAL)
4726 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4727 #if TG3_VLAN_TAG_USED
4728 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4729 base_flags |= (TXD_FLAG_VLAN |
4730 (vlan_tx_tag_get(skb) << 16));
4731 #endif
4732
4733 /* Queue skb data, a.k.a. the main skb fragment. */
4734 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4735
4736 tp->tx_buffers[entry].skb = skb;
4737 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4738
4739 tg3_set_txd(tp, entry, mapping, len, base_flags,
4740 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4741
4742 entry = NEXT_TX(entry);
4743
4744 /* Now loop through additional data fragments, and queue them. */
4745 if (skb_shinfo(skb)->nr_frags > 0) {
4746 unsigned int i, last;
4747
4748 last = skb_shinfo(skb)->nr_frags - 1;
4749 for (i = 0; i <= last; i++) {
4750 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4751
4752 len = frag->size;
4753 mapping = pci_map_page(tp->pdev,
4754 frag->page,
4755 frag->page_offset,
4756 len, PCI_DMA_TODEVICE);
4757
4758 tp->tx_buffers[entry].skb = NULL;
4759 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4760
4761 tg3_set_txd(tp, entry, mapping, len,
4762 base_flags, (i == last) | (mss << 1));
4763
4764 entry = NEXT_TX(entry);
4765 }
4766 }
4767
4768 /* Packets are ready, update Tx producer idx local and on card. */
4769 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4770
4771 tp->tx_prod = entry;
4772 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4773 netif_stop_queue(dev);
4774 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4775 netif_wake_queue(tp->dev);
4776 }
4777
4778 out_unlock:
4779 mmiowb();
4780
4781 dev->trans_start = jiffies;
4782
4783 return NETDEV_TX_OK;
4784 }
4785
4786 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
4787
4788 /* Use GSO to workaround a rare TSO bug that may be triggered when the
4789 * TSO header is greater than 80 bytes.
4790 */
4791 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
4792 {
4793 struct sk_buff *segs, *nskb;
4794
4795 /* Estimate the number of fragments in the worst case */
4796 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
4797 netif_stop_queue(tp->dev);
4798 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4799 return NETDEV_TX_BUSY;
4800
4801 netif_wake_queue(tp->dev);
4802 }
4803
4804 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4805 if (IS_ERR(segs))
4806 goto tg3_tso_bug_end;
4807
4808 do {
4809 nskb = segs;
4810 segs = segs->next;
4811 nskb->next = NULL;
4812 tg3_start_xmit_dma_bug(nskb, tp->dev);
4813 } while (segs);
4814
4815 tg3_tso_bug_end:
4816 dev_kfree_skb(skb);
4817
4818 return NETDEV_TX_OK;
4819 }
4820
4821 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4822 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4823 */
4824 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4825 {
4826 struct tg3 *tp = netdev_priv(dev);
4827 dma_addr_t mapping;
4828 u32 len, entry, base_flags, mss;
4829 int would_hit_hwbug;
4830
4831 len = skb_headlen(skb);
4832
4833 /* We are running in BH disabled context with netif_tx_lock
4834 * and TX reclaim runs via tp->napi.poll inside of a software
4835 * interrupt. Furthermore, IRQ processing runs lockless so we have
4836 * no IRQ context deadlocks to worry about either. Rejoice!
4837 */
4838 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4839 if (!netif_queue_stopped(dev)) {
4840 netif_stop_queue(dev);
4841
4842 /* This is a hard error, log it. */
4843 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4844 "queue awake!\n", dev->name);
4845 }
4846 return NETDEV_TX_BUSY;
4847 }
4848
4849 entry = tp->tx_prod;
4850 base_flags = 0;
4851 if (skb->ip_summed == CHECKSUM_PARTIAL)
4852 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4853 mss = 0;
4854 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4855 struct iphdr *iph;
4856 int tcp_opt_len, ip_tcp_len, hdr_len;
4857
4858 if (skb_header_cloned(skb) &&
4859 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4860 dev_kfree_skb(skb);
4861 goto out_unlock;
4862 }
4863
4864 tcp_opt_len = tcp_optlen(skb);
4865 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4866
4867 hdr_len = ip_tcp_len + tcp_opt_len;
4868 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4869 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4870 return (tg3_tso_bug(tp, skb));
4871
4872 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4873 TXD_FLAG_CPU_POST_DMA);
4874
4875 iph = ip_hdr(skb);
4876 iph->check = 0;
4877 iph->tot_len = htons(mss + hdr_len);
4878 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4879 tcp_hdr(skb)->check = 0;
4880 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4881 } else
4882 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4883 iph->daddr, 0,
4884 IPPROTO_TCP,
4885 0);
4886
4887 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4888 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4889 if (tcp_opt_len || iph->ihl > 5) {
4890 int tsflags;
4891
4892 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4893 mss |= (tsflags << 11);
4894 }
4895 } else {
4896 if (tcp_opt_len || iph->ihl > 5) {
4897 int tsflags;
4898
4899 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4900 base_flags |= tsflags << 12;
4901 }
4902 }
4903 }
4904 #if TG3_VLAN_TAG_USED
4905 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4906 base_flags |= (TXD_FLAG_VLAN |
4907 (vlan_tx_tag_get(skb) << 16));
4908 #endif
4909
4910 /* Queue skb data, a.k.a. the main skb fragment. */
4911 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4912
4913 tp->tx_buffers[entry].skb = skb;
4914 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4915
4916 would_hit_hwbug = 0;
4917
4918 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
4919 would_hit_hwbug = 1;
4920 else if (tg3_4g_overflow_test(mapping, len))
4921 would_hit_hwbug = 1;
4922
4923 tg3_set_txd(tp, entry, mapping, len, base_flags,
4924 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4925
4926 entry = NEXT_TX(entry);
4927
4928 /* Now loop through additional data fragments, and queue them. */
4929 if (skb_shinfo(skb)->nr_frags > 0) {
4930 unsigned int i, last;
4931
4932 last = skb_shinfo(skb)->nr_frags - 1;
4933 for (i = 0; i <= last; i++) {
4934 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4935
4936 len = frag->size;
4937 mapping = pci_map_page(tp->pdev,
4938 frag->page,
4939 frag->page_offset,
4940 len, PCI_DMA_TODEVICE);
4941
4942 tp->tx_buffers[entry].skb = NULL;
4943 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4944
4945 if (tg3_4g_overflow_test(mapping, len))
4946 would_hit_hwbug = 1;
4947
4948 if (tg3_40bit_overflow_test(tp, mapping, len))
4949 would_hit_hwbug = 1;
4950
4951 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4952 tg3_set_txd(tp, entry, mapping, len,
4953 base_flags, (i == last)|(mss << 1));
4954 else
4955 tg3_set_txd(tp, entry, mapping, len,
4956 base_flags, (i == last));
4957
4958 entry = NEXT_TX(entry);
4959 }
4960 }
4961
4962 if (would_hit_hwbug) {
4963 u32 last_plus_one = entry;
4964 u32 start;
4965
4966 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4967 start &= (TG3_TX_RING_SIZE - 1);
4968
4969 /* If the workaround fails due to memory/mapping
4970 * failure, silently drop this packet.
4971 */
4972 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4973 &start, base_flags, mss))
4974 goto out_unlock;
4975
4976 entry = start;
4977 }
4978
4979 /* Packets are ready, update Tx producer idx local and on card. */
4980 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4981
4982 tp->tx_prod = entry;
4983 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4984 netif_stop_queue(dev);
4985 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4986 netif_wake_queue(tp->dev);
4987 }
4988
4989 out_unlock:
4990 mmiowb();
4991
4992 dev->trans_start = jiffies;
4993
4994 return NETDEV_TX_OK;
4995 }
4996
4997 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4998 int new_mtu)
4999 {
5000 dev->mtu = new_mtu;
5001
5002 if (new_mtu > ETH_DATA_LEN) {
5003 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5004 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5005 ethtool_op_set_tso(dev, 0);
5006 }
5007 else
5008 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5009 } else {
5010 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5011 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5012 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5013 }
5014 }
5015
5016 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5017 {
5018 struct tg3 *tp = netdev_priv(dev);
5019 int err;
5020
5021 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5022 return -EINVAL;
5023
5024 if (!netif_running(dev)) {
5025 /* We'll just catch it later when the
5026 * device is up'd.
5027 */
5028 tg3_set_mtu(dev, tp, new_mtu);
5029 return 0;
5030 }
5031
5032 tg3_phy_stop(tp);
5033
5034 tg3_netif_stop(tp);
5035
5036 tg3_full_lock(tp, 1);
5037
5038 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5039
5040 tg3_set_mtu(dev, tp, new_mtu);
5041
5042 err = tg3_restart_hw(tp, 0);
5043
5044 if (!err)
5045 tg3_netif_start(tp);
5046
5047 tg3_full_unlock(tp);
5048
5049 if (!err)
5050 tg3_phy_start(tp);
5051
5052 return err;
5053 }
5054
5055 /* Free up pending packets in all rx/tx rings.
5056 *
5057 * The chip has been shut down and the driver detached from
5058 * the networking, so no interrupts or new tx packets will
5059 * end up in the driver. tp->{tx,}lock is not held and we are not
5060 * in an interrupt context and thus may sleep.
5061 */
5062 static void tg3_free_rings(struct tg3 *tp)
5063 {
5064 struct ring_info *rxp;
5065 int i;
5066
5067 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5068 rxp = &tp->rx_std_buffers[i];
5069
5070 if (rxp->skb == NULL)
5071 continue;
5072 pci_unmap_single(tp->pdev,
5073 pci_unmap_addr(rxp, mapping),
5074 tp->rx_pkt_buf_sz - tp->rx_offset,
5075 PCI_DMA_FROMDEVICE);
5076 dev_kfree_skb_any(rxp->skb);
5077 rxp->skb = NULL;
5078 }
5079
5080 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5081 rxp = &tp->rx_jumbo_buffers[i];
5082
5083 if (rxp->skb == NULL)
5084 continue;
5085 pci_unmap_single(tp->pdev,
5086 pci_unmap_addr(rxp, mapping),
5087 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
5088 PCI_DMA_FROMDEVICE);
5089 dev_kfree_skb_any(rxp->skb);
5090 rxp->skb = NULL;
5091 }
5092
5093 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5094 struct tx_ring_info *txp;
5095 struct sk_buff *skb;
5096 int j;
5097
5098 txp = &tp->tx_buffers[i];
5099 skb = txp->skb;
5100
5101 if (skb == NULL) {
5102 i++;
5103 continue;
5104 }
5105
5106 pci_unmap_single(tp->pdev,
5107 pci_unmap_addr(txp, mapping),
5108 skb_headlen(skb),
5109 PCI_DMA_TODEVICE);
5110 txp->skb = NULL;
5111
5112 i++;
5113
5114 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
5115 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
5116 pci_unmap_page(tp->pdev,
5117 pci_unmap_addr(txp, mapping),
5118 skb_shinfo(skb)->frags[j].size,
5119 PCI_DMA_TODEVICE);
5120 i++;
5121 }
5122
5123 dev_kfree_skb_any(skb);
5124 }
5125 }
5126
5127 /* Initialize tx/rx rings for packet processing.
5128 *
5129 * The chip has been shut down and the driver detached from
5130 * the networking, so no interrupts or new tx packets will
5131 * end up in the driver. tp->{tx,}lock are held and thus
5132 * we may not sleep.
5133 */
5134 static int tg3_init_rings(struct tg3 *tp)
5135 {
5136 u32 i;
5137
5138 /* Free up all the SKBs. */
5139 tg3_free_rings(tp);
5140
5141 /* Zero out all descriptors. */
5142 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
5143 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
5144 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5145 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5146
5147 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
5148 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5149 (tp->dev->mtu > ETH_DATA_LEN))
5150 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
5151
5152 /* Initialize invariants of the rings, we only set this
5153 * stuff once. This works because the card does not
5154 * write into the rx buffer posting rings.
5155 */
5156 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5157 struct tg3_rx_buffer_desc *rxd;
5158
5159 rxd = &tp->rx_std[i];
5160 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
5161 << RXD_LEN_SHIFT;
5162 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5163 rxd->opaque = (RXD_OPAQUE_RING_STD |
5164 (i << RXD_OPAQUE_INDEX_SHIFT));
5165 }
5166
5167 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5168 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5169 struct tg3_rx_buffer_desc *rxd;
5170
5171 rxd = &tp->rx_jumbo[i];
5172 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
5173 << RXD_LEN_SHIFT;
5174 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5175 RXD_FLAG_JUMBO;
5176 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5177 (i << RXD_OPAQUE_INDEX_SHIFT));
5178 }
5179 }
5180
5181 /* Now allocate fresh SKBs for each rx ring. */
5182 for (i = 0; i < tp->rx_pending; i++) {
5183 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5184 printk(KERN_WARNING PFX
5185 "%s: Using a smaller RX standard ring, "
5186 "only %d out of %d buffers were allocated "
5187 "successfully.\n",
5188 tp->dev->name, i, tp->rx_pending);
5189 if (i == 0)
5190 return -ENOMEM;
5191 tp->rx_pending = i;
5192 break;
5193 }
5194 }
5195
5196 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5197 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5198 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
5199 -1, i) < 0) {
5200 printk(KERN_WARNING PFX
5201 "%s: Using a smaller RX jumbo ring, "
5202 "only %d out of %d buffers were "
5203 "allocated successfully.\n",
5204 tp->dev->name, i, tp->rx_jumbo_pending);
5205 if (i == 0) {
5206 tg3_free_rings(tp);
5207 return -ENOMEM;
5208 }
5209 tp->rx_jumbo_pending = i;
5210 break;
5211 }
5212 }
5213 }
5214 return 0;
5215 }
5216
5217 /*
5218 * Must not be invoked with interrupt sources disabled and
5219 * the hardware shutdown down.
5220 */
5221 static void tg3_free_consistent(struct tg3 *tp)
5222 {
5223 kfree(tp->rx_std_buffers);
5224 tp->rx_std_buffers = NULL;
5225 if (tp->rx_std) {
5226 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5227 tp->rx_std, tp->rx_std_mapping);
5228 tp->rx_std = NULL;
5229 }
5230 if (tp->rx_jumbo) {
5231 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5232 tp->rx_jumbo, tp->rx_jumbo_mapping);
5233 tp->rx_jumbo = NULL;
5234 }
5235 if (tp->rx_rcb) {
5236 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5237 tp->rx_rcb, tp->rx_rcb_mapping);
5238 tp->rx_rcb = NULL;
5239 }
5240 if (tp->tx_ring) {
5241 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5242 tp->tx_ring, tp->tx_desc_mapping);
5243 tp->tx_ring = NULL;
5244 }
5245 if (tp->hw_status) {
5246 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5247 tp->hw_status, tp->status_mapping);
5248 tp->hw_status = NULL;
5249 }
5250 if (tp->hw_stats) {
5251 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5252 tp->hw_stats, tp->stats_mapping);
5253 tp->hw_stats = NULL;
5254 }
5255 }
5256
5257 /*
5258 * Must not be invoked with interrupt sources disabled and
5259 * the hardware shutdown down. Can sleep.
5260 */
5261 static int tg3_alloc_consistent(struct tg3 *tp)
5262 {
5263 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
5264 (TG3_RX_RING_SIZE +
5265 TG3_RX_JUMBO_RING_SIZE)) +
5266 (sizeof(struct tx_ring_info) *
5267 TG3_TX_RING_SIZE),
5268 GFP_KERNEL);
5269 if (!tp->rx_std_buffers)
5270 return -ENOMEM;
5271
5272 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
5273 tp->tx_buffers = (struct tx_ring_info *)
5274 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
5275
5276 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5277 &tp->rx_std_mapping);
5278 if (!tp->rx_std)
5279 goto err_out;
5280
5281 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5282 &tp->rx_jumbo_mapping);
5283
5284 if (!tp->rx_jumbo)
5285 goto err_out;
5286
5287 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5288 &tp->rx_rcb_mapping);
5289 if (!tp->rx_rcb)
5290 goto err_out;
5291
5292 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5293 &tp->tx_desc_mapping);
5294 if (!tp->tx_ring)
5295 goto err_out;
5296
5297 tp->hw_status = pci_alloc_consistent(tp->pdev,
5298 TG3_HW_STATUS_SIZE,
5299 &tp->status_mapping);
5300 if (!tp->hw_status)
5301 goto err_out;
5302
5303 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5304 sizeof(struct tg3_hw_stats),
5305 &tp->stats_mapping);
5306 if (!tp->hw_stats)
5307 goto err_out;
5308
5309 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5310 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5311
5312 return 0;
5313
5314 err_out:
5315 tg3_free_consistent(tp);
5316 return -ENOMEM;
5317 }
5318
5319 #define MAX_WAIT_CNT 1000
5320
5321 /* To stop a block, clear the enable bit and poll till it
5322 * clears. tp->lock is held.
5323 */
5324 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
5325 {
5326 unsigned int i;
5327 u32 val;
5328
5329 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5330 switch (ofs) {
5331 case RCVLSC_MODE:
5332 case DMAC_MODE:
5333 case MBFREE_MODE:
5334 case BUFMGR_MODE:
5335 case MEMARB_MODE:
5336 /* We can't enable/disable these bits of the
5337 * 5705/5750, just say success.
5338 */
5339 return 0;
5340
5341 default:
5342 break;
5343 }
5344 }
5345
5346 val = tr32(ofs);
5347 val &= ~enable_bit;
5348 tw32_f(ofs, val);
5349
5350 for (i = 0; i < MAX_WAIT_CNT; i++) {
5351 udelay(100);
5352 val = tr32(ofs);
5353 if ((val & enable_bit) == 0)
5354 break;
5355 }
5356
5357 if (i == MAX_WAIT_CNT && !silent) {
5358 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5359 "ofs=%lx enable_bit=%x\n",
5360 ofs, enable_bit);
5361 return -ENODEV;
5362 }
5363
5364 return 0;
5365 }
5366
5367 /* tp->lock is held. */
5368 static int tg3_abort_hw(struct tg3 *tp, int silent)
5369 {
5370 int i, err;
5371
5372 tg3_disable_ints(tp);
5373
5374 tp->rx_mode &= ~RX_MODE_ENABLE;
5375 tw32_f(MAC_RX_MODE, tp->rx_mode);
5376 udelay(10);
5377
5378 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5379 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5380 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5381 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5382 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5383 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5384
5385 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5386 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5387 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5388 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5389 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5390 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5391 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
5392
5393 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5394 tw32_f(MAC_MODE, tp->mac_mode);
5395 udelay(40);
5396
5397 tp->tx_mode &= ~TX_MODE_ENABLE;
5398 tw32_f(MAC_TX_MODE, tp->tx_mode);
5399
5400 for (i = 0; i < MAX_WAIT_CNT; i++) {
5401 udelay(100);
5402 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5403 break;
5404 }
5405 if (i >= MAX_WAIT_CNT) {
5406 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5407 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5408 tp->dev->name, tr32(MAC_TX_MODE));
5409 err |= -ENODEV;
5410 }
5411
5412 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
5413 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5414 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
5415
5416 tw32(FTQ_RESET, 0xffffffff);
5417 tw32(FTQ_RESET, 0x00000000);
5418
5419 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5420 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
5421
5422 if (tp->hw_status)
5423 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5424 if (tp->hw_stats)
5425 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5426
5427 return err;
5428 }
5429
5430 /* tp->lock is held. */
5431 static int tg3_nvram_lock(struct tg3 *tp)
5432 {
5433 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5434 int i;
5435
5436 if (tp->nvram_lock_cnt == 0) {
5437 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
5438 for (i = 0; i < 8000; i++) {
5439 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
5440 break;
5441 udelay(20);
5442 }
5443 if (i == 8000) {
5444 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
5445 return -ENODEV;
5446 }
5447 }
5448 tp->nvram_lock_cnt++;
5449 }
5450 return 0;
5451 }
5452
5453 /* tp->lock is held. */
5454 static void tg3_nvram_unlock(struct tg3 *tp)
5455 {
5456 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5457 if (tp->nvram_lock_cnt > 0)
5458 tp->nvram_lock_cnt--;
5459 if (tp->nvram_lock_cnt == 0)
5460 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
5461 }
5462 }
5463
5464 /* tp->lock is held. */
5465 static void tg3_enable_nvram_access(struct tg3 *tp)
5466 {
5467 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5468 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5469 u32 nvaccess = tr32(NVRAM_ACCESS);
5470
5471 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
5472 }
5473 }
5474
5475 /* tp->lock is held. */
5476 static void tg3_disable_nvram_access(struct tg3 *tp)
5477 {
5478 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5479 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5480 u32 nvaccess = tr32(NVRAM_ACCESS);
5481
5482 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
5483 }
5484 }
5485
5486 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5487 {
5488 int i;
5489 u32 apedata;
5490
5491 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5492 if (apedata != APE_SEG_SIG_MAGIC)
5493 return;
5494
5495 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5496 if (apedata != APE_FW_STATUS_READY)
5497 return;
5498
5499 /* Wait for up to 1 millisecond for APE to service previous event. */
5500 for (i = 0; i < 10; i++) {
5501 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5502 return;
5503
5504 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5505
5506 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5507 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5508 event | APE_EVENT_STATUS_EVENT_PENDING);
5509
5510 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5511
5512 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5513 break;
5514
5515 udelay(100);
5516 }
5517
5518 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5519 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5520 }
5521
5522 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5523 {
5524 u32 event;
5525 u32 apedata;
5526
5527 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5528 return;
5529
5530 switch (kind) {
5531 case RESET_KIND_INIT:
5532 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5533 APE_HOST_SEG_SIG_MAGIC);
5534 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5535 APE_HOST_SEG_LEN_MAGIC);
5536 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5537 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5538 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5539 APE_HOST_DRIVER_ID_MAGIC);
5540 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5541 APE_HOST_BEHAV_NO_PHYLOCK);
5542
5543 event = APE_EVENT_STATUS_STATE_START;
5544 break;
5545 case RESET_KIND_SHUTDOWN:
5546 event = APE_EVENT_STATUS_STATE_UNLOAD;
5547 break;
5548 case RESET_KIND_SUSPEND:
5549 event = APE_EVENT_STATUS_STATE_SUSPEND;
5550 break;
5551 default:
5552 return;
5553 }
5554
5555 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5556
5557 tg3_ape_send_event(tp, event);
5558 }
5559
5560 /* tp->lock is held. */
5561 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5562 {
5563 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5564 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
5565
5566 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5567 switch (kind) {
5568 case RESET_KIND_INIT:
5569 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5570 DRV_STATE_START);
5571 break;
5572
5573 case RESET_KIND_SHUTDOWN:
5574 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5575 DRV_STATE_UNLOAD);
5576 break;
5577
5578 case RESET_KIND_SUSPEND:
5579 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5580 DRV_STATE_SUSPEND);
5581 break;
5582
5583 default:
5584 break;
5585 }
5586 }
5587
5588 if (kind == RESET_KIND_INIT ||
5589 kind == RESET_KIND_SUSPEND)
5590 tg3_ape_driver_state_change(tp, kind);
5591 }
5592
5593 /* tp->lock is held. */
5594 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5595 {
5596 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5597 switch (kind) {
5598 case RESET_KIND_INIT:
5599 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5600 DRV_STATE_START_DONE);
5601 break;
5602
5603 case RESET_KIND_SHUTDOWN:
5604 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5605 DRV_STATE_UNLOAD_DONE);
5606 break;
5607
5608 default:
5609 break;
5610 }
5611 }
5612
5613 if (kind == RESET_KIND_SHUTDOWN)
5614 tg3_ape_driver_state_change(tp, kind);
5615 }
5616
5617 /* tp->lock is held. */
5618 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5619 {
5620 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5621 switch (kind) {
5622 case RESET_KIND_INIT:
5623 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5624 DRV_STATE_START);
5625 break;
5626
5627 case RESET_KIND_SHUTDOWN:
5628 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5629 DRV_STATE_UNLOAD);
5630 break;
5631
5632 case RESET_KIND_SUSPEND:
5633 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5634 DRV_STATE_SUSPEND);
5635 break;
5636
5637 default:
5638 break;
5639 }
5640 }
5641 }
5642
5643 static int tg3_poll_fw(struct tg3 *tp)
5644 {
5645 int i;
5646 u32 val;
5647
5648 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5649 /* Wait up to 20ms for init done. */
5650 for (i = 0; i < 200; i++) {
5651 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
5652 return 0;
5653 udelay(100);
5654 }
5655 return -ENODEV;
5656 }
5657
5658 /* Wait for firmware initialization to complete. */
5659 for (i = 0; i < 100000; i++) {
5660 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
5661 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
5662 break;
5663 udelay(10);
5664 }
5665
5666 /* Chip might not be fitted with firmware. Some Sun onboard
5667 * parts are configured like that. So don't signal the timeout
5668 * of the above loop as an error, but do report the lack of
5669 * running firmware once.
5670 */
5671 if (i >= 100000 &&
5672 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
5673 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
5674
5675 printk(KERN_INFO PFX "%s: No firmware running.\n",
5676 tp->dev->name);
5677 }
5678
5679 return 0;
5680 }
5681
5682 /* Save PCI command register before chip reset */
5683 static void tg3_save_pci_state(struct tg3 *tp)
5684 {
5685 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
5686 }
5687
5688 /* Restore PCI state after chip reset */
5689 static void tg3_restore_pci_state(struct tg3 *tp)
5690 {
5691 u32 val;
5692
5693 /* Re-enable indirect register accesses. */
5694 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
5695 tp->misc_host_ctrl);
5696
5697 /* Set MAX PCI retry to zero. */
5698 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
5699 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5700 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
5701 val |= PCISTATE_RETRY_SAME_DMA;
5702 /* Allow reads and writes to the APE register and memory space. */
5703 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
5704 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
5705 PCISTATE_ALLOW_APE_SHMEM_WR;
5706 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
5707
5708 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
5709
5710 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5711 pcie_set_readrq(tp->pdev, 4096);
5712 else {
5713 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
5714 tp->pci_cacheline_sz);
5715 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
5716 tp->pci_lat_timer);
5717 }
5718
5719 /* Make sure PCI-X relaxed ordering bit is clear. */
5720 if (tp->pcix_cap) {
5721 u16 pcix_cmd;
5722
5723 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5724 &pcix_cmd);
5725 pcix_cmd &= ~PCI_X_CMD_ERO;
5726 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5727 pcix_cmd);
5728 }
5729
5730 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5731
5732 /* Chip reset on 5780 will reset MSI enable bit,
5733 * so need to restore it.
5734 */
5735 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
5736 u16 ctrl;
5737
5738 pci_read_config_word(tp->pdev,
5739 tp->msi_cap + PCI_MSI_FLAGS,
5740 &ctrl);
5741 pci_write_config_word(tp->pdev,
5742 tp->msi_cap + PCI_MSI_FLAGS,
5743 ctrl | PCI_MSI_FLAGS_ENABLE);
5744 val = tr32(MSGINT_MODE);
5745 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
5746 }
5747 }
5748 }
5749
5750 static void tg3_stop_fw(struct tg3 *);
5751
5752 /* tp->lock is held. */
5753 static int tg3_chip_reset(struct tg3 *tp)
5754 {
5755 u32 val;
5756 void (*write_op)(struct tg3 *, u32, u32);
5757 int err;
5758
5759 tg3_nvram_lock(tp);
5760
5761 tg3_mdio_stop(tp);
5762
5763 /* No matching tg3_nvram_unlock() after this because
5764 * chip reset below will undo the nvram lock.
5765 */
5766 tp->nvram_lock_cnt = 0;
5767
5768 /* GRC_MISC_CFG core clock reset will clear the memory
5769 * enable bit in PCI register 4 and the MSI enable bit
5770 * on some chips, so we save relevant registers here.
5771 */
5772 tg3_save_pci_state(tp);
5773
5774 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
5775 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
5776 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
5777 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
5778 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
5779 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
5780 tw32(GRC_FASTBOOT_PC, 0);
5781
5782 /*
5783 * We must avoid the readl() that normally takes place.
5784 * It locks machines, causes machine checks, and other
5785 * fun things. So, temporarily disable the 5701
5786 * hardware workaround, while we do the reset.
5787 */
5788 write_op = tp->write32;
5789 if (write_op == tg3_write_flush_reg32)
5790 tp->write32 = tg3_write32;
5791
5792 /* Prevent the irq handler from reading or writing PCI registers
5793 * during chip reset when the memory enable bit in the PCI command
5794 * register may be cleared. The chip does not generate interrupt
5795 * at this time, but the irq handler may still be called due to irq
5796 * sharing or irqpoll.
5797 */
5798 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
5799 if (tp->hw_status) {
5800 tp->hw_status->status = 0;
5801 tp->hw_status->status_tag = 0;
5802 }
5803 tp->last_tag = 0;
5804 smp_mb();
5805 synchronize_irq(tp->pdev->irq);
5806
5807 /* do the reset */
5808 val = GRC_MISC_CFG_CORECLK_RESET;
5809
5810 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5811 if (tr32(0x7e2c) == 0x60) {
5812 tw32(0x7e2c, 0x20);
5813 }
5814 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5815 tw32(GRC_MISC_CFG, (1 << 29));
5816 val |= (1 << 29);
5817 }
5818 }
5819
5820 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5821 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
5822 tw32(GRC_VCPU_EXT_CTRL,
5823 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
5824 }
5825
5826 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5827 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
5828 tw32(GRC_MISC_CFG, val);
5829
5830 /* restore 5701 hardware bug workaround write method */
5831 tp->write32 = write_op;
5832
5833 /* Unfortunately, we have to delay before the PCI read back.
5834 * Some 575X chips even will not respond to a PCI cfg access
5835 * when the reset command is given to the chip.
5836 *
5837 * How do these hardware designers expect things to work
5838 * properly if the PCI write is posted for a long period
5839 * of time? It is always necessary to have some method by
5840 * which a register read back can occur to push the write
5841 * out which does the reset.
5842 *
5843 * For most tg3 variants the trick below was working.
5844 * Ho hum...
5845 */
5846 udelay(120);
5847
5848 /* Flush PCI posted writes. The normal MMIO registers
5849 * are inaccessible at this time so this is the only
5850 * way to make this reliably (actually, this is no longer
5851 * the case, see above). I tried to use indirect
5852 * register read/write but this upset some 5701 variants.
5853 */
5854 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
5855
5856 udelay(120);
5857
5858 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5859 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
5860 int i;
5861 u32 cfg_val;
5862
5863 /* Wait for link training to complete. */
5864 for (i = 0; i < 5000; i++)
5865 udelay(100);
5866
5867 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
5868 pci_write_config_dword(tp->pdev, 0xc4,
5869 cfg_val | (1 << 15));
5870 }
5871 /* Set PCIE max payload size and clear error status. */
5872 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
5873 }
5874
5875 tg3_restore_pci_state(tp);
5876
5877 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
5878
5879 val = 0;
5880 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5881 val = tr32(MEMARB_MODE);
5882 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
5883
5884 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
5885 tg3_stop_fw(tp);
5886 tw32(0x5000, 0x400);
5887 }
5888
5889 tw32(GRC_MODE, tp->grc_mode);
5890
5891 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
5892 val = tr32(0xc4);
5893
5894 tw32(0xc4, val | (1 << 15));
5895 }
5896
5897 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
5898 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5899 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
5900 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
5901 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
5902 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5903 }
5904
5905 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5906 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
5907 tw32_f(MAC_MODE, tp->mac_mode);
5908 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
5909 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
5910 tw32_f(MAC_MODE, tp->mac_mode);
5911 } else
5912 tw32_f(MAC_MODE, 0);
5913 udelay(40);
5914
5915 tg3_mdio_start(tp);
5916
5917 err = tg3_poll_fw(tp);
5918 if (err)
5919 return err;
5920
5921 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
5922 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5923 val = tr32(0x7c00);
5924
5925 tw32(0x7c00, val | (1 << 25));
5926 }
5927
5928 /* Reprobe ASF enable state. */
5929 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
5930 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
5931 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
5932 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
5933 u32 nic_cfg;
5934
5935 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5936 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5937 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
5938 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
5939 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5940 }
5941 }
5942
5943 return 0;
5944 }
5945
5946 /* tp->lock is held. */
5947 static void tg3_stop_fw(struct tg3 *tp)
5948 {
5949 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
5950 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
5951 u32 val;
5952
5953 /* Wait for RX cpu to ACK the previous event. */
5954 tg3_wait_for_event_ack(tp);
5955
5956 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5957 val = tr32(GRC_RX_CPU_EVENT);
5958 val |= GRC_RX_CPU_DRIVER_EVENT;
5959 tw32(GRC_RX_CPU_EVENT, val);
5960
5961 /* Wait for RX cpu to ACK this event. */
5962 tg3_wait_for_event_ack(tp);
5963 }
5964 }
5965
5966 /* tp->lock is held. */
5967 static int tg3_halt(struct tg3 *tp, int kind, int silent)
5968 {
5969 int err;
5970
5971 tg3_stop_fw(tp);
5972
5973 tg3_write_sig_pre_reset(tp, kind);
5974
5975 tg3_abort_hw(tp, silent);
5976 err = tg3_chip_reset(tp);
5977
5978 tg3_write_sig_legacy(tp, kind);
5979 tg3_write_sig_post_reset(tp, kind);
5980
5981 if (err)
5982 return err;
5983
5984 return 0;
5985 }
5986
5987 #define TG3_FW_RELEASE_MAJOR 0x0
5988 #define TG3_FW_RELASE_MINOR 0x0
5989 #define TG3_FW_RELEASE_FIX 0x0
5990 #define TG3_FW_START_ADDR 0x08000000
5991 #define TG3_FW_TEXT_ADDR 0x08000000
5992 #define TG3_FW_TEXT_LEN 0x9c0
5993 #define TG3_FW_RODATA_ADDR 0x080009c0
5994 #define TG3_FW_RODATA_LEN 0x60
5995 #define TG3_FW_DATA_ADDR 0x08000a40
5996 #define TG3_FW_DATA_LEN 0x20
5997 #define TG3_FW_SBSS_ADDR 0x08000a60
5998 #define TG3_FW_SBSS_LEN 0xc
5999 #define TG3_FW_BSS_ADDR 0x08000a70
6000 #define TG3_FW_BSS_LEN 0x10
6001
6002 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
6003 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
6004 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
6005 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
6006 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
6007 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
6008 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
6009 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
6010 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
6011 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
6012 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
6013 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
6014 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
6015 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
6016 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
6017 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
6018 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
6019 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
6020 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
6021 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
6022 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
6023 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
6024 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
6025 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
6026 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6027 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6028 0, 0, 0, 0, 0, 0,
6029 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
6030 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6031 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6032 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6033 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
6034 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
6035 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
6036 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
6037 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6038 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6039 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
6040 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6041 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6042 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6043 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
6044 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
6045 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
6046 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
6047 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
6048 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
6049 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
6050 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
6051 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
6052 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
6053 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
6054 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
6055 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
6056 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
6057 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
6058 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
6059 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
6060 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
6061 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
6062 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
6063 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
6064 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
6065 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
6066 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
6067 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
6068 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
6069 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
6070 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
6071 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
6072 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
6073 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
6074 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
6075 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
6076 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
6077 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
6078 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
6079 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
6080 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
6081 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
6082 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
6083 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
6084 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
6085 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
6086 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
6087 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
6088 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
6089 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
6090 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
6091 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
6092 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
6093 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
6094 };
6095
6096 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
6097 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
6098 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
6099 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
6100 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
6101 0x00000000
6102 };
6103
6104 #if 0 /* All zeros, don't eat up space with it. */
6105 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
6106 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
6107 0x00000000, 0x00000000, 0x00000000, 0x00000000
6108 };
6109 #endif
6110
6111 #define RX_CPU_SCRATCH_BASE 0x30000
6112 #define RX_CPU_SCRATCH_SIZE 0x04000
6113 #define TX_CPU_SCRATCH_BASE 0x34000
6114 #define TX_CPU_SCRATCH_SIZE 0x04000
6115
6116 /* tp->lock is held. */
6117 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6118 {
6119 int i;
6120
6121 BUG_ON(offset == TX_CPU_BASE &&
6122 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6123
6124 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6125 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6126
6127 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6128 return 0;
6129 }
6130 if (offset == RX_CPU_BASE) {
6131 for (i = 0; i < 10000; i++) {
6132 tw32(offset + CPU_STATE, 0xffffffff);
6133 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6134 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6135 break;
6136 }
6137
6138 tw32(offset + CPU_STATE, 0xffffffff);
6139 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6140 udelay(10);
6141 } else {
6142 for (i = 0; i < 10000; i++) {
6143 tw32(offset + CPU_STATE, 0xffffffff);
6144 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6145 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6146 break;
6147 }
6148 }
6149
6150 if (i >= 10000) {
6151 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6152 "and %s CPU\n",
6153 tp->dev->name,
6154 (offset == RX_CPU_BASE ? "RX" : "TX"));
6155 return -ENODEV;
6156 }
6157
6158 /* Clear firmware's nvram arbitration. */
6159 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6160 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6161 return 0;
6162 }
6163
6164 struct fw_info {
6165 unsigned int text_base;
6166 unsigned int text_len;
6167 const u32 *text_data;
6168 unsigned int rodata_base;
6169 unsigned int rodata_len;
6170 const u32 *rodata_data;
6171 unsigned int data_base;
6172 unsigned int data_len;
6173 const u32 *data_data;
6174 };
6175
6176 /* tp->lock is held. */
6177 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6178 int cpu_scratch_size, struct fw_info *info)
6179 {
6180 int err, lock_err, i;
6181 void (*write_op)(struct tg3 *, u32, u32);
6182
6183 if (cpu_base == TX_CPU_BASE &&
6184 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6185 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6186 "TX cpu firmware on %s which is 5705.\n",
6187 tp->dev->name);
6188 return -EINVAL;
6189 }
6190
6191 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6192 write_op = tg3_write_mem;
6193 else
6194 write_op = tg3_write_indirect_reg32;
6195
6196 /* It is possible that bootcode is still loading at this point.
6197 * Get the nvram lock first before halting the cpu.
6198 */
6199 lock_err = tg3_nvram_lock(tp);
6200 err = tg3_halt_cpu(tp, cpu_base);
6201 if (!lock_err)
6202 tg3_nvram_unlock(tp);
6203 if (err)
6204 goto out;
6205
6206 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6207 write_op(tp, cpu_scratch_base + i, 0);
6208 tw32(cpu_base + CPU_STATE, 0xffffffff);
6209 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6210 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
6211 write_op(tp, (cpu_scratch_base +
6212 (info->text_base & 0xffff) +
6213 (i * sizeof(u32))),
6214 (info->text_data ?
6215 info->text_data[i] : 0));
6216 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
6217 write_op(tp, (cpu_scratch_base +
6218 (info->rodata_base & 0xffff) +
6219 (i * sizeof(u32))),
6220 (info->rodata_data ?
6221 info->rodata_data[i] : 0));
6222 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
6223 write_op(tp, (cpu_scratch_base +
6224 (info->data_base & 0xffff) +
6225 (i * sizeof(u32))),
6226 (info->data_data ?
6227 info->data_data[i] : 0));
6228
6229 err = 0;
6230
6231 out:
6232 return err;
6233 }
6234
6235 /* tp->lock is held. */
6236 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6237 {
6238 struct fw_info info;
6239 int err, i;
6240
6241 info.text_base = TG3_FW_TEXT_ADDR;
6242 info.text_len = TG3_FW_TEXT_LEN;
6243 info.text_data = &tg3FwText[0];
6244 info.rodata_base = TG3_FW_RODATA_ADDR;
6245 info.rodata_len = TG3_FW_RODATA_LEN;
6246 info.rodata_data = &tg3FwRodata[0];
6247 info.data_base = TG3_FW_DATA_ADDR;
6248 info.data_len = TG3_FW_DATA_LEN;
6249 info.data_data = NULL;
6250
6251 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6252 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6253 &info);
6254 if (err)
6255 return err;
6256
6257 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6258 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6259 &info);
6260 if (err)
6261 return err;
6262
6263 /* Now startup only the RX cpu. */
6264 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6265 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
6266
6267 for (i = 0; i < 5; i++) {
6268 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
6269 break;
6270 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6271 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
6272 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
6273 udelay(1000);
6274 }
6275 if (i >= 5) {
6276 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6277 "to set RX CPU PC, is %08x should be %08x\n",
6278 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6279 TG3_FW_TEXT_ADDR);
6280 return -ENODEV;
6281 }
6282 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6283 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6284
6285 return 0;
6286 }
6287
6288
6289 #define TG3_TSO_FW_RELEASE_MAJOR 0x1
6290 #define TG3_TSO_FW_RELASE_MINOR 0x6
6291 #define TG3_TSO_FW_RELEASE_FIX 0x0
6292 #define TG3_TSO_FW_START_ADDR 0x08000000
6293 #define TG3_TSO_FW_TEXT_ADDR 0x08000000
6294 #define TG3_TSO_FW_TEXT_LEN 0x1aa0
6295 #define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
6296 #define TG3_TSO_FW_RODATA_LEN 0x60
6297 #define TG3_TSO_FW_DATA_ADDR 0x08001b20
6298 #define TG3_TSO_FW_DATA_LEN 0x30
6299 #define TG3_TSO_FW_SBSS_ADDR 0x08001b50
6300 #define TG3_TSO_FW_SBSS_LEN 0x2c
6301 #define TG3_TSO_FW_BSS_ADDR 0x08001b80
6302 #define TG3_TSO_FW_BSS_LEN 0x894
6303
6304 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
6305 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
6306 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
6307 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
6308 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
6309 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
6310 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
6311 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
6312 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
6313 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
6314 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
6315 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
6316 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
6317 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
6318 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
6319 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
6320 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
6321 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
6322 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
6323 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
6324 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
6325 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
6326 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
6327 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
6328 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
6329 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
6330 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
6331 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
6332 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
6333 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
6334 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6335 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
6336 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
6337 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
6338 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
6339 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
6340 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
6341 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
6342 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
6343 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
6344 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
6345 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
6346 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
6347 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
6348 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
6349 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
6350 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
6351 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
6352 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
6353 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
6354 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
6355 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
6356 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
6357 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
6358 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
6359 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
6360 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
6361 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
6362 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
6363 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
6364 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
6365 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
6366 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
6367 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
6368 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
6369 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
6370 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
6371 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
6372 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
6373 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
6374 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
6375 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
6376 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
6377 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
6378 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
6379 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
6380 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
6381 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
6382 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
6383 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
6384 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
6385 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
6386 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
6387 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
6388 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
6389 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
6390 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
6391 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
6392 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
6393 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
6394 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
6395 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
6396 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
6397 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
6398 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
6399 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
6400 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
6401 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
6402 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
6403 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
6404 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
6405 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
6406 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
6407 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
6408 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
6409 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
6410 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
6411 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
6412 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
6413 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
6414 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
6415 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
6416 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
6417 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
6418 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
6419 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
6420 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
6421 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
6422 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
6423 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
6424 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
6425 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
6426 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
6427 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
6428 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
6429 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
6430 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
6431 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
6432 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
6433 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
6434 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
6435 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
6436 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
6437 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
6438 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
6439 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
6440 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
6441 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
6442 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
6443 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
6444 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
6445 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
6446 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
6447 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
6448 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
6449 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
6450 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
6451 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
6452 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
6453 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
6454 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
6455 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
6456 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
6457 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
6458 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
6459 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
6460 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
6461 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
6462 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
6463 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
6464 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
6465 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
6466 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
6467 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
6468 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
6469 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
6470 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
6471 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
6472 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
6473 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
6474 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
6475 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
6476 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
6477 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
6478 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
6479 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
6480 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
6481 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
6482 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
6483 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
6484 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
6485 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
6486 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
6487 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
6488 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
6489 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
6490 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
6491 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
6492 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
6493 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
6494 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
6495 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
6496 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
6497 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
6498 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
6499 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
6500 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
6501 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
6502 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
6503 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
6504 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
6505 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
6506 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
6507 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
6508 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
6509 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
6510 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
6511 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
6512 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
6513 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
6514 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
6515 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
6516 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
6517 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
6518 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
6519 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
6520 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
6521 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
6522 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
6523 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
6524 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
6525 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
6526 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
6527 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
6528 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
6529 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
6530 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
6531 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
6532 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
6533 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
6534 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
6535 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
6536 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
6537 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
6538 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
6539 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
6540 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
6541 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
6542 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
6543 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
6544 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
6545 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
6546 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
6547 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
6548 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
6549 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
6550 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
6551 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
6552 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
6553 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
6554 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
6555 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
6556 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
6557 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
6558 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
6559 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
6560 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
6561 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
6562 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
6563 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
6564 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
6565 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
6566 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
6567 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
6568 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
6569 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
6570 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
6571 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
6572 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
6573 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
6574 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
6575 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
6576 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
6577 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
6578 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
6579 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
6580 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
6581 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
6582 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
6583 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
6584 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
6585 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
6586 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
6587 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
6588 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
6589 };
6590
6591 static const u32 tg3TsoFwRodata[] = {
6592 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
6593 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
6594 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
6595 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
6596 0x00000000,
6597 };
6598
6599 static const u32 tg3TsoFwData[] = {
6600 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
6601 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
6602 0x00000000,
6603 };
6604
6605 /* 5705 needs a special version of the TSO firmware. */
6606 #define TG3_TSO5_FW_RELEASE_MAJOR 0x1
6607 #define TG3_TSO5_FW_RELASE_MINOR 0x2
6608 #define TG3_TSO5_FW_RELEASE_FIX 0x0
6609 #define TG3_TSO5_FW_START_ADDR 0x00010000
6610 #define TG3_TSO5_FW_TEXT_ADDR 0x00010000
6611 #define TG3_TSO5_FW_TEXT_LEN 0xe90
6612 #define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
6613 #define TG3_TSO5_FW_RODATA_LEN 0x50
6614 #define TG3_TSO5_FW_DATA_ADDR 0x00010f00
6615 #define TG3_TSO5_FW_DATA_LEN 0x20
6616 #define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
6617 #define TG3_TSO5_FW_SBSS_LEN 0x28
6618 #define TG3_TSO5_FW_BSS_ADDR 0x00010f50
6619 #define TG3_TSO5_FW_BSS_LEN 0x88
6620
6621 static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
6622 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
6623 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
6624 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
6625 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
6626 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
6627 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
6628 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6629 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
6630 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
6631 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
6632 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
6633 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
6634 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
6635 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
6636 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
6637 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
6638 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
6639 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
6640 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
6641 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
6642 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
6643 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
6644 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
6645 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
6646 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
6647 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
6648 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
6649 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
6650 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
6651 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
6652 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
6653 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
6654 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
6655 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
6656 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
6657 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
6658 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
6659 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
6660 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
6661 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
6662 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
6663 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
6664 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
6665 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
6666 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
6667 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
6668 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
6669 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
6670 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
6671 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
6672 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
6673 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
6674 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
6675 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
6676 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
6677 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
6678 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
6679 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
6680 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
6681 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
6682 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
6683 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
6684 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
6685 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
6686 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
6687 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
6688 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
6689 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
6690 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
6691 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
6692 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
6693 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
6694 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
6695 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
6696 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
6697 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
6698 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
6699 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
6700 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
6701 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
6702 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
6703 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
6704 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
6705 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
6706 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
6707 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
6708 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
6709 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
6710 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
6711 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
6712 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
6713 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
6714 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
6715 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
6716 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
6717 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
6718 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
6719 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
6720 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
6721 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
6722 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
6723 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
6724 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
6725 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
6726 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
6727 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
6728 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
6729 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
6730 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
6731 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
6732 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
6733 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
6734 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
6735 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
6736 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
6737 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
6738 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
6739 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
6740 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
6741 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
6742 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
6743 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
6744 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
6745 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6746 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
6747 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
6748 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
6749 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
6750 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
6751 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
6752 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
6753 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
6754 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
6755 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
6756 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
6757 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
6758 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
6759 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
6760 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
6761 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
6762 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
6763 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
6764 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
6765 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
6766 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
6767 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
6768 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
6769 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
6770 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
6771 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
6772 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
6773 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
6774 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
6775 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
6776 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
6777 0x00000000, 0x00000000, 0x00000000,
6778 };
6779
6780 static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
6781 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
6782 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
6783 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
6784 0x00000000, 0x00000000, 0x00000000,
6785 };
6786
6787 static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
6788 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
6789 0x00000000, 0x00000000, 0x00000000,
6790 };
6791
6792 /* tp->lock is held. */
6793 static int tg3_load_tso_firmware(struct tg3 *tp)
6794 {
6795 struct fw_info info;
6796 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6797 int err, i;
6798
6799 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6800 return 0;
6801
6802 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6803 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
6804 info.text_len = TG3_TSO5_FW_TEXT_LEN;
6805 info.text_data = &tg3Tso5FwText[0];
6806 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
6807 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
6808 info.rodata_data = &tg3Tso5FwRodata[0];
6809 info.data_base = TG3_TSO5_FW_DATA_ADDR;
6810 info.data_len = TG3_TSO5_FW_DATA_LEN;
6811 info.data_data = &tg3Tso5FwData[0];
6812 cpu_base = RX_CPU_BASE;
6813 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6814 cpu_scratch_size = (info.text_len +
6815 info.rodata_len +
6816 info.data_len +
6817 TG3_TSO5_FW_SBSS_LEN +
6818 TG3_TSO5_FW_BSS_LEN);
6819 } else {
6820 info.text_base = TG3_TSO_FW_TEXT_ADDR;
6821 info.text_len = TG3_TSO_FW_TEXT_LEN;
6822 info.text_data = &tg3TsoFwText[0];
6823 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
6824 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
6825 info.rodata_data = &tg3TsoFwRodata[0];
6826 info.data_base = TG3_TSO_FW_DATA_ADDR;
6827 info.data_len = TG3_TSO_FW_DATA_LEN;
6828 info.data_data = &tg3TsoFwData[0];
6829 cpu_base = TX_CPU_BASE;
6830 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6831 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6832 }
6833
6834 err = tg3_load_firmware_cpu(tp, cpu_base,
6835 cpu_scratch_base, cpu_scratch_size,
6836 &info);
6837 if (err)
6838 return err;
6839
6840 /* Now startup the cpu. */
6841 tw32(cpu_base + CPU_STATE, 0xffffffff);
6842 tw32_f(cpu_base + CPU_PC, info.text_base);
6843
6844 for (i = 0; i < 5; i++) {
6845 if (tr32(cpu_base + CPU_PC) == info.text_base)
6846 break;
6847 tw32(cpu_base + CPU_STATE, 0xffffffff);
6848 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
6849 tw32_f(cpu_base + CPU_PC, info.text_base);
6850 udelay(1000);
6851 }
6852 if (i >= 5) {
6853 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6854 "to set CPU PC, is %08x should be %08x\n",
6855 tp->dev->name, tr32(cpu_base + CPU_PC),
6856 info.text_base);
6857 return -ENODEV;
6858 }
6859 tw32(cpu_base + CPU_STATE, 0xffffffff);
6860 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6861 return 0;
6862 }
6863
6864
6865 /* tp->lock is held. */
6866 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
6867 {
6868 u32 addr_high, addr_low;
6869 int i;
6870
6871 addr_high = ((tp->dev->dev_addr[0] << 8) |
6872 tp->dev->dev_addr[1]);
6873 addr_low = ((tp->dev->dev_addr[2] << 24) |
6874 (tp->dev->dev_addr[3] << 16) |
6875 (tp->dev->dev_addr[4] << 8) |
6876 (tp->dev->dev_addr[5] << 0));
6877 for (i = 0; i < 4; i++) {
6878 if (i == 1 && skip_mac_1)
6879 continue;
6880 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
6881 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
6882 }
6883
6884 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
6885 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6886 for (i = 0; i < 12; i++) {
6887 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
6888 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
6889 }
6890 }
6891
6892 addr_high = (tp->dev->dev_addr[0] +
6893 tp->dev->dev_addr[1] +
6894 tp->dev->dev_addr[2] +
6895 tp->dev->dev_addr[3] +
6896 tp->dev->dev_addr[4] +
6897 tp->dev->dev_addr[5]) &
6898 TX_BACKOFF_SEED_MASK;
6899 tw32(MAC_TX_BACKOFF_SEED, addr_high);
6900 }
6901
6902 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6903 {
6904 struct tg3 *tp = netdev_priv(dev);
6905 struct sockaddr *addr = p;
6906 int err = 0, skip_mac_1 = 0;
6907
6908 if (!is_valid_ether_addr(addr->sa_data))
6909 return -EINVAL;
6910
6911 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6912
6913 if (!netif_running(dev))
6914 return 0;
6915
6916 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6917 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6918
6919 addr0_high = tr32(MAC_ADDR_0_HIGH);
6920 addr0_low = tr32(MAC_ADDR_0_LOW);
6921 addr1_high = tr32(MAC_ADDR_1_HIGH);
6922 addr1_low = tr32(MAC_ADDR_1_LOW);
6923
6924 /* Skip MAC addr 1 if ASF is using it. */
6925 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6926 !(addr1_high == 0 && addr1_low == 0))
6927 skip_mac_1 = 1;
6928 }
6929 spin_lock_bh(&tp->lock);
6930 __tg3_set_mac_addr(tp, skip_mac_1);
6931 spin_unlock_bh(&tp->lock);
6932
6933 return err;
6934 }
6935
6936 /* tp->lock is held. */
6937 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6938 dma_addr_t mapping, u32 maxlen_flags,
6939 u32 nic_addr)
6940 {
6941 tg3_write_mem(tp,
6942 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6943 ((u64) mapping >> 32));
6944 tg3_write_mem(tp,
6945 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6946 ((u64) mapping & 0xffffffff));
6947 tg3_write_mem(tp,
6948 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6949 maxlen_flags);
6950
6951 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6952 tg3_write_mem(tp,
6953 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6954 nic_addr);
6955 }
6956
6957 static void __tg3_set_rx_mode(struct net_device *);
6958 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6959 {
6960 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6961 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6962 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6963 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6964 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6965 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6966 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6967 }
6968 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6969 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6970 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6971 u32 val = ec->stats_block_coalesce_usecs;
6972
6973 if (!netif_carrier_ok(tp->dev))
6974 val = 0;
6975
6976 tw32(HOSTCC_STAT_COAL_TICKS, val);
6977 }
6978 }
6979
6980 /* tp->lock is held. */
6981 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6982 {
6983 u32 val, rdmac_mode;
6984 int i, err, limit;
6985
6986 tg3_disable_ints(tp);
6987
6988 tg3_stop_fw(tp);
6989
6990 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6991
6992 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6993 tg3_abort_hw(tp, 1);
6994 }
6995
6996 if (reset_phy &&
6997 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
6998 tg3_phy_reset(tp);
6999
7000 err = tg3_chip_reset(tp);
7001 if (err)
7002 return err;
7003
7004 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7005
7006 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
7007 tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
7008 val = tr32(TG3_CPMU_CTRL);
7009 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7010 tw32(TG3_CPMU_CTRL, val);
7011
7012 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7013 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7014 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7015 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7016
7017 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7018 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7019 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7020 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7021
7022 val = tr32(TG3_CPMU_HST_ACC);
7023 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7024 val |= CPMU_HST_ACC_MACCLK_6_25;
7025 tw32(TG3_CPMU_HST_ACC, val);
7026 }
7027
7028 /* This works around an issue with Athlon chipsets on
7029 * B3 tigon3 silicon. This bit has no effect on any
7030 * other revision. But do not set this on PCI Express
7031 * chips and don't even touch the clocks if the CPMU is present.
7032 */
7033 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7034 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7035 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7036 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7037 }
7038
7039 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7040 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7041 val = tr32(TG3PCI_PCISTATE);
7042 val |= PCISTATE_RETRY_SAME_DMA;
7043 tw32(TG3PCI_PCISTATE, val);
7044 }
7045
7046 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7047 /* Allow reads and writes to the
7048 * APE register and memory space.
7049 */
7050 val = tr32(TG3PCI_PCISTATE);
7051 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7052 PCISTATE_ALLOW_APE_SHMEM_WR;
7053 tw32(TG3PCI_PCISTATE, val);
7054 }
7055
7056 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7057 /* Enable some hw fixes. */
7058 val = tr32(TG3PCI_MSI_DATA);
7059 val |= (1 << 26) | (1 << 28) | (1 << 29);
7060 tw32(TG3PCI_MSI_DATA, val);
7061 }
7062
7063 /* Descriptor ring init may make accesses to the
7064 * NIC SRAM area to setup the TX descriptors, so we
7065 * can only do this after the hardware has been
7066 * successfully reset.
7067 */
7068 err = tg3_init_rings(tp);
7069 if (err)
7070 return err;
7071
7072 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7073 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
7074 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
7075 /* This value is determined during the probe time DMA
7076 * engine test, tg3_test_dma.
7077 */
7078 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7079 }
7080
7081 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7082 GRC_MODE_4X_NIC_SEND_RINGS |
7083 GRC_MODE_NO_TX_PHDR_CSUM |
7084 GRC_MODE_NO_RX_PHDR_CSUM);
7085 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7086
7087 /* Pseudo-header checksum is done by hardware logic and not
7088 * the offload processers, so make the chip do the pseudo-
7089 * header checksums on receive. For transmit it is more
7090 * convenient to do the pseudo-header checksum in software
7091 * as Linux does that on transmit for us in all cases.
7092 */
7093 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7094
7095 tw32(GRC_MODE,
7096 tp->grc_mode |
7097 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7098
7099 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7100 val = tr32(GRC_MISC_CFG);
7101 val &= ~0xff;
7102 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7103 tw32(GRC_MISC_CFG, val);
7104
7105 /* Initialize MBUF/DESC pool. */
7106 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7107 /* Do nothing. */
7108 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7109 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7110 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7111 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7112 else
7113 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7114 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7115 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7116 }
7117 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7118 int fw_len;
7119
7120 fw_len = (TG3_TSO5_FW_TEXT_LEN +
7121 TG3_TSO5_FW_RODATA_LEN +
7122 TG3_TSO5_FW_DATA_LEN +
7123 TG3_TSO5_FW_SBSS_LEN +
7124 TG3_TSO5_FW_BSS_LEN);
7125 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7126 tw32(BUFMGR_MB_POOL_ADDR,
7127 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7128 tw32(BUFMGR_MB_POOL_SIZE,
7129 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7130 }
7131
7132 if (tp->dev->mtu <= ETH_DATA_LEN) {
7133 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7134 tp->bufmgr_config.mbuf_read_dma_low_water);
7135 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7136 tp->bufmgr_config.mbuf_mac_rx_low_water);
7137 tw32(BUFMGR_MB_HIGH_WATER,
7138 tp->bufmgr_config.mbuf_high_water);
7139 } else {
7140 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7141 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7142 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7143 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7144 tw32(BUFMGR_MB_HIGH_WATER,
7145 tp->bufmgr_config.mbuf_high_water_jumbo);
7146 }
7147 tw32(BUFMGR_DMA_LOW_WATER,
7148 tp->bufmgr_config.dma_low_water);
7149 tw32(BUFMGR_DMA_HIGH_WATER,
7150 tp->bufmgr_config.dma_high_water);
7151
7152 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7153 for (i = 0; i < 2000; i++) {
7154 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7155 break;
7156 udelay(10);
7157 }
7158 if (i >= 2000) {
7159 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7160 tp->dev->name);
7161 return -ENODEV;
7162 }
7163
7164 /* Setup replenish threshold. */
7165 val = tp->rx_pending / 8;
7166 if (val == 0)
7167 val = 1;
7168 else if (val > tp->rx_std_max_post)
7169 val = tp->rx_std_max_post;
7170 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7171 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7172 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7173
7174 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7175 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7176 }
7177
7178 tw32(RCVBDI_STD_THRESH, val);
7179
7180 /* Initialize TG3_BDINFO's at:
7181 * RCVDBDI_STD_BD: standard eth size rx ring
7182 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7183 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7184 *
7185 * like so:
7186 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7187 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7188 * ring attribute flags
7189 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7190 *
7191 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7192 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7193 *
7194 * The size of each ring is fixed in the firmware, but the location is
7195 * configurable.
7196 */
7197 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7198 ((u64) tp->rx_std_mapping >> 32));
7199 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7200 ((u64) tp->rx_std_mapping & 0xffffffff));
7201 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7202 NIC_SRAM_RX_BUFFER_DESC);
7203
7204 /* Don't even try to program the JUMBO/MINI buffer descriptor
7205 * configs on 5705.
7206 */
7207 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
7208 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
7209 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
7210 } else {
7211 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
7212 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
7213
7214 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7215 BDINFO_FLAGS_DISABLED);
7216
7217 /* Setup replenish threshold. */
7218 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7219
7220 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7221 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7222 ((u64) tp->rx_jumbo_mapping >> 32));
7223 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7224 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
7225 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7226 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
7227 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7228 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7229 } else {
7230 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7231 BDINFO_FLAGS_DISABLED);
7232 }
7233
7234 }
7235
7236 /* There is only one send ring on 5705/5750, no need to explicitly
7237 * disable the others.
7238 */
7239 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7240 /* Clear out send RCB ring in SRAM. */
7241 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
7242 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7243 BDINFO_FLAGS_DISABLED);
7244 }
7245
7246 tp->tx_prod = 0;
7247 tp->tx_cons = 0;
7248 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7249 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7250
7251 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
7252 tp->tx_desc_mapping,
7253 (TG3_TX_RING_SIZE <<
7254 BDINFO_FLAGS_MAXLEN_SHIFT),
7255 NIC_SRAM_TX_BUFFER_DESC);
7256
7257 /* There is only one receive return ring on 5705/5750, no need
7258 * to explicitly disable the others.
7259 */
7260 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7261 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
7262 i += TG3_BDINFO_SIZE) {
7263 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7264 BDINFO_FLAGS_DISABLED);
7265 }
7266 }
7267
7268 tp->rx_rcb_ptr = 0;
7269 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
7270
7271 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
7272 tp->rx_rcb_mapping,
7273 (TG3_RX_RCB_RING_SIZE(tp) <<
7274 BDINFO_FLAGS_MAXLEN_SHIFT),
7275 0);
7276
7277 tp->rx_std_ptr = tp->rx_pending;
7278 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7279 tp->rx_std_ptr);
7280
7281 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7282 tp->rx_jumbo_pending : 0;
7283 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7284 tp->rx_jumbo_ptr);
7285
7286 /* Initialize MAC address and backoff seed. */
7287 __tg3_set_mac_addr(tp, 0);
7288
7289 /* MTU + ethernet header + FCS + optional VLAN tag */
7290 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
7291
7292 /* The slot time is changed by tg3_setup_phy if we
7293 * run at gigabit with half duplex.
7294 */
7295 tw32(MAC_TX_LENGTHS,
7296 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7297 (6 << TX_LENGTHS_IPG_SHIFT) |
7298 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7299
7300 /* Receive rules. */
7301 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7302 tw32(RCVLPC_CONFIG, 0x0181);
7303
7304 /* Calculate RDMAC_MODE setting early, we need it to determine
7305 * the RCVLPC_STATE_ENABLE mask.
7306 */
7307 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7308 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7309 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7310 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7311 RDMAC_MODE_LNGREAD_ENAB);
7312
7313 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7314 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7315 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7316 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7317 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7318
7319 /* If statement applies to 5705 and 5750 PCI devices only */
7320 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7321 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7322 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7323 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7324 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7325 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7326 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7327 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7328 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7329 }
7330 }
7331
7332 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7333 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7334
7335 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7336 rdmac_mode |= (1 << 27);
7337
7338 /* Receive/send statistics. */
7339 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7340 val = tr32(RCVLPC_STATS_ENABLE);
7341 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7342 tw32(RCVLPC_STATS_ENABLE, val);
7343 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7344 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7345 val = tr32(RCVLPC_STATS_ENABLE);
7346 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7347 tw32(RCVLPC_STATS_ENABLE, val);
7348 } else {
7349 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7350 }
7351 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7352 tw32(SNDDATAI_STATSENAB, 0xffffff);
7353 tw32(SNDDATAI_STATSCTRL,
7354 (SNDDATAI_SCTRL_ENABLE |
7355 SNDDATAI_SCTRL_FASTUPD));
7356
7357 /* Setup host coalescing engine. */
7358 tw32(HOSTCC_MODE, 0);
7359 for (i = 0; i < 2000; i++) {
7360 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7361 break;
7362 udelay(10);
7363 }
7364
7365 __tg3_set_coalesce(tp, &tp->coal);
7366
7367 /* set status block DMA address */
7368 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7369 ((u64) tp->status_mapping >> 32));
7370 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7371 ((u64) tp->status_mapping & 0xffffffff));
7372
7373 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7374 /* Status/statistics block address. See tg3_timer,
7375 * the tg3_periodic_fetch_stats call there, and
7376 * tg3_get_stats to see how this works for 5705/5750 chips.
7377 */
7378 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7379 ((u64) tp->stats_mapping >> 32));
7380 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7381 ((u64) tp->stats_mapping & 0xffffffff));
7382 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7383 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7384 }
7385
7386 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7387
7388 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7389 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7390 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7391 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7392
7393 /* Clear statistics/status block in chip, and status block in ram. */
7394 for (i = NIC_SRAM_STATS_BLK;
7395 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7396 i += sizeof(u32)) {
7397 tg3_write_mem(tp, i, 0);
7398 udelay(40);
7399 }
7400 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
7401
7402 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7403 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7404 /* reset to prevent losing 1st rx packet intermittently */
7405 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7406 udelay(10);
7407 }
7408
7409 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7410 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7411 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7412 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7413 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7414 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7415 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7416 udelay(40);
7417
7418 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7419 * If TG3_FLG2_IS_NIC is zero, we should read the
7420 * register to preserve the GPIO settings for LOMs. The GPIOs,
7421 * whether used as inputs or outputs, are set by boot code after
7422 * reset.
7423 */
7424 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7425 u32 gpio_mask;
7426
7427 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7428 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7429 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7430
7431 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7432 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7433 GRC_LCLCTRL_GPIO_OUTPUT3;
7434
7435 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7436 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7437
7438 tp->grc_local_ctrl &= ~gpio_mask;
7439 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7440
7441 /* GPIO1 must be driven high for eeprom write protect */
7442 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7443 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7444 GRC_LCLCTRL_GPIO_OUTPUT1);
7445 }
7446 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7447 udelay(100);
7448
7449 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
7450 tp->last_tag = 0;
7451
7452 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7453 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7454 udelay(40);
7455 }
7456
7457 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7458 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7459 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7460 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7461 WDMAC_MODE_LNGREAD_ENAB);
7462
7463 /* If statement applies to 5705 and 5750 PCI devices only */
7464 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7465 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7466 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7467 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
7468 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7469 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7470 /* nothing */
7471 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7472 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7473 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7474 val |= WDMAC_MODE_RX_ACCEL;
7475 }
7476 }
7477
7478 /* Enable host coalescing bug fix */
7479 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
7480 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) ||
7481 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) ||
7482 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) ||
7483 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785))
7484 val |= WDMAC_MODE_STATUS_TAG_FIX;
7485
7486 tw32_f(WDMAC_MODE, val);
7487 udelay(40);
7488
7489 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7490 u16 pcix_cmd;
7491
7492 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7493 &pcix_cmd);
7494 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7495 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7496 pcix_cmd |= PCI_X_CMD_READ_2K;
7497 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7498 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7499 pcix_cmd |= PCI_X_CMD_READ_2K;
7500 }
7501 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7502 pcix_cmd);
7503 }
7504
7505 tw32_f(RDMAC_MODE, rdmac_mode);
7506 udelay(40);
7507
7508 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7509 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7510 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7511
7512 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7513 tw32(SNDDATAC_MODE,
7514 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7515 else
7516 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7517
7518 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7519 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7520 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7521 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7522 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7523 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7524 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7525 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7526
7527 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7528 err = tg3_load_5701_a0_firmware_fix(tp);
7529 if (err)
7530 return err;
7531 }
7532
7533 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7534 err = tg3_load_tso_firmware(tp);
7535 if (err)
7536 return err;
7537 }
7538
7539 tp->tx_mode = TX_MODE_ENABLE;
7540 tw32_f(MAC_TX_MODE, tp->tx_mode);
7541 udelay(100);
7542
7543 tp->rx_mode = RX_MODE_ENABLE;
7544 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7545 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7546 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
7547 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7548 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7549
7550 tw32_f(MAC_RX_MODE, tp->rx_mode);
7551 udelay(10);
7552
7553 tw32(MAC_LED_CTRL, tp->led_ctrl);
7554
7555 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7556 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7557 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7558 udelay(10);
7559 }
7560 tw32_f(MAC_RX_MODE, tp->rx_mode);
7561 udelay(10);
7562
7563 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7564 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7565 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7566 /* Set drive transmission level to 1.2V */
7567 /* only if the signal pre-emphasis bit is not set */
7568 val = tr32(MAC_SERDES_CFG);
7569 val &= 0xfffff000;
7570 val |= 0x880;
7571 tw32(MAC_SERDES_CFG, val);
7572 }
7573 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7574 tw32(MAC_SERDES_CFG, 0x616000);
7575 }
7576
7577 /* Prevent chip from dropping frames when flow control
7578 * is enabled.
7579 */
7580 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7581
7582 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7583 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7584 /* Use hardware link auto-negotiation */
7585 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7586 }
7587
7588 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7589 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7590 u32 tmp;
7591
7592 tmp = tr32(SERDES_RX_CTRL);
7593 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7594 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7595 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7596 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7597 }
7598
7599 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7600 if (tp->link_config.phy_is_low_power) {
7601 tp->link_config.phy_is_low_power = 0;
7602 tp->link_config.speed = tp->link_config.orig_speed;
7603 tp->link_config.duplex = tp->link_config.orig_duplex;
7604 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7605 }
7606
7607 err = tg3_setup_phy(tp, 0);
7608 if (err)
7609 return err;
7610
7611 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7612 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
7613 u32 tmp;
7614
7615 /* Clear CRC stats. */
7616 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7617 tg3_writephy(tp, MII_TG3_TEST1,
7618 tmp | MII_TG3_TEST1_CRC_EN);
7619 tg3_readphy(tp, 0x14, &tmp);
7620 }
7621 }
7622 }
7623
7624 __tg3_set_rx_mode(tp->dev);
7625
7626 /* Initialize receive rules. */
7627 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7628 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7629 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7630 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7631
7632 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7633 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7634 limit = 8;
7635 else
7636 limit = 16;
7637 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7638 limit -= 4;
7639 switch (limit) {
7640 case 16:
7641 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7642 case 15:
7643 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7644 case 14:
7645 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7646 case 13:
7647 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7648 case 12:
7649 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7650 case 11:
7651 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7652 case 10:
7653 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7654 case 9:
7655 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7656 case 8:
7657 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7658 case 7:
7659 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7660 case 6:
7661 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7662 case 5:
7663 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7664 case 4:
7665 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7666 case 3:
7667 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7668 case 2:
7669 case 1:
7670
7671 default:
7672 break;
7673 }
7674
7675 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7676 /* Write our heartbeat update interval to APE. */
7677 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7678 APE_HOST_HEARTBEAT_INT_DISABLE);
7679
7680 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7681
7682 return 0;
7683 }
7684
7685 /* Called at device open time to get the chip ready for
7686 * packet processing. Invoked with tp->lock held.
7687 */
7688 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7689 {
7690 int err;
7691
7692 /* Force the chip into D0. */
7693 err = tg3_set_power_state(tp, PCI_D0);
7694 if (err)
7695 goto out;
7696
7697 tg3_switch_clocks(tp);
7698
7699 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7700
7701 err = tg3_reset_hw(tp, reset_phy);
7702
7703 out:
7704 return err;
7705 }
7706
7707 #define TG3_STAT_ADD32(PSTAT, REG) \
7708 do { u32 __val = tr32(REG); \
7709 (PSTAT)->low += __val; \
7710 if ((PSTAT)->low < __val) \
7711 (PSTAT)->high += 1; \
7712 } while (0)
7713
7714 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7715 {
7716 struct tg3_hw_stats *sp = tp->hw_stats;
7717
7718 if (!netif_carrier_ok(tp->dev))
7719 return;
7720
7721 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7722 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7723 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7724 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7725 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7726 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7727 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7728 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7729 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7730 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7731 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7732 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7733 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7734
7735 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7736 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7737 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7738 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7739 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7740 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7741 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7742 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7743 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7744 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7745 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7746 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7747 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7748 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7749
7750 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7751 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7752 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7753 }
7754
7755 static void tg3_timer(unsigned long __opaque)
7756 {
7757 struct tg3 *tp = (struct tg3 *) __opaque;
7758
7759 if (tp->irq_sync)
7760 goto restart_timer;
7761
7762 spin_lock(&tp->lock);
7763
7764 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7765 /* All of this garbage is because when using non-tagged
7766 * IRQ status the mailbox/status_block protocol the chip
7767 * uses with the cpu is race prone.
7768 */
7769 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7770 tw32(GRC_LOCAL_CTRL,
7771 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7772 } else {
7773 tw32(HOSTCC_MODE, tp->coalesce_mode |
7774 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7775 }
7776
7777 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7778 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7779 spin_unlock(&tp->lock);
7780 schedule_work(&tp->reset_task);
7781 return;
7782 }
7783 }
7784
7785 /* This part only runs once per second. */
7786 if (!--tp->timer_counter) {
7787 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7788 tg3_periodic_fetch_stats(tp);
7789
7790 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7791 u32 mac_stat;
7792 int phy_event;
7793
7794 mac_stat = tr32(MAC_STATUS);
7795
7796 phy_event = 0;
7797 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7798 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7799 phy_event = 1;
7800 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7801 phy_event = 1;
7802
7803 if (phy_event)
7804 tg3_setup_phy(tp, 0);
7805 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7806 u32 mac_stat = tr32(MAC_STATUS);
7807 int need_setup = 0;
7808
7809 if (netif_carrier_ok(tp->dev) &&
7810 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7811 need_setup = 1;
7812 }
7813 if (! netif_carrier_ok(tp->dev) &&
7814 (mac_stat & (MAC_STATUS_PCS_SYNCED |
7815 MAC_STATUS_SIGNAL_DET))) {
7816 need_setup = 1;
7817 }
7818 if (need_setup) {
7819 if (!tp->serdes_counter) {
7820 tw32_f(MAC_MODE,
7821 (tp->mac_mode &
7822 ~MAC_MODE_PORT_MODE_MASK));
7823 udelay(40);
7824 tw32_f(MAC_MODE, tp->mac_mode);
7825 udelay(40);
7826 }
7827 tg3_setup_phy(tp, 0);
7828 }
7829 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7830 tg3_serdes_parallel_detect(tp);
7831
7832 tp->timer_counter = tp->timer_multiplier;
7833 }
7834
7835 /* Heartbeat is only sent once every 2 seconds.
7836 *
7837 * The heartbeat is to tell the ASF firmware that the host
7838 * driver is still alive. In the event that the OS crashes,
7839 * ASF needs to reset the hardware to free up the FIFO space
7840 * that may be filled with rx packets destined for the host.
7841 * If the FIFO is full, ASF will no longer function properly.
7842 *
7843 * Unintended resets have been reported on real time kernels
7844 * where the timer doesn't run on time. Netpoll will also have
7845 * same problem.
7846 *
7847 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7848 * to check the ring condition when the heartbeat is expiring
7849 * before doing the reset. This will prevent most unintended
7850 * resets.
7851 */
7852 if (!--tp->asf_counter) {
7853 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7854 u32 val;
7855
7856 tg3_wait_for_event_ack(tp);
7857
7858 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
7859 FWCMD_NICDRV_ALIVE3);
7860 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
7861 /* 5 seconds timeout */
7862 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
7863 val = tr32(GRC_RX_CPU_EVENT);
7864 val |= GRC_RX_CPU_DRIVER_EVENT;
7865 tw32_f(GRC_RX_CPU_EVENT, val);
7866 }
7867 tp->asf_counter = tp->asf_multiplier;
7868 }
7869
7870 spin_unlock(&tp->lock);
7871
7872 restart_timer:
7873 tp->timer.expires = jiffies + tp->timer_offset;
7874 add_timer(&tp->timer);
7875 }
7876
7877 static int tg3_request_irq(struct tg3 *tp)
7878 {
7879 irq_handler_t fn;
7880 unsigned long flags;
7881 struct net_device *dev = tp->dev;
7882
7883 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7884 fn = tg3_msi;
7885 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7886 fn = tg3_msi_1shot;
7887 flags = IRQF_SAMPLE_RANDOM;
7888 } else {
7889 fn = tg3_interrupt;
7890 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7891 fn = tg3_interrupt_tagged;
7892 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
7893 }
7894 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7895 }
7896
7897 static int tg3_test_interrupt(struct tg3 *tp)
7898 {
7899 struct net_device *dev = tp->dev;
7900 int err, i, intr_ok = 0;
7901
7902 if (!netif_running(dev))
7903 return -ENODEV;
7904
7905 tg3_disable_ints(tp);
7906
7907 free_irq(tp->pdev->irq, dev);
7908
7909 err = request_irq(tp->pdev->irq, tg3_test_isr,
7910 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7911 if (err)
7912 return err;
7913
7914 tp->hw_status->status &= ~SD_STATUS_UPDATED;
7915 tg3_enable_ints(tp);
7916
7917 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7918 HOSTCC_MODE_NOW);
7919
7920 for (i = 0; i < 5; i++) {
7921 u32 int_mbox, misc_host_ctrl;
7922
7923 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7924 TG3_64BIT_REG_LOW);
7925 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7926
7927 if ((int_mbox != 0) ||
7928 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7929 intr_ok = 1;
7930 break;
7931 }
7932
7933 msleep(10);
7934 }
7935
7936 tg3_disable_ints(tp);
7937
7938 free_irq(tp->pdev->irq, dev);
7939
7940 err = tg3_request_irq(tp);
7941
7942 if (err)
7943 return err;
7944
7945 if (intr_ok)
7946 return 0;
7947
7948 return -EIO;
7949 }
7950
7951 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7952 * successfully restored
7953 */
7954 static int tg3_test_msi(struct tg3 *tp)
7955 {
7956 struct net_device *dev = tp->dev;
7957 int err;
7958 u16 pci_cmd;
7959
7960 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7961 return 0;
7962
7963 /* Turn off SERR reporting in case MSI terminates with Master
7964 * Abort.
7965 */
7966 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7967 pci_write_config_word(tp->pdev, PCI_COMMAND,
7968 pci_cmd & ~PCI_COMMAND_SERR);
7969
7970 err = tg3_test_interrupt(tp);
7971
7972 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7973
7974 if (!err)
7975 return 0;
7976
7977 /* other failures */
7978 if (err != -EIO)
7979 return err;
7980
7981 /* MSI test failed, go back to INTx mode */
7982 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7983 "switching to INTx mode. Please report this failure to "
7984 "the PCI maintainer and include system chipset information.\n",
7985 tp->dev->name);
7986
7987 free_irq(tp->pdev->irq, dev);
7988 pci_disable_msi(tp->pdev);
7989
7990 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7991
7992 err = tg3_request_irq(tp);
7993 if (err)
7994 return err;
7995
7996 /* Need to reset the chip because the MSI cycle may have terminated
7997 * with Master Abort.
7998 */
7999 tg3_full_lock(tp, 1);
8000
8001 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8002 err = tg3_init_hw(tp, 1);
8003
8004 tg3_full_unlock(tp);
8005
8006 if (err)
8007 free_irq(tp->pdev->irq, dev);
8008
8009 return err;
8010 }
8011
8012 static int tg3_open(struct net_device *dev)
8013 {
8014 struct tg3 *tp = netdev_priv(dev);
8015 int err;
8016
8017 netif_carrier_off(tp->dev);
8018
8019 tg3_full_lock(tp, 0);
8020
8021 err = tg3_set_power_state(tp, PCI_D0);
8022 if (err) {
8023 tg3_full_unlock(tp);
8024 return err;
8025 }
8026
8027 tg3_disable_ints(tp);
8028 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8029
8030 tg3_full_unlock(tp);
8031
8032 /* The placement of this call is tied
8033 * to the setup and use of Host TX descriptors.
8034 */
8035 err = tg3_alloc_consistent(tp);
8036 if (err)
8037 return err;
8038
8039 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
8040 /* All MSI supporting chips should support tagged
8041 * status. Assert that this is the case.
8042 */
8043 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8044 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8045 "Not using MSI.\n", tp->dev->name);
8046 } else if (pci_enable_msi(tp->pdev) == 0) {
8047 u32 msi_mode;
8048
8049 msi_mode = tr32(MSGINT_MODE);
8050 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8051 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8052 }
8053 }
8054 err = tg3_request_irq(tp);
8055
8056 if (err) {
8057 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8058 pci_disable_msi(tp->pdev);
8059 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8060 }
8061 tg3_free_consistent(tp);
8062 return err;
8063 }
8064
8065 napi_enable(&tp->napi);
8066
8067 tg3_full_lock(tp, 0);
8068
8069 err = tg3_init_hw(tp, 1);
8070 if (err) {
8071 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8072 tg3_free_rings(tp);
8073 } else {
8074 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8075 tp->timer_offset = HZ;
8076 else
8077 tp->timer_offset = HZ / 10;
8078
8079 BUG_ON(tp->timer_offset > HZ);
8080 tp->timer_counter = tp->timer_multiplier =
8081 (HZ / tp->timer_offset);
8082 tp->asf_counter = tp->asf_multiplier =
8083 ((HZ / tp->timer_offset) * 2);
8084
8085 init_timer(&tp->timer);
8086 tp->timer.expires = jiffies + tp->timer_offset;
8087 tp->timer.data = (unsigned long) tp;
8088 tp->timer.function = tg3_timer;
8089 }
8090
8091 tg3_full_unlock(tp);
8092
8093 if (err) {
8094 napi_disable(&tp->napi);
8095 free_irq(tp->pdev->irq, dev);
8096 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8097 pci_disable_msi(tp->pdev);
8098 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8099 }
8100 tg3_free_consistent(tp);
8101 return err;
8102 }
8103
8104 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8105 err = tg3_test_msi(tp);
8106
8107 if (err) {
8108 tg3_full_lock(tp, 0);
8109
8110 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8111 pci_disable_msi(tp->pdev);
8112 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8113 }
8114 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8115 tg3_free_rings(tp);
8116 tg3_free_consistent(tp);
8117
8118 tg3_full_unlock(tp);
8119
8120 napi_disable(&tp->napi);
8121
8122 return err;
8123 }
8124
8125 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8126 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
8127 u32 val = tr32(PCIE_TRANSACTION_CFG);
8128
8129 tw32(PCIE_TRANSACTION_CFG,
8130 val | PCIE_TRANS_CFG_1SHOT_MSI);
8131 }
8132 }
8133 }
8134
8135 tg3_phy_start(tp);
8136
8137 tg3_full_lock(tp, 0);
8138
8139 add_timer(&tp->timer);
8140 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8141 tg3_enable_ints(tp);
8142
8143 tg3_full_unlock(tp);
8144
8145 netif_start_queue(dev);
8146
8147 return 0;
8148 }
8149
8150 #if 0
8151 /*static*/ void tg3_dump_state(struct tg3 *tp)
8152 {
8153 u32 val32, val32_2, val32_3, val32_4, val32_5;
8154 u16 val16;
8155 int i;
8156
8157 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8158 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8159 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8160 val16, val32);
8161
8162 /* MAC block */
8163 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8164 tr32(MAC_MODE), tr32(MAC_STATUS));
8165 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8166 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8167 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8168 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8169 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8170 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8171
8172 /* Send data initiator control block */
8173 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8174 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8175 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8176 tr32(SNDDATAI_STATSCTRL));
8177
8178 /* Send data completion control block */
8179 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8180
8181 /* Send BD ring selector block */
8182 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8183 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8184
8185 /* Send BD initiator control block */
8186 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8187 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8188
8189 /* Send BD completion control block */
8190 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8191
8192 /* Receive list placement control block */
8193 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8194 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8195 printk(" RCVLPC_STATSCTRL[%08x]\n",
8196 tr32(RCVLPC_STATSCTRL));
8197
8198 /* Receive data and receive BD initiator control block */
8199 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8200 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8201
8202 /* Receive data completion control block */
8203 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8204 tr32(RCVDCC_MODE));
8205
8206 /* Receive BD initiator control block */
8207 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8208 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8209
8210 /* Receive BD completion control block */
8211 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8212 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8213
8214 /* Receive list selector control block */
8215 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8216 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8217
8218 /* Mbuf cluster free block */
8219 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8220 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8221
8222 /* Host coalescing control block */
8223 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8224 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8225 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8226 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8227 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8228 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8229 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8230 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8231 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8232 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8233 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8234 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8235
8236 /* Memory arbiter control block */
8237 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8238 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8239
8240 /* Buffer manager control block */
8241 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8242 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8243 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8244 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8245 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8246 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8247 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8248 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8249
8250 /* Read DMA control block */
8251 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8252 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8253
8254 /* Write DMA control block */
8255 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8256 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8257
8258 /* DMA completion block */
8259 printk("DEBUG: DMAC_MODE[%08x]\n",
8260 tr32(DMAC_MODE));
8261
8262 /* GRC block */
8263 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8264 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8265 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8266 tr32(GRC_LOCAL_CTRL));
8267
8268 /* TG3_BDINFOs */
8269 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8270 tr32(RCVDBDI_JUMBO_BD + 0x0),
8271 tr32(RCVDBDI_JUMBO_BD + 0x4),
8272 tr32(RCVDBDI_JUMBO_BD + 0x8),
8273 tr32(RCVDBDI_JUMBO_BD + 0xc));
8274 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8275 tr32(RCVDBDI_STD_BD + 0x0),
8276 tr32(RCVDBDI_STD_BD + 0x4),
8277 tr32(RCVDBDI_STD_BD + 0x8),
8278 tr32(RCVDBDI_STD_BD + 0xc));
8279 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8280 tr32(RCVDBDI_MINI_BD + 0x0),
8281 tr32(RCVDBDI_MINI_BD + 0x4),
8282 tr32(RCVDBDI_MINI_BD + 0x8),
8283 tr32(RCVDBDI_MINI_BD + 0xc));
8284
8285 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8286 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8287 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8288 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8289 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8290 val32, val32_2, val32_3, val32_4);
8291
8292 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8293 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8294 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8295 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8296 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8297 val32, val32_2, val32_3, val32_4);
8298
8299 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8300 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8301 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8302 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8303 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8304 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8305 val32, val32_2, val32_3, val32_4, val32_5);
8306
8307 /* SW status block */
8308 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8309 tp->hw_status->status,
8310 tp->hw_status->status_tag,
8311 tp->hw_status->rx_jumbo_consumer,
8312 tp->hw_status->rx_consumer,
8313 tp->hw_status->rx_mini_consumer,
8314 tp->hw_status->idx[0].rx_producer,
8315 tp->hw_status->idx[0].tx_consumer);
8316
8317 /* SW statistics block */
8318 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8319 ((u32 *)tp->hw_stats)[0],
8320 ((u32 *)tp->hw_stats)[1],
8321 ((u32 *)tp->hw_stats)[2],
8322 ((u32 *)tp->hw_stats)[3]);
8323
8324 /* Mailboxes */
8325 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8326 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8327 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8328 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8329 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8330
8331 /* NIC side send descriptors. */
8332 for (i = 0; i < 6; i++) {
8333 unsigned long txd;
8334
8335 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8336 + (i * sizeof(struct tg3_tx_buffer_desc));
8337 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8338 i,
8339 readl(txd + 0x0), readl(txd + 0x4),
8340 readl(txd + 0x8), readl(txd + 0xc));
8341 }
8342
8343 /* NIC side RX descriptors. */
8344 for (i = 0; i < 6; i++) {
8345 unsigned long rxd;
8346
8347 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8348 + (i * sizeof(struct tg3_rx_buffer_desc));
8349 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8350 i,
8351 readl(rxd + 0x0), readl(rxd + 0x4),
8352 readl(rxd + 0x8), readl(rxd + 0xc));
8353 rxd += (4 * sizeof(u32));
8354 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8355 i,
8356 readl(rxd + 0x0), readl(rxd + 0x4),
8357 readl(rxd + 0x8), readl(rxd + 0xc));
8358 }
8359
8360 for (i = 0; i < 6; i++) {
8361 unsigned long rxd;
8362
8363 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8364 + (i * sizeof(struct tg3_rx_buffer_desc));
8365 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8366 i,
8367 readl(rxd + 0x0), readl(rxd + 0x4),
8368 readl(rxd + 0x8), readl(rxd + 0xc));
8369 rxd += (4 * sizeof(u32));
8370 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8371 i,
8372 readl(rxd + 0x0), readl(rxd + 0x4),
8373 readl(rxd + 0x8), readl(rxd + 0xc));
8374 }
8375 }
8376 #endif
8377
8378 static struct net_device_stats *tg3_get_stats(struct net_device *);
8379 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8380
8381 static int tg3_close(struct net_device *dev)
8382 {
8383 struct tg3 *tp = netdev_priv(dev);
8384
8385 napi_disable(&tp->napi);
8386 cancel_work_sync(&tp->reset_task);
8387
8388 netif_stop_queue(dev);
8389
8390 del_timer_sync(&tp->timer);
8391
8392 tg3_full_lock(tp, 1);
8393 #if 0
8394 tg3_dump_state(tp);
8395 #endif
8396
8397 tg3_disable_ints(tp);
8398
8399 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8400 tg3_free_rings(tp);
8401 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8402
8403 tg3_full_unlock(tp);
8404
8405 free_irq(tp->pdev->irq, dev);
8406 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8407 pci_disable_msi(tp->pdev);
8408 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8409 }
8410
8411 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8412 sizeof(tp->net_stats_prev));
8413 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8414 sizeof(tp->estats_prev));
8415
8416 tg3_free_consistent(tp);
8417
8418 tg3_set_power_state(tp, PCI_D3hot);
8419
8420 netif_carrier_off(tp->dev);
8421
8422 return 0;
8423 }
8424
8425 static inline unsigned long get_stat64(tg3_stat64_t *val)
8426 {
8427 unsigned long ret;
8428
8429 #if (BITS_PER_LONG == 32)
8430 ret = val->low;
8431 #else
8432 ret = ((u64)val->high << 32) | ((u64)val->low);
8433 #endif
8434 return ret;
8435 }
8436
8437 static unsigned long calc_crc_errors(struct tg3 *tp)
8438 {
8439 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8440
8441 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8442 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8443 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8444 u32 val;
8445
8446 spin_lock_bh(&tp->lock);
8447 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8448 tg3_writephy(tp, MII_TG3_TEST1,
8449 val | MII_TG3_TEST1_CRC_EN);
8450 tg3_readphy(tp, 0x14, &val);
8451 } else
8452 val = 0;
8453 spin_unlock_bh(&tp->lock);
8454
8455 tp->phy_crc_errors += val;
8456
8457 return tp->phy_crc_errors;
8458 }
8459
8460 return get_stat64(&hw_stats->rx_fcs_errors);
8461 }
8462
8463 #define ESTAT_ADD(member) \
8464 estats->member = old_estats->member + \
8465 get_stat64(&hw_stats->member)
8466
8467 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8468 {
8469 struct tg3_ethtool_stats *estats = &tp->estats;
8470 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8471 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8472
8473 if (!hw_stats)
8474 return old_estats;
8475
8476 ESTAT_ADD(rx_octets);
8477 ESTAT_ADD(rx_fragments);
8478 ESTAT_ADD(rx_ucast_packets);
8479 ESTAT_ADD(rx_mcast_packets);
8480 ESTAT_ADD(rx_bcast_packets);
8481 ESTAT_ADD(rx_fcs_errors);
8482 ESTAT_ADD(rx_align_errors);
8483 ESTAT_ADD(rx_xon_pause_rcvd);
8484 ESTAT_ADD(rx_xoff_pause_rcvd);
8485 ESTAT_ADD(rx_mac_ctrl_rcvd);
8486 ESTAT_ADD(rx_xoff_entered);
8487 ESTAT_ADD(rx_frame_too_long_errors);
8488 ESTAT_ADD(rx_jabbers);
8489 ESTAT_ADD(rx_undersize_packets);
8490 ESTAT_ADD(rx_in_length_errors);
8491 ESTAT_ADD(rx_out_length_errors);
8492 ESTAT_ADD(rx_64_or_less_octet_packets);
8493 ESTAT_ADD(rx_65_to_127_octet_packets);
8494 ESTAT_ADD(rx_128_to_255_octet_packets);
8495 ESTAT_ADD(rx_256_to_511_octet_packets);
8496 ESTAT_ADD(rx_512_to_1023_octet_packets);
8497 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8498 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8499 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8500 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8501 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8502
8503 ESTAT_ADD(tx_octets);
8504 ESTAT_ADD(tx_collisions);
8505 ESTAT_ADD(tx_xon_sent);
8506 ESTAT_ADD(tx_xoff_sent);
8507 ESTAT_ADD(tx_flow_control);
8508 ESTAT_ADD(tx_mac_errors);
8509 ESTAT_ADD(tx_single_collisions);
8510 ESTAT_ADD(tx_mult_collisions);
8511 ESTAT_ADD(tx_deferred);
8512 ESTAT_ADD(tx_excessive_collisions);
8513 ESTAT_ADD(tx_late_collisions);
8514 ESTAT_ADD(tx_collide_2times);
8515 ESTAT_ADD(tx_collide_3times);
8516 ESTAT_ADD(tx_collide_4times);
8517 ESTAT_ADD(tx_collide_5times);
8518 ESTAT_ADD(tx_collide_6times);
8519 ESTAT_ADD(tx_collide_7times);
8520 ESTAT_ADD(tx_collide_8times);
8521 ESTAT_ADD(tx_collide_9times);
8522 ESTAT_ADD(tx_collide_10times);
8523 ESTAT_ADD(tx_collide_11times);
8524 ESTAT_ADD(tx_collide_12times);
8525 ESTAT_ADD(tx_collide_13times);
8526 ESTAT_ADD(tx_collide_14times);
8527 ESTAT_ADD(tx_collide_15times);
8528 ESTAT_ADD(tx_ucast_packets);
8529 ESTAT_ADD(tx_mcast_packets);
8530 ESTAT_ADD(tx_bcast_packets);
8531 ESTAT_ADD(tx_carrier_sense_errors);
8532 ESTAT_ADD(tx_discards);
8533 ESTAT_ADD(tx_errors);
8534
8535 ESTAT_ADD(dma_writeq_full);
8536 ESTAT_ADD(dma_write_prioq_full);
8537 ESTAT_ADD(rxbds_empty);
8538 ESTAT_ADD(rx_discards);
8539 ESTAT_ADD(rx_errors);
8540 ESTAT_ADD(rx_threshold_hit);
8541
8542 ESTAT_ADD(dma_readq_full);
8543 ESTAT_ADD(dma_read_prioq_full);
8544 ESTAT_ADD(tx_comp_queue_full);
8545
8546 ESTAT_ADD(ring_set_send_prod_index);
8547 ESTAT_ADD(ring_status_update);
8548 ESTAT_ADD(nic_irqs);
8549 ESTAT_ADD(nic_avoided_irqs);
8550 ESTAT_ADD(nic_tx_threshold_hit);
8551
8552 return estats;
8553 }
8554
8555 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8556 {
8557 struct tg3 *tp = netdev_priv(dev);
8558 struct net_device_stats *stats = &tp->net_stats;
8559 struct net_device_stats *old_stats = &tp->net_stats_prev;
8560 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8561
8562 if (!hw_stats)
8563 return old_stats;
8564
8565 stats->rx_packets = old_stats->rx_packets +
8566 get_stat64(&hw_stats->rx_ucast_packets) +
8567 get_stat64(&hw_stats->rx_mcast_packets) +
8568 get_stat64(&hw_stats->rx_bcast_packets);
8569
8570 stats->tx_packets = old_stats->tx_packets +
8571 get_stat64(&hw_stats->tx_ucast_packets) +
8572 get_stat64(&hw_stats->tx_mcast_packets) +
8573 get_stat64(&hw_stats->tx_bcast_packets);
8574
8575 stats->rx_bytes = old_stats->rx_bytes +
8576 get_stat64(&hw_stats->rx_octets);
8577 stats->tx_bytes = old_stats->tx_bytes +
8578 get_stat64(&hw_stats->tx_octets);
8579
8580 stats->rx_errors = old_stats->rx_errors +
8581 get_stat64(&hw_stats->rx_errors);
8582 stats->tx_errors = old_stats->tx_errors +
8583 get_stat64(&hw_stats->tx_errors) +
8584 get_stat64(&hw_stats->tx_mac_errors) +
8585 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8586 get_stat64(&hw_stats->tx_discards);
8587
8588 stats->multicast = old_stats->multicast +
8589 get_stat64(&hw_stats->rx_mcast_packets);
8590 stats->collisions = old_stats->collisions +
8591 get_stat64(&hw_stats->tx_collisions);
8592
8593 stats->rx_length_errors = old_stats->rx_length_errors +
8594 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8595 get_stat64(&hw_stats->rx_undersize_packets);
8596
8597 stats->rx_over_errors = old_stats->rx_over_errors +
8598 get_stat64(&hw_stats->rxbds_empty);
8599 stats->rx_frame_errors = old_stats->rx_frame_errors +
8600 get_stat64(&hw_stats->rx_align_errors);
8601 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8602 get_stat64(&hw_stats->tx_discards);
8603 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8604 get_stat64(&hw_stats->tx_carrier_sense_errors);
8605
8606 stats->rx_crc_errors = old_stats->rx_crc_errors +
8607 calc_crc_errors(tp);
8608
8609 stats->rx_missed_errors = old_stats->rx_missed_errors +
8610 get_stat64(&hw_stats->rx_discards);
8611
8612 return stats;
8613 }
8614
8615 static inline u32 calc_crc(unsigned char *buf, int len)
8616 {
8617 u32 reg;
8618 u32 tmp;
8619 int j, k;
8620
8621 reg = 0xffffffff;
8622
8623 for (j = 0; j < len; j++) {
8624 reg ^= buf[j];
8625
8626 for (k = 0; k < 8; k++) {
8627 tmp = reg & 0x01;
8628
8629 reg >>= 1;
8630
8631 if (tmp) {
8632 reg ^= 0xedb88320;
8633 }
8634 }
8635 }
8636
8637 return ~reg;
8638 }
8639
8640 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8641 {
8642 /* accept or reject all multicast frames */
8643 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8644 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8645 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8646 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8647 }
8648
8649 static void __tg3_set_rx_mode(struct net_device *dev)
8650 {
8651 struct tg3 *tp = netdev_priv(dev);
8652 u32 rx_mode;
8653
8654 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8655 RX_MODE_KEEP_VLAN_TAG);
8656
8657 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8658 * flag clear.
8659 */
8660 #if TG3_VLAN_TAG_USED
8661 if (!tp->vlgrp &&
8662 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8663 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8664 #else
8665 /* By definition, VLAN is disabled always in this
8666 * case.
8667 */
8668 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8669 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8670 #endif
8671
8672 if (dev->flags & IFF_PROMISC) {
8673 /* Promiscuous mode. */
8674 rx_mode |= RX_MODE_PROMISC;
8675 } else if (dev->flags & IFF_ALLMULTI) {
8676 /* Accept all multicast. */
8677 tg3_set_multi (tp, 1);
8678 } else if (dev->mc_count < 1) {
8679 /* Reject all multicast. */
8680 tg3_set_multi (tp, 0);
8681 } else {
8682 /* Accept one or more multicast(s). */
8683 struct dev_mc_list *mclist;
8684 unsigned int i;
8685 u32 mc_filter[4] = { 0, };
8686 u32 regidx;
8687 u32 bit;
8688 u32 crc;
8689
8690 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8691 i++, mclist = mclist->next) {
8692
8693 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8694 bit = ~crc & 0x7f;
8695 regidx = (bit & 0x60) >> 5;
8696 bit &= 0x1f;
8697 mc_filter[regidx] |= (1 << bit);
8698 }
8699
8700 tw32(MAC_HASH_REG_0, mc_filter[0]);
8701 tw32(MAC_HASH_REG_1, mc_filter[1]);
8702 tw32(MAC_HASH_REG_2, mc_filter[2]);
8703 tw32(MAC_HASH_REG_3, mc_filter[3]);
8704 }
8705
8706 if (rx_mode != tp->rx_mode) {
8707 tp->rx_mode = rx_mode;
8708 tw32_f(MAC_RX_MODE, rx_mode);
8709 udelay(10);
8710 }
8711 }
8712
8713 static void tg3_set_rx_mode(struct net_device *dev)
8714 {
8715 struct tg3 *tp = netdev_priv(dev);
8716
8717 if (!netif_running(dev))
8718 return;
8719
8720 tg3_full_lock(tp, 0);
8721 __tg3_set_rx_mode(dev);
8722 tg3_full_unlock(tp);
8723 }
8724
8725 #define TG3_REGDUMP_LEN (32 * 1024)
8726
8727 static int tg3_get_regs_len(struct net_device *dev)
8728 {
8729 return TG3_REGDUMP_LEN;
8730 }
8731
8732 static void tg3_get_regs(struct net_device *dev,
8733 struct ethtool_regs *regs, void *_p)
8734 {
8735 u32 *p = _p;
8736 struct tg3 *tp = netdev_priv(dev);
8737 u8 *orig_p = _p;
8738 int i;
8739
8740 regs->version = 0;
8741
8742 memset(p, 0, TG3_REGDUMP_LEN);
8743
8744 if (tp->link_config.phy_is_low_power)
8745 return;
8746
8747 tg3_full_lock(tp, 0);
8748
8749 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
8750 #define GET_REG32_LOOP(base,len) \
8751 do { p = (u32 *)(orig_p + (base)); \
8752 for (i = 0; i < len; i += 4) \
8753 __GET_REG32((base) + i); \
8754 } while (0)
8755 #define GET_REG32_1(reg) \
8756 do { p = (u32 *)(orig_p + (reg)); \
8757 __GET_REG32((reg)); \
8758 } while (0)
8759
8760 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8761 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8762 GET_REG32_LOOP(MAC_MODE, 0x4f0);
8763 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8764 GET_REG32_1(SNDDATAC_MODE);
8765 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8766 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8767 GET_REG32_1(SNDBDC_MODE);
8768 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8769 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8770 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8771 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8772 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8773 GET_REG32_1(RCVDCC_MODE);
8774 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8775 GET_REG32_LOOP(RCVCC_MODE, 0x14);
8776 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8777 GET_REG32_1(MBFREE_MODE);
8778 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8779 GET_REG32_LOOP(MEMARB_MODE, 0x10);
8780 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8781 GET_REG32_LOOP(RDMAC_MODE, 0x08);
8782 GET_REG32_LOOP(WDMAC_MODE, 0x08);
8783 GET_REG32_1(RX_CPU_MODE);
8784 GET_REG32_1(RX_CPU_STATE);
8785 GET_REG32_1(RX_CPU_PGMCTR);
8786 GET_REG32_1(RX_CPU_HWBKPT);
8787 GET_REG32_1(TX_CPU_MODE);
8788 GET_REG32_1(TX_CPU_STATE);
8789 GET_REG32_1(TX_CPU_PGMCTR);
8790 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8791 GET_REG32_LOOP(FTQ_RESET, 0x120);
8792 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8793 GET_REG32_1(DMAC_MODE);
8794 GET_REG32_LOOP(GRC_MODE, 0x4c);
8795 if (tp->tg3_flags & TG3_FLAG_NVRAM)
8796 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8797
8798 #undef __GET_REG32
8799 #undef GET_REG32_LOOP
8800 #undef GET_REG32_1
8801
8802 tg3_full_unlock(tp);
8803 }
8804
8805 static int tg3_get_eeprom_len(struct net_device *dev)
8806 {
8807 struct tg3 *tp = netdev_priv(dev);
8808
8809 return tp->nvram_size;
8810 }
8811
8812 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
8813 static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val);
8814 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
8815
8816 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8817 {
8818 struct tg3 *tp = netdev_priv(dev);
8819 int ret;
8820 u8 *pd;
8821 u32 i, offset, len, b_offset, b_count;
8822 __le32 val;
8823
8824 if (tp->link_config.phy_is_low_power)
8825 return -EAGAIN;
8826
8827 offset = eeprom->offset;
8828 len = eeprom->len;
8829 eeprom->len = 0;
8830
8831 eeprom->magic = TG3_EEPROM_MAGIC;
8832
8833 if (offset & 3) {
8834 /* adjustments to start on required 4 byte boundary */
8835 b_offset = offset & 3;
8836 b_count = 4 - b_offset;
8837 if (b_count > len) {
8838 /* i.e. offset=1 len=2 */
8839 b_count = len;
8840 }
8841 ret = tg3_nvram_read_le(tp, offset-b_offset, &val);
8842 if (ret)
8843 return ret;
8844 memcpy(data, ((char*)&val) + b_offset, b_count);
8845 len -= b_count;
8846 offset += b_count;
8847 eeprom->len += b_count;
8848 }
8849
8850 /* read bytes upto the last 4 byte boundary */
8851 pd = &data[eeprom->len];
8852 for (i = 0; i < (len - (len & 3)); i += 4) {
8853 ret = tg3_nvram_read_le(tp, offset + i, &val);
8854 if (ret) {
8855 eeprom->len += i;
8856 return ret;
8857 }
8858 memcpy(pd + i, &val, 4);
8859 }
8860 eeprom->len += i;
8861
8862 if (len & 3) {
8863 /* read last bytes not ending on 4 byte boundary */
8864 pd = &data[eeprom->len];
8865 b_count = len & 3;
8866 b_offset = offset + len - b_count;
8867 ret = tg3_nvram_read_le(tp, b_offset, &val);
8868 if (ret)
8869 return ret;
8870 memcpy(pd, &val, b_count);
8871 eeprom->len += b_count;
8872 }
8873 return 0;
8874 }
8875
8876 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
8877
8878 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8879 {
8880 struct tg3 *tp = netdev_priv(dev);
8881 int ret;
8882 u32 offset, len, b_offset, odd_len;
8883 u8 *buf;
8884 __le32 start, end;
8885
8886 if (tp->link_config.phy_is_low_power)
8887 return -EAGAIN;
8888
8889 if (eeprom->magic != TG3_EEPROM_MAGIC)
8890 return -EINVAL;
8891
8892 offset = eeprom->offset;
8893 len = eeprom->len;
8894
8895 if ((b_offset = (offset & 3))) {
8896 /* adjustments to start on required 4 byte boundary */
8897 ret = tg3_nvram_read_le(tp, offset-b_offset, &start);
8898 if (ret)
8899 return ret;
8900 len += b_offset;
8901 offset &= ~3;
8902 if (len < 4)
8903 len = 4;
8904 }
8905
8906 odd_len = 0;
8907 if (len & 3) {
8908 /* adjustments to end on required 4 byte boundary */
8909 odd_len = 1;
8910 len = (len + 3) & ~3;
8911 ret = tg3_nvram_read_le(tp, offset+len-4, &end);
8912 if (ret)
8913 return ret;
8914 }
8915
8916 buf = data;
8917 if (b_offset || odd_len) {
8918 buf = kmalloc(len, GFP_KERNEL);
8919 if (!buf)
8920 return -ENOMEM;
8921 if (b_offset)
8922 memcpy(buf, &start, 4);
8923 if (odd_len)
8924 memcpy(buf+len-4, &end, 4);
8925 memcpy(buf + b_offset, data, eeprom->len);
8926 }
8927
8928 ret = tg3_nvram_write_block(tp, offset, len, buf);
8929
8930 if (buf != data)
8931 kfree(buf);
8932
8933 return ret;
8934 }
8935
8936 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8937 {
8938 struct tg3 *tp = netdev_priv(dev);
8939
8940 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8941 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8942 return -EAGAIN;
8943 return phy_ethtool_gset(tp->mdio_bus.phy_map[PHY_ADDR], cmd);
8944 }
8945
8946 cmd->supported = (SUPPORTED_Autoneg);
8947
8948 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8949 cmd->supported |= (SUPPORTED_1000baseT_Half |
8950 SUPPORTED_1000baseT_Full);
8951
8952 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
8953 cmd->supported |= (SUPPORTED_100baseT_Half |
8954 SUPPORTED_100baseT_Full |
8955 SUPPORTED_10baseT_Half |
8956 SUPPORTED_10baseT_Full |
8957 SUPPORTED_TP);
8958 cmd->port = PORT_TP;
8959 } else {
8960 cmd->supported |= SUPPORTED_FIBRE;
8961 cmd->port = PORT_FIBRE;
8962 }
8963
8964 cmd->advertising = tp->link_config.advertising;
8965 if (netif_running(dev)) {
8966 cmd->speed = tp->link_config.active_speed;
8967 cmd->duplex = tp->link_config.active_duplex;
8968 }
8969 cmd->phy_address = PHY_ADDR;
8970 cmd->transceiver = 0;
8971 cmd->autoneg = tp->link_config.autoneg;
8972 cmd->maxtxpkt = 0;
8973 cmd->maxrxpkt = 0;
8974 return 0;
8975 }
8976
8977 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8978 {
8979 struct tg3 *tp = netdev_priv(dev);
8980
8981 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8982 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8983 return -EAGAIN;
8984 return phy_ethtool_sset(tp->mdio_bus.phy_map[PHY_ADDR], cmd);
8985 }
8986
8987 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8988 /* These are the only valid advertisement bits allowed. */
8989 if (cmd->autoneg == AUTONEG_ENABLE &&
8990 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
8991 ADVERTISED_1000baseT_Full |
8992 ADVERTISED_Autoneg |
8993 ADVERTISED_FIBRE)))
8994 return -EINVAL;
8995 /* Fiber can only do SPEED_1000. */
8996 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8997 (cmd->speed != SPEED_1000))
8998 return -EINVAL;
8999 /* Copper cannot force SPEED_1000. */
9000 } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
9001 (cmd->speed == SPEED_1000))
9002 return -EINVAL;
9003 else if ((cmd->speed == SPEED_1000) &&
9004 (tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9005 return -EINVAL;
9006
9007 tg3_full_lock(tp, 0);
9008
9009 tp->link_config.autoneg = cmd->autoneg;
9010 if (cmd->autoneg == AUTONEG_ENABLE) {
9011 tp->link_config.advertising = (cmd->advertising |
9012 ADVERTISED_Autoneg);
9013 tp->link_config.speed = SPEED_INVALID;
9014 tp->link_config.duplex = DUPLEX_INVALID;
9015 } else {
9016 tp->link_config.advertising = 0;
9017 tp->link_config.speed = cmd->speed;
9018 tp->link_config.duplex = cmd->duplex;
9019 }
9020
9021 tp->link_config.orig_speed = tp->link_config.speed;
9022 tp->link_config.orig_duplex = tp->link_config.duplex;
9023 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9024
9025 if (netif_running(dev))
9026 tg3_setup_phy(tp, 1);
9027
9028 tg3_full_unlock(tp);
9029
9030 return 0;
9031 }
9032
9033 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9034 {
9035 struct tg3 *tp = netdev_priv(dev);
9036
9037 strcpy(info->driver, DRV_MODULE_NAME);
9038 strcpy(info->version, DRV_MODULE_VERSION);
9039 strcpy(info->fw_version, tp->fw_ver);
9040 strcpy(info->bus_info, pci_name(tp->pdev));
9041 }
9042
9043 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9044 {
9045 struct tg3 *tp = netdev_priv(dev);
9046
9047 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9048 device_can_wakeup(&tp->pdev->dev))
9049 wol->supported = WAKE_MAGIC;
9050 else
9051 wol->supported = 0;
9052 wol->wolopts = 0;
9053 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
9054 wol->wolopts = WAKE_MAGIC;
9055 memset(&wol->sopass, 0, sizeof(wol->sopass));
9056 }
9057
9058 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9059 {
9060 struct tg3 *tp = netdev_priv(dev);
9061 struct device *dp = &tp->pdev->dev;
9062
9063 if (wol->wolopts & ~WAKE_MAGIC)
9064 return -EINVAL;
9065 if ((wol->wolopts & WAKE_MAGIC) &&
9066 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9067 return -EINVAL;
9068
9069 spin_lock_bh(&tp->lock);
9070 if (wol->wolopts & WAKE_MAGIC) {
9071 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9072 device_set_wakeup_enable(dp, true);
9073 } else {
9074 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9075 device_set_wakeup_enable(dp, false);
9076 }
9077 spin_unlock_bh(&tp->lock);
9078
9079 return 0;
9080 }
9081
9082 static u32 tg3_get_msglevel(struct net_device *dev)
9083 {
9084 struct tg3 *tp = netdev_priv(dev);
9085 return tp->msg_enable;
9086 }
9087
9088 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9089 {
9090 struct tg3 *tp = netdev_priv(dev);
9091 tp->msg_enable = value;
9092 }
9093
9094 static int tg3_set_tso(struct net_device *dev, u32 value)
9095 {
9096 struct tg3 *tp = netdev_priv(dev);
9097
9098 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9099 if (value)
9100 return -EINVAL;
9101 return 0;
9102 }
9103 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
9104 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
9105 if (value) {
9106 dev->features |= NETIF_F_TSO6;
9107 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9108 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9109 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9110 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
9111 dev->features |= NETIF_F_TSO_ECN;
9112 } else
9113 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9114 }
9115 return ethtool_op_set_tso(dev, value);
9116 }
9117
9118 static int tg3_nway_reset(struct net_device *dev)
9119 {
9120 struct tg3 *tp = netdev_priv(dev);
9121 int r;
9122
9123 if (!netif_running(dev))
9124 return -EAGAIN;
9125
9126 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9127 return -EINVAL;
9128
9129 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9130 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9131 return -EAGAIN;
9132 r = phy_start_aneg(tp->mdio_bus.phy_map[PHY_ADDR]);
9133 } else {
9134 u32 bmcr;
9135
9136 spin_lock_bh(&tp->lock);
9137 r = -EINVAL;
9138 tg3_readphy(tp, MII_BMCR, &bmcr);
9139 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9140 ((bmcr & BMCR_ANENABLE) ||
9141 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9142 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9143 BMCR_ANENABLE);
9144 r = 0;
9145 }
9146 spin_unlock_bh(&tp->lock);
9147 }
9148
9149 return r;
9150 }
9151
9152 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9153 {
9154 struct tg3 *tp = netdev_priv(dev);
9155
9156 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9157 ering->rx_mini_max_pending = 0;
9158 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9159 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9160 else
9161 ering->rx_jumbo_max_pending = 0;
9162
9163 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9164
9165 ering->rx_pending = tp->rx_pending;
9166 ering->rx_mini_pending = 0;
9167 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9168 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9169 else
9170 ering->rx_jumbo_pending = 0;
9171
9172 ering->tx_pending = tp->tx_pending;
9173 }
9174
9175 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9176 {
9177 struct tg3 *tp = netdev_priv(dev);
9178 int irq_sync = 0, err = 0;
9179
9180 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9181 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9182 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9183 (ering->tx_pending <= MAX_SKB_FRAGS) ||
9184 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9185 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9186 return -EINVAL;
9187
9188 if (netif_running(dev)) {
9189 tg3_phy_stop(tp);
9190 tg3_netif_stop(tp);
9191 irq_sync = 1;
9192 }
9193
9194 tg3_full_lock(tp, irq_sync);
9195
9196 tp->rx_pending = ering->rx_pending;
9197
9198 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9199 tp->rx_pending > 63)
9200 tp->rx_pending = 63;
9201 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9202 tp->tx_pending = ering->tx_pending;
9203
9204 if (netif_running(dev)) {
9205 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9206 err = tg3_restart_hw(tp, 1);
9207 if (!err)
9208 tg3_netif_start(tp);
9209 }
9210
9211 tg3_full_unlock(tp);
9212
9213 if (irq_sync && !err)
9214 tg3_phy_start(tp);
9215
9216 return err;
9217 }
9218
9219 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9220 {
9221 struct tg3 *tp = netdev_priv(dev);
9222
9223 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9224
9225 if (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX)
9226 epause->rx_pause = 1;
9227 else
9228 epause->rx_pause = 0;
9229
9230 if (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX)
9231 epause->tx_pause = 1;
9232 else
9233 epause->tx_pause = 0;
9234 }
9235
9236 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9237 {
9238 struct tg3 *tp = netdev_priv(dev);
9239 int err = 0;
9240
9241 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9242 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9243 return -EAGAIN;
9244
9245 if (epause->autoneg) {
9246 u32 newadv;
9247 struct phy_device *phydev;
9248
9249 phydev = tp->mdio_bus.phy_map[PHY_ADDR];
9250
9251 if (epause->rx_pause) {
9252 if (epause->tx_pause)
9253 newadv = ADVERTISED_Pause;
9254 else
9255 newadv = ADVERTISED_Pause |
9256 ADVERTISED_Asym_Pause;
9257 } else if (epause->tx_pause) {
9258 newadv = ADVERTISED_Asym_Pause;
9259 } else
9260 newadv = 0;
9261
9262 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9263 u32 oldadv = phydev->advertising &
9264 (ADVERTISED_Pause |
9265 ADVERTISED_Asym_Pause);
9266 if (oldadv != newadv) {
9267 phydev->advertising &=
9268 ~(ADVERTISED_Pause |
9269 ADVERTISED_Asym_Pause);
9270 phydev->advertising |= newadv;
9271 err = phy_start_aneg(phydev);
9272 }
9273 } else {
9274 tp->link_config.advertising &=
9275 ~(ADVERTISED_Pause |
9276 ADVERTISED_Asym_Pause);
9277 tp->link_config.advertising |= newadv;
9278 }
9279 } else {
9280 if (epause->rx_pause)
9281 tp->link_config.flowctrl |= TG3_FLOW_CTRL_RX;
9282 else
9283 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_RX;
9284
9285 if (epause->tx_pause)
9286 tp->link_config.flowctrl |= TG3_FLOW_CTRL_TX;
9287 else
9288 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_TX;
9289
9290 if (netif_running(dev))
9291 tg3_setup_flow_control(tp, 0, 0);
9292 }
9293 } else {
9294 int irq_sync = 0;
9295
9296 if (netif_running(dev)) {
9297 tg3_netif_stop(tp);
9298 irq_sync = 1;
9299 }
9300
9301 tg3_full_lock(tp, irq_sync);
9302
9303 if (epause->autoneg)
9304 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9305 else
9306 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9307 if (epause->rx_pause)
9308 tp->link_config.flowctrl |= TG3_FLOW_CTRL_RX;
9309 else
9310 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_RX;
9311 if (epause->tx_pause)
9312 tp->link_config.flowctrl |= TG3_FLOW_CTRL_TX;
9313 else
9314 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_TX;
9315
9316 if (netif_running(dev)) {
9317 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9318 err = tg3_restart_hw(tp, 1);
9319 if (!err)
9320 tg3_netif_start(tp);
9321 }
9322
9323 tg3_full_unlock(tp);
9324 }
9325
9326 return err;
9327 }
9328
9329 static u32 tg3_get_rx_csum(struct net_device *dev)
9330 {
9331 struct tg3 *tp = netdev_priv(dev);
9332 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9333 }
9334
9335 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9336 {
9337 struct tg3 *tp = netdev_priv(dev);
9338
9339 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9340 if (data != 0)
9341 return -EINVAL;
9342 return 0;
9343 }
9344
9345 spin_lock_bh(&tp->lock);
9346 if (data)
9347 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9348 else
9349 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9350 spin_unlock_bh(&tp->lock);
9351
9352 return 0;
9353 }
9354
9355 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9356 {
9357 struct tg3 *tp = netdev_priv(dev);
9358
9359 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9360 if (data != 0)
9361 return -EINVAL;
9362 return 0;
9363 }
9364
9365 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
9366 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9367 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9368 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9369 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
9370 ethtool_op_set_tx_ipv6_csum(dev, data);
9371 else
9372 ethtool_op_set_tx_csum(dev, data);
9373
9374 return 0;
9375 }
9376
9377 static int tg3_get_sset_count (struct net_device *dev, int sset)
9378 {
9379 switch (sset) {
9380 case ETH_SS_TEST:
9381 return TG3_NUM_TEST;
9382 case ETH_SS_STATS:
9383 return TG3_NUM_STATS;
9384 default:
9385 return -EOPNOTSUPP;
9386 }
9387 }
9388
9389 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9390 {
9391 switch (stringset) {
9392 case ETH_SS_STATS:
9393 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9394 break;
9395 case ETH_SS_TEST:
9396 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9397 break;
9398 default:
9399 WARN_ON(1); /* we need a WARN() */
9400 break;
9401 }
9402 }
9403
9404 static int tg3_phys_id(struct net_device *dev, u32 data)
9405 {
9406 struct tg3 *tp = netdev_priv(dev);
9407 int i;
9408
9409 if (!netif_running(tp->dev))
9410 return -EAGAIN;
9411
9412 if (data == 0)
9413 data = UINT_MAX / 2;
9414
9415 for (i = 0; i < (data * 2); i++) {
9416 if ((i % 2) == 0)
9417 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9418 LED_CTRL_1000MBPS_ON |
9419 LED_CTRL_100MBPS_ON |
9420 LED_CTRL_10MBPS_ON |
9421 LED_CTRL_TRAFFIC_OVERRIDE |
9422 LED_CTRL_TRAFFIC_BLINK |
9423 LED_CTRL_TRAFFIC_LED);
9424
9425 else
9426 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9427 LED_CTRL_TRAFFIC_OVERRIDE);
9428
9429 if (msleep_interruptible(500))
9430 break;
9431 }
9432 tw32(MAC_LED_CTRL, tp->led_ctrl);
9433 return 0;
9434 }
9435
9436 static void tg3_get_ethtool_stats (struct net_device *dev,
9437 struct ethtool_stats *estats, u64 *tmp_stats)
9438 {
9439 struct tg3 *tp = netdev_priv(dev);
9440 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9441 }
9442
9443 #define NVRAM_TEST_SIZE 0x100
9444 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9445 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9446 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
9447 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9448 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9449
9450 static int tg3_test_nvram(struct tg3 *tp)
9451 {
9452 u32 csum, magic;
9453 __le32 *buf;
9454 int i, j, k, err = 0, size;
9455
9456 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
9457 return -EIO;
9458
9459 if (magic == TG3_EEPROM_MAGIC)
9460 size = NVRAM_TEST_SIZE;
9461 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9462 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9463 TG3_EEPROM_SB_FORMAT_1) {
9464 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9465 case TG3_EEPROM_SB_REVISION_0:
9466 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9467 break;
9468 case TG3_EEPROM_SB_REVISION_2:
9469 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9470 break;
9471 case TG3_EEPROM_SB_REVISION_3:
9472 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9473 break;
9474 default:
9475 return 0;
9476 }
9477 } else
9478 return 0;
9479 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9480 size = NVRAM_SELFBOOT_HW_SIZE;
9481 else
9482 return -EIO;
9483
9484 buf = kmalloc(size, GFP_KERNEL);
9485 if (buf == NULL)
9486 return -ENOMEM;
9487
9488 err = -EIO;
9489 for (i = 0, j = 0; i < size; i += 4, j++) {
9490 if ((err = tg3_nvram_read_le(tp, i, &buf[j])) != 0)
9491 break;
9492 }
9493 if (i < size)
9494 goto out;
9495
9496 /* Selfboot format */
9497 magic = swab32(le32_to_cpu(buf[0]));
9498 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9499 TG3_EEPROM_MAGIC_FW) {
9500 u8 *buf8 = (u8 *) buf, csum8 = 0;
9501
9502 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9503 TG3_EEPROM_SB_REVISION_2) {
9504 /* For rev 2, the csum doesn't include the MBA. */
9505 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9506 csum8 += buf8[i];
9507 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9508 csum8 += buf8[i];
9509 } else {
9510 for (i = 0; i < size; i++)
9511 csum8 += buf8[i];
9512 }
9513
9514 if (csum8 == 0) {
9515 err = 0;
9516 goto out;
9517 }
9518
9519 err = -EIO;
9520 goto out;
9521 }
9522
9523 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9524 TG3_EEPROM_MAGIC_HW) {
9525 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9526 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9527 u8 *buf8 = (u8 *) buf;
9528
9529 /* Separate the parity bits and the data bytes. */
9530 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9531 if ((i == 0) || (i == 8)) {
9532 int l;
9533 u8 msk;
9534
9535 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9536 parity[k++] = buf8[i] & msk;
9537 i++;
9538 }
9539 else if (i == 16) {
9540 int l;
9541 u8 msk;
9542
9543 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9544 parity[k++] = buf8[i] & msk;
9545 i++;
9546
9547 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9548 parity[k++] = buf8[i] & msk;
9549 i++;
9550 }
9551 data[j++] = buf8[i];
9552 }
9553
9554 err = -EIO;
9555 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9556 u8 hw8 = hweight8(data[i]);
9557
9558 if ((hw8 & 0x1) && parity[i])
9559 goto out;
9560 else if (!(hw8 & 0x1) && !parity[i])
9561 goto out;
9562 }
9563 err = 0;
9564 goto out;
9565 }
9566
9567 /* Bootstrap checksum at offset 0x10 */
9568 csum = calc_crc((unsigned char *) buf, 0x10);
9569 if(csum != le32_to_cpu(buf[0x10/4]))
9570 goto out;
9571
9572 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9573 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9574 if (csum != le32_to_cpu(buf[0xfc/4]))
9575 goto out;
9576
9577 err = 0;
9578
9579 out:
9580 kfree(buf);
9581 return err;
9582 }
9583
9584 #define TG3_SERDES_TIMEOUT_SEC 2
9585 #define TG3_COPPER_TIMEOUT_SEC 6
9586
9587 static int tg3_test_link(struct tg3 *tp)
9588 {
9589 int i, max;
9590
9591 if (!netif_running(tp->dev))
9592 return -ENODEV;
9593
9594 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9595 max = TG3_SERDES_TIMEOUT_SEC;
9596 else
9597 max = TG3_COPPER_TIMEOUT_SEC;
9598
9599 for (i = 0; i < max; i++) {
9600 if (netif_carrier_ok(tp->dev))
9601 return 0;
9602
9603 if (msleep_interruptible(1000))
9604 break;
9605 }
9606
9607 return -EIO;
9608 }
9609
9610 /* Only test the commonly used registers */
9611 static int tg3_test_registers(struct tg3 *tp)
9612 {
9613 int i, is_5705, is_5750;
9614 u32 offset, read_mask, write_mask, val, save_val, read_val;
9615 static struct {
9616 u16 offset;
9617 u16 flags;
9618 #define TG3_FL_5705 0x1
9619 #define TG3_FL_NOT_5705 0x2
9620 #define TG3_FL_NOT_5788 0x4
9621 #define TG3_FL_NOT_5750 0x8
9622 u32 read_mask;
9623 u32 write_mask;
9624 } reg_tbl[] = {
9625 /* MAC Control Registers */
9626 { MAC_MODE, TG3_FL_NOT_5705,
9627 0x00000000, 0x00ef6f8c },
9628 { MAC_MODE, TG3_FL_5705,
9629 0x00000000, 0x01ef6b8c },
9630 { MAC_STATUS, TG3_FL_NOT_5705,
9631 0x03800107, 0x00000000 },
9632 { MAC_STATUS, TG3_FL_5705,
9633 0x03800100, 0x00000000 },
9634 { MAC_ADDR_0_HIGH, 0x0000,
9635 0x00000000, 0x0000ffff },
9636 { MAC_ADDR_0_LOW, 0x0000,
9637 0x00000000, 0xffffffff },
9638 { MAC_RX_MTU_SIZE, 0x0000,
9639 0x00000000, 0x0000ffff },
9640 { MAC_TX_MODE, 0x0000,
9641 0x00000000, 0x00000070 },
9642 { MAC_TX_LENGTHS, 0x0000,
9643 0x00000000, 0x00003fff },
9644 { MAC_RX_MODE, TG3_FL_NOT_5705,
9645 0x00000000, 0x000007fc },
9646 { MAC_RX_MODE, TG3_FL_5705,
9647 0x00000000, 0x000007dc },
9648 { MAC_HASH_REG_0, 0x0000,
9649 0x00000000, 0xffffffff },
9650 { MAC_HASH_REG_1, 0x0000,
9651 0x00000000, 0xffffffff },
9652 { MAC_HASH_REG_2, 0x0000,
9653 0x00000000, 0xffffffff },
9654 { MAC_HASH_REG_3, 0x0000,
9655 0x00000000, 0xffffffff },
9656
9657 /* Receive Data and Receive BD Initiator Control Registers. */
9658 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9659 0x00000000, 0xffffffff },
9660 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9661 0x00000000, 0xffffffff },
9662 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9663 0x00000000, 0x00000003 },
9664 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9665 0x00000000, 0xffffffff },
9666 { RCVDBDI_STD_BD+0, 0x0000,
9667 0x00000000, 0xffffffff },
9668 { RCVDBDI_STD_BD+4, 0x0000,
9669 0x00000000, 0xffffffff },
9670 { RCVDBDI_STD_BD+8, 0x0000,
9671 0x00000000, 0xffff0002 },
9672 { RCVDBDI_STD_BD+0xc, 0x0000,
9673 0x00000000, 0xffffffff },
9674
9675 /* Receive BD Initiator Control Registers. */
9676 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9677 0x00000000, 0xffffffff },
9678 { RCVBDI_STD_THRESH, TG3_FL_5705,
9679 0x00000000, 0x000003ff },
9680 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9681 0x00000000, 0xffffffff },
9682
9683 /* Host Coalescing Control Registers. */
9684 { HOSTCC_MODE, TG3_FL_NOT_5705,
9685 0x00000000, 0x00000004 },
9686 { HOSTCC_MODE, TG3_FL_5705,
9687 0x00000000, 0x000000f6 },
9688 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9689 0x00000000, 0xffffffff },
9690 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9691 0x00000000, 0x000003ff },
9692 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9693 0x00000000, 0xffffffff },
9694 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9695 0x00000000, 0x000003ff },
9696 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9697 0x00000000, 0xffffffff },
9698 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9699 0x00000000, 0x000000ff },
9700 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9701 0x00000000, 0xffffffff },
9702 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9703 0x00000000, 0x000000ff },
9704 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9705 0x00000000, 0xffffffff },
9706 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9707 0x00000000, 0xffffffff },
9708 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9709 0x00000000, 0xffffffff },
9710 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9711 0x00000000, 0x000000ff },
9712 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9713 0x00000000, 0xffffffff },
9714 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9715 0x00000000, 0x000000ff },
9716 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9717 0x00000000, 0xffffffff },
9718 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9719 0x00000000, 0xffffffff },
9720 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9721 0x00000000, 0xffffffff },
9722 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9723 0x00000000, 0xffffffff },
9724 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9725 0x00000000, 0xffffffff },
9726 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9727 0xffffffff, 0x00000000 },
9728 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9729 0xffffffff, 0x00000000 },
9730
9731 /* Buffer Manager Control Registers. */
9732 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
9733 0x00000000, 0x007fff80 },
9734 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
9735 0x00000000, 0x007fffff },
9736 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9737 0x00000000, 0x0000003f },
9738 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9739 0x00000000, 0x000001ff },
9740 { BUFMGR_MB_HIGH_WATER, 0x0000,
9741 0x00000000, 0x000001ff },
9742 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9743 0xffffffff, 0x00000000 },
9744 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9745 0xffffffff, 0x00000000 },
9746
9747 /* Mailbox Registers */
9748 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9749 0x00000000, 0x000001ff },
9750 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9751 0x00000000, 0x000001ff },
9752 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9753 0x00000000, 0x000007ff },
9754 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9755 0x00000000, 0x000001ff },
9756
9757 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9758 };
9759
9760 is_5705 = is_5750 = 0;
9761 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9762 is_5705 = 1;
9763 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9764 is_5750 = 1;
9765 }
9766
9767 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9768 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9769 continue;
9770
9771 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9772 continue;
9773
9774 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9775 (reg_tbl[i].flags & TG3_FL_NOT_5788))
9776 continue;
9777
9778 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9779 continue;
9780
9781 offset = (u32) reg_tbl[i].offset;
9782 read_mask = reg_tbl[i].read_mask;
9783 write_mask = reg_tbl[i].write_mask;
9784
9785 /* Save the original register content */
9786 save_val = tr32(offset);
9787
9788 /* Determine the read-only value. */
9789 read_val = save_val & read_mask;
9790
9791 /* Write zero to the register, then make sure the read-only bits
9792 * are not changed and the read/write bits are all zeros.
9793 */
9794 tw32(offset, 0);
9795
9796 val = tr32(offset);
9797
9798 /* Test the read-only and read/write bits. */
9799 if (((val & read_mask) != read_val) || (val & write_mask))
9800 goto out;
9801
9802 /* Write ones to all the bits defined by RdMask and WrMask, then
9803 * make sure the read-only bits are not changed and the
9804 * read/write bits are all ones.
9805 */
9806 tw32(offset, read_mask | write_mask);
9807
9808 val = tr32(offset);
9809
9810 /* Test the read-only bits. */
9811 if ((val & read_mask) != read_val)
9812 goto out;
9813
9814 /* Test the read/write bits. */
9815 if ((val & write_mask) != write_mask)
9816 goto out;
9817
9818 tw32(offset, save_val);
9819 }
9820
9821 return 0;
9822
9823 out:
9824 if (netif_msg_hw(tp))
9825 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9826 offset);
9827 tw32(offset, save_val);
9828 return -EIO;
9829 }
9830
9831 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9832 {
9833 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
9834 int i;
9835 u32 j;
9836
9837 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
9838 for (j = 0; j < len; j += 4) {
9839 u32 val;
9840
9841 tg3_write_mem(tp, offset + j, test_pattern[i]);
9842 tg3_read_mem(tp, offset + j, &val);
9843 if (val != test_pattern[i])
9844 return -EIO;
9845 }
9846 }
9847 return 0;
9848 }
9849
9850 static int tg3_test_memory(struct tg3 *tp)
9851 {
9852 static struct mem_entry {
9853 u32 offset;
9854 u32 len;
9855 } mem_tbl_570x[] = {
9856 { 0x00000000, 0x00b50},
9857 { 0x00002000, 0x1c000},
9858 { 0xffffffff, 0x00000}
9859 }, mem_tbl_5705[] = {
9860 { 0x00000100, 0x0000c},
9861 { 0x00000200, 0x00008},
9862 { 0x00004000, 0x00800},
9863 { 0x00006000, 0x01000},
9864 { 0x00008000, 0x02000},
9865 { 0x00010000, 0x0e000},
9866 { 0xffffffff, 0x00000}
9867 }, mem_tbl_5755[] = {
9868 { 0x00000200, 0x00008},
9869 { 0x00004000, 0x00800},
9870 { 0x00006000, 0x00800},
9871 { 0x00008000, 0x02000},
9872 { 0x00010000, 0x0c000},
9873 { 0xffffffff, 0x00000}
9874 }, mem_tbl_5906[] = {
9875 { 0x00000200, 0x00008},
9876 { 0x00004000, 0x00400},
9877 { 0x00006000, 0x00400},
9878 { 0x00008000, 0x01000},
9879 { 0x00010000, 0x01000},
9880 { 0xffffffff, 0x00000}
9881 };
9882 struct mem_entry *mem_tbl;
9883 int err = 0;
9884 int i;
9885
9886 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9887 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
9888 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9889 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9890 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9891 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
9892 mem_tbl = mem_tbl_5755;
9893 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9894 mem_tbl = mem_tbl_5906;
9895 else
9896 mem_tbl = mem_tbl_5705;
9897 } else
9898 mem_tbl = mem_tbl_570x;
9899
9900 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9901 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9902 mem_tbl[i].len)) != 0)
9903 break;
9904 }
9905
9906 return err;
9907 }
9908
9909 #define TG3_MAC_LOOPBACK 0
9910 #define TG3_PHY_LOOPBACK 1
9911
9912 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
9913 {
9914 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
9915 u32 desc_idx;
9916 struct sk_buff *skb, *rx_skb;
9917 u8 *tx_data;
9918 dma_addr_t map;
9919 int num_pkts, tx_len, rx_len, i, err;
9920 struct tg3_rx_buffer_desc *desc;
9921
9922 if (loopback_mode == TG3_MAC_LOOPBACK) {
9923 /* HW errata - mac loopback fails in some cases on 5780.
9924 * Normal traffic and PHY loopback are not affected by
9925 * errata.
9926 */
9927 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9928 return 0;
9929
9930 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
9931 MAC_MODE_PORT_INT_LPBACK;
9932 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9933 mac_mode |= MAC_MODE_LINK_POLARITY;
9934 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9935 mac_mode |= MAC_MODE_PORT_MODE_MII;
9936 else
9937 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9938 tw32(MAC_MODE, mac_mode);
9939 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
9940 u32 val;
9941
9942 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9943 u32 phytest;
9944
9945 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
9946 u32 phy;
9947
9948 tg3_writephy(tp, MII_TG3_EPHY_TEST,
9949 phytest | MII_TG3_EPHY_SHADOW_EN);
9950 if (!tg3_readphy(tp, 0x1b, &phy))
9951 tg3_writephy(tp, 0x1b, phy & ~0x20);
9952 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
9953 }
9954 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9955 } else
9956 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
9957
9958 tg3_phy_toggle_automdix(tp, 0);
9959
9960 tg3_writephy(tp, MII_BMCR, val);
9961 udelay(40);
9962
9963 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
9964 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9965 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
9966 mac_mode |= MAC_MODE_PORT_MODE_MII;
9967 } else
9968 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9969
9970 /* reset to prevent losing 1st rx packet intermittently */
9971 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9972 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9973 udelay(10);
9974 tw32_f(MAC_RX_MODE, tp->rx_mode);
9975 }
9976 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9977 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9978 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9979 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9980 mac_mode |= MAC_MODE_LINK_POLARITY;
9981 tg3_writephy(tp, MII_TG3_EXT_CTRL,
9982 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9983 }
9984 tw32(MAC_MODE, mac_mode);
9985 }
9986 else
9987 return -EINVAL;
9988
9989 err = -EIO;
9990
9991 tx_len = 1514;
9992 skb = netdev_alloc_skb(tp->dev, tx_len);
9993 if (!skb)
9994 return -ENOMEM;
9995
9996 tx_data = skb_put(skb, tx_len);
9997 memcpy(tx_data, tp->dev->dev_addr, 6);
9998 memset(tx_data + 6, 0x0, 8);
9999
10000 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10001
10002 for (i = 14; i < tx_len; i++)
10003 tx_data[i] = (u8) (i & 0xff);
10004
10005 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10006
10007 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10008 HOSTCC_MODE_NOW);
10009
10010 udelay(10);
10011
10012 rx_start_idx = tp->hw_status->idx[0].rx_producer;
10013
10014 num_pkts = 0;
10015
10016 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
10017
10018 tp->tx_prod++;
10019 num_pkts++;
10020
10021 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
10022 tp->tx_prod);
10023 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
10024
10025 udelay(10);
10026
10027 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
10028 for (i = 0; i < 25; i++) {
10029 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10030 HOSTCC_MODE_NOW);
10031
10032 udelay(10);
10033
10034 tx_idx = tp->hw_status->idx[0].tx_consumer;
10035 rx_idx = tp->hw_status->idx[0].rx_producer;
10036 if ((tx_idx == tp->tx_prod) &&
10037 (rx_idx == (rx_start_idx + num_pkts)))
10038 break;
10039 }
10040
10041 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10042 dev_kfree_skb(skb);
10043
10044 if (tx_idx != tp->tx_prod)
10045 goto out;
10046
10047 if (rx_idx != rx_start_idx + num_pkts)
10048 goto out;
10049
10050 desc = &tp->rx_rcb[rx_start_idx];
10051 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10052 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10053 if (opaque_key != RXD_OPAQUE_RING_STD)
10054 goto out;
10055
10056 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10057 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10058 goto out;
10059
10060 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10061 if (rx_len != tx_len)
10062 goto out;
10063
10064 rx_skb = tp->rx_std_buffers[desc_idx].skb;
10065
10066 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
10067 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10068
10069 for (i = 14; i < tx_len; i++) {
10070 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10071 goto out;
10072 }
10073 err = 0;
10074
10075 /* tg3_free_rings will unmap and free the rx_skb */
10076 out:
10077 return err;
10078 }
10079
10080 #define TG3_MAC_LOOPBACK_FAILED 1
10081 #define TG3_PHY_LOOPBACK_FAILED 2
10082 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10083 TG3_PHY_LOOPBACK_FAILED)
10084
10085 static int tg3_test_loopback(struct tg3 *tp)
10086 {
10087 int err = 0;
10088 u32 cpmuctrl = 0;
10089
10090 if (!netif_running(tp->dev))
10091 return TG3_LOOPBACK_FAILED;
10092
10093 err = tg3_reset_hw(tp, 1);
10094 if (err)
10095 return TG3_LOOPBACK_FAILED;
10096
10097 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10098 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
10099 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
10100 int i;
10101 u32 status;
10102
10103 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10104
10105 /* Wait for up to 40 microseconds to acquire lock. */
10106 for (i = 0; i < 4; i++) {
10107 status = tr32(TG3_CPMU_MUTEX_GNT);
10108 if (status == CPMU_MUTEX_GNT_DRIVER)
10109 break;
10110 udelay(10);
10111 }
10112
10113 if (status != CPMU_MUTEX_GNT_DRIVER)
10114 return TG3_LOOPBACK_FAILED;
10115
10116 /* Turn off link-based power management. */
10117 cpmuctrl = tr32(TG3_CPMU_CTRL);
10118 tw32(TG3_CPMU_CTRL,
10119 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10120 CPMU_CTRL_LINK_AWARE_MODE));
10121 }
10122
10123 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10124 err |= TG3_MAC_LOOPBACK_FAILED;
10125
10126 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10127 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
10128 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
10129 tw32(TG3_CPMU_CTRL, cpmuctrl);
10130
10131 /* Release the mutex */
10132 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10133 }
10134
10135 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10136 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10137 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10138 err |= TG3_PHY_LOOPBACK_FAILED;
10139 }
10140
10141 return err;
10142 }
10143
10144 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10145 u64 *data)
10146 {
10147 struct tg3 *tp = netdev_priv(dev);
10148
10149 if (tp->link_config.phy_is_low_power)
10150 tg3_set_power_state(tp, PCI_D0);
10151
10152 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10153
10154 if (tg3_test_nvram(tp) != 0) {
10155 etest->flags |= ETH_TEST_FL_FAILED;
10156 data[0] = 1;
10157 }
10158 if (tg3_test_link(tp) != 0) {
10159 etest->flags |= ETH_TEST_FL_FAILED;
10160 data[1] = 1;
10161 }
10162 if (etest->flags & ETH_TEST_FL_OFFLINE) {
10163 int err, err2 = 0, irq_sync = 0;
10164
10165 if (netif_running(dev)) {
10166 tg3_phy_stop(tp);
10167 tg3_netif_stop(tp);
10168 irq_sync = 1;
10169 }
10170
10171 tg3_full_lock(tp, irq_sync);
10172
10173 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10174 err = tg3_nvram_lock(tp);
10175 tg3_halt_cpu(tp, RX_CPU_BASE);
10176 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10177 tg3_halt_cpu(tp, TX_CPU_BASE);
10178 if (!err)
10179 tg3_nvram_unlock(tp);
10180
10181 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10182 tg3_phy_reset(tp);
10183
10184 if (tg3_test_registers(tp) != 0) {
10185 etest->flags |= ETH_TEST_FL_FAILED;
10186 data[2] = 1;
10187 }
10188 if (tg3_test_memory(tp) != 0) {
10189 etest->flags |= ETH_TEST_FL_FAILED;
10190 data[3] = 1;
10191 }
10192 if ((data[4] = tg3_test_loopback(tp)) != 0)
10193 etest->flags |= ETH_TEST_FL_FAILED;
10194
10195 tg3_full_unlock(tp);
10196
10197 if (tg3_test_interrupt(tp) != 0) {
10198 etest->flags |= ETH_TEST_FL_FAILED;
10199 data[5] = 1;
10200 }
10201
10202 tg3_full_lock(tp, 0);
10203
10204 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10205 if (netif_running(dev)) {
10206 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10207 err2 = tg3_restart_hw(tp, 1);
10208 if (!err2)
10209 tg3_netif_start(tp);
10210 }
10211
10212 tg3_full_unlock(tp);
10213
10214 if (irq_sync && !err2)
10215 tg3_phy_start(tp);
10216 }
10217 if (tp->link_config.phy_is_low_power)
10218 tg3_set_power_state(tp, PCI_D3hot);
10219
10220 }
10221
10222 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10223 {
10224 struct mii_ioctl_data *data = if_mii(ifr);
10225 struct tg3 *tp = netdev_priv(dev);
10226 int err;
10227
10228 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10229 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10230 return -EAGAIN;
10231 return phy_mii_ioctl(tp->mdio_bus.phy_map[PHY_ADDR], data, cmd);
10232 }
10233
10234 switch(cmd) {
10235 case SIOCGMIIPHY:
10236 data->phy_id = PHY_ADDR;
10237
10238 /* fallthru */
10239 case SIOCGMIIREG: {
10240 u32 mii_regval;
10241
10242 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10243 break; /* We have no PHY */
10244
10245 if (tp->link_config.phy_is_low_power)
10246 return -EAGAIN;
10247
10248 spin_lock_bh(&tp->lock);
10249 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10250 spin_unlock_bh(&tp->lock);
10251
10252 data->val_out = mii_regval;
10253
10254 return err;
10255 }
10256
10257 case SIOCSMIIREG:
10258 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10259 break; /* We have no PHY */
10260
10261 if (!capable(CAP_NET_ADMIN))
10262 return -EPERM;
10263
10264 if (tp->link_config.phy_is_low_power)
10265 return -EAGAIN;
10266
10267 spin_lock_bh(&tp->lock);
10268 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10269 spin_unlock_bh(&tp->lock);
10270
10271 return err;
10272
10273 default:
10274 /* do nothing */
10275 break;
10276 }
10277 return -EOPNOTSUPP;
10278 }
10279
10280 #if TG3_VLAN_TAG_USED
10281 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10282 {
10283 struct tg3 *tp = netdev_priv(dev);
10284
10285 if (netif_running(dev))
10286 tg3_netif_stop(tp);
10287
10288 tg3_full_lock(tp, 0);
10289
10290 tp->vlgrp = grp;
10291
10292 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10293 __tg3_set_rx_mode(dev);
10294
10295 if (netif_running(dev))
10296 tg3_netif_start(tp);
10297
10298 tg3_full_unlock(tp);
10299 }
10300 #endif
10301
10302 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10303 {
10304 struct tg3 *tp = netdev_priv(dev);
10305
10306 memcpy(ec, &tp->coal, sizeof(*ec));
10307 return 0;
10308 }
10309
10310 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10311 {
10312 struct tg3 *tp = netdev_priv(dev);
10313 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10314 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10315
10316 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10317 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10318 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10319 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10320 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10321 }
10322
10323 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10324 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10325 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10326 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10327 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10328 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10329 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10330 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10331 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10332 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10333 return -EINVAL;
10334
10335 /* No rx interrupts will be generated if both are zero */
10336 if ((ec->rx_coalesce_usecs == 0) &&
10337 (ec->rx_max_coalesced_frames == 0))
10338 return -EINVAL;
10339
10340 /* No tx interrupts will be generated if both are zero */
10341 if ((ec->tx_coalesce_usecs == 0) &&
10342 (ec->tx_max_coalesced_frames == 0))
10343 return -EINVAL;
10344
10345 /* Only copy relevant parameters, ignore all others. */
10346 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10347 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10348 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10349 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10350 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10351 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10352 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10353 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10354 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10355
10356 if (netif_running(dev)) {
10357 tg3_full_lock(tp, 0);
10358 __tg3_set_coalesce(tp, &tp->coal);
10359 tg3_full_unlock(tp);
10360 }
10361 return 0;
10362 }
10363
10364 static const struct ethtool_ops tg3_ethtool_ops = {
10365 .get_settings = tg3_get_settings,
10366 .set_settings = tg3_set_settings,
10367 .get_drvinfo = tg3_get_drvinfo,
10368 .get_regs_len = tg3_get_regs_len,
10369 .get_regs = tg3_get_regs,
10370 .get_wol = tg3_get_wol,
10371 .set_wol = tg3_set_wol,
10372 .get_msglevel = tg3_get_msglevel,
10373 .set_msglevel = tg3_set_msglevel,
10374 .nway_reset = tg3_nway_reset,
10375 .get_link = ethtool_op_get_link,
10376 .get_eeprom_len = tg3_get_eeprom_len,
10377 .get_eeprom = tg3_get_eeprom,
10378 .set_eeprom = tg3_set_eeprom,
10379 .get_ringparam = tg3_get_ringparam,
10380 .set_ringparam = tg3_set_ringparam,
10381 .get_pauseparam = tg3_get_pauseparam,
10382 .set_pauseparam = tg3_set_pauseparam,
10383 .get_rx_csum = tg3_get_rx_csum,
10384 .set_rx_csum = tg3_set_rx_csum,
10385 .set_tx_csum = tg3_set_tx_csum,
10386 .set_sg = ethtool_op_set_sg,
10387 .set_tso = tg3_set_tso,
10388 .self_test = tg3_self_test,
10389 .get_strings = tg3_get_strings,
10390 .phys_id = tg3_phys_id,
10391 .get_ethtool_stats = tg3_get_ethtool_stats,
10392 .get_coalesce = tg3_get_coalesce,
10393 .set_coalesce = tg3_set_coalesce,
10394 .get_sset_count = tg3_get_sset_count,
10395 };
10396
10397 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10398 {
10399 u32 cursize, val, magic;
10400
10401 tp->nvram_size = EEPROM_CHIP_SIZE;
10402
10403 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
10404 return;
10405
10406 if ((magic != TG3_EEPROM_MAGIC) &&
10407 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10408 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10409 return;
10410
10411 /*
10412 * Size the chip by reading offsets at increasing powers of two.
10413 * When we encounter our validation signature, we know the addressing
10414 * has wrapped around, and thus have our chip size.
10415 */
10416 cursize = 0x10;
10417
10418 while (cursize < tp->nvram_size) {
10419 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
10420 return;
10421
10422 if (val == magic)
10423 break;
10424
10425 cursize <<= 1;
10426 }
10427
10428 tp->nvram_size = cursize;
10429 }
10430
10431 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10432 {
10433 u32 val;
10434
10435 if (tg3_nvram_read_swab(tp, 0, &val) != 0)
10436 return;
10437
10438 /* Selfboot format */
10439 if (val != TG3_EEPROM_MAGIC) {
10440 tg3_get_eeprom_size(tp);
10441 return;
10442 }
10443
10444 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10445 if (val != 0) {
10446 tp->nvram_size = (val >> 16) * 1024;
10447 return;
10448 }
10449 }
10450 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10451 }
10452
10453 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10454 {
10455 u32 nvcfg1;
10456
10457 nvcfg1 = tr32(NVRAM_CFG1);
10458 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10459 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10460 }
10461 else {
10462 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10463 tw32(NVRAM_CFG1, nvcfg1);
10464 }
10465
10466 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10467 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10468 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10469 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10470 tp->nvram_jedecnum = JEDEC_ATMEL;
10471 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10472 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10473 break;
10474 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10475 tp->nvram_jedecnum = JEDEC_ATMEL;
10476 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10477 break;
10478 case FLASH_VENDOR_ATMEL_EEPROM:
10479 tp->nvram_jedecnum = JEDEC_ATMEL;
10480 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10481 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10482 break;
10483 case FLASH_VENDOR_ST:
10484 tp->nvram_jedecnum = JEDEC_ST;
10485 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10486 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10487 break;
10488 case FLASH_VENDOR_SAIFUN:
10489 tp->nvram_jedecnum = JEDEC_SAIFUN;
10490 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10491 break;
10492 case FLASH_VENDOR_SST_SMALL:
10493 case FLASH_VENDOR_SST_LARGE:
10494 tp->nvram_jedecnum = JEDEC_SST;
10495 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10496 break;
10497 }
10498 }
10499 else {
10500 tp->nvram_jedecnum = JEDEC_ATMEL;
10501 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10502 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10503 }
10504 }
10505
10506 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10507 {
10508 u32 nvcfg1;
10509
10510 nvcfg1 = tr32(NVRAM_CFG1);
10511
10512 /* NVRAM protection for TPM */
10513 if (nvcfg1 & (1 << 27))
10514 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10515
10516 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10517 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10518 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10519 tp->nvram_jedecnum = JEDEC_ATMEL;
10520 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10521 break;
10522 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10523 tp->nvram_jedecnum = JEDEC_ATMEL;
10524 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10525 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10526 break;
10527 case FLASH_5752VENDOR_ST_M45PE10:
10528 case FLASH_5752VENDOR_ST_M45PE20:
10529 case FLASH_5752VENDOR_ST_M45PE40:
10530 tp->nvram_jedecnum = JEDEC_ST;
10531 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10532 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10533 break;
10534 }
10535
10536 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10537 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10538 case FLASH_5752PAGE_SIZE_256:
10539 tp->nvram_pagesize = 256;
10540 break;
10541 case FLASH_5752PAGE_SIZE_512:
10542 tp->nvram_pagesize = 512;
10543 break;
10544 case FLASH_5752PAGE_SIZE_1K:
10545 tp->nvram_pagesize = 1024;
10546 break;
10547 case FLASH_5752PAGE_SIZE_2K:
10548 tp->nvram_pagesize = 2048;
10549 break;
10550 case FLASH_5752PAGE_SIZE_4K:
10551 tp->nvram_pagesize = 4096;
10552 break;
10553 case FLASH_5752PAGE_SIZE_264:
10554 tp->nvram_pagesize = 264;
10555 break;
10556 }
10557 }
10558 else {
10559 /* For eeprom, set pagesize to maximum eeprom size */
10560 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10561
10562 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10563 tw32(NVRAM_CFG1, nvcfg1);
10564 }
10565 }
10566
10567 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10568 {
10569 u32 nvcfg1, protect = 0;
10570
10571 nvcfg1 = tr32(NVRAM_CFG1);
10572
10573 /* NVRAM protection for TPM */
10574 if (nvcfg1 & (1 << 27)) {
10575 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10576 protect = 1;
10577 }
10578
10579 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10580 switch (nvcfg1) {
10581 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10582 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10583 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10584 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10585 tp->nvram_jedecnum = JEDEC_ATMEL;
10586 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10587 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10588 tp->nvram_pagesize = 264;
10589 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10590 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10591 tp->nvram_size = (protect ? 0x3e200 :
10592 TG3_NVRAM_SIZE_512KB);
10593 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10594 tp->nvram_size = (protect ? 0x1f200 :
10595 TG3_NVRAM_SIZE_256KB);
10596 else
10597 tp->nvram_size = (protect ? 0x1f200 :
10598 TG3_NVRAM_SIZE_128KB);
10599 break;
10600 case FLASH_5752VENDOR_ST_M45PE10:
10601 case FLASH_5752VENDOR_ST_M45PE20:
10602 case FLASH_5752VENDOR_ST_M45PE40:
10603 tp->nvram_jedecnum = JEDEC_ST;
10604 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10605 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10606 tp->nvram_pagesize = 256;
10607 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10608 tp->nvram_size = (protect ?
10609 TG3_NVRAM_SIZE_64KB :
10610 TG3_NVRAM_SIZE_128KB);
10611 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10612 tp->nvram_size = (protect ?
10613 TG3_NVRAM_SIZE_64KB :
10614 TG3_NVRAM_SIZE_256KB);
10615 else
10616 tp->nvram_size = (protect ?
10617 TG3_NVRAM_SIZE_128KB :
10618 TG3_NVRAM_SIZE_512KB);
10619 break;
10620 }
10621 }
10622
10623 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10624 {
10625 u32 nvcfg1;
10626
10627 nvcfg1 = tr32(NVRAM_CFG1);
10628
10629 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10630 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10631 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10632 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10633 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10634 tp->nvram_jedecnum = JEDEC_ATMEL;
10635 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10636 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10637
10638 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10639 tw32(NVRAM_CFG1, nvcfg1);
10640 break;
10641 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10642 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10643 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10644 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10645 tp->nvram_jedecnum = JEDEC_ATMEL;
10646 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10647 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10648 tp->nvram_pagesize = 264;
10649 break;
10650 case FLASH_5752VENDOR_ST_M45PE10:
10651 case FLASH_5752VENDOR_ST_M45PE20:
10652 case FLASH_5752VENDOR_ST_M45PE40:
10653 tp->nvram_jedecnum = JEDEC_ST;
10654 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10655 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10656 tp->nvram_pagesize = 256;
10657 break;
10658 }
10659 }
10660
10661 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10662 {
10663 u32 nvcfg1, protect = 0;
10664
10665 nvcfg1 = tr32(NVRAM_CFG1);
10666
10667 /* NVRAM protection for TPM */
10668 if (nvcfg1 & (1 << 27)) {
10669 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10670 protect = 1;
10671 }
10672
10673 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10674 switch (nvcfg1) {
10675 case FLASH_5761VENDOR_ATMEL_ADB021D:
10676 case FLASH_5761VENDOR_ATMEL_ADB041D:
10677 case FLASH_5761VENDOR_ATMEL_ADB081D:
10678 case FLASH_5761VENDOR_ATMEL_ADB161D:
10679 case FLASH_5761VENDOR_ATMEL_MDB021D:
10680 case FLASH_5761VENDOR_ATMEL_MDB041D:
10681 case FLASH_5761VENDOR_ATMEL_MDB081D:
10682 case FLASH_5761VENDOR_ATMEL_MDB161D:
10683 tp->nvram_jedecnum = JEDEC_ATMEL;
10684 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10685 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10686 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10687 tp->nvram_pagesize = 256;
10688 break;
10689 case FLASH_5761VENDOR_ST_A_M45PE20:
10690 case FLASH_5761VENDOR_ST_A_M45PE40:
10691 case FLASH_5761VENDOR_ST_A_M45PE80:
10692 case FLASH_5761VENDOR_ST_A_M45PE16:
10693 case FLASH_5761VENDOR_ST_M_M45PE20:
10694 case FLASH_5761VENDOR_ST_M_M45PE40:
10695 case FLASH_5761VENDOR_ST_M_M45PE80:
10696 case FLASH_5761VENDOR_ST_M_M45PE16:
10697 tp->nvram_jedecnum = JEDEC_ST;
10698 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10699 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10700 tp->nvram_pagesize = 256;
10701 break;
10702 }
10703
10704 if (protect) {
10705 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10706 } else {
10707 switch (nvcfg1) {
10708 case FLASH_5761VENDOR_ATMEL_ADB161D:
10709 case FLASH_5761VENDOR_ATMEL_MDB161D:
10710 case FLASH_5761VENDOR_ST_A_M45PE16:
10711 case FLASH_5761VENDOR_ST_M_M45PE16:
10712 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10713 break;
10714 case FLASH_5761VENDOR_ATMEL_ADB081D:
10715 case FLASH_5761VENDOR_ATMEL_MDB081D:
10716 case FLASH_5761VENDOR_ST_A_M45PE80:
10717 case FLASH_5761VENDOR_ST_M_M45PE80:
10718 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10719 break;
10720 case FLASH_5761VENDOR_ATMEL_ADB041D:
10721 case FLASH_5761VENDOR_ATMEL_MDB041D:
10722 case FLASH_5761VENDOR_ST_A_M45PE40:
10723 case FLASH_5761VENDOR_ST_M_M45PE40:
10724 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10725 break;
10726 case FLASH_5761VENDOR_ATMEL_ADB021D:
10727 case FLASH_5761VENDOR_ATMEL_MDB021D:
10728 case FLASH_5761VENDOR_ST_A_M45PE20:
10729 case FLASH_5761VENDOR_ST_M_M45PE20:
10730 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10731 break;
10732 }
10733 }
10734 }
10735
10736 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10737 {
10738 tp->nvram_jedecnum = JEDEC_ATMEL;
10739 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10740 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10741 }
10742
10743 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
10744 static void __devinit tg3_nvram_init(struct tg3 *tp)
10745 {
10746 tw32_f(GRC_EEPROM_ADDR,
10747 (EEPROM_ADDR_FSM_RESET |
10748 (EEPROM_DEFAULT_CLOCK_PERIOD <<
10749 EEPROM_ADDR_CLKPERD_SHIFT)));
10750
10751 msleep(1);
10752
10753 /* Enable seeprom accesses. */
10754 tw32_f(GRC_LOCAL_CTRL,
10755 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10756 udelay(100);
10757
10758 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10759 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10760 tp->tg3_flags |= TG3_FLAG_NVRAM;
10761
10762 if (tg3_nvram_lock(tp)) {
10763 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10764 "tg3_nvram_init failed.\n", tp->dev->name);
10765 return;
10766 }
10767 tg3_enable_nvram_access(tp);
10768
10769 tp->nvram_size = 0;
10770
10771 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10772 tg3_get_5752_nvram_info(tp);
10773 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10774 tg3_get_5755_nvram_info(tp);
10775 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10776 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10777 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10778 tg3_get_5787_nvram_info(tp);
10779 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10780 tg3_get_5761_nvram_info(tp);
10781 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10782 tg3_get_5906_nvram_info(tp);
10783 else
10784 tg3_get_nvram_info(tp);
10785
10786 if (tp->nvram_size == 0)
10787 tg3_get_nvram_size(tp);
10788
10789 tg3_disable_nvram_access(tp);
10790 tg3_nvram_unlock(tp);
10791
10792 } else {
10793 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10794
10795 tg3_get_eeprom_size(tp);
10796 }
10797 }
10798
10799 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
10800 u32 offset, u32 *val)
10801 {
10802 u32 tmp;
10803 int i;
10804
10805 if (offset > EEPROM_ADDR_ADDR_MASK ||
10806 (offset % 4) != 0)
10807 return -EINVAL;
10808
10809 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
10810 EEPROM_ADDR_DEVID_MASK |
10811 EEPROM_ADDR_READ);
10812 tw32(GRC_EEPROM_ADDR,
10813 tmp |
10814 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10815 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
10816 EEPROM_ADDR_ADDR_MASK) |
10817 EEPROM_ADDR_READ | EEPROM_ADDR_START);
10818
10819 for (i = 0; i < 1000; i++) {
10820 tmp = tr32(GRC_EEPROM_ADDR);
10821
10822 if (tmp & EEPROM_ADDR_COMPLETE)
10823 break;
10824 msleep(1);
10825 }
10826 if (!(tmp & EEPROM_ADDR_COMPLETE))
10827 return -EBUSY;
10828
10829 *val = tr32(GRC_EEPROM_DATA);
10830 return 0;
10831 }
10832
10833 #define NVRAM_CMD_TIMEOUT 10000
10834
10835 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
10836 {
10837 int i;
10838
10839 tw32(NVRAM_CMD, nvram_cmd);
10840 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
10841 udelay(10);
10842 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
10843 udelay(10);
10844 break;
10845 }
10846 }
10847 if (i == NVRAM_CMD_TIMEOUT) {
10848 return -EBUSY;
10849 }
10850 return 0;
10851 }
10852
10853 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
10854 {
10855 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
10856 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
10857 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
10858 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
10859 (tp->nvram_jedecnum == JEDEC_ATMEL))
10860
10861 addr = ((addr / tp->nvram_pagesize) <<
10862 ATMEL_AT45DB0X1B_PAGE_POS) +
10863 (addr % tp->nvram_pagesize);
10864
10865 return addr;
10866 }
10867
10868 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
10869 {
10870 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
10871 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
10872 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
10873 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
10874 (tp->nvram_jedecnum == JEDEC_ATMEL))
10875
10876 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
10877 tp->nvram_pagesize) +
10878 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
10879
10880 return addr;
10881 }
10882
10883 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
10884 {
10885 int ret;
10886
10887 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
10888 return tg3_nvram_read_using_eeprom(tp, offset, val);
10889
10890 offset = tg3_nvram_phys_addr(tp, offset);
10891
10892 if (offset > NVRAM_ADDR_MSK)
10893 return -EINVAL;
10894
10895 ret = tg3_nvram_lock(tp);
10896 if (ret)
10897 return ret;
10898
10899 tg3_enable_nvram_access(tp);
10900
10901 tw32(NVRAM_ADDR, offset);
10902 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
10903 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
10904
10905 if (ret == 0)
10906 *val = swab32(tr32(NVRAM_RDDATA));
10907
10908 tg3_disable_nvram_access(tp);
10909
10910 tg3_nvram_unlock(tp);
10911
10912 return ret;
10913 }
10914
10915 static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val)
10916 {
10917 u32 v;
10918 int res = tg3_nvram_read(tp, offset, &v);
10919 if (!res)
10920 *val = cpu_to_le32(v);
10921 return res;
10922 }
10923
10924 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
10925 {
10926 int err;
10927 u32 tmp;
10928
10929 err = tg3_nvram_read(tp, offset, &tmp);
10930 *val = swab32(tmp);
10931 return err;
10932 }
10933
10934 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10935 u32 offset, u32 len, u8 *buf)
10936 {
10937 int i, j, rc = 0;
10938 u32 val;
10939
10940 for (i = 0; i < len; i += 4) {
10941 u32 addr;
10942 __le32 data;
10943
10944 addr = offset + i;
10945
10946 memcpy(&data, buf + i, 4);
10947
10948 tw32(GRC_EEPROM_DATA, le32_to_cpu(data));
10949
10950 val = tr32(GRC_EEPROM_ADDR);
10951 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10952
10953 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10954 EEPROM_ADDR_READ);
10955 tw32(GRC_EEPROM_ADDR, val |
10956 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10957 (addr & EEPROM_ADDR_ADDR_MASK) |
10958 EEPROM_ADDR_START |
10959 EEPROM_ADDR_WRITE);
10960
10961 for (j = 0; j < 1000; j++) {
10962 val = tr32(GRC_EEPROM_ADDR);
10963
10964 if (val & EEPROM_ADDR_COMPLETE)
10965 break;
10966 msleep(1);
10967 }
10968 if (!(val & EEPROM_ADDR_COMPLETE)) {
10969 rc = -EBUSY;
10970 break;
10971 }
10972 }
10973
10974 return rc;
10975 }
10976
10977 /* offset and length are dword aligned */
10978 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10979 u8 *buf)
10980 {
10981 int ret = 0;
10982 u32 pagesize = tp->nvram_pagesize;
10983 u32 pagemask = pagesize - 1;
10984 u32 nvram_cmd;
10985 u8 *tmp;
10986
10987 tmp = kmalloc(pagesize, GFP_KERNEL);
10988 if (tmp == NULL)
10989 return -ENOMEM;
10990
10991 while (len) {
10992 int j;
10993 u32 phy_addr, page_off, size;
10994
10995 phy_addr = offset & ~pagemask;
10996
10997 for (j = 0; j < pagesize; j += 4) {
10998 if ((ret = tg3_nvram_read_le(tp, phy_addr + j,
10999 (__le32 *) (tmp + j))))
11000 break;
11001 }
11002 if (ret)
11003 break;
11004
11005 page_off = offset & pagemask;
11006 size = pagesize;
11007 if (len < size)
11008 size = len;
11009
11010 len -= size;
11011
11012 memcpy(tmp + page_off, buf, size);
11013
11014 offset = offset + (pagesize - page_off);
11015
11016 tg3_enable_nvram_access(tp);
11017
11018 /*
11019 * Before we can erase the flash page, we need
11020 * to issue a special "write enable" command.
11021 */
11022 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11023
11024 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11025 break;
11026
11027 /* Erase the target page */
11028 tw32(NVRAM_ADDR, phy_addr);
11029
11030 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11031 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11032
11033 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11034 break;
11035
11036 /* Issue another write enable to start the write. */
11037 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11038
11039 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11040 break;
11041
11042 for (j = 0; j < pagesize; j += 4) {
11043 __be32 data;
11044
11045 data = *((__be32 *) (tmp + j));
11046 /* swab32(le32_to_cpu(data)), actually */
11047 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11048
11049 tw32(NVRAM_ADDR, phy_addr + j);
11050
11051 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11052 NVRAM_CMD_WR;
11053
11054 if (j == 0)
11055 nvram_cmd |= NVRAM_CMD_FIRST;
11056 else if (j == (pagesize - 4))
11057 nvram_cmd |= NVRAM_CMD_LAST;
11058
11059 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11060 break;
11061 }
11062 if (ret)
11063 break;
11064 }
11065
11066 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11067 tg3_nvram_exec_cmd(tp, nvram_cmd);
11068
11069 kfree(tmp);
11070
11071 return ret;
11072 }
11073
11074 /* offset and length are dword aligned */
11075 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11076 u8 *buf)
11077 {
11078 int i, ret = 0;
11079
11080 for (i = 0; i < len; i += 4, offset += 4) {
11081 u32 page_off, phy_addr, nvram_cmd;
11082 __be32 data;
11083
11084 memcpy(&data, buf + i, 4);
11085 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11086
11087 page_off = offset % tp->nvram_pagesize;
11088
11089 phy_addr = tg3_nvram_phys_addr(tp, offset);
11090
11091 tw32(NVRAM_ADDR, phy_addr);
11092
11093 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11094
11095 if ((page_off == 0) || (i == 0))
11096 nvram_cmd |= NVRAM_CMD_FIRST;
11097 if (page_off == (tp->nvram_pagesize - 4))
11098 nvram_cmd |= NVRAM_CMD_LAST;
11099
11100 if (i == (len - 4))
11101 nvram_cmd |= NVRAM_CMD_LAST;
11102
11103 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
11104 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
11105 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
11106 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784) &&
11107 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) &&
11108 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) &&
11109 (tp->nvram_jedecnum == JEDEC_ST) &&
11110 (nvram_cmd & NVRAM_CMD_FIRST)) {
11111
11112 if ((ret = tg3_nvram_exec_cmd(tp,
11113 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11114 NVRAM_CMD_DONE)))
11115
11116 break;
11117 }
11118 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11119 /* We always do complete word writes to eeprom. */
11120 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11121 }
11122
11123 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11124 break;
11125 }
11126 return ret;
11127 }
11128
11129 /* offset and length are dword aligned */
11130 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11131 {
11132 int ret;
11133
11134 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11135 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11136 ~GRC_LCLCTRL_GPIO_OUTPUT1);
11137 udelay(40);
11138 }
11139
11140 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11141 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11142 }
11143 else {
11144 u32 grc_mode;
11145
11146 ret = tg3_nvram_lock(tp);
11147 if (ret)
11148 return ret;
11149
11150 tg3_enable_nvram_access(tp);
11151 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11152 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
11153 tw32(NVRAM_WRITE1, 0x406);
11154
11155 grc_mode = tr32(GRC_MODE);
11156 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11157
11158 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11159 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11160
11161 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11162 buf);
11163 }
11164 else {
11165 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11166 buf);
11167 }
11168
11169 grc_mode = tr32(GRC_MODE);
11170 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11171
11172 tg3_disable_nvram_access(tp);
11173 tg3_nvram_unlock(tp);
11174 }
11175
11176 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11177 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11178 udelay(40);
11179 }
11180
11181 return ret;
11182 }
11183
11184 struct subsys_tbl_ent {
11185 u16 subsys_vendor, subsys_devid;
11186 u32 phy_id;
11187 };
11188
11189 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11190 /* Broadcom boards. */
11191 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11192 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11193 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11194 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
11195 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11196 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11197 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
11198 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11199 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11200 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11201 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11202
11203 /* 3com boards. */
11204 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11205 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11206 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
11207 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11208 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11209
11210 /* DELL boards. */
11211 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11212 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11213 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11214 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11215
11216 /* Compaq boards. */
11217 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11218 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11219 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
11220 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11221 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11222
11223 /* IBM boards. */
11224 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11225 };
11226
11227 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11228 {
11229 int i;
11230
11231 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11232 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11233 tp->pdev->subsystem_vendor) &&
11234 (subsys_id_to_phy_id[i].subsys_devid ==
11235 tp->pdev->subsystem_device))
11236 return &subsys_id_to_phy_id[i];
11237 }
11238 return NULL;
11239 }
11240
11241 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11242 {
11243 u32 val;
11244 u16 pmcsr;
11245
11246 /* On some early chips the SRAM cannot be accessed in D3hot state,
11247 * so need make sure we're in D0.
11248 */
11249 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11250 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11251 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11252 msleep(1);
11253
11254 /* Make sure register accesses (indirect or otherwise)
11255 * will function correctly.
11256 */
11257 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11258 tp->misc_host_ctrl);
11259
11260 /* The memory arbiter has to be enabled in order for SRAM accesses
11261 * to succeed. Normally on powerup the tg3 chip firmware will make
11262 * sure it is enabled, but other entities such as system netboot
11263 * code might disable it.
11264 */
11265 val = tr32(MEMARB_MODE);
11266 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11267
11268 tp->phy_id = PHY_ID_INVALID;
11269 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11270
11271 /* Assume an onboard device and WOL capable by default. */
11272 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11273
11274 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11275 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11276 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11277 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11278 }
11279 val = tr32(VCPU_CFGSHDW);
11280 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11281 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11282 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11283 (val & VCPU_CFGSHDW_WOL_MAGPKT) &&
11284 device_may_wakeup(&tp->pdev->dev))
11285 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11286 return;
11287 }
11288
11289 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11290 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11291 u32 nic_cfg, led_cfg;
11292 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11293 int eeprom_phy_serdes = 0;
11294
11295 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11296 tp->nic_sram_data_cfg = nic_cfg;
11297
11298 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11299 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11300 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11301 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11302 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11303 (ver > 0) && (ver < 0x100))
11304 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11305
11306 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11307 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11308
11309 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11310 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11311 eeprom_phy_serdes = 1;
11312
11313 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11314 if (nic_phy_id != 0) {
11315 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11316 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11317
11318 eeprom_phy_id = (id1 >> 16) << 10;
11319 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11320 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11321 } else
11322 eeprom_phy_id = 0;
11323
11324 tp->phy_id = eeprom_phy_id;
11325 if (eeprom_phy_serdes) {
11326 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11327 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11328 else
11329 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11330 }
11331
11332 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11333 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11334 SHASTA_EXT_LED_MODE_MASK);
11335 else
11336 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11337
11338 switch (led_cfg) {
11339 default:
11340 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11341 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11342 break;
11343
11344 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11345 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11346 break;
11347
11348 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11349 tp->led_ctrl = LED_CTRL_MODE_MAC;
11350
11351 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11352 * read on some older 5700/5701 bootcode.
11353 */
11354 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11355 ASIC_REV_5700 ||
11356 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11357 ASIC_REV_5701)
11358 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11359
11360 break;
11361
11362 case SHASTA_EXT_LED_SHARED:
11363 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11364 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11365 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11366 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11367 LED_CTRL_MODE_PHY_2);
11368 break;
11369
11370 case SHASTA_EXT_LED_MAC:
11371 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11372 break;
11373
11374 case SHASTA_EXT_LED_COMBO:
11375 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11376 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11377 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11378 LED_CTRL_MODE_PHY_2);
11379 break;
11380
11381 }
11382
11383 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11384 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11385 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11386 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11387
11388 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11389 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11390
11391 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11392 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11393 if ((tp->pdev->subsystem_vendor ==
11394 PCI_VENDOR_ID_ARIMA) &&
11395 (tp->pdev->subsystem_device == 0x205a ||
11396 tp->pdev->subsystem_device == 0x2063))
11397 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11398 } else {
11399 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11400 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11401 }
11402
11403 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11404 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11405 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11406 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11407 }
11408 if (nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE)
11409 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11410 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11411 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11412 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11413
11414 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11415 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE) &&
11416 device_may_wakeup(&tp->pdev->dev))
11417 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11418
11419 if (cfg2 & (1 << 17))
11420 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11421
11422 /* serdes signal pre-emphasis in register 0x590 set by */
11423 /* bootcode if bit 18 is set */
11424 if (cfg2 & (1 << 18))
11425 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11426
11427 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11428 u32 cfg3;
11429
11430 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11431 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11432 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11433 }
11434
11435 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11436 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11437 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11438 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11439 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11440 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11441 }
11442 }
11443
11444 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11445 {
11446 int i;
11447 u32 val;
11448
11449 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11450 tw32(OTP_CTRL, cmd);
11451
11452 /* Wait for up to 1 ms for command to execute. */
11453 for (i = 0; i < 100; i++) {
11454 val = tr32(OTP_STATUS);
11455 if (val & OTP_STATUS_CMD_DONE)
11456 break;
11457 udelay(10);
11458 }
11459
11460 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11461 }
11462
11463 /* Read the gphy configuration from the OTP region of the chip. The gphy
11464 * configuration is a 32-bit value that straddles the alignment boundary.
11465 * We do two 32-bit reads and then shift and merge the results.
11466 */
11467 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11468 {
11469 u32 bhalf_otp, thalf_otp;
11470
11471 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11472
11473 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11474 return 0;
11475
11476 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11477
11478 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11479 return 0;
11480
11481 thalf_otp = tr32(OTP_READ_DATA);
11482
11483 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11484
11485 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11486 return 0;
11487
11488 bhalf_otp = tr32(OTP_READ_DATA);
11489
11490 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11491 }
11492
11493 static int __devinit tg3_phy_probe(struct tg3 *tp)
11494 {
11495 u32 hw_phy_id_1, hw_phy_id_2;
11496 u32 hw_phy_id, hw_phy_id_masked;
11497 int err;
11498
11499 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11500 return tg3_phy_init(tp);
11501
11502 /* Reading the PHY ID register can conflict with ASF
11503 * firwmare access to the PHY hardware.
11504 */
11505 err = 0;
11506 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11507 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11508 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11509 } else {
11510 /* Now read the physical PHY_ID from the chip and verify
11511 * that it is sane. If it doesn't look good, we fall back
11512 * to either the hard-coded table based PHY_ID and failing
11513 * that the value found in the eeprom area.
11514 */
11515 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11516 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11517
11518 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11519 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11520 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11521
11522 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11523 }
11524
11525 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11526 tp->phy_id = hw_phy_id;
11527 if (hw_phy_id_masked == PHY_ID_BCM8002)
11528 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11529 else
11530 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11531 } else {
11532 if (tp->phy_id != PHY_ID_INVALID) {
11533 /* Do nothing, phy ID already set up in
11534 * tg3_get_eeprom_hw_cfg().
11535 */
11536 } else {
11537 struct subsys_tbl_ent *p;
11538
11539 /* No eeprom signature? Try the hardcoded
11540 * subsys device table.
11541 */
11542 p = lookup_by_subsys(tp);
11543 if (!p)
11544 return -ENODEV;
11545
11546 tp->phy_id = p->phy_id;
11547 if (!tp->phy_id ||
11548 tp->phy_id == PHY_ID_BCM8002)
11549 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11550 }
11551 }
11552
11553 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
11554 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
11555 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
11556 u32 bmsr, adv_reg, tg3_ctrl, mask;
11557
11558 tg3_readphy(tp, MII_BMSR, &bmsr);
11559 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11560 (bmsr & BMSR_LSTATUS))
11561 goto skip_phy_reset;
11562
11563 err = tg3_phy_reset(tp);
11564 if (err)
11565 return err;
11566
11567 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11568 ADVERTISE_100HALF | ADVERTISE_100FULL |
11569 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11570 tg3_ctrl = 0;
11571 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11572 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11573 MII_TG3_CTRL_ADV_1000_FULL);
11574 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11575 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11576 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11577 MII_TG3_CTRL_ENABLE_AS_MASTER);
11578 }
11579
11580 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11581 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11582 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11583 if (!tg3_copper_is_advertising_all(tp, mask)) {
11584 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11585
11586 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11587 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11588
11589 tg3_writephy(tp, MII_BMCR,
11590 BMCR_ANENABLE | BMCR_ANRESTART);
11591 }
11592 tg3_phy_set_wirespeed(tp);
11593
11594 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11595 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11596 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11597 }
11598
11599 skip_phy_reset:
11600 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11601 err = tg3_init_5401phy_dsp(tp);
11602 if (err)
11603 return err;
11604 }
11605
11606 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11607 err = tg3_init_5401phy_dsp(tp);
11608 }
11609
11610 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
11611 tp->link_config.advertising =
11612 (ADVERTISED_1000baseT_Half |
11613 ADVERTISED_1000baseT_Full |
11614 ADVERTISED_Autoneg |
11615 ADVERTISED_FIBRE);
11616 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11617 tp->link_config.advertising &=
11618 ~(ADVERTISED_1000baseT_Half |
11619 ADVERTISED_1000baseT_Full);
11620
11621 return err;
11622 }
11623
11624 static void __devinit tg3_read_partno(struct tg3 *tp)
11625 {
11626 unsigned char vpd_data[256];
11627 unsigned int i;
11628 u32 magic;
11629
11630 if (tg3_nvram_read_swab(tp, 0x0, &magic))
11631 goto out_not_found;
11632
11633 if (magic == TG3_EEPROM_MAGIC) {
11634 for (i = 0; i < 256; i += 4) {
11635 u32 tmp;
11636
11637 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
11638 goto out_not_found;
11639
11640 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
11641 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
11642 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
11643 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
11644 }
11645 } else {
11646 int vpd_cap;
11647
11648 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11649 for (i = 0; i < 256; i += 4) {
11650 u32 tmp, j = 0;
11651 __le32 v;
11652 u16 tmp16;
11653
11654 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11655 i);
11656 while (j++ < 100) {
11657 pci_read_config_word(tp->pdev, vpd_cap +
11658 PCI_VPD_ADDR, &tmp16);
11659 if (tmp16 & 0x8000)
11660 break;
11661 msleep(1);
11662 }
11663 if (!(tmp16 & 0x8000))
11664 goto out_not_found;
11665
11666 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11667 &tmp);
11668 v = cpu_to_le32(tmp);
11669 memcpy(&vpd_data[i], &v, 4);
11670 }
11671 }
11672
11673 /* Now parse and find the part number. */
11674 for (i = 0; i < 254; ) {
11675 unsigned char val = vpd_data[i];
11676 unsigned int block_end;
11677
11678 if (val == 0x82 || val == 0x91) {
11679 i = (i + 3 +
11680 (vpd_data[i + 1] +
11681 (vpd_data[i + 2] << 8)));
11682 continue;
11683 }
11684
11685 if (val != 0x90)
11686 goto out_not_found;
11687
11688 block_end = (i + 3 +
11689 (vpd_data[i + 1] +
11690 (vpd_data[i + 2] << 8)));
11691 i += 3;
11692
11693 if (block_end > 256)
11694 goto out_not_found;
11695
11696 while (i < (block_end - 2)) {
11697 if (vpd_data[i + 0] == 'P' &&
11698 vpd_data[i + 1] == 'N') {
11699 int partno_len = vpd_data[i + 2];
11700
11701 i += 3;
11702 if (partno_len > 24 || (partno_len + i) > 256)
11703 goto out_not_found;
11704
11705 memcpy(tp->board_part_number,
11706 &vpd_data[i], partno_len);
11707
11708 /* Success. */
11709 return;
11710 }
11711 i += 3 + vpd_data[i + 2];
11712 }
11713
11714 /* Part number not found. */
11715 goto out_not_found;
11716 }
11717
11718 out_not_found:
11719 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11720 strcpy(tp->board_part_number, "BCM95906");
11721 else
11722 strcpy(tp->board_part_number, "none");
11723 }
11724
11725 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11726 {
11727 u32 val;
11728
11729 if (tg3_nvram_read_swab(tp, offset, &val) ||
11730 (val & 0xfc000000) != 0x0c000000 ||
11731 tg3_nvram_read_swab(tp, offset + 4, &val) ||
11732 val != 0)
11733 return 0;
11734
11735 return 1;
11736 }
11737
11738 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11739 {
11740 u32 val, offset, start;
11741 u32 ver_offset;
11742 int i, bcnt;
11743
11744 if (tg3_nvram_read_swab(tp, 0, &val))
11745 return;
11746
11747 if (val != TG3_EEPROM_MAGIC)
11748 return;
11749
11750 if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
11751 tg3_nvram_read_swab(tp, 0x4, &start))
11752 return;
11753
11754 offset = tg3_nvram_logical_addr(tp, offset);
11755
11756 if (!tg3_fw_img_is_valid(tp, offset) ||
11757 tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
11758 return;
11759
11760 offset = offset + ver_offset - start;
11761 for (i = 0; i < 16; i += 4) {
11762 __le32 v;
11763 if (tg3_nvram_read_le(tp, offset + i, &v))
11764 return;
11765
11766 memcpy(tp->fw_ver + i, &v, 4);
11767 }
11768
11769 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11770 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11771 return;
11772
11773 for (offset = TG3_NVM_DIR_START;
11774 offset < TG3_NVM_DIR_END;
11775 offset += TG3_NVM_DIRENT_SIZE) {
11776 if (tg3_nvram_read_swab(tp, offset, &val))
11777 return;
11778
11779 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11780 break;
11781 }
11782
11783 if (offset == TG3_NVM_DIR_END)
11784 return;
11785
11786 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11787 start = 0x08000000;
11788 else if (tg3_nvram_read_swab(tp, offset - 4, &start))
11789 return;
11790
11791 if (tg3_nvram_read_swab(tp, offset + 4, &offset) ||
11792 !tg3_fw_img_is_valid(tp, offset) ||
11793 tg3_nvram_read_swab(tp, offset + 8, &val))
11794 return;
11795
11796 offset += val - start;
11797
11798 bcnt = strlen(tp->fw_ver);
11799
11800 tp->fw_ver[bcnt++] = ',';
11801 tp->fw_ver[bcnt++] = ' ';
11802
11803 for (i = 0; i < 4; i++) {
11804 __le32 v;
11805 if (tg3_nvram_read_le(tp, offset, &v))
11806 return;
11807
11808 offset += sizeof(v);
11809
11810 if (bcnt > TG3_VER_SIZE - sizeof(v)) {
11811 memcpy(&tp->fw_ver[bcnt], &v, TG3_VER_SIZE - bcnt);
11812 break;
11813 }
11814
11815 memcpy(&tp->fw_ver[bcnt], &v, sizeof(v));
11816 bcnt += sizeof(v);
11817 }
11818
11819 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
11820 }
11821
11822 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11823
11824 static int __devinit tg3_get_invariants(struct tg3 *tp)
11825 {
11826 static struct pci_device_id write_reorder_chipsets[] = {
11827 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11828 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
11829 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11830 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
11831 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11832 PCI_DEVICE_ID_VIA_8385_0) },
11833 { },
11834 };
11835 u32 misc_ctrl_reg;
11836 u32 cacheline_sz_reg;
11837 u32 pci_state_reg, grc_misc_cfg;
11838 u32 val;
11839 u16 pci_cmd;
11840 int err, pcie_cap;
11841
11842 /* Force memory write invalidate off. If we leave it on,
11843 * then on 5700_BX chips we have to enable a workaround.
11844 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11845 * to match the cacheline size. The Broadcom driver have this
11846 * workaround but turns MWI off all the times so never uses
11847 * it. This seems to suggest that the workaround is insufficient.
11848 */
11849 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11850 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11851 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11852
11853 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11854 * has the register indirect write enable bit set before
11855 * we try to access any of the MMIO registers. It is also
11856 * critical that the PCI-X hw workaround situation is decided
11857 * before that as well.
11858 */
11859 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11860 &misc_ctrl_reg);
11861
11862 tp->pci_chip_rev_id = (misc_ctrl_reg >>
11863 MISC_HOST_CTRL_CHIPREV_SHIFT);
11864 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11865 u32 prod_id_asic_rev;
11866
11867 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11868 &prod_id_asic_rev);
11869 tp->pci_chip_rev_id = prod_id_asic_rev & PROD_ID_ASIC_REV_MASK;
11870 }
11871
11872 /* Wrong chip ID in 5752 A0. This code can be removed later
11873 * as A0 is not in production.
11874 */
11875 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11876 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11877
11878 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11879 * we need to disable memory and use config. cycles
11880 * only to access all registers. The 5702/03 chips
11881 * can mistakenly decode the special cycles from the
11882 * ICH chipsets as memory write cycles, causing corruption
11883 * of register and memory space. Only certain ICH bridges
11884 * will drive special cycles with non-zero data during the
11885 * address phase which can fall within the 5703's address
11886 * range. This is not an ICH bug as the PCI spec allows
11887 * non-zero address during special cycles. However, only
11888 * these ICH bridges are known to drive non-zero addresses
11889 * during special cycles.
11890 *
11891 * Since special cycles do not cross PCI bridges, we only
11892 * enable this workaround if the 5703 is on the secondary
11893 * bus of these ICH bridges.
11894 */
11895 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11896 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11897 static struct tg3_dev_id {
11898 u32 vendor;
11899 u32 device;
11900 u32 rev;
11901 } ich_chipsets[] = {
11902 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11903 PCI_ANY_ID },
11904 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11905 PCI_ANY_ID },
11906 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11907 0xa },
11908 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11909 PCI_ANY_ID },
11910 { },
11911 };
11912 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11913 struct pci_dev *bridge = NULL;
11914
11915 while (pci_id->vendor != 0) {
11916 bridge = pci_get_device(pci_id->vendor, pci_id->device,
11917 bridge);
11918 if (!bridge) {
11919 pci_id++;
11920 continue;
11921 }
11922 if (pci_id->rev != PCI_ANY_ID) {
11923 if (bridge->revision > pci_id->rev)
11924 continue;
11925 }
11926 if (bridge->subordinate &&
11927 (bridge->subordinate->number ==
11928 tp->pdev->bus->number)) {
11929
11930 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11931 pci_dev_put(bridge);
11932 break;
11933 }
11934 }
11935 }
11936
11937 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11938 static struct tg3_dev_id {
11939 u32 vendor;
11940 u32 device;
11941 } bridge_chipsets[] = {
11942 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11943 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11944 { },
11945 };
11946 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
11947 struct pci_dev *bridge = NULL;
11948
11949 while (pci_id->vendor != 0) {
11950 bridge = pci_get_device(pci_id->vendor,
11951 pci_id->device,
11952 bridge);
11953 if (!bridge) {
11954 pci_id++;
11955 continue;
11956 }
11957 if (bridge->subordinate &&
11958 (bridge->subordinate->number <=
11959 tp->pdev->bus->number) &&
11960 (bridge->subordinate->subordinate >=
11961 tp->pdev->bus->number)) {
11962 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
11963 pci_dev_put(bridge);
11964 break;
11965 }
11966 }
11967 }
11968
11969 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
11970 * DMA addresses > 40-bit. This bridge may have other additional
11971 * 57xx devices behind it in some 4-port NIC designs for example.
11972 * Any tg3 device found behind the bridge will also need the 40-bit
11973 * DMA workaround.
11974 */
11975 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11976 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11977 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
11978 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11979 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
11980 }
11981 else {
11982 struct pci_dev *bridge = NULL;
11983
11984 do {
11985 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
11986 PCI_DEVICE_ID_SERVERWORKS_EPB,
11987 bridge);
11988 if (bridge && bridge->subordinate &&
11989 (bridge->subordinate->number <=
11990 tp->pdev->bus->number) &&
11991 (bridge->subordinate->subordinate >=
11992 tp->pdev->bus->number)) {
11993 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11994 pci_dev_put(bridge);
11995 break;
11996 }
11997 } while (bridge);
11998 }
11999
12000 /* Initialize misc host control in PCI block. */
12001 tp->misc_host_ctrl |= (misc_ctrl_reg &
12002 MISC_HOST_CTRL_CHIPREV);
12003 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12004 tp->misc_host_ctrl);
12005
12006 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
12007 &cacheline_sz_reg);
12008
12009 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
12010 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
12011 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
12012 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
12013
12014 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12015 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
12016 tp->pdev_peer = tg3_find_peer(tp);
12017
12018 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12019 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12020 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12021 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12022 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12023 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12024 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12025 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12026 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12027 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12028
12029 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12030 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12031 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12032
12033 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12034 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12035 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12036 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12037 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12038 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12039 tp->pdev_peer == tp->pdev))
12040 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12041
12042 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12043 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12044 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12045 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12046 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12047 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12048 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12049 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
12050 } else {
12051 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12052 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12053 ASIC_REV_5750 &&
12054 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12055 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12056 }
12057 }
12058
12059 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12060 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12061 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
12062
12063 pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12064 if (pcie_cap != 0) {
12065 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12066
12067 pcie_set_readrq(tp->pdev, 4096);
12068
12069 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12070 u16 lnkctl;
12071
12072 pci_read_config_word(tp->pdev,
12073 pcie_cap + PCI_EXP_LNKCTL,
12074 &lnkctl);
12075 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
12076 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12077 }
12078 }
12079
12080 /* If we have an AMD 762 or VIA K8T800 chipset, write
12081 * reordering to the mailbox registers done by the host
12082 * controller can cause major troubles. We read back from
12083 * every mailbox register write to force the writes to be
12084 * posted to the chip in order.
12085 */
12086 if (pci_dev_present(write_reorder_chipsets) &&
12087 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12088 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12089
12090 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12091 tp->pci_lat_timer < 64) {
12092 tp->pci_lat_timer = 64;
12093
12094 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
12095 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
12096 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
12097 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
12098
12099 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
12100 cacheline_sz_reg);
12101 }
12102
12103 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12104 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12105 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12106 if (!tp->pcix_cap) {
12107 printk(KERN_ERR PFX "Cannot find PCI-X "
12108 "capability, aborting.\n");
12109 return -EIO;
12110 }
12111 }
12112
12113 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12114 &pci_state_reg);
12115
12116 if (tp->pcix_cap && (pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
12117 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12118
12119 /* If this is a 5700 BX chipset, and we are in PCI-X
12120 * mode, enable register write workaround.
12121 *
12122 * The workaround is to use indirect register accesses
12123 * for all chip writes not to mailbox registers.
12124 */
12125 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12126 u32 pm_reg;
12127
12128 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12129
12130 /* The chip can have it's power management PCI config
12131 * space registers clobbered due to this bug.
12132 * So explicitly force the chip into D0 here.
12133 */
12134 pci_read_config_dword(tp->pdev,
12135 tp->pm_cap + PCI_PM_CTRL,
12136 &pm_reg);
12137 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12138 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12139 pci_write_config_dword(tp->pdev,
12140 tp->pm_cap + PCI_PM_CTRL,
12141 pm_reg);
12142
12143 /* Also, force SERR#/PERR# in PCI command. */
12144 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12145 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12146 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12147 }
12148 }
12149
12150 /* 5700 BX chips need to have their TX producer index mailboxes
12151 * written twice to workaround a bug.
12152 */
12153 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
12154 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12155
12156 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12157 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12158 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12159 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12160
12161 /* Chip-specific fixup from Broadcom driver */
12162 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12163 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12164 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12165 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12166 }
12167
12168 /* Default fast path register access methods */
12169 tp->read32 = tg3_read32;
12170 tp->write32 = tg3_write32;
12171 tp->read32_mbox = tg3_read32;
12172 tp->write32_mbox = tg3_write32;
12173 tp->write32_tx_mbox = tg3_write32;
12174 tp->write32_rx_mbox = tg3_write32;
12175
12176 /* Various workaround register access methods */
12177 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12178 tp->write32 = tg3_write_indirect_reg32;
12179 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12180 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12181 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12182 /*
12183 * Back to back register writes can cause problems on these
12184 * chips, the workaround is to read back all reg writes
12185 * except those to mailbox regs.
12186 *
12187 * See tg3_write_indirect_reg32().
12188 */
12189 tp->write32 = tg3_write_flush_reg32;
12190 }
12191
12192
12193 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12194 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12195 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12196 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12197 tp->write32_rx_mbox = tg3_write_flush_reg32;
12198 }
12199
12200 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12201 tp->read32 = tg3_read_indirect_reg32;
12202 tp->write32 = tg3_write_indirect_reg32;
12203 tp->read32_mbox = tg3_read_indirect_mbox;
12204 tp->write32_mbox = tg3_write_indirect_mbox;
12205 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12206 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12207
12208 iounmap(tp->regs);
12209 tp->regs = NULL;
12210
12211 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12212 pci_cmd &= ~PCI_COMMAND_MEMORY;
12213 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12214 }
12215 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12216 tp->read32_mbox = tg3_read32_mbox_5906;
12217 tp->write32_mbox = tg3_write32_mbox_5906;
12218 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12219 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12220 }
12221
12222 if (tp->write32 == tg3_write_indirect_reg32 ||
12223 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12224 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12225 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12226 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12227
12228 /* Get eeprom hw config before calling tg3_set_power_state().
12229 * In particular, the TG3_FLG2_IS_NIC flag must be
12230 * determined before calling tg3_set_power_state() so that
12231 * we know whether or not to switch out of Vaux power.
12232 * When the flag is set, it means that GPIO1 is used for eeprom
12233 * write protect and also implies that it is a LOM where GPIOs
12234 * are not used to switch power.
12235 */
12236 tg3_get_eeprom_hw_cfg(tp);
12237
12238 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12239 /* Allow reads and writes to the
12240 * APE register and memory space.
12241 */
12242 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12243 PCISTATE_ALLOW_APE_SHMEM_WR;
12244 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12245 pci_state_reg);
12246 }
12247
12248 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12249 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12250 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12251 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12252
12253 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
12254 tp->pci_chip_rev_id == CHIPREV_ID_5784_A1 ||
12255 tp->pci_chip_rev_id == CHIPREV_ID_5761_A0 ||
12256 tp->pci_chip_rev_id == CHIPREV_ID_5761_A1)
12257 tp->tg3_flags3 |= TG3_FLG3_5761_5784_AX_FIXES;
12258 }
12259
12260 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12261 * GPIO1 driven high will bring 5700's external PHY out of reset.
12262 * It is also used as eeprom write protect on LOMs.
12263 */
12264 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12265 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12266 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12267 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12268 GRC_LCLCTRL_GPIO_OUTPUT1);
12269 /* Unused GPIO3 must be driven as output on 5752 because there
12270 * are no pull-up resistors on unused GPIO pins.
12271 */
12272 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12273 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12274
12275 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12276 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12277
12278 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
12279 /* Turn off the debug UART. */
12280 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12281 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12282 /* Keep VMain power. */
12283 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12284 GRC_LCLCTRL_GPIO_OUTPUT0;
12285 }
12286
12287 /* Force the chip into D0. */
12288 err = tg3_set_power_state(tp, PCI_D0);
12289 if (err) {
12290 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12291 pci_name(tp->pdev));
12292 return err;
12293 }
12294
12295 /* 5700 B0 chips do not support checksumming correctly due
12296 * to hardware bugs.
12297 */
12298 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12299 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12300
12301 /* Derive initial jumbo mode from MTU assigned in
12302 * ether_setup() via the alloc_etherdev() call
12303 */
12304 if (tp->dev->mtu > ETH_DATA_LEN &&
12305 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12306 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12307
12308 /* Determine WakeOnLan speed to use. */
12309 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12310 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12311 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12312 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12313 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12314 } else {
12315 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12316 }
12317
12318 /* A few boards don't want Ethernet@WireSpeed phy feature */
12319 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12320 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12321 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12322 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12323 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
12324 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12325 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12326
12327 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12328 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12329 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12330 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12331 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12332
12333 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12334 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12335 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12336 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12337 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12338 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12339 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12340 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12341 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12342 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12343 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906 &&
12344 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
12345 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12346 }
12347
12348 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12349 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12350 tp->phy_otp = tg3_read_otp_phycfg(tp);
12351 if (tp->phy_otp == 0)
12352 tp->phy_otp = TG3_OTP_DEFAULT;
12353 }
12354
12355 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12356 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12357 else
12358 tp->mi_mode = MAC_MI_MODE_BASE;
12359
12360 tp->coalesce_mode = 0;
12361 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12362 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12363 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12364
12365 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12366 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12367
12368 err = tg3_mdio_init(tp);
12369 if (err)
12370 return err;
12371
12372 /* Initialize data/descriptor byte/word swapping. */
12373 val = tr32(GRC_MODE);
12374 val &= GRC_MODE_HOST_STACKUP;
12375 tw32(GRC_MODE, val | tp->grc_mode);
12376
12377 tg3_switch_clocks(tp);
12378
12379 /* Clear this out for sanity. */
12380 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12381
12382 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12383 &pci_state_reg);
12384 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12385 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12386 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12387
12388 if (chiprevid == CHIPREV_ID_5701_A0 ||
12389 chiprevid == CHIPREV_ID_5701_B0 ||
12390 chiprevid == CHIPREV_ID_5701_B2 ||
12391 chiprevid == CHIPREV_ID_5701_B5) {
12392 void __iomem *sram_base;
12393
12394 /* Write some dummy words into the SRAM status block
12395 * area, see if it reads back correctly. If the return
12396 * value is bad, force enable the PCIX workaround.
12397 */
12398 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12399
12400 writel(0x00000000, sram_base);
12401 writel(0x00000000, sram_base + 4);
12402 writel(0xffffffff, sram_base + 4);
12403 if (readl(sram_base) != 0x00000000)
12404 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12405 }
12406 }
12407
12408 udelay(50);
12409 tg3_nvram_init(tp);
12410
12411 grc_misc_cfg = tr32(GRC_MISC_CFG);
12412 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12413
12414 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12415 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12416 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12417 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12418
12419 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12420 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12421 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12422 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12423 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12424 HOSTCC_MODE_CLRTICK_TXBD);
12425
12426 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12427 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12428 tp->misc_host_ctrl);
12429 }
12430
12431 /* these are limited to 10/100 only */
12432 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12433 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12434 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12435 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12436 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12437 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12438 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12439 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12440 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
12441 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12442 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
12443 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12444 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12445
12446 err = tg3_phy_probe(tp);
12447 if (err) {
12448 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12449 pci_name(tp->pdev), err);
12450 /* ... but do not return immediately ... */
12451 tg3_mdio_fini(tp);
12452 }
12453
12454 tg3_read_partno(tp);
12455 tg3_read_fw_ver(tp);
12456
12457 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12458 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12459 } else {
12460 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12461 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12462 else
12463 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12464 }
12465
12466 /* 5700 {AX,BX} chips have a broken status block link
12467 * change bit implementation, so we must use the
12468 * status register in those cases.
12469 */
12470 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12471 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12472 else
12473 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12474
12475 /* The led_ctrl is set during tg3_phy_probe, here we might
12476 * have to force the link status polling mechanism based
12477 * upon subsystem IDs.
12478 */
12479 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
12480 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12481 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12482 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12483 TG3_FLAG_USE_LINKCHG_REG);
12484 }
12485
12486 /* For all SERDES we poll the MAC status register. */
12487 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12488 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12489 else
12490 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12491
12492 /* All chips before 5787 can get confused if TX buffers
12493 * straddle the 4GB address boundary in some cases.
12494 */
12495 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12496 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12497 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12498 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12499 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12500 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12501 tp->dev->hard_start_xmit = tg3_start_xmit;
12502 else
12503 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
12504
12505 tp->rx_offset = 2;
12506 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12507 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12508 tp->rx_offset = 0;
12509
12510 tp->rx_std_max_post = TG3_RX_RING_SIZE;
12511
12512 /* Increment the rx prod index on the rx std ring by at most
12513 * 8 for these chips to workaround hw errata.
12514 */
12515 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12516 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12517 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12518 tp->rx_std_max_post = 8;
12519
12520 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12521 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12522 PCIE_PWR_MGMT_L1_THRESH_MSK;
12523
12524 return err;
12525 }
12526
12527 #ifdef CONFIG_SPARC
12528 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12529 {
12530 struct net_device *dev = tp->dev;
12531 struct pci_dev *pdev = tp->pdev;
12532 struct device_node *dp = pci_device_to_OF_node(pdev);
12533 const unsigned char *addr;
12534 int len;
12535
12536 addr = of_get_property(dp, "local-mac-address", &len);
12537 if (addr && len == 6) {
12538 memcpy(dev->dev_addr, addr, 6);
12539 memcpy(dev->perm_addr, dev->dev_addr, 6);
12540 return 0;
12541 }
12542 return -ENODEV;
12543 }
12544
12545 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12546 {
12547 struct net_device *dev = tp->dev;
12548
12549 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
12550 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
12551 return 0;
12552 }
12553 #endif
12554
12555 static int __devinit tg3_get_device_address(struct tg3 *tp)
12556 {
12557 struct net_device *dev = tp->dev;
12558 u32 hi, lo, mac_offset;
12559 int addr_ok = 0;
12560
12561 #ifdef CONFIG_SPARC
12562 if (!tg3_get_macaddr_sparc(tp))
12563 return 0;
12564 #endif
12565
12566 mac_offset = 0x7c;
12567 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12568 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12569 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12570 mac_offset = 0xcc;
12571 if (tg3_nvram_lock(tp))
12572 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12573 else
12574 tg3_nvram_unlock(tp);
12575 }
12576 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12577 mac_offset = 0x10;
12578
12579 /* First try to get it from MAC address mailbox. */
12580 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12581 if ((hi >> 16) == 0x484b) {
12582 dev->dev_addr[0] = (hi >> 8) & 0xff;
12583 dev->dev_addr[1] = (hi >> 0) & 0xff;
12584
12585 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12586 dev->dev_addr[2] = (lo >> 24) & 0xff;
12587 dev->dev_addr[3] = (lo >> 16) & 0xff;
12588 dev->dev_addr[4] = (lo >> 8) & 0xff;
12589 dev->dev_addr[5] = (lo >> 0) & 0xff;
12590
12591 /* Some old bootcode may report a 0 MAC address in SRAM */
12592 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12593 }
12594 if (!addr_ok) {
12595 /* Next, try NVRAM. */
12596 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
12597 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
12598 dev->dev_addr[0] = ((hi >> 16) & 0xff);
12599 dev->dev_addr[1] = ((hi >> 24) & 0xff);
12600 dev->dev_addr[2] = ((lo >> 0) & 0xff);
12601 dev->dev_addr[3] = ((lo >> 8) & 0xff);
12602 dev->dev_addr[4] = ((lo >> 16) & 0xff);
12603 dev->dev_addr[5] = ((lo >> 24) & 0xff);
12604 }
12605 /* Finally just fetch it out of the MAC control regs. */
12606 else {
12607 hi = tr32(MAC_ADDR_0_HIGH);
12608 lo = tr32(MAC_ADDR_0_LOW);
12609
12610 dev->dev_addr[5] = lo & 0xff;
12611 dev->dev_addr[4] = (lo >> 8) & 0xff;
12612 dev->dev_addr[3] = (lo >> 16) & 0xff;
12613 dev->dev_addr[2] = (lo >> 24) & 0xff;
12614 dev->dev_addr[1] = hi & 0xff;
12615 dev->dev_addr[0] = (hi >> 8) & 0xff;
12616 }
12617 }
12618
12619 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
12620 #ifdef CONFIG_SPARC
12621 if (!tg3_get_default_macaddr_sparc(tp))
12622 return 0;
12623 #endif
12624 return -EINVAL;
12625 }
12626 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
12627 return 0;
12628 }
12629
12630 #define BOUNDARY_SINGLE_CACHELINE 1
12631 #define BOUNDARY_MULTI_CACHELINE 2
12632
12633 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12634 {
12635 int cacheline_size;
12636 u8 byte;
12637 int goal;
12638
12639 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12640 if (byte == 0)
12641 cacheline_size = 1024;
12642 else
12643 cacheline_size = (int) byte * 4;
12644
12645 /* On 5703 and later chips, the boundary bits have no
12646 * effect.
12647 */
12648 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12649 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12650 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12651 goto out;
12652
12653 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12654 goal = BOUNDARY_MULTI_CACHELINE;
12655 #else
12656 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12657 goal = BOUNDARY_SINGLE_CACHELINE;
12658 #else
12659 goal = 0;
12660 #endif
12661 #endif
12662
12663 if (!goal)
12664 goto out;
12665
12666 /* PCI controllers on most RISC systems tend to disconnect
12667 * when a device tries to burst across a cache-line boundary.
12668 * Therefore, letting tg3 do so just wastes PCI bandwidth.
12669 *
12670 * Unfortunately, for PCI-E there are only limited
12671 * write-side controls for this, and thus for reads
12672 * we will still get the disconnects. We'll also waste
12673 * these PCI cycles for both read and write for chips
12674 * other than 5700 and 5701 which do not implement the
12675 * boundary bits.
12676 */
12677 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12678 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12679 switch (cacheline_size) {
12680 case 16:
12681 case 32:
12682 case 64:
12683 case 128:
12684 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12685 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12686 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12687 } else {
12688 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12689 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12690 }
12691 break;
12692
12693 case 256:
12694 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12695 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12696 break;
12697
12698 default:
12699 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12700 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12701 break;
12702 }
12703 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12704 switch (cacheline_size) {
12705 case 16:
12706 case 32:
12707 case 64:
12708 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12709 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12710 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12711 break;
12712 }
12713 /* fallthrough */
12714 case 128:
12715 default:
12716 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12717 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12718 break;
12719 }
12720 } else {
12721 switch (cacheline_size) {
12722 case 16:
12723 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12724 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12725 DMA_RWCTRL_WRITE_BNDRY_16);
12726 break;
12727 }
12728 /* fallthrough */
12729 case 32:
12730 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12731 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12732 DMA_RWCTRL_WRITE_BNDRY_32);
12733 break;
12734 }
12735 /* fallthrough */
12736 case 64:
12737 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12738 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12739 DMA_RWCTRL_WRITE_BNDRY_64);
12740 break;
12741 }
12742 /* fallthrough */
12743 case 128:
12744 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12745 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12746 DMA_RWCTRL_WRITE_BNDRY_128);
12747 break;
12748 }
12749 /* fallthrough */
12750 case 256:
12751 val |= (DMA_RWCTRL_READ_BNDRY_256 |
12752 DMA_RWCTRL_WRITE_BNDRY_256);
12753 break;
12754 case 512:
12755 val |= (DMA_RWCTRL_READ_BNDRY_512 |
12756 DMA_RWCTRL_WRITE_BNDRY_512);
12757 break;
12758 case 1024:
12759 default:
12760 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12761 DMA_RWCTRL_WRITE_BNDRY_1024);
12762 break;
12763 }
12764 }
12765
12766 out:
12767 return val;
12768 }
12769
12770 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12771 {
12772 struct tg3_internal_buffer_desc test_desc;
12773 u32 sram_dma_descs;
12774 int i, ret;
12775
12776 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12777
12778 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12779 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12780 tw32(RDMAC_STATUS, 0);
12781 tw32(WDMAC_STATUS, 0);
12782
12783 tw32(BUFMGR_MODE, 0);
12784 tw32(FTQ_RESET, 0);
12785
12786 test_desc.addr_hi = ((u64) buf_dma) >> 32;
12787 test_desc.addr_lo = buf_dma & 0xffffffff;
12788 test_desc.nic_mbuf = 0x00002100;
12789 test_desc.len = size;
12790
12791 /*
12792 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12793 * the *second* time the tg3 driver was getting loaded after an
12794 * initial scan.
12795 *
12796 * Broadcom tells me:
12797 * ...the DMA engine is connected to the GRC block and a DMA
12798 * reset may affect the GRC block in some unpredictable way...
12799 * The behavior of resets to individual blocks has not been tested.
12800 *
12801 * Broadcom noted the GRC reset will also reset all sub-components.
12802 */
12803 if (to_device) {
12804 test_desc.cqid_sqid = (13 << 8) | 2;
12805
12806 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12807 udelay(40);
12808 } else {
12809 test_desc.cqid_sqid = (16 << 8) | 7;
12810
12811 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12812 udelay(40);
12813 }
12814 test_desc.flags = 0x00000005;
12815
12816 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12817 u32 val;
12818
12819 val = *(((u32 *)&test_desc) + i);
12820 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12821 sram_dma_descs + (i * sizeof(u32)));
12822 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12823 }
12824 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12825
12826 if (to_device) {
12827 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12828 } else {
12829 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12830 }
12831
12832 ret = -ENODEV;
12833 for (i = 0; i < 40; i++) {
12834 u32 val;
12835
12836 if (to_device)
12837 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12838 else
12839 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12840 if ((val & 0xffff) == sram_dma_descs) {
12841 ret = 0;
12842 break;
12843 }
12844
12845 udelay(100);
12846 }
12847
12848 return ret;
12849 }
12850
12851 #define TEST_BUFFER_SIZE 0x2000
12852
12853 static int __devinit tg3_test_dma(struct tg3 *tp)
12854 {
12855 dma_addr_t buf_dma;
12856 u32 *buf, saved_dma_rwctrl;
12857 int ret;
12858
12859 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12860 if (!buf) {
12861 ret = -ENOMEM;
12862 goto out_nofree;
12863 }
12864
12865 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12866 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12867
12868 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
12869
12870 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12871 /* DMA read watermark not used on PCIE */
12872 tp->dma_rwctrl |= 0x00180000;
12873 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
12874 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12875 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
12876 tp->dma_rwctrl |= 0x003f0000;
12877 else
12878 tp->dma_rwctrl |= 0x003f000f;
12879 } else {
12880 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12881 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12882 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
12883 u32 read_water = 0x7;
12884
12885 /* If the 5704 is behind the EPB bridge, we can
12886 * do the less restrictive ONE_DMA workaround for
12887 * better performance.
12888 */
12889 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12890 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12891 tp->dma_rwctrl |= 0x8000;
12892 else if (ccval == 0x6 || ccval == 0x7)
12893 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12894
12895 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12896 read_water = 4;
12897 /* Set bit 23 to enable PCIX hw bug fix */
12898 tp->dma_rwctrl |=
12899 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12900 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12901 (1 << 23);
12902 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12903 /* 5780 always in PCIX mode */
12904 tp->dma_rwctrl |= 0x00144000;
12905 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12906 /* 5714 always in PCIX mode */
12907 tp->dma_rwctrl |= 0x00148000;
12908 } else {
12909 tp->dma_rwctrl |= 0x001b000f;
12910 }
12911 }
12912
12913 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12914 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12915 tp->dma_rwctrl &= 0xfffffff0;
12916
12917 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12918 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12919 /* Remove this if it causes problems for some boards. */
12920 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12921
12922 /* On 5700/5701 chips, we need to set this bit.
12923 * Otherwise the chip will issue cacheline transactions
12924 * to streamable DMA memory with not all the byte
12925 * enables turned on. This is an error on several
12926 * RISC PCI controllers, in particular sparc64.
12927 *
12928 * On 5703/5704 chips, this bit has been reassigned
12929 * a different meaning. In particular, it is used
12930 * on those chips to enable a PCI-X workaround.
12931 */
12932 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12933 }
12934
12935 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12936
12937 #if 0
12938 /* Unneeded, already done by tg3_get_invariants. */
12939 tg3_switch_clocks(tp);
12940 #endif
12941
12942 ret = 0;
12943 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12944 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12945 goto out;
12946
12947 /* It is best to perform DMA test with maximum write burst size
12948 * to expose the 5700/5701 write DMA bug.
12949 */
12950 saved_dma_rwctrl = tp->dma_rwctrl;
12951 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12952 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12953
12954 while (1) {
12955 u32 *p = buf, i;
12956
12957 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
12958 p[i] = i;
12959
12960 /* Send the buffer to the chip. */
12961 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
12962 if (ret) {
12963 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
12964 break;
12965 }
12966
12967 #if 0
12968 /* validate data reached card RAM correctly. */
12969 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12970 u32 val;
12971 tg3_read_mem(tp, 0x2100 + (i*4), &val);
12972 if (le32_to_cpu(val) != p[i]) {
12973 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
12974 /* ret = -ENODEV here? */
12975 }
12976 p[i] = 0;
12977 }
12978 #endif
12979 /* Now read it back. */
12980 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
12981 if (ret) {
12982 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
12983
12984 break;
12985 }
12986
12987 /* Verify it. */
12988 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12989 if (p[i] == i)
12990 continue;
12991
12992 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12993 DMA_RWCTRL_WRITE_BNDRY_16) {
12994 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12995 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12996 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12997 break;
12998 } else {
12999 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13000 ret = -ENODEV;
13001 goto out;
13002 }
13003 }
13004
13005 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13006 /* Success. */
13007 ret = 0;
13008 break;
13009 }
13010 }
13011 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13012 DMA_RWCTRL_WRITE_BNDRY_16) {
13013 static struct pci_device_id dma_wait_state_chipsets[] = {
13014 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13015 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13016 { },
13017 };
13018
13019 /* DMA test passed without adjusting DMA boundary,
13020 * now look for chipsets that are known to expose the
13021 * DMA bug without failing the test.
13022 */
13023 if (pci_dev_present(dma_wait_state_chipsets)) {
13024 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13025 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13026 }
13027 else
13028 /* Safe to use the calculated DMA boundary. */
13029 tp->dma_rwctrl = saved_dma_rwctrl;
13030
13031 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13032 }
13033
13034 out:
13035 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13036 out_nofree:
13037 return ret;
13038 }
13039
13040 static void __devinit tg3_init_link_config(struct tg3 *tp)
13041 {
13042 tp->link_config.advertising =
13043 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13044 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13045 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13046 ADVERTISED_Autoneg | ADVERTISED_MII);
13047 tp->link_config.speed = SPEED_INVALID;
13048 tp->link_config.duplex = DUPLEX_INVALID;
13049 tp->link_config.autoneg = AUTONEG_ENABLE;
13050 tp->link_config.active_speed = SPEED_INVALID;
13051 tp->link_config.active_duplex = DUPLEX_INVALID;
13052 tp->link_config.phy_is_low_power = 0;
13053 tp->link_config.orig_speed = SPEED_INVALID;
13054 tp->link_config.orig_duplex = DUPLEX_INVALID;
13055 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13056 }
13057
13058 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13059 {
13060 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13061 tp->bufmgr_config.mbuf_read_dma_low_water =
13062 DEFAULT_MB_RDMA_LOW_WATER_5705;
13063 tp->bufmgr_config.mbuf_mac_rx_low_water =
13064 DEFAULT_MB_MACRX_LOW_WATER_5705;
13065 tp->bufmgr_config.mbuf_high_water =
13066 DEFAULT_MB_HIGH_WATER_5705;
13067 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13068 tp->bufmgr_config.mbuf_mac_rx_low_water =
13069 DEFAULT_MB_MACRX_LOW_WATER_5906;
13070 tp->bufmgr_config.mbuf_high_water =
13071 DEFAULT_MB_HIGH_WATER_5906;
13072 }
13073
13074 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13075 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13076 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13077 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13078 tp->bufmgr_config.mbuf_high_water_jumbo =
13079 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13080 } else {
13081 tp->bufmgr_config.mbuf_read_dma_low_water =
13082 DEFAULT_MB_RDMA_LOW_WATER;
13083 tp->bufmgr_config.mbuf_mac_rx_low_water =
13084 DEFAULT_MB_MACRX_LOW_WATER;
13085 tp->bufmgr_config.mbuf_high_water =
13086 DEFAULT_MB_HIGH_WATER;
13087
13088 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13089 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13090 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13091 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13092 tp->bufmgr_config.mbuf_high_water_jumbo =
13093 DEFAULT_MB_HIGH_WATER_JUMBO;
13094 }
13095
13096 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13097 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13098 }
13099
13100 static char * __devinit tg3_phy_string(struct tg3 *tp)
13101 {
13102 switch (tp->phy_id & PHY_ID_MASK) {
13103 case PHY_ID_BCM5400: return "5400";
13104 case PHY_ID_BCM5401: return "5401";
13105 case PHY_ID_BCM5411: return "5411";
13106 case PHY_ID_BCM5701: return "5701";
13107 case PHY_ID_BCM5703: return "5703";
13108 case PHY_ID_BCM5704: return "5704";
13109 case PHY_ID_BCM5705: return "5705";
13110 case PHY_ID_BCM5750: return "5750";
13111 case PHY_ID_BCM5752: return "5752";
13112 case PHY_ID_BCM5714: return "5714";
13113 case PHY_ID_BCM5780: return "5780";
13114 case PHY_ID_BCM5755: return "5755";
13115 case PHY_ID_BCM5787: return "5787";
13116 case PHY_ID_BCM5784: return "5784";
13117 case PHY_ID_BCM5756: return "5722/5756";
13118 case PHY_ID_BCM5906: return "5906";
13119 case PHY_ID_BCM5761: return "5761";
13120 case PHY_ID_BCM8002: return "8002/serdes";
13121 case 0: return "serdes";
13122 default: return "unknown";
13123 }
13124 }
13125
13126 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13127 {
13128 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13129 strcpy(str, "PCI Express");
13130 return str;
13131 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13132 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13133
13134 strcpy(str, "PCIX:");
13135
13136 if ((clock_ctrl == 7) ||
13137 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13138 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13139 strcat(str, "133MHz");
13140 else if (clock_ctrl == 0)
13141 strcat(str, "33MHz");
13142 else if (clock_ctrl == 2)
13143 strcat(str, "50MHz");
13144 else if (clock_ctrl == 4)
13145 strcat(str, "66MHz");
13146 else if (clock_ctrl == 6)
13147 strcat(str, "100MHz");
13148 } else {
13149 strcpy(str, "PCI:");
13150 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13151 strcat(str, "66MHz");
13152 else
13153 strcat(str, "33MHz");
13154 }
13155 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13156 strcat(str, ":32-bit");
13157 else
13158 strcat(str, ":64-bit");
13159 return str;
13160 }
13161
13162 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13163 {
13164 struct pci_dev *peer;
13165 unsigned int func, devnr = tp->pdev->devfn & ~7;
13166
13167 for (func = 0; func < 8; func++) {
13168 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13169 if (peer && peer != tp->pdev)
13170 break;
13171 pci_dev_put(peer);
13172 }
13173 /* 5704 can be configured in single-port mode, set peer to
13174 * tp->pdev in that case.
13175 */
13176 if (!peer) {
13177 peer = tp->pdev;
13178 return peer;
13179 }
13180
13181 /*
13182 * We don't need to keep the refcount elevated; there's no way
13183 * to remove one half of this device without removing the other
13184 */
13185 pci_dev_put(peer);
13186
13187 return peer;
13188 }
13189
13190 static void __devinit tg3_init_coal(struct tg3 *tp)
13191 {
13192 struct ethtool_coalesce *ec = &tp->coal;
13193
13194 memset(ec, 0, sizeof(*ec));
13195 ec->cmd = ETHTOOL_GCOALESCE;
13196 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13197 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13198 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13199 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13200 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13201 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13202 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13203 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13204 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13205
13206 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13207 HOSTCC_MODE_CLRTICK_TXBD)) {
13208 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13209 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13210 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13211 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13212 }
13213
13214 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13215 ec->rx_coalesce_usecs_irq = 0;
13216 ec->tx_coalesce_usecs_irq = 0;
13217 ec->stats_block_coalesce_usecs = 0;
13218 }
13219 }
13220
13221 static int __devinit tg3_init_one(struct pci_dev *pdev,
13222 const struct pci_device_id *ent)
13223 {
13224 static int tg3_version_printed = 0;
13225 resource_size_t tg3reg_base;
13226 unsigned long tg3reg_len;
13227 struct net_device *dev;
13228 struct tg3 *tp;
13229 int err, pm_cap;
13230 char str[40];
13231 u64 dma_mask, persist_dma_mask;
13232 DECLARE_MAC_BUF(mac);
13233
13234 if (tg3_version_printed++ == 0)
13235 printk(KERN_INFO "%s", version);
13236
13237 err = pci_enable_device(pdev);
13238 if (err) {
13239 printk(KERN_ERR PFX "Cannot enable PCI device, "
13240 "aborting.\n");
13241 return err;
13242 }
13243
13244 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
13245 printk(KERN_ERR PFX "Cannot find proper PCI device "
13246 "base address, aborting.\n");
13247 err = -ENODEV;
13248 goto err_out_disable_pdev;
13249 }
13250
13251 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13252 if (err) {
13253 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13254 "aborting.\n");
13255 goto err_out_disable_pdev;
13256 }
13257
13258 pci_set_master(pdev);
13259
13260 /* Find power-management capability. */
13261 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13262 if (pm_cap == 0) {
13263 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13264 "aborting.\n");
13265 err = -EIO;
13266 goto err_out_free_res;
13267 }
13268
13269 tg3reg_base = pci_resource_start(pdev, 0);
13270 tg3reg_len = pci_resource_len(pdev, 0);
13271
13272 dev = alloc_etherdev(sizeof(*tp));
13273 if (!dev) {
13274 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13275 err = -ENOMEM;
13276 goto err_out_free_res;
13277 }
13278
13279 SET_NETDEV_DEV(dev, &pdev->dev);
13280
13281 #if TG3_VLAN_TAG_USED
13282 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13283 dev->vlan_rx_register = tg3_vlan_rx_register;
13284 #endif
13285
13286 tp = netdev_priv(dev);
13287 tp->pdev = pdev;
13288 tp->dev = dev;
13289 tp->pm_cap = pm_cap;
13290 tp->mac_mode = TG3_DEF_MAC_MODE;
13291 tp->rx_mode = TG3_DEF_RX_MODE;
13292 tp->tx_mode = TG3_DEF_TX_MODE;
13293
13294 if (tg3_debug > 0)
13295 tp->msg_enable = tg3_debug;
13296 else
13297 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13298
13299 /* The word/byte swap controls here control register access byte
13300 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13301 * setting below.
13302 */
13303 tp->misc_host_ctrl =
13304 MISC_HOST_CTRL_MASK_PCI_INT |
13305 MISC_HOST_CTRL_WORD_SWAP |
13306 MISC_HOST_CTRL_INDIR_ACCESS |
13307 MISC_HOST_CTRL_PCISTATE_RW;
13308
13309 /* The NONFRM (non-frame) byte/word swap controls take effect
13310 * on descriptor entries, anything which isn't packet data.
13311 *
13312 * The StrongARM chips on the board (one for tx, one for rx)
13313 * are running in big-endian mode.
13314 */
13315 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13316 GRC_MODE_WSWAP_NONFRM_DATA);
13317 #ifdef __BIG_ENDIAN
13318 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13319 #endif
13320 spin_lock_init(&tp->lock);
13321 spin_lock_init(&tp->indirect_lock);
13322 INIT_WORK(&tp->reset_task, tg3_reset_task);
13323
13324 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
13325 if (!tp->regs) {
13326 printk(KERN_ERR PFX "Cannot map device registers, "
13327 "aborting.\n");
13328 err = -ENOMEM;
13329 goto err_out_free_dev;
13330 }
13331
13332 tg3_init_link_config(tp);
13333
13334 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13335 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13336 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13337
13338 dev->open = tg3_open;
13339 dev->stop = tg3_close;
13340 dev->get_stats = tg3_get_stats;
13341 dev->set_multicast_list = tg3_set_rx_mode;
13342 dev->set_mac_address = tg3_set_mac_addr;
13343 dev->do_ioctl = tg3_ioctl;
13344 dev->tx_timeout = tg3_tx_timeout;
13345 netif_napi_add(dev, &tp->napi, tg3_poll, 64);
13346 dev->ethtool_ops = &tg3_ethtool_ops;
13347 dev->watchdog_timeo = TG3_TX_TIMEOUT;
13348 dev->change_mtu = tg3_change_mtu;
13349 dev->irq = pdev->irq;
13350 #ifdef CONFIG_NET_POLL_CONTROLLER
13351 dev->poll_controller = tg3_poll_controller;
13352 #endif
13353
13354 err = tg3_get_invariants(tp);
13355 if (err) {
13356 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13357 "aborting.\n");
13358 goto err_out_iounmap;
13359 }
13360
13361 /* The EPB bridge inside 5714, 5715, and 5780 and any
13362 * device behind the EPB cannot support DMA addresses > 40-bit.
13363 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13364 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13365 * do DMA address check in tg3_start_xmit().
13366 */
13367 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
13368 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
13369 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
13370 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
13371 #ifdef CONFIG_HIGHMEM
13372 dma_mask = DMA_64BIT_MASK;
13373 #endif
13374 } else
13375 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
13376
13377 /* Configure DMA attributes. */
13378 if (dma_mask > DMA_32BIT_MASK) {
13379 err = pci_set_dma_mask(pdev, dma_mask);
13380 if (!err) {
13381 dev->features |= NETIF_F_HIGHDMA;
13382 err = pci_set_consistent_dma_mask(pdev,
13383 persist_dma_mask);
13384 if (err < 0) {
13385 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13386 "DMA for consistent allocations\n");
13387 goto err_out_iounmap;
13388 }
13389 }
13390 }
13391 if (err || dma_mask == DMA_32BIT_MASK) {
13392 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
13393 if (err) {
13394 printk(KERN_ERR PFX "No usable DMA configuration, "
13395 "aborting.\n");
13396 goto err_out_iounmap;
13397 }
13398 }
13399
13400 tg3_init_bufmgr_config(tp);
13401
13402 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13403 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13404 }
13405 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13406 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13407 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
13408 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13409 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13410 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13411 } else {
13412 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
13413 }
13414
13415 /* TSO is on by default on chips that support hardware TSO.
13416 * Firmware TSO on older chips gives lower performance, so it
13417 * is off by default, but can be enabled using ethtool.
13418 */
13419 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13420 dev->features |= NETIF_F_TSO;
13421 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
13422 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
13423 dev->features |= NETIF_F_TSO6;
13424 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13425 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13426 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
13427 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
13428 dev->features |= NETIF_F_TSO_ECN;
13429 }
13430
13431
13432 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13433 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13434 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13435 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13436 tp->rx_pending = 63;
13437 }
13438
13439 err = tg3_get_device_address(tp);
13440 if (err) {
13441 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13442 "aborting.\n");
13443 goto err_out_iounmap;
13444 }
13445
13446 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13447 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
13448 printk(KERN_ERR PFX "Cannot find proper PCI device "
13449 "base address for APE, aborting.\n");
13450 err = -ENODEV;
13451 goto err_out_iounmap;
13452 }
13453
13454 tg3reg_base = pci_resource_start(pdev, 2);
13455 tg3reg_len = pci_resource_len(pdev, 2);
13456
13457 tp->aperegs = ioremap_nocache(tg3reg_base, tg3reg_len);
13458 if (!tp->aperegs) {
13459 printk(KERN_ERR PFX "Cannot map APE registers, "
13460 "aborting.\n");
13461 err = -ENOMEM;
13462 goto err_out_iounmap;
13463 }
13464
13465 tg3_ape_lock_init(tp);
13466 }
13467
13468 /*
13469 * Reset chip in case UNDI or EFI driver did not shutdown
13470 * DMA self test will enable WDMAC and we'll see (spurious)
13471 * pending DMA on the PCI bus at that point.
13472 */
13473 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13474 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
13475 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
13476 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13477 }
13478
13479 err = tg3_test_dma(tp);
13480 if (err) {
13481 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
13482 goto err_out_apeunmap;
13483 }
13484
13485 /* Tigon3 can do ipv4 only... and some chips have buggy
13486 * checksumming.
13487 */
13488 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
13489 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13490 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13491 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13492 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13493 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13494 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
13495 dev->features |= NETIF_F_IPV6_CSUM;
13496
13497 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13498 } else
13499 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
13500
13501 /* flow control autonegotiation is default behavior */
13502 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
13503 tp->link_config.flowctrl = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
13504
13505 tg3_init_coal(tp);
13506
13507 pci_set_drvdata(pdev, dev);
13508
13509 err = register_netdev(dev);
13510 if (err) {
13511 printk(KERN_ERR PFX "Cannot register net device, "
13512 "aborting.\n");
13513 goto err_out_apeunmap;
13514 }
13515
13516 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] "
13517 "(%s) %s Ethernet %s\n",
13518 dev->name,
13519 tp->board_part_number,
13520 tp->pci_chip_rev_id,
13521 tg3_phy_string(tp),
13522 tg3_bus_string(tp, str),
13523 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13524 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13525 "10/100/1000Base-T")),
13526 print_mac(mac, dev->dev_addr));
13527
13528 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
13529 "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
13530 dev->name,
13531 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13532 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13533 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13534 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
13535 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
13536 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
13537 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13538 dev->name, tp->dma_rwctrl,
13539 (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
13540 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
13541
13542 return 0;
13543
13544 err_out_apeunmap:
13545 if (tp->aperegs) {
13546 iounmap(tp->aperegs);
13547 tp->aperegs = NULL;
13548 }
13549
13550 err_out_iounmap:
13551 if (tp->regs) {
13552 iounmap(tp->regs);
13553 tp->regs = NULL;
13554 }
13555
13556 err_out_free_dev:
13557 free_netdev(dev);
13558
13559 err_out_free_res:
13560 pci_release_regions(pdev);
13561
13562 err_out_disable_pdev:
13563 pci_disable_device(pdev);
13564 pci_set_drvdata(pdev, NULL);
13565 return err;
13566 }
13567
13568 static void __devexit tg3_remove_one(struct pci_dev *pdev)
13569 {
13570 struct net_device *dev = pci_get_drvdata(pdev);
13571
13572 if (dev) {
13573 struct tg3 *tp = netdev_priv(dev);
13574
13575 flush_scheduled_work();
13576
13577 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13578 tg3_phy_fini(tp);
13579 tg3_mdio_fini(tp);
13580 }
13581
13582 unregister_netdev(dev);
13583 if (tp->aperegs) {
13584 iounmap(tp->aperegs);
13585 tp->aperegs = NULL;
13586 }
13587 if (tp->regs) {
13588 iounmap(tp->regs);
13589 tp->regs = NULL;
13590 }
13591 free_netdev(dev);
13592 pci_release_regions(pdev);
13593 pci_disable_device(pdev);
13594 pci_set_drvdata(pdev, NULL);
13595 }
13596 }
13597
13598 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13599 {
13600 struct net_device *dev = pci_get_drvdata(pdev);
13601 struct tg3 *tp = netdev_priv(dev);
13602 pci_power_t target_state;
13603 int err;
13604
13605 /* PCI register 4 needs to be saved whether netif_running() or not.
13606 * MSI address and data need to be saved if using MSI and
13607 * netif_running().
13608 */
13609 pci_save_state(pdev);
13610
13611 if (!netif_running(dev))
13612 return 0;
13613
13614 flush_scheduled_work();
13615 tg3_phy_stop(tp);
13616 tg3_netif_stop(tp);
13617
13618 del_timer_sync(&tp->timer);
13619
13620 tg3_full_lock(tp, 1);
13621 tg3_disable_ints(tp);
13622 tg3_full_unlock(tp);
13623
13624 netif_device_detach(dev);
13625
13626 tg3_full_lock(tp, 0);
13627 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13628 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
13629 tg3_full_unlock(tp);
13630
13631 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13632
13633 err = tg3_set_power_state(tp, target_state);
13634 if (err) {
13635 int err2;
13636
13637 tg3_full_lock(tp, 0);
13638
13639 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13640 err2 = tg3_restart_hw(tp, 1);
13641 if (err2)
13642 goto out;
13643
13644 tp->timer.expires = jiffies + tp->timer_offset;
13645 add_timer(&tp->timer);
13646
13647 netif_device_attach(dev);
13648 tg3_netif_start(tp);
13649
13650 out:
13651 tg3_full_unlock(tp);
13652
13653 if (!err2)
13654 tg3_phy_start(tp);
13655 }
13656
13657 return err;
13658 }
13659
13660 static int tg3_resume(struct pci_dev *pdev)
13661 {
13662 struct net_device *dev = pci_get_drvdata(pdev);
13663 struct tg3 *tp = netdev_priv(dev);
13664 int err;
13665
13666 pci_restore_state(tp->pdev);
13667
13668 if (!netif_running(dev))
13669 return 0;
13670
13671 err = tg3_set_power_state(tp, PCI_D0);
13672 if (err)
13673 return err;
13674
13675 netif_device_attach(dev);
13676
13677 tg3_full_lock(tp, 0);
13678
13679 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13680 err = tg3_restart_hw(tp, 1);
13681 if (err)
13682 goto out;
13683
13684 tp->timer.expires = jiffies + tp->timer_offset;
13685 add_timer(&tp->timer);
13686
13687 tg3_netif_start(tp);
13688
13689 out:
13690 tg3_full_unlock(tp);
13691
13692 if (!err)
13693 tg3_phy_start(tp);
13694
13695 return err;
13696 }
13697
13698 static struct pci_driver tg3_driver = {
13699 .name = DRV_MODULE_NAME,
13700 .id_table = tg3_pci_tbl,
13701 .probe = tg3_init_one,
13702 .remove = __devexit_p(tg3_remove_one),
13703 .suspend = tg3_suspend,
13704 .resume = tg3_resume
13705 };
13706
13707 static int __init tg3_init(void)
13708 {
13709 return pci_register_driver(&tg3_driver);
13710 }
13711
13712 static void __exit tg3_cleanup(void)
13713 {
13714 pci_unregister_driver(&tg3_driver);
13715 }
13716
13717 module_init(tg3_init);
13718 module_exit(tg3_cleanup);
Support for the Chinese Samsung S3C2440 based development boards