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pciehp: Mask hotplug interrupt at controller release
[linux-2.6/mini2440.git] / drivers / scsi / gdth.c
blobc6d6e7c6559a6664008cbcf9fe75ae106577b476
1 /************************************************************************
2 * Linux driver for *
3 * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
4 * Intel Corporation: Storage RAID Controllers *
5 * *
6 * gdth.c *
7 * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
8 * Copyright (C) 2002-04 Intel Corporation *
9 * Copyright (C) 2003-06 Adaptec Inc. *
10 * <achim_leubner@adaptec.com> *
11 * *
12 * Additions/Fixes: *
13 * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
14 * Johannes Dinner <johannes_dinner@adaptec.com> *
15 * *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published *
18 * by the Free Software Foundation; either version 2 of the License, *
19 * or (at your option) any later version. *
20 * *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
25 * *
26 * You should have received a copy of the GNU General Public License *
27 * along with this kernel; if not, write to the Free Software *
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
29 * *
30 * Linux kernel 2.6.x supported *
31 * *
32 ************************************************************************/
33
34 /* All GDT Disk Array Controllers are fully supported by this driver.
35 * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
36 * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
37 * list of all controller types.
38 *
39 * If you have one or more GDT3000/3020 EISA controllers with
40 * controller BIOS disabled, you have to set the IRQ values with the
41 * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
42 * the IRQ values for the EISA controllers.
43 *
44 * After the optional list of IRQ values, other possible
45 * command line options are:
46 * disable:Y disable driver
47 * disable:N enable driver
48 * reserve_mode:0 reserve no drives for the raw service
49 * reserve_mode:1 reserve all not init., removable drives
50 * reserve_mode:2 reserve all not init. drives
51 * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
52 * h- controller no., b- channel no.,
53 * t- target ID, l- LUN
54 * reverse_scan:Y reverse scan order for PCI controllers
55 * reverse_scan:N scan PCI controllers like BIOS
56 * max_ids:x x - target ID count per channel (1..MAXID)
57 * rescan:Y rescan all channels/IDs
58 * rescan:N use all devices found until now
59 * hdr_channel:x x - number of virtual bus for host drives
60 * shared_access:Y disable driver reserve/release protocol to
61 * access a shared resource from several nodes,
62 * appropriate controller firmware required
63 * shared_access:N enable driver reserve/release protocol
64 * probe_eisa_isa:Y scan for EISA/ISA controllers
65 * probe_eisa_isa:N do not scan for EISA/ISA controllers
66 * force_dma32:Y use only 32 bit DMA mode
67 * force_dma32:N use 64 bit DMA mode, if supported
68 *
69 * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
70 * max_ids:127,rescan:N,hdr_channel:0,
71 * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
72 * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
73 *
74 * When loading the gdth driver as a module, the same options are available.
75 * You can set the IRQs with "IRQ=...". However, the syntax to specify the
76 * options changes slightly. You must replace all ',' between options
77 * with ' ' and all ':' with '=' and you must use
78 * '1' in place of 'Y' and '0' in place of 'N'.
79 *
80 * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
81 * max_ids=127 rescan=0 hdr_channel=0 shared_access=0
82 * probe_eisa_isa=0 force_dma32=0"
83 * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
84 */
85
86 /* The meaning of the Scsi_Pointer members in this driver is as follows:
87 * ptr: Chaining
88 * this_residual: unused
89 * buffer: unused
90 * dma_handle: unused
91 * buffers_residual: unused
92 * Status: unused
93 * Message: unused
94 * have_data_in: unused
95 * sent_command: unused
96 * phase: unused
97 */
98
99
100 /* interrupt coalescing */
101 /* #define INT_COAL */
102
103 /* statistics */
104 #define GDTH_STATISTICS
105
106 #include <linux/module.h>
107
108 #include <linux/version.h>
109 #include <linux/kernel.h>
110 #include <linux/types.h>
111 #include <linux/pci.h>
112 #include <linux/string.h>
113 #include <linux/ctype.h>
114 #include <linux/ioport.h>
115 #include <linux/delay.h>
116 #include <linux/interrupt.h>
117 #include <linux/in.h>
118 #include <linux/proc_fs.h>
119 #include <linux/time.h>
120 #include <linux/timer.h>
121 #include <linux/dma-mapping.h>
122 #include <linux/list.h>
123
124 #ifdef GDTH_RTC
125 #include <linux/mc146818rtc.h>
126 #endif
127 #include <linux/reboot.h>
128
129 #include <asm/dma.h>
130 #include <asm/system.h>
131 #include <asm/io.h>
132 #include <asm/uaccess.h>
133 #include <linux/spinlock.h>
134 #include <linux/blkdev.h>
135 #include <linux/scatterlist.h>
136
137 #include "scsi.h"
138 #include <scsi/scsi_host.h>
139 #include "gdth.h"
140
141 static void gdth_delay(int milliseconds);
142 static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs);
143 static irqreturn_t gdth_interrupt(int irq, void *dev_id);
144 static irqreturn_t __gdth_interrupt(gdth_ha_str *ha,
145 int gdth_from_wait, int* pIndex);
146 static int gdth_sync_event(gdth_ha_str *ha, int service, unchar index,
147 Scsi_Cmnd *scp);
148 static int gdth_async_event(gdth_ha_str *ha);
149 static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
150
151 static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar priority);
152 static void gdth_next(gdth_ha_str *ha);
153 static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar b);
154 static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
155 static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
156 ushort idx, gdth_evt_data *evt);
157 static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
158 static void gdth_readapp_event(gdth_ha_str *ha, unchar application,
159 gdth_evt_str *estr);
160 static void gdth_clear_events(void);
161
162 static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
163 char *buffer, ushort count);
164 static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
165 static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, ushort hdrive);
166
167 static void gdth_enable_int(gdth_ha_str *ha);
168 static int gdth_test_busy(gdth_ha_str *ha);
169 static int gdth_get_cmd_index(gdth_ha_str *ha);
170 static void gdth_release_event(gdth_ha_str *ha);
171 static int gdth_wait(gdth_ha_str *ha, int index,ulong32 time);
172 static int gdth_internal_cmd(gdth_ha_str *ha, unchar service, ushort opcode,
173 ulong32 p1, ulong64 p2,ulong64 p3);
174 static int gdth_search_drives(gdth_ha_str *ha);
175 static int gdth_analyse_hdrive(gdth_ha_str *ha, ushort hdrive);
176
177 static const char *gdth_ctr_name(gdth_ha_str *ha);
178
179 static int gdth_open(struct inode *inode, struct file *filep);
180 static int gdth_close(struct inode *inode, struct file *filep);
181 static int gdth_ioctl(struct inode *inode, struct file *filep,
182 unsigned int cmd, unsigned long arg);
183
184 static void gdth_flush(gdth_ha_str *ha);
185 static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *));
186 static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
187 struct gdth_cmndinfo *cmndinfo);
188 static void gdth_scsi_done(struct scsi_cmnd *scp);
189
190 #ifdef DEBUG_GDTH
191 static unchar DebugState = DEBUG_GDTH;
192
193 #ifdef __SERIAL__
194 #define MAX_SERBUF 160
195 static void ser_init(void);
196 static void ser_puts(char *str);
197 static void ser_putc(char c);
198 static int ser_printk(const char *fmt, ...);
199 static char strbuf[MAX_SERBUF+1];
200 #ifdef __COM2__
201 #define COM_BASE 0x2f8
202 #else
203 #define COM_BASE 0x3f8
204 #endif
205 static void ser_init()
206 {
207 unsigned port=COM_BASE;
208
209 outb(0x80,port+3);
210 outb(0,port+1);
211 /* 19200 Baud, if 9600: outb(12,port) */
212 outb(6, port);
213 outb(3,port+3);
214 outb(0,port+1);
215 /*
216 ser_putc('I');
217 ser_putc(' ');
218 */
219 }
220
221 static void ser_puts(char *str)
222 {
223 char *ptr;
224
225 ser_init();
226 for (ptr=str;*ptr;++ptr)
227 ser_putc(*ptr);
228 }
229
230 static void ser_putc(char c)
231 {
232 unsigned port=COM_BASE;
233
234 while ((inb(port+5) & 0x20)==0);
235 outb(c,port);
236 if (c==0x0a)
237 {
238 while ((inb(port+5) & 0x20)==0);
239 outb(0x0d,port);
240 }
241 }
242
243 static int ser_printk(const char *fmt, ...)
244 {
245 va_list args;
246 int i;
247
248 va_start(args,fmt);
249 i = vsprintf(strbuf,fmt,args);
250 ser_puts(strbuf);
251 va_end(args);
252 return i;
253 }
254
255 #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
256 #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
257 #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
258
259 #else /* !__SERIAL__ */
260 #define TRACE(a) {if (DebugState==1) {printk a;}}
261 #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
262 #define TRACE3(a) {if (DebugState!=0) {printk a;}}
263 #endif
264
265 #else /* !DEBUG */
266 #define TRACE(a)
267 #define TRACE2(a)
268 #define TRACE3(a)
269 #endif
270
271 #ifdef GDTH_STATISTICS
272 static ulong32 max_rq=0, max_index=0, max_sg=0;
273 #ifdef INT_COAL
274 static ulong32 max_int_coal=0;
275 #endif
276 static ulong32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
277 static struct timer_list gdth_timer;
278 #endif
279
280 #define PTR2USHORT(a) (ushort)(ulong)(a)
281 #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
282 #define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
283
284 #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
285
286 #ifdef CONFIG_ISA
287 static unchar gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
288 #endif
289 #if defined(CONFIG_EISA) || defined(CONFIG_ISA)
290 static unchar gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
291 #endif
292 static unchar gdth_polling; /* polling if TRUE */
293 static int gdth_ctr_count = 0; /* controller count */
294 static LIST_HEAD(gdth_instances); /* controller list */
295 static unchar gdth_write_through = FALSE; /* write through */
296 static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
297 static int elastidx;
298 static int eoldidx;
299 static int major;
300
301 #define DIN 1 /* IN data direction */
302 #define DOU 2 /* OUT data direction */
303 #define DNO DIN /* no data transfer */
304 #define DUN DIN /* unknown data direction */
305 static unchar gdth_direction_tab[0x100] = {
306 DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
307 DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
308 DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
309 DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
310 DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
311 DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
312 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
313 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
314 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
315 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
316 DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
317 DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
318 DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
319 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
320 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
321 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
322 };
323
324 /* LILO and modprobe/insmod parameters */
325 /* IRQ list for GDT3000/3020 EISA controllers */
326 static int irq[MAXHA] __initdata =
327 {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
328 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
329 /* disable driver flag */
330 static int disable __initdata = 0;
331 /* reserve flag */
332 static int reserve_mode = 1;
333 /* reserve list */
334 static int reserve_list[MAX_RES_ARGS] =
335 {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
336 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
337 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
338 /* scan order for PCI controllers */
339 static int reverse_scan = 0;
340 /* virtual channel for the host drives */
341 static int hdr_channel = 0;
342 /* max. IDs per channel */
343 static int max_ids = MAXID;
344 /* rescan all IDs */
345 static int rescan = 0;
346 /* shared access */
347 static int shared_access = 1;
348 /* enable support for EISA and ISA controllers */
349 static int probe_eisa_isa = 0;
350 /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
351 static int force_dma32 = 0;
352
353 /* parameters for modprobe/insmod */
354 module_param_array(irq, int, NULL, 0);
355 module_param(disable, int, 0);
356 module_param(reserve_mode, int, 0);
357 module_param_array(reserve_list, int, NULL, 0);
358 module_param(reverse_scan, int, 0);
359 module_param(hdr_channel, int, 0);
360 module_param(max_ids, int, 0);
361 module_param(rescan, int, 0);
362 module_param(shared_access, int, 0);
363 module_param(probe_eisa_isa, int, 0);
364 module_param(force_dma32, int, 0);
365 MODULE_AUTHOR("Achim Leubner");
366 MODULE_LICENSE("GPL");
367
368 /* ioctl interface */
369 static const struct file_operations gdth_fops = {
370 .ioctl = gdth_ioctl,
371 .open = gdth_open,
372 .release = gdth_close,
373 };
374
375 #include "gdth_proc.h"
376 #include "gdth_proc.c"
377
378 static gdth_ha_str *gdth_find_ha(int hanum)
379 {
380 gdth_ha_str *ha;
381
382 list_for_each_entry(ha, &gdth_instances, list)
383 if (hanum == ha->hanum)
384 return ha;
385
386 return NULL;
387 }
388
389 static struct gdth_cmndinfo *gdth_get_cmndinfo(gdth_ha_str *ha)
390 {
391 struct gdth_cmndinfo *priv = NULL;
392 ulong flags;
393 int i;
394
395 spin_lock_irqsave(&ha->smp_lock, flags);
396
397 for (i=0; i<GDTH_MAXCMDS; ++i) {
398 if (ha->cmndinfo[i].index == 0) {
399 priv = &ha->cmndinfo[i];
400 memset(priv, 0, sizeof(*priv));
401 priv->index = i+1;
402 break;
403 }
404 }
405
406 spin_unlock_irqrestore(&ha->smp_lock, flags);
407
408 return priv;
409 }
410
411 static void gdth_put_cmndinfo(struct gdth_cmndinfo *priv)
412 {
413 BUG_ON(!priv);
414 priv->index = 0;
415 }
416
417 static void gdth_delay(int milliseconds)
418 {
419 if (milliseconds == 0) {
420 udelay(1);
421 } else {
422 mdelay(milliseconds);
423 }
424 }
425
426 static void gdth_scsi_done(struct scsi_cmnd *scp)
427 {
428 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
429 int internal_command = cmndinfo->internal_command;
430
431 TRACE2(("gdth_scsi_done()\n"));
432
433 gdth_put_cmndinfo(cmndinfo);
434 scp->host_scribble = NULL;
435
436 if (internal_command)
437 complete((struct completion *)scp->request);
438 else
439 scp->scsi_done(scp);
440 }
441
442 int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
443 int timeout, u32 *info)
444 {
445 gdth_ha_str *ha = shost_priv(sdev->host);
446 Scsi_Cmnd *scp;
447 struct gdth_cmndinfo cmndinfo;
448 DECLARE_COMPLETION_ONSTACK(wait);
449 int rval;
450
451 scp = kzalloc(sizeof(*scp), GFP_KERNEL);
452 if (!scp)
453 return -ENOMEM;
454
455 scp->sense_buffer = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
456 if (!scp->sense_buffer) {
457 kfree(scp);
458 return -ENOMEM;
459 }
460
461 scp->device = sdev;
462 memset(&cmndinfo, 0, sizeof(cmndinfo));
463
464 /* use request field to save the ptr. to completion struct. */
465 scp->request = (struct request *)&wait;
466 scp->timeout_per_command = timeout*HZ;
467 scp->cmd_len = 12;
468 memcpy(scp->cmnd, cmnd, 12);
469 cmndinfo.priority = IOCTL_PRI;
470 cmndinfo.internal_cmd_str = gdtcmd;
471 cmndinfo.internal_command = 1;
472
473 TRACE(("__gdth_execute() cmd 0x%x\n", scp->cmnd[0]));
474 __gdth_queuecommand(ha, scp, &cmndinfo);
475
476 wait_for_completion(&wait);
477
478 rval = cmndinfo.status;
479 if (info)
480 *info = cmndinfo.info;
481 kfree(scp->sense_buffer);
482 kfree(scp);
483 return rval;
484 }
485
486 int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
487 int timeout, u32 *info)
488 {
489 struct scsi_device *sdev = scsi_get_host_dev(shost);
490 int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
491
492 scsi_free_host_dev(sdev);
493 return rval;
494 }
495
496 static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs)
497 {
498 *cyls = size /HEADS/SECS;
499 if (*cyls <= MAXCYLS) {
500 *heads = HEADS;
501 *secs = SECS;
502 } else { /* too high for 64*32 */
503 *cyls = size /MEDHEADS/MEDSECS;
504 if (*cyls <= MAXCYLS) {
505 *heads = MEDHEADS;
506 *secs = MEDSECS;
507 } else { /* too high for 127*63 */
508 *cyls = size /BIGHEADS/BIGSECS;
509 *heads = BIGHEADS;
510 *secs = BIGSECS;
511 }
512 }
513 }
514
515 /* controller search and initialization functions */
516 #ifdef CONFIG_EISA
517 static int __init gdth_search_eisa(ushort eisa_adr)
518 {
519 ulong32 id;
520
521 TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
522 id = inl(eisa_adr+ID0REG);
523 if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
524 if ((inb(eisa_adr+EISAREG) & 8) == 0)
525 return 0; /* not EISA configured */
526 return 1;
527 }
528 if (id == GDT3_ID) /* GDT3000 */
529 return 1;
530
531 return 0;
532 }
533 #endif /* CONFIG_EISA */
534
535 #ifdef CONFIG_ISA
536 static int __init gdth_search_isa(ulong32 bios_adr)
537 {
538 void __iomem *addr;
539 ulong32 id;
540
541 TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
542 if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(ulong32))) != NULL) {
543 id = readl(addr);
544 iounmap(addr);
545 if (id == GDT2_ID) /* GDT2000 */
546 return 1;
547 }
548 return 0;
549 }
550 #endif /* CONFIG_ISA */
551
552 #ifdef CONFIG_PCI
553 static bool gdth_pci_registered;
554
555 static bool gdth_search_vortex(ushort device)
556 {
557 if (device <= PCI_DEVICE_ID_VORTEX_GDT6555)
558 return true;
559 if (device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP &&
560 device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP)
561 return true;
562 if (device == PCI_DEVICE_ID_VORTEX_GDTNEWRX ||
563 device == PCI_DEVICE_ID_VORTEX_GDTNEWRX2)
564 return true;
565 return false;
566 }
567
568 static int gdth_pci_probe_one(gdth_pci_str *pcistr, gdth_ha_str **ha_out);
569 static int gdth_pci_init_one(struct pci_dev *pdev,
570 const struct pci_device_id *ent);
571 static void gdth_pci_remove_one(struct pci_dev *pdev);
572 static void gdth_remove_one(gdth_ha_str *ha);
573
574 /* Vortex only makes RAID controllers.
575 * We do not really want to specify all 550 ids here, so wildcard match.
576 */
577 static const struct pci_device_id gdthtable[] = {
578 { PCI_VDEVICE(VORTEX, PCI_ANY_ID) },
579 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SRC) },
580 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SRC_XSCALE) },
581 { } /* terminate list */
582 };
583 MODULE_DEVICE_TABLE(pci, gdthtable);
584
585 static struct pci_driver gdth_pci_driver = {
586 .name = "gdth",
587 .id_table = gdthtable,
588 .probe = gdth_pci_init_one,
589 .remove = gdth_pci_remove_one,
590 };
591
592 static void gdth_pci_remove_one(struct pci_dev *pdev)
593 {
594 gdth_ha_str *ha = pci_get_drvdata(pdev);
595
596 pci_set_drvdata(pdev, NULL);
597
598 list_del(&ha->list);
599 gdth_remove_one(ha);
600
601 pci_disable_device(pdev);
602 }
603
604 static int gdth_pci_init_one(struct pci_dev *pdev,
605 const struct pci_device_id *ent)
606 {
607 ushort vendor = pdev->vendor;
608 ushort device = pdev->device;
609 ulong base0, base1, base2;
610 int rc;
611 gdth_pci_str gdth_pcistr;
612 gdth_ha_str *ha = NULL;
613
614 TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
615 gdth_ctr_count, vendor, device));
616
617 memset(&gdth_pcistr, 0, sizeof(gdth_pcistr));
618
619 if (vendor == PCI_VENDOR_ID_VORTEX && !gdth_search_vortex(device))
620 return -ENODEV;
621
622 rc = pci_enable_device(pdev);
623 if (rc)
624 return rc;
625
626 if (gdth_ctr_count >= MAXHA)
627 return -EBUSY;
628
629 /* GDT PCI controller found, resources are already in pdev */
630 gdth_pcistr.pdev = pdev;
631 base0 = pci_resource_flags(pdev, 0);
632 base1 = pci_resource_flags(pdev, 1);
633 base2 = pci_resource_flags(pdev, 2);
634 if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
635 device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
636 if (!(base0 & IORESOURCE_MEM))
637 return -ENODEV;
638 gdth_pcistr.dpmem = pci_resource_start(pdev, 0);
639 } else { /* GDT6110, GDT6120, .. */
640 if (!(base0 & IORESOURCE_MEM) ||
641 !(base2 & IORESOURCE_MEM) ||
642 !(base1 & IORESOURCE_IO))
643 return -ENODEV;
644 gdth_pcistr.dpmem = pci_resource_start(pdev, 2);
645 gdth_pcistr.io = pci_resource_start(pdev, 1);
646 }
647 TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
648 gdth_pcistr.pdev->bus->number,
649 PCI_SLOT(gdth_pcistr.pdev->devfn),
650 gdth_pcistr.irq,
651 gdth_pcistr.dpmem));
652
653 rc = gdth_pci_probe_one(&gdth_pcistr, &ha);
654 if (rc)
655 return rc;
656
657 return 0;
658 }
659 #endif /* CONFIG_PCI */
660
661 #ifdef CONFIG_EISA
662 static int __init gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha)
663 {
664 ulong32 retries,id;
665 unchar prot_ver,eisacf,i,irq_found;
666
667 TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
668
669 /* disable board interrupts, deinitialize services */
670 outb(0xff,eisa_adr+EDOORREG);
671 outb(0x00,eisa_adr+EDENABREG);
672 outb(0x00,eisa_adr+EINTENABREG);
673
674 outb(0xff,eisa_adr+LDOORREG);
675 retries = INIT_RETRIES;
676 gdth_delay(20);
677 while (inb(eisa_adr+EDOORREG) != 0xff) {
678 if (--retries == 0) {
679 printk("GDT-EISA: Initialization error (DEINIT failed)\n");
680 return 0;
681 }
682 gdth_delay(1);
683 TRACE2(("wait for DEINIT: retries=%d\n",retries));
684 }
685 prot_ver = inb(eisa_adr+MAILBOXREG);
686 outb(0xff,eisa_adr+EDOORREG);
687 if (prot_ver != PROTOCOL_VERSION) {
688 printk("GDT-EISA: Illegal protocol version\n");
689 return 0;
690 }
691 ha->bmic = eisa_adr;
692 ha->brd_phys = (ulong32)eisa_adr >> 12;
693
694 outl(0,eisa_adr+MAILBOXREG);
695 outl(0,eisa_adr+MAILBOXREG+4);
696 outl(0,eisa_adr+MAILBOXREG+8);
697 outl(0,eisa_adr+MAILBOXREG+12);
698
699 /* detect IRQ */
700 if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
701 ha->oem_id = OEM_ID_ICP;
702 ha->type = GDT_EISA;
703 ha->stype = id;
704 outl(1,eisa_adr+MAILBOXREG+8);
705 outb(0xfe,eisa_adr+LDOORREG);
706 retries = INIT_RETRIES;
707 gdth_delay(20);
708 while (inb(eisa_adr+EDOORREG) != 0xfe) {
709 if (--retries == 0) {
710 printk("GDT-EISA: Initialization error (get IRQ failed)\n");
711 return 0;
712 }
713 gdth_delay(1);
714 }
715 ha->irq = inb(eisa_adr+MAILBOXREG);
716 outb(0xff,eisa_adr+EDOORREG);
717 TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
718 /* check the result */
719 if (ha->irq == 0) {
720 TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
721 for (i = 0, irq_found = FALSE;
722 i < MAXHA && irq[i] != 0xff; ++i) {
723 if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
724 irq_found = TRUE;
725 break;
726 }
727 }
728 if (irq_found) {
729 ha->irq = irq[i];
730 irq[i] = 0;
731 printk("GDT-EISA: Can not detect controller IRQ,\n");
732 printk("Use IRQ setting from command line (IRQ = %d)\n",
733 ha->irq);
734 } else {
735 printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
736 printk("the controller BIOS or use command line parameters\n");
737 return 0;
738 }
739 }
740 } else {
741 eisacf = inb(eisa_adr+EISAREG) & 7;
742 if (eisacf > 4) /* level triggered */
743 eisacf -= 4;
744 ha->irq = gdth_irq_tab[eisacf];
745 ha->oem_id = OEM_ID_ICP;
746 ha->type = GDT_EISA;
747 ha->stype = id;
748 }
749
750 ha->dma64_support = 0;
751 return 1;
752 }
753 #endif /* CONFIG_EISA */
754
755 #ifdef CONFIG_ISA
756 static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha)
757 {
758 register gdt2_dpram_str __iomem *dp2_ptr;
759 int i;
760 unchar irq_drq,prot_ver;
761 ulong32 retries;
762
763 TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
764
765 ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
766 if (ha->brd == NULL) {
767 printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
768 return 0;
769 }
770 dp2_ptr = ha->brd;
771 writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
772 /* reset interface area */
773 memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
774 if (readl(&dp2_ptr->u) != 0) {
775 printk("GDT-ISA: Initialization error (DPMEM write error)\n");
776 iounmap(ha->brd);
777 return 0;
778 }
779
780 /* disable board interrupts, read DRQ and IRQ */
781 writeb(0xff, &dp2_ptr->io.irqdel);
782 writeb(0x00, &dp2_ptr->io.irqen);
783 writeb(0x00, &dp2_ptr->u.ic.S_Status);
784 writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
785
786 irq_drq = readb(&dp2_ptr->io.rq);
787 for (i=0; i<3; ++i) {
788 if ((irq_drq & 1)==0)
789 break;
790 irq_drq >>= 1;
791 }
792 ha->drq = gdth_drq_tab[i];
793
794 irq_drq = readb(&dp2_ptr->io.rq) >> 3;
795 for (i=1; i<5; ++i) {
796 if ((irq_drq & 1)==0)
797 break;
798 irq_drq >>= 1;
799 }
800 ha->irq = gdth_irq_tab[i];
801
802 /* deinitialize services */
803 writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
804 writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
805 writeb(0, &dp2_ptr->io.event);
806 retries = INIT_RETRIES;
807 gdth_delay(20);
808 while (readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
809 if (--retries == 0) {
810 printk("GDT-ISA: Initialization error (DEINIT failed)\n");
811 iounmap(ha->brd);
812 return 0;
813 }
814 gdth_delay(1);
815 }
816 prot_ver = (unchar)readl(&dp2_ptr->u.ic.S_Info[0]);
817 writeb(0, &dp2_ptr->u.ic.Status);
818 writeb(0xff, &dp2_ptr->io.irqdel);
819 if (prot_ver != PROTOCOL_VERSION) {
820 printk("GDT-ISA: Illegal protocol version\n");
821 iounmap(ha->brd);
822 return 0;
823 }
824
825 ha->oem_id = OEM_ID_ICP;
826 ha->type = GDT_ISA;
827 ha->ic_all_size = sizeof(dp2_ptr->u);
828 ha->stype= GDT2_ID;
829 ha->brd_phys = bios_adr >> 4;
830
831 /* special request to controller BIOS */
832 writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
833 writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
834 writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
835 writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
836 writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
837 writeb(0, &dp2_ptr->io.event);
838 retries = INIT_RETRIES;
839 gdth_delay(20);
840 while (readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
841 if (--retries == 0) {
842 printk("GDT-ISA: Initialization error\n");
843 iounmap(ha->brd);
844 return 0;
845 }
846 gdth_delay(1);
847 }
848 writeb(0, &dp2_ptr->u.ic.Status);
849 writeb(0xff, &dp2_ptr->io.irqdel);
850
851 ha->dma64_support = 0;
852 return 1;
853 }
854 #endif /* CONFIG_ISA */
855
856 #ifdef CONFIG_PCI
857 static int gdth_init_pci(struct pci_dev *pdev, gdth_pci_str *pcistr,
858 gdth_ha_str *ha)
859 {
860 register gdt6_dpram_str __iomem *dp6_ptr;
861 register gdt6c_dpram_str __iomem *dp6c_ptr;
862 register gdt6m_dpram_str __iomem *dp6m_ptr;
863 ulong32 retries;
864 unchar prot_ver;
865 ushort command;
866 int i, found = FALSE;
867
868 TRACE(("gdth_init_pci()\n"));
869
870 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
871 ha->oem_id = OEM_ID_INTEL;
872 else
873 ha->oem_id = OEM_ID_ICP;
874 ha->brd_phys = (pdev->bus->number << 8) | (pdev->devfn & 0xf8);
875 ha->stype = (ulong32)pdev->device;
876 ha->irq = pdev->irq;
877 ha->pdev = pdev;
878
879 if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
880 TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
881 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
882 if (ha->brd == NULL) {
883 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
884 return 0;
885 }
886 /* check and reset interface area */
887 dp6_ptr = ha->brd;
888 writel(DPMEM_MAGIC, &dp6_ptr->u);
889 if (readl(&dp6_ptr->u) != DPMEM_MAGIC) {
890 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
891 pcistr->dpmem);
892 found = FALSE;
893 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
894 iounmap(ha->brd);
895 ha->brd = ioremap(i, sizeof(ushort));
896 if (ha->brd == NULL) {
897 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
898 return 0;
899 }
900 if (readw(ha->brd) != 0xffff) {
901 TRACE2(("init_pci_old() address 0x%x busy\n", i));
902 continue;
903 }
904 iounmap(ha->brd);
905 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, i);
906 ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
907 if (ha->brd == NULL) {
908 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
909 return 0;
910 }
911 dp6_ptr = ha->brd;
912 writel(DPMEM_MAGIC, &dp6_ptr->u);
913 if (readl(&dp6_ptr->u) == DPMEM_MAGIC) {
914 printk("GDT-PCI: Use free address at 0x%x\n", i);
915 found = TRUE;
916 break;
917 }
918 }
919 if (!found) {
920 printk("GDT-PCI: No free address found!\n");
921 iounmap(ha->brd);
922 return 0;
923 }
924 }
925 memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
926 if (readl(&dp6_ptr->u) != 0) {
927 printk("GDT-PCI: Initialization error (DPMEM write error)\n");
928 iounmap(ha->brd);
929 return 0;
930 }
931
932 /* disable board interrupts, deinit services */
933 writeb(0xff, &dp6_ptr->io.irqdel);
934 writeb(0x00, &dp6_ptr->io.irqen);
935 writeb(0x00, &dp6_ptr->u.ic.S_Status);
936 writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
937
938 writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
939 writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
940 writeb(0, &dp6_ptr->io.event);
941 retries = INIT_RETRIES;
942 gdth_delay(20);
943 while (readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
944 if (--retries == 0) {
945 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
946 iounmap(ha->brd);
947 return 0;
948 }
949 gdth_delay(1);
950 }
951 prot_ver = (unchar)readl(&dp6_ptr->u.ic.S_Info[0]);
952 writeb(0, &dp6_ptr->u.ic.S_Status);
953 writeb(0xff, &dp6_ptr->io.irqdel);
954 if (prot_ver != PROTOCOL_VERSION) {
955 printk("GDT-PCI: Illegal protocol version\n");
956 iounmap(ha->brd);
957 return 0;
958 }
959
960 ha->type = GDT_PCI;
961 ha->ic_all_size = sizeof(dp6_ptr->u);
962
963 /* special command to controller BIOS */
964 writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
965 writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
966 writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
967 writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
968 writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
969 writeb(0, &dp6_ptr->io.event);
970 retries = INIT_RETRIES;
971 gdth_delay(20);
972 while (readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
973 if (--retries == 0) {
974 printk("GDT-PCI: Initialization error\n");
975 iounmap(ha->brd);
976 return 0;
977 }
978 gdth_delay(1);
979 }
980 writeb(0, &dp6_ptr->u.ic.S_Status);
981 writeb(0xff, &dp6_ptr->io.irqdel);
982
983 ha->dma64_support = 0;
984
985 } else if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
986 ha->plx = (gdt6c_plx_regs *)pcistr->io;
987 TRACE2(("init_pci_new() dpmem %lx irq %d\n",
988 pcistr->dpmem,ha->irq));
989 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
990 if (ha->brd == NULL) {
991 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
992 iounmap(ha->brd);
993 return 0;
994 }
995 /* check and reset interface area */
996 dp6c_ptr = ha->brd;
997 writel(DPMEM_MAGIC, &dp6c_ptr->u);
998 if (readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
999 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
1000 pcistr->dpmem);
1001 found = FALSE;
1002 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
1003 iounmap(ha->brd);
1004 ha->brd = ioremap(i, sizeof(ushort));
1005 if (ha->brd == NULL) {
1006 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1007 return 0;
1008 }
1009 if (readw(ha->brd) != 0xffff) {
1010 TRACE2(("init_pci_plx() address 0x%x busy\n", i));
1011 continue;
1012 }
1013 iounmap(ha->brd);
1014 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_2, i);
1015 ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
1016 if (ha->brd == NULL) {
1017 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1018 return 0;
1019 }
1020 dp6c_ptr = ha->brd;
1021 writel(DPMEM_MAGIC, &dp6c_ptr->u);
1022 if (readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
1023 printk("GDT-PCI: Use free address at 0x%x\n", i);
1024 found = TRUE;
1025 break;
1026 }
1027 }
1028 if (!found) {
1029 printk("GDT-PCI: No free address found!\n");
1030 iounmap(ha->brd);
1031 return 0;
1032 }
1033 }
1034 memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
1035 if (readl(&dp6c_ptr->u) != 0) {
1036 printk("GDT-PCI: Initialization error (DPMEM write error)\n");
1037 iounmap(ha->brd);
1038 return 0;
1039 }
1040
1041 /* disable board interrupts, deinit services */
1042 outb(0x00,PTR2USHORT(&ha->plx->control1));
1043 outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
1044
1045 writeb(0x00, &dp6c_ptr->u.ic.S_Status);
1046 writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
1047
1048 writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
1049 writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
1050
1051 outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
1052
1053 retries = INIT_RETRIES;
1054 gdth_delay(20);
1055 while (readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
1056 if (--retries == 0) {
1057 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1058 iounmap(ha->brd);
1059 return 0;
1060 }
1061 gdth_delay(1);
1062 }
1063 prot_ver = (unchar)readl(&dp6c_ptr->u.ic.S_Info[0]);
1064 writeb(0, &dp6c_ptr->u.ic.Status);
1065 if (prot_ver != PROTOCOL_VERSION) {
1066 printk("GDT-PCI: Illegal protocol version\n");
1067 iounmap(ha->brd);
1068 return 0;
1069 }
1070
1071 ha->type = GDT_PCINEW;
1072 ha->ic_all_size = sizeof(dp6c_ptr->u);
1073
1074 /* special command to controller BIOS */
1075 writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
1076 writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
1077 writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
1078 writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
1079 writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
1080
1081 outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
1082
1083 retries = INIT_RETRIES;
1084 gdth_delay(20);
1085 while (readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
1086 if (--retries == 0) {
1087 printk("GDT-PCI: Initialization error\n");
1088 iounmap(ha->brd);
1089 return 0;
1090 }
1091 gdth_delay(1);
1092 }
1093 writeb(0, &dp6c_ptr->u.ic.S_Status);
1094
1095 ha->dma64_support = 0;
1096
1097 } else { /* MPR */
1098 TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
1099 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
1100 if (ha->brd == NULL) {
1101 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1102 return 0;
1103 }
1104
1105 /* manipulate config. space to enable DPMEM, start RP controller */
1106 pci_read_config_word(pdev, PCI_COMMAND, &command);
1107 command |= 6;
1108 pci_write_config_word(pdev, PCI_COMMAND, command);
1109 if (pci_resource_start(pdev, 8) == 1UL)
1110 pci_resource_start(pdev, 8) = 0UL;
1111 i = 0xFEFF0001UL;
1112 pci_write_config_dword(pdev, PCI_ROM_ADDRESS, i);
1113 gdth_delay(1);
1114 pci_write_config_dword(pdev, PCI_ROM_ADDRESS,
1115 pci_resource_start(pdev, 8));
1116
1117 dp6m_ptr = ha->brd;
1118
1119 /* Ensure that it is safe to access the non HW portions of DPMEM.
1120 * Aditional check needed for Xscale based RAID controllers */
1121 while( ((int)readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
1122 gdth_delay(1);
1123
1124 /* check and reset interface area */
1125 writel(DPMEM_MAGIC, &dp6m_ptr->u);
1126 if (readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
1127 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
1128 pcistr->dpmem);
1129 found = FALSE;
1130 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
1131 iounmap(ha->brd);
1132 ha->brd = ioremap(i, sizeof(ushort));
1133 if (ha->brd == NULL) {
1134 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1135 return 0;
1136 }
1137 if (readw(ha->brd) != 0xffff) {
1138 TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
1139 continue;
1140 }
1141 iounmap(ha->brd);
1142 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, i);
1143 ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
1144 if (ha->brd == NULL) {
1145 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1146 return 0;
1147 }
1148 dp6m_ptr = ha->brd;
1149 writel(DPMEM_MAGIC, &dp6m_ptr->u);
1150 if (readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
1151 printk("GDT-PCI: Use free address at 0x%x\n", i);
1152 found = TRUE;
1153 break;
1154 }
1155 }
1156 if (!found) {
1157 printk("GDT-PCI: No free address found!\n");
1158 iounmap(ha->brd);
1159 return 0;
1160 }
1161 }
1162 memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
1163
1164 /* disable board interrupts, deinit services */
1165 writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
1166 &dp6m_ptr->i960r.edoor_en_reg);
1167 writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
1168 writeb(0x00, &dp6m_ptr->u.ic.S_Status);
1169 writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
1170
1171 writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
1172 writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
1173 writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1174 retries = INIT_RETRIES;
1175 gdth_delay(20);
1176 while (readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
1177 if (--retries == 0) {
1178 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1179 iounmap(ha->brd);
1180 return 0;
1181 }
1182 gdth_delay(1);
1183 }
1184 prot_ver = (unchar)readl(&dp6m_ptr->u.ic.S_Info[0]);
1185 writeb(0, &dp6m_ptr->u.ic.S_Status);
1186 if (prot_ver != PROTOCOL_VERSION) {
1187 printk("GDT-PCI: Illegal protocol version\n");
1188 iounmap(ha->brd);
1189 return 0;
1190 }
1191
1192 ha->type = GDT_PCIMPR;
1193 ha->ic_all_size = sizeof(dp6m_ptr->u);
1194
1195 /* special command to controller BIOS */
1196 writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
1197 writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
1198 writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
1199 writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
1200 writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
1201 writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1202 retries = INIT_RETRIES;
1203 gdth_delay(20);
1204 while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
1205 if (--retries == 0) {
1206 printk("GDT-PCI: Initialization error\n");
1207 iounmap(ha->brd);
1208 return 0;
1209 }
1210 gdth_delay(1);
1211 }
1212 writeb(0, &dp6m_ptr->u.ic.S_Status);
1213
1214 /* read FW version to detect 64-bit DMA support */
1215 writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
1216 writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1217 retries = INIT_RETRIES;
1218 gdth_delay(20);
1219 while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
1220 if (--retries == 0) {
1221 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1222 iounmap(ha->brd);
1223 return 0;
1224 }
1225 gdth_delay(1);
1226 }
1227 prot_ver = (unchar)(readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
1228 writeb(0, &dp6m_ptr->u.ic.S_Status);
1229 if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
1230 ha->dma64_support = 0;
1231 else
1232 ha->dma64_support = 1;
1233 }
1234
1235 return 1;
1236 }
1237 #endif /* CONFIG_PCI */
1238
1239 /* controller protocol functions */
1240
1241 static void __init gdth_enable_int(gdth_ha_str *ha)
1242 {
1243 ulong flags;
1244 gdt2_dpram_str __iomem *dp2_ptr;
1245 gdt6_dpram_str __iomem *dp6_ptr;
1246 gdt6m_dpram_str __iomem *dp6m_ptr;
1247
1248 TRACE(("gdth_enable_int() hanum %d\n",ha->hanum));
1249 spin_lock_irqsave(&ha->smp_lock, flags);
1250
1251 if (ha->type == GDT_EISA) {
1252 outb(0xff, ha->bmic + EDOORREG);
1253 outb(0xff, ha->bmic + EDENABREG);
1254 outb(0x01, ha->bmic + EINTENABREG);
1255 } else if (ha->type == GDT_ISA) {
1256 dp2_ptr = ha->brd;
1257 writeb(1, &dp2_ptr->io.irqdel);
1258 writeb(0, &dp2_ptr->u.ic.Cmd_Index);
1259 writeb(1, &dp2_ptr->io.irqen);
1260 } else if (ha->type == GDT_PCI) {
1261 dp6_ptr = ha->brd;
1262 writeb(1, &dp6_ptr->io.irqdel);
1263 writeb(0, &dp6_ptr->u.ic.Cmd_Index);
1264 writeb(1, &dp6_ptr->io.irqen);
1265 } else if (ha->type == GDT_PCINEW) {
1266 outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
1267 outb(0x03, PTR2USHORT(&ha->plx->control1));
1268 } else if (ha->type == GDT_PCIMPR) {
1269 dp6m_ptr = ha->brd;
1270 writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
1271 writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
1272 &dp6m_ptr->i960r.edoor_en_reg);
1273 }
1274 spin_unlock_irqrestore(&ha->smp_lock, flags);
1275 }
1276
1277 /* return IStatus if interrupt was from this card else 0 */
1278 static unchar gdth_get_status(gdth_ha_str *ha)
1279 {
1280 unchar IStatus = 0;
1281
1282 TRACE(("gdth_get_status() irq %d ctr_count %d\n", ha->irq, gdth_ctr_count));
1283
1284 if (ha->type == GDT_EISA)
1285 IStatus = inb((ushort)ha->bmic + EDOORREG);
1286 else if (ha->type == GDT_ISA)
1287 IStatus =
1288 readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
1289 else if (ha->type == GDT_PCI)
1290 IStatus =
1291 readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
1292 else if (ha->type == GDT_PCINEW)
1293 IStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
1294 else if (ha->type == GDT_PCIMPR)
1295 IStatus =
1296 readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
1297
1298 return IStatus;
1299 }
1300
1301 static int gdth_test_busy(gdth_ha_str *ha)
1302 {
1303 register int gdtsema0 = 0;
1304
1305 TRACE(("gdth_test_busy() hanum %d\n", ha->hanum));
1306
1307 if (ha->type == GDT_EISA)
1308 gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
1309 else if (ha->type == GDT_ISA)
1310 gdtsema0 = (int)readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1311 else if (ha->type == GDT_PCI)
1312 gdtsema0 = (int)readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1313 else if (ha->type == GDT_PCINEW)
1314 gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
1315 else if (ha->type == GDT_PCIMPR)
1316 gdtsema0 =
1317 (int)readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
1318
1319 return (gdtsema0 & 1);
1320 }
1321
1322
1323 static int gdth_get_cmd_index(gdth_ha_str *ha)
1324 {
1325 int i;
1326
1327 TRACE(("gdth_get_cmd_index() hanum %d\n", ha->hanum));
1328
1329 for (i=0; i<GDTH_MAXCMDS; ++i) {
1330 if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
1331 ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
1332 ha->cmd_tab[i].service = ha->pccb->Service;
1333 ha->pccb->CommandIndex = (ulong32)i+2;
1334 return (i+2);
1335 }
1336 }
1337 return 0;
1338 }
1339
1340
1341 static void gdth_set_sema0(gdth_ha_str *ha)
1342 {
1343 TRACE(("gdth_set_sema0() hanum %d\n", ha->hanum));
1344
1345 if (ha->type == GDT_EISA) {
1346 outb(1, ha->bmic + SEMA0REG);
1347 } else if (ha->type == GDT_ISA) {
1348 writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1349 } else if (ha->type == GDT_PCI) {
1350 writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1351 } else if (ha->type == GDT_PCINEW) {
1352 outb(1, PTR2USHORT(&ha->plx->sema0_reg));
1353 } else if (ha->type == GDT_PCIMPR) {
1354 writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
1355 }
1356 }
1357
1358
1359 static void gdth_copy_command(gdth_ha_str *ha)
1360 {
1361 register gdth_cmd_str *cmd_ptr;
1362 register gdt6m_dpram_str __iomem *dp6m_ptr;
1363 register gdt6c_dpram_str __iomem *dp6c_ptr;
1364 gdt6_dpram_str __iomem *dp6_ptr;
1365 gdt2_dpram_str __iomem *dp2_ptr;
1366 ushort cp_count,dp_offset,cmd_no;
1367
1368 TRACE(("gdth_copy_command() hanum %d\n", ha->hanum));
1369
1370 cp_count = ha->cmd_len;
1371 dp_offset= ha->cmd_offs_dpmem;
1372 cmd_no = ha->cmd_cnt;
1373 cmd_ptr = ha->pccb;
1374
1375 ++ha->cmd_cnt;
1376 if (ha->type == GDT_EISA)
1377 return; /* no DPMEM, no copy */
1378
1379 /* set cpcount dword aligned */
1380 if (cp_count & 3)
1381 cp_count += (4 - (cp_count & 3));
1382
1383 ha->cmd_offs_dpmem += cp_count;
1384
1385 /* set offset and service, copy command to DPMEM */
1386 if (ha->type == GDT_ISA) {
1387 dp2_ptr = ha->brd;
1388 writew(dp_offset + DPMEM_COMMAND_OFFSET,
1389 &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
1390 writew((ushort)cmd_ptr->Service,
1391 &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
1392 memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1393 } else if (ha->type == GDT_PCI) {
1394 dp6_ptr = ha->brd;
1395 writew(dp_offset + DPMEM_COMMAND_OFFSET,
1396 &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
1397 writew((ushort)cmd_ptr->Service,
1398 &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
1399 memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1400 } else if (ha->type == GDT_PCINEW) {
1401 dp6c_ptr = ha->brd;
1402 writew(dp_offset + DPMEM_COMMAND_OFFSET,
1403 &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
1404 writew((ushort)cmd_ptr->Service,
1405 &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
1406 memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1407 } else if (ha->type == GDT_PCIMPR) {
1408 dp6m_ptr = ha->brd;
1409 writew(dp_offset + DPMEM_COMMAND_OFFSET,
1410 &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
1411 writew((ushort)cmd_ptr->Service,
1412 &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
1413 memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1414 }
1415 }
1416
1417
1418 static void gdth_release_event(gdth_ha_str *ha)
1419 {
1420 TRACE(("gdth_release_event() hanum %d\n", ha->hanum));
1421
1422 #ifdef GDTH_STATISTICS
1423 {
1424 ulong32 i,j;
1425 for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
1426 if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
1427 ++i;
1428 }
1429 if (max_index < i) {
1430 max_index = i;
1431 TRACE3(("GDT: max_index = %d\n",(ushort)i));
1432 }
1433 }
1434 #endif
1435
1436 if (ha->pccb->OpCode == GDT_INIT)
1437 ha->pccb->Service |= 0x80;
1438
1439 if (ha->type == GDT_EISA) {
1440 if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
1441 outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
1442 outb(ha->pccb->Service, ha->bmic + LDOORREG);
1443 } else if (ha->type == GDT_ISA) {
1444 writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
1445 } else if (ha->type == GDT_PCI) {
1446 writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
1447 } else if (ha->type == GDT_PCINEW) {
1448 outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
1449 } else if (ha->type == GDT_PCIMPR) {
1450 writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
1451 }
1452 }
1453
1454 static int gdth_wait(gdth_ha_str *ha, int index, ulong32 time)
1455 {
1456 int answer_found = FALSE;
1457 int wait_index = 0;
1458
1459 TRACE(("gdth_wait() hanum %d index %d time %d\n", ha->hanum, index, time));
1460
1461 if (index == 0)
1462 return 1; /* no wait required */
1463
1464 do {
1465 __gdth_interrupt(ha, true, &wait_index);
1466 if (wait_index == index) {
1467 answer_found = TRUE;
1468 break;
1469 }
1470 gdth_delay(1);
1471 } while (--time);
1472
1473 while (gdth_test_busy(ha))
1474 gdth_delay(0);
1475
1476 return (answer_found);
1477 }
1478
1479
1480 static int gdth_internal_cmd(gdth_ha_str *ha, unchar service, ushort opcode,
1481 ulong32 p1, ulong64 p2, ulong64 p3)
1482 {
1483 register gdth_cmd_str *cmd_ptr;
1484 int retries,index;
1485
1486 TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
1487
1488 cmd_ptr = ha->pccb;
1489 memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
1490
1491 /* make command */
1492 for (retries = INIT_RETRIES;;) {
1493 cmd_ptr->Service = service;
1494 cmd_ptr->RequestBuffer = INTERNAL_CMND;
1495 if (!(index=gdth_get_cmd_index(ha))) {
1496 TRACE(("GDT: No free command index found\n"));
1497 return 0;
1498 }
1499 gdth_set_sema0(ha);
1500 cmd_ptr->OpCode = opcode;
1501 cmd_ptr->BoardNode = LOCALBOARD;
1502 if (service == CACHESERVICE) {
1503 if (opcode == GDT_IOCTL) {
1504 cmd_ptr->u.ioctl.subfunc = p1;
1505 cmd_ptr->u.ioctl.channel = (ulong32)p2;
1506 cmd_ptr->u.ioctl.param_size = (ushort)p3;
1507 cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
1508 } else {
1509 if (ha->cache_feat & GDT_64BIT) {
1510 cmd_ptr->u.cache64.DeviceNo = (ushort)p1;
1511 cmd_ptr->u.cache64.BlockNo = p2;
1512 } else {
1513 cmd_ptr->u.cache.DeviceNo = (ushort)p1;
1514 cmd_ptr->u.cache.BlockNo = (ulong32)p2;
1515 }
1516 }
1517 } else if (service == SCSIRAWSERVICE) {
1518 if (ha->raw_feat & GDT_64BIT) {
1519 cmd_ptr->u.raw64.direction = p1;
1520 cmd_ptr->u.raw64.bus = (unchar)p2;
1521 cmd_ptr->u.raw64.target = (unchar)p3;
1522 cmd_ptr->u.raw64.lun = (unchar)(p3 >> 8);
1523 } else {
1524 cmd_ptr->u.raw.direction = p1;
1525 cmd_ptr->u.raw.bus = (unchar)p2;
1526 cmd_ptr->u.raw.target = (unchar)p3;
1527 cmd_ptr->u.raw.lun = (unchar)(p3 >> 8);
1528 }
1529 } else if (service == SCREENSERVICE) {
1530 if (opcode == GDT_REALTIME) {
1531 *(ulong32 *)&cmd_ptr->u.screen.su.data[0] = p1;
1532 *(ulong32 *)&cmd_ptr->u.screen.su.data[4] = (ulong32)p2;
1533 *(ulong32 *)&cmd_ptr->u.screen.su.data[8] = (ulong32)p3;
1534 }
1535 }
1536 ha->cmd_len = sizeof(gdth_cmd_str);
1537 ha->cmd_offs_dpmem = 0;
1538 ha->cmd_cnt = 0;
1539 gdth_copy_command(ha);
1540 gdth_release_event(ha);
1541 gdth_delay(20);
1542 if (!gdth_wait(ha, index, INIT_TIMEOUT)) {
1543 printk("GDT: Initialization error (timeout service %d)\n",service);
1544 return 0;
1545 }
1546 if (ha->status != S_BSY || --retries == 0)
1547 break;
1548 gdth_delay(1);
1549 }
1550
1551 return (ha->status != S_OK ? 0:1);
1552 }
1553
1554
1555 /* search for devices */
1556
1557 static int __init gdth_search_drives(gdth_ha_str *ha)
1558 {
1559 ushort cdev_cnt, i;
1560 int ok;
1561 ulong32 bus_no, drv_cnt, drv_no, j;
1562 gdth_getch_str *chn;
1563 gdth_drlist_str *drl;
1564 gdth_iochan_str *ioc;
1565 gdth_raw_iochan_str *iocr;
1566 gdth_arcdl_str *alst;
1567 gdth_alist_str *alst2;
1568 gdth_oem_str_ioctl *oemstr;
1569 #ifdef INT_COAL
1570 gdth_perf_modes *pmod;
1571 #endif
1572
1573 #ifdef GDTH_RTC
1574 unchar rtc[12];
1575 ulong flags;
1576 #endif
1577
1578 TRACE(("gdth_search_drives() hanum %d\n", ha->hanum));
1579 ok = 0;
1580
1581 /* initialize controller services, at first: screen service */
1582 ha->screen_feat = 0;
1583 if (!force_dma32) {
1584 ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_X_INIT_SCR, 0, 0, 0);
1585 if (ok)
1586 ha->screen_feat = GDT_64BIT;
1587 }
1588 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
1589 ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_INIT, 0, 0, 0);
1590 if (!ok) {
1591 printk("GDT-HA %d: Initialization error screen service (code %d)\n",
1592 ha->hanum, ha->status);
1593 return 0;
1594 }
1595 TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
1596
1597 #ifdef GDTH_RTC
1598 /* read realtime clock info, send to controller */
1599 /* 1. wait for the falling edge of update flag */
1600 spin_lock_irqsave(&rtc_lock, flags);
1601 for (j = 0; j < 1000000; ++j)
1602 if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
1603 break;
1604 for (j = 0; j < 1000000; ++j)
1605 if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
1606 break;
1607 /* 2. read info */
1608 do {
1609 for (j = 0; j < 12; ++j)
1610 rtc[j] = CMOS_READ(j);
1611 } while (rtc[0] != CMOS_READ(0));
1612 spin_unlock_irqrestore(&rtc_lock, flags);
1613 TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(ulong32 *)&rtc[0],
1614 *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]));
1615 /* 3. send to controller firmware */
1616 gdth_internal_cmd(ha, SCREENSERVICE, GDT_REALTIME, *(ulong32 *)&rtc[0],
1617 *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]);
1618 #endif
1619
1620 /* unfreeze all IOs */
1621 gdth_internal_cmd(ha, CACHESERVICE, GDT_UNFREEZE_IO, 0, 0, 0);
1622
1623 /* initialize cache service */
1624 ha->cache_feat = 0;
1625 if (!force_dma32) {
1626 ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INIT_HOST, LINUX_OS,
1627 0, 0);
1628 if (ok)
1629 ha->cache_feat = GDT_64BIT;
1630 }
1631 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
1632 ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_INIT, LINUX_OS, 0, 0);
1633 if (!ok) {
1634 printk("GDT-HA %d: Initialization error cache service (code %d)\n",
1635 ha->hanum, ha->status);
1636 return 0;
1637 }
1638 TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
1639 cdev_cnt = (ushort)ha->info;
1640 ha->fw_vers = ha->service;
1641
1642 #ifdef INT_COAL
1643 if (ha->type == GDT_PCIMPR) {
1644 /* set perf. modes */
1645 pmod = (gdth_perf_modes *)ha->pscratch;
1646 pmod->version = 1;
1647 pmod->st_mode = 1; /* enable one status buffer */
1648 *((ulong64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
1649 pmod->st_buff_indx1 = COALINDEX;
1650 pmod->st_buff_addr2 = 0;
1651 pmod->st_buff_u_addr2 = 0;
1652 pmod->st_buff_indx2 = 0;
1653 pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
1654 pmod->cmd_mode = 0; // disable all cmd buffers
1655 pmod->cmd_buff_addr1 = 0;
1656 pmod->cmd_buff_u_addr1 = 0;
1657 pmod->cmd_buff_indx1 = 0;
1658 pmod->cmd_buff_addr2 = 0;
1659 pmod->cmd_buff_u_addr2 = 0;
1660 pmod->cmd_buff_indx2 = 0;
1661 pmod->cmd_buff_size = 0;
1662 pmod->reserved1 = 0;
1663 pmod->reserved2 = 0;
1664 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, SET_PERF_MODES,
1665 INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
1666 printk("GDT-HA %d: Interrupt coalescing activated\n", ha->hanum);
1667 }
1668 }
1669 #endif
1670
1671 /* detect number of buses - try new IOCTL */
1672 iocr = (gdth_raw_iochan_str *)ha->pscratch;
1673 iocr->hdr.version = 0xffffffff;
1674 iocr->hdr.list_entries = MAXBUS;
1675 iocr->hdr.first_chan = 0;
1676 iocr->hdr.last_chan = MAXBUS-1;
1677 iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
1678 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_RAW_DESC,
1679 INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
1680 TRACE2(("IOCHAN_RAW_DESC supported!\n"));
1681 ha->bus_cnt = iocr->hdr.chan_count;
1682 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1683 if (iocr->list[bus_no].proc_id < MAXID)
1684 ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
1685 else
1686 ha->bus_id[bus_no] = 0xff;
1687 }
1688 } else {
1689 /* old method */
1690 chn = (gdth_getch_str *)ha->pscratch;
1691 for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
1692 chn->channel_no = bus_no;
1693 if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1694 SCSI_CHAN_CNT | L_CTRL_PATTERN,
1695 IO_CHANNEL | INVALID_CHANNEL,
1696 sizeof(gdth_getch_str))) {
1697 if (bus_no == 0) {
1698 printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
1699 ha->hanum, ha->status);
1700 return 0;
1701 }
1702 break;
1703 }
1704 if (chn->siop_id < MAXID)
1705 ha->bus_id[bus_no] = chn->siop_id;
1706 else
1707 ha->bus_id[bus_no] = 0xff;
1708 }
1709 ha->bus_cnt = (unchar)bus_no;
1710 }
1711 TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
1712
1713 /* read cache configuration */
1714 if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_INFO,
1715 INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
1716 printk("GDT-HA %d: Initialization error cache service (code %d)\n",
1717 ha->hanum, ha->status);
1718 return 0;
1719 }
1720 ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
1721 TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
1722 ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
1723 ha->cpar.write_back,ha->cpar.block_size));
1724
1725 /* read board info and features */
1726 ha->more_proc = FALSE;
1727 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_INFO,
1728 INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
1729 memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
1730 sizeof(gdth_binfo_str));
1731 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_FEATURES,
1732 INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
1733 TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
1734 ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
1735 ha->more_proc = TRUE;
1736 }
1737 } else {
1738 TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
1739 strcpy(ha->binfo.type_string, gdth_ctr_name(ha));
1740 }
1741 TRACE2(("Controller name: %s\n",ha->binfo.type_string));
1742
1743 /* read more informations */
1744 if (ha->more_proc) {
1745 /* physical drives, channel addresses */
1746 ioc = (gdth_iochan_str *)ha->pscratch;
1747 ioc->hdr.version = 0xffffffff;
1748 ioc->hdr.list_entries = MAXBUS;
1749 ioc->hdr.first_chan = 0;
1750 ioc->hdr.last_chan = MAXBUS-1;
1751 ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
1752 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_DESC,
1753 INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
1754 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1755 ha->raw[bus_no].address = ioc->list[bus_no].address;
1756 ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
1757 }
1758 } else {
1759 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1760 ha->raw[bus_no].address = IO_CHANNEL;
1761 ha->raw[bus_no].local_no = bus_no;
1762 }
1763 }
1764 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1765 chn = (gdth_getch_str *)ha->pscratch;
1766 chn->channel_no = ha->raw[bus_no].local_no;
1767 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1768 SCSI_CHAN_CNT | L_CTRL_PATTERN,
1769 ha->raw[bus_no].address | INVALID_CHANNEL,
1770 sizeof(gdth_getch_str))) {
1771 ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
1772 TRACE2(("Channel %d: %d phys. drives\n",
1773 bus_no,chn->drive_cnt));
1774 }
1775 if (ha->raw[bus_no].pdev_cnt > 0) {
1776 drl = (gdth_drlist_str *)ha->pscratch;
1777 drl->sc_no = ha->raw[bus_no].local_no;
1778 drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
1779 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1780 SCSI_DR_LIST | L_CTRL_PATTERN,
1781 ha->raw[bus_no].address | INVALID_CHANNEL,
1782 sizeof(gdth_drlist_str))) {
1783 for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
1784 ha->raw[bus_no].id_list[j] = drl->sc_list[j];
1785 } else {
1786 ha->raw[bus_no].pdev_cnt = 0;
1787 }
1788 }
1789 }
1790
1791 /* logical drives */
1792 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_CNT,
1793 INVALID_CHANNEL,sizeof(ulong32))) {
1794 drv_cnt = *(ulong32 *)ha->pscratch;
1795 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_LIST,
1796 INVALID_CHANNEL,drv_cnt * sizeof(ulong32))) {
1797 for (j = 0; j < drv_cnt; ++j) {
1798 drv_no = ((ulong32 *)ha->pscratch)[j];
1799 if (drv_no < MAX_LDRIVES) {
1800 ha->hdr[drv_no].is_logdrv = TRUE;
1801 TRACE2(("Drive %d is log. drive\n",drv_no));
1802 }
1803 }
1804 }
1805 alst = (gdth_arcdl_str *)ha->pscratch;
1806 alst->entries_avail = MAX_LDRIVES;
1807 alst->first_entry = 0;
1808 alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
1809 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1810 ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
1811 INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
1812 (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
1813 for (j = 0; j < alst->entries_init; ++j) {
1814 ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
1815 ha->hdr[j].is_master = alst->list[j].is_master;
1816 ha->hdr[j].is_parity = alst->list[j].is_parity;
1817 ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
1818 ha->hdr[j].master_no = alst->list[j].cd_handle;
1819 }
1820 } else if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1821 ARRAY_DRV_LIST | LA_CTRL_PATTERN,
1822 0, 35 * sizeof(gdth_alist_str))) {
1823 for (j = 0; j < 35; ++j) {
1824 alst2 = &((gdth_alist_str *)ha->pscratch)[j];
1825 ha->hdr[j].is_arraydrv = alst2->is_arrayd;
1826 ha->hdr[j].is_master = alst2->is_master;
1827 ha->hdr[j].is_parity = alst2->is_parity;
1828 ha->hdr[j].is_hotfix = alst2->is_hotfix;
1829 ha->hdr[j].master_no = alst2->cd_handle;
1830 }
1831 }
1832 }
1833 }
1834
1835 /* initialize raw service */
1836 ha->raw_feat = 0;
1837 if (!force_dma32) {
1838 ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_X_INIT_RAW, 0, 0, 0);
1839 if (ok)
1840 ha->raw_feat = GDT_64BIT;
1841 }
1842 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
1843 ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_INIT, 0, 0, 0);
1844 if (!ok) {
1845 printk("GDT-HA %d: Initialization error raw service (code %d)\n",
1846 ha->hanum, ha->status);
1847 return 0;
1848 }
1849 TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
1850
1851 /* set/get features raw service (scatter/gather) */
1852 if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_SET_FEAT, SCATTER_GATHER,
1853 0, 0)) {
1854 TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
1855 if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_GET_FEAT, 0, 0, 0)) {
1856 TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
1857 ha->info));
1858 ha->raw_feat |= (ushort)ha->info;
1859 }
1860 }
1861
1862 /* set/get features cache service (equal to raw service) */
1863 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_SET_FEAT, 0,
1864 SCATTER_GATHER,0)) {
1865 TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
1866 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_GET_FEAT, 0, 0, 0)) {
1867 TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
1868 ha->info));
1869 ha->cache_feat |= (ushort)ha->info;
1870 }
1871 }
1872
1873 /* reserve drives for raw service */
1874 if (reserve_mode != 0) {
1875 gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE_ALL,
1876 reserve_mode == 1 ? 1 : 3, 0, 0);
1877 TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
1878 ha->status));
1879 }
1880 for (i = 0; i < MAX_RES_ARGS; i += 4) {
1881 if (reserve_list[i] == ha->hanum && reserve_list[i+1] < ha->bus_cnt &&
1882 reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
1883 TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
1884 reserve_list[i], reserve_list[i+1],
1885 reserve_list[i+2], reserve_list[i+3]));
1886 if (!gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE, 0,
1887 reserve_list[i+1], reserve_list[i+2] |
1888 (reserve_list[i+3] << 8))) {
1889 printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
1890 ha->hanum, ha->status);
1891 }
1892 }
1893 }
1894
1895 /* Determine OEM string using IOCTL */
1896 oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
1897 oemstr->params.ctl_version = 0x01;
1898 oemstr->params.buffer_size = sizeof(oemstr->text);
1899 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1900 CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
1901 sizeof(gdth_oem_str_ioctl))) {
1902 TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
1903 printk("GDT-HA %d: Vendor: %s Name: %s\n",
1904 ha->hanum, oemstr->text.oem_company_name, ha->binfo.type_string);
1905 /* Save the Host Drive inquiry data */
1906 strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
1907 sizeof(ha->oem_name));
1908 } else {
1909 /* Old method, based on PCI ID */
1910 TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
1911 printk("GDT-HA %d: Name: %s\n",
1912 ha->hanum, ha->binfo.type_string);
1913 if (ha->oem_id == OEM_ID_INTEL)
1914 strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
1915 else
1916 strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
1917 }
1918
1919 /* scanning for host drives */
1920 for (i = 0; i < cdev_cnt; ++i)
1921 gdth_analyse_hdrive(ha, i);
1922
1923 TRACE(("gdth_search_drives() OK\n"));
1924 return 1;
1925 }
1926
1927 static int gdth_analyse_hdrive(gdth_ha_str *ha, ushort hdrive)
1928 {
1929 ulong32 drv_cyls;
1930 int drv_hds, drv_secs;
1931
1932 TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n", ha->hanum, hdrive));
1933 if (hdrive >= MAX_HDRIVES)
1934 return 0;
1935
1936 if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_INFO, hdrive, 0, 0))
1937 return 0;
1938 ha->hdr[hdrive].present = TRUE;
1939 ha->hdr[hdrive].size = ha->info;
1940
1941 /* evaluate mapping (sectors per head, heads per cylinder) */
1942 ha->hdr[hdrive].size &= ~SECS32;
1943 if (ha->info2 == 0) {
1944 gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
1945 } else {
1946 drv_hds = ha->info2 & 0xff;
1947 drv_secs = (ha->info2 >> 8) & 0xff;
1948 drv_cyls = (ulong32)ha->hdr[hdrive].size / drv_hds / drv_secs;
1949 }
1950 ha->hdr[hdrive].heads = (unchar)drv_hds;
1951 ha->hdr[hdrive].secs = (unchar)drv_secs;
1952 /* round size */
1953 ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
1954
1955 if (ha->cache_feat & GDT_64BIT) {
1956 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INFO, hdrive, 0, 0)
1957 && ha->info2 != 0) {
1958 ha->hdr[hdrive].size = ((ulong64)ha->info2 << 32) | ha->info;
1959 }
1960 }
1961 TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
1962 hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
1963
1964 /* get informations about device */
1965 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_DEVTYPE, hdrive, 0, 0)) {
1966 TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
1967 hdrive,ha->info));
1968 ha->hdr[hdrive].devtype = (ushort)ha->info;
1969 }
1970
1971 /* cluster info */
1972 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_CLUST_INFO, hdrive, 0, 0)) {
1973 TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
1974 hdrive,ha->info));
1975 if (!shared_access)
1976 ha->hdr[hdrive].cluster_type = (unchar)ha->info;
1977 }
1978
1979 /* R/W attributes */
1980 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_RW_ATTRIBS, hdrive, 0, 0)) {
1981 TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
1982 hdrive,ha->info));
1983 ha->hdr[hdrive].rw_attribs = (unchar)ha->info;
1984 }
1985
1986 return 1;
1987 }
1988
1989
1990 /* command queueing/sending functions */
1991
1992 static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar priority)
1993 {
1994 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
1995 register Scsi_Cmnd *pscp;
1996 register Scsi_Cmnd *nscp;
1997 ulong flags;
1998 unchar b, t;
1999
2000 TRACE(("gdth_putq() priority %d\n",priority));
2001 spin_lock_irqsave(&ha->smp_lock, flags);
2002
2003 if (!cmndinfo->internal_command) {
2004 cmndinfo->priority = priority;
2005 b = scp->device->channel;
2006 t = scp->device->id;
2007 if (priority >= DEFAULT_PRI) {
2008 if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
2009 (b==ha->virt_bus && t<MAX_HDRIVES && ha->hdr[t].lock)) {
2010 TRACE2(("gdth_putq(): locked IO ->update_timeout()\n"));
2011 cmndinfo->timeout = gdth_update_timeout(scp, 0);
2012 }
2013 }
2014 }
2015
2016 if (ha->req_first==NULL) {
2017 ha->req_first = scp; /* queue was empty */
2018 scp->SCp.ptr = NULL;
2019 } else { /* queue not empty */
2020 pscp = ha->req_first;
2021 nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2022 /* priority: 0-highest,..,0xff-lowest */
2023 while (nscp && gdth_cmnd_priv(nscp)->priority <= priority) {
2024 pscp = nscp;
2025 nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2026 }
2027 pscp->SCp.ptr = (char *)scp;
2028 scp->SCp.ptr = (char *)nscp;
2029 }
2030 spin_unlock_irqrestore(&ha->smp_lock, flags);
2031
2032 #ifdef GDTH_STATISTICS
2033 flags = 0;
2034 for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
2035 ++flags;
2036 if (max_rq < flags) {
2037 max_rq = flags;
2038 TRACE3(("GDT: max_rq = %d\n",(ushort)max_rq));
2039 }
2040 #endif
2041 }
2042
2043 static void gdth_next(gdth_ha_str *ha)
2044 {
2045 register Scsi_Cmnd *pscp;
2046 register Scsi_Cmnd *nscp;
2047 unchar b, t, l, firsttime;
2048 unchar this_cmd, next_cmd;
2049 ulong flags = 0;
2050 int cmd_index;
2051
2052 TRACE(("gdth_next() hanum %d\n", ha->hanum));
2053 if (!gdth_polling)
2054 spin_lock_irqsave(&ha->smp_lock, flags);
2055
2056 ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
2057 this_cmd = firsttime = TRUE;
2058 next_cmd = gdth_polling ? FALSE:TRUE;
2059 cmd_index = 0;
2060
2061 for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
2062 struct gdth_cmndinfo *nscp_cmndinfo = gdth_cmnd_priv(nscp);
2063 if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
2064 pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2065 if (!nscp_cmndinfo->internal_command) {
2066 b = nscp->device->channel;
2067 t = nscp->device->id;
2068 l = nscp->device->lun;
2069 if (nscp_cmndinfo->priority >= DEFAULT_PRI) {
2070 if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
2071 (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
2072 continue;
2073 }
2074 } else
2075 b = t = l = 0;
2076
2077 if (firsttime) {
2078 if (gdth_test_busy(ha)) { /* controller busy ? */
2079 TRACE(("gdth_next() controller %d busy !\n", ha->hanum));
2080 if (!gdth_polling) {
2081 spin_unlock_irqrestore(&ha->smp_lock, flags);
2082 return;
2083 }
2084 while (gdth_test_busy(ha))
2085 gdth_delay(1);
2086 }
2087 firsttime = FALSE;
2088 }
2089
2090 if (!nscp_cmndinfo->internal_command) {
2091 if (nscp_cmndinfo->phase == -1) {
2092 nscp_cmndinfo->phase = CACHESERVICE; /* default: cache svc. */
2093 if (nscp->cmnd[0] == TEST_UNIT_READY) {
2094 TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
2095 b, t, l));
2096 /* TEST_UNIT_READY -> set scan mode */
2097 if ((ha->scan_mode & 0x0f) == 0) {
2098 if (b == 0 && t == 0 && l == 0) {
2099 ha->scan_mode |= 1;
2100 TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
2101 }
2102 } else if ((ha->scan_mode & 0x0f) == 1) {
2103 if (b == 0 && ((t == 0 && l == 1) ||
2104 (t == 1 && l == 0))) {
2105 nscp_cmndinfo->OpCode = GDT_SCAN_START;
2106 nscp_cmndinfo->phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
2107 | SCSIRAWSERVICE;
2108 ha->scan_mode = 0x12;
2109 TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
2110 ha->scan_mode));
2111 } else {
2112 ha->scan_mode &= 0x10;
2113 TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
2114 }
2115 } else if (ha->scan_mode == 0x12) {
2116 if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
2117 nscp_cmndinfo->phase = SCSIRAWSERVICE;
2118 nscp_cmndinfo->OpCode = GDT_SCAN_END;
2119 ha->scan_mode &= 0x10;
2120 TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
2121 ha->scan_mode));
2122 }
2123 }
2124 }
2125 if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
2126 nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
2127 (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
2128 /* always GDT_CLUST_INFO! */
2129 nscp_cmndinfo->OpCode = GDT_CLUST_INFO;
2130 }
2131 }
2132 }
2133
2134 if (nscp_cmndinfo->OpCode != -1) {
2135 if ((nscp_cmndinfo->phase & 0xff) == CACHESERVICE) {
2136 if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
2137 this_cmd = FALSE;
2138 next_cmd = FALSE;
2139 } else if ((nscp_cmndinfo->phase & 0xff) == SCSIRAWSERVICE) {
2140 if (!(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
2141 this_cmd = FALSE;
2142 next_cmd = FALSE;
2143 } else {
2144 memset((char*)nscp->sense_buffer,0,16);
2145 nscp->sense_buffer[0] = 0x70;
2146 nscp->sense_buffer[2] = NOT_READY;
2147 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2148 if (!nscp_cmndinfo->wait_for_completion)
2149 nscp_cmndinfo->wait_for_completion++;
2150 else
2151 gdth_scsi_done(nscp);
2152 }
2153 } else if (gdth_cmnd_priv(nscp)->internal_command) {
2154 if (!(cmd_index=gdth_special_cmd(ha, nscp)))
2155 this_cmd = FALSE;
2156 next_cmd = FALSE;
2157 } else if (b != ha->virt_bus) {
2158 if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
2159 !(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
2160 this_cmd = FALSE;
2161 else
2162 ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
2163 } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
2164 TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
2165 nscp->cmnd[0], b, t, l));
2166 nscp->result = DID_BAD_TARGET << 16;
2167 if (!nscp_cmndinfo->wait_for_completion)
2168 nscp_cmndinfo->wait_for_completion++;
2169 else
2170 gdth_scsi_done(nscp);
2171 } else {
2172 switch (nscp->cmnd[0]) {
2173 case TEST_UNIT_READY:
2174 case INQUIRY:
2175 case REQUEST_SENSE:
2176 case READ_CAPACITY:
2177 case VERIFY:
2178 case START_STOP:
2179 case MODE_SENSE:
2180 case SERVICE_ACTION_IN:
2181 TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
2182 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2183 nscp->cmnd[4],nscp->cmnd[5]));
2184 if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
2185 /* return UNIT_ATTENTION */
2186 TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
2187 nscp->cmnd[0], t));
2188 ha->hdr[t].media_changed = FALSE;
2189 memset((char*)nscp->sense_buffer,0,16);
2190 nscp->sense_buffer[0] = 0x70;
2191 nscp->sense_buffer[2] = UNIT_ATTENTION;
2192 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2193 if (!nscp_cmndinfo->wait_for_completion)
2194 nscp_cmndinfo->wait_for_completion++;
2195 else
2196 gdth_scsi_done(nscp);
2197 } else if (gdth_internal_cache_cmd(ha, nscp))
2198 gdth_scsi_done(nscp);
2199 break;
2200
2201 case ALLOW_MEDIUM_REMOVAL:
2202 TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
2203 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2204 nscp->cmnd[4],nscp->cmnd[5]));
2205 if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
2206 TRACE(("Prevent r. nonremov. drive->do nothing\n"));
2207 nscp->result = DID_OK << 16;
2208 nscp->sense_buffer[0] = 0;
2209 if (!nscp_cmndinfo->wait_for_completion)
2210 nscp_cmndinfo->wait_for_completion++;
2211 else
2212 gdth_scsi_done(nscp);
2213 } else {
2214 nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
2215 TRACE(("Prevent/allow r. %d rem. drive %d\n",
2216 nscp->cmnd[4],nscp->cmnd[3]));
2217 if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
2218 this_cmd = FALSE;
2219 }
2220 break;
2221
2222 case RESERVE:
2223 case RELEASE:
2224 TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
2225 "RESERVE" : "RELEASE"));
2226 if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
2227 this_cmd = FALSE;
2228 break;
2229
2230 case READ_6:
2231 case WRITE_6:
2232 case READ_10:
2233 case WRITE_10:
2234 case READ_16:
2235 case WRITE_16:
2236 if (ha->hdr[t].media_changed) {
2237 /* return UNIT_ATTENTION */
2238 TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
2239 nscp->cmnd[0], t));
2240 ha->hdr[t].media_changed = FALSE;
2241 memset((char*)nscp->sense_buffer,0,16);
2242 nscp->sense_buffer[0] = 0x70;
2243 nscp->sense_buffer[2] = UNIT_ATTENTION;
2244 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2245 if (!nscp_cmndinfo->wait_for_completion)
2246 nscp_cmndinfo->wait_for_completion++;
2247 else
2248 gdth_scsi_done(nscp);
2249 } else if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
2250 this_cmd = FALSE;
2251 break;
2252
2253 default:
2254 TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
2255 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2256 nscp->cmnd[4],nscp->cmnd[5]));
2257 printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
2258 ha->hanum, nscp->cmnd[0]);
2259 nscp->result = DID_ABORT << 16;
2260 if (!nscp_cmndinfo->wait_for_completion)
2261 nscp_cmndinfo->wait_for_completion++;
2262 else
2263 gdth_scsi_done(nscp);
2264 break;
2265 }
2266 }
2267
2268 if (!this_cmd)
2269 break;
2270 if (nscp == ha->req_first)
2271 ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
2272 else
2273 pscp->SCp.ptr = nscp->SCp.ptr;
2274 if (!next_cmd)
2275 break;
2276 }
2277
2278 if (ha->cmd_cnt > 0) {
2279 gdth_release_event(ha);
2280 }
2281
2282 if (!gdth_polling)
2283 spin_unlock_irqrestore(&ha->smp_lock, flags);
2284
2285 if (gdth_polling && ha->cmd_cnt > 0) {
2286 if (!gdth_wait(ha, cmd_index, POLL_TIMEOUT))
2287 printk("GDT-HA %d: Command %d timed out !\n",
2288 ha->hanum, cmd_index);
2289 }
2290 }
2291
2292 /*
2293 * gdth_copy_internal_data() - copy to/from a buffer onto a scsi_cmnd's
2294 * buffers, kmap_atomic() as needed.
2295 */
2296 static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
2297 char *buffer, ushort count)
2298 {
2299 ushort cpcount,i, max_sg = scsi_sg_count(scp);
2300 ushort cpsum,cpnow;
2301 struct scatterlist *sl;
2302 char *address;
2303
2304 cpcount = min_t(ushort, count, scsi_bufflen(scp));
2305
2306 if (cpcount) {
2307 cpsum=0;
2308 scsi_for_each_sg(scp, sl, max_sg, i) {
2309 unsigned long flags;
2310 cpnow = (ushort)sl->length;
2311 TRACE(("copy_internal() now %d sum %d count %d %d\n",
2312 cpnow, cpsum, cpcount, scsi_bufflen(scp)));
2313 if (cpsum+cpnow > cpcount)
2314 cpnow = cpcount - cpsum;
2315 cpsum += cpnow;
2316 if (!sg_page(sl)) {
2317 printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
2318 ha->hanum);
2319 return;
2320 }
2321 local_irq_save(flags);
2322 address = kmap_atomic(sg_page(sl), KM_BIO_SRC_IRQ) + sl->offset;
2323 memcpy(address, buffer, cpnow);
2324 flush_dcache_page(sg_page(sl));
2325 kunmap_atomic(address, KM_BIO_SRC_IRQ);
2326 local_irq_restore(flags);
2327 if (cpsum == cpcount)
2328 break;
2329 buffer += cpnow;
2330 }
2331 } else if (count) {
2332 printk("GDT-HA %d: SCSI command with no buffers but data transfer expected!\n",
2333 ha->hanum);
2334 WARN_ON(1);
2335 }
2336 }
2337
2338 static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
2339 {
2340 unchar t;
2341 gdth_inq_data inq;
2342 gdth_rdcap_data rdc;
2343 gdth_sense_data sd;
2344 gdth_modep_data mpd;
2345 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
2346
2347 t = scp->device->id;
2348 TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
2349 scp->cmnd[0],t));
2350
2351 scp->result = DID_OK << 16;
2352 scp->sense_buffer[0] = 0;
2353
2354 switch (scp->cmnd[0]) {
2355 case TEST_UNIT_READY:
2356 case VERIFY:
2357 case START_STOP:
2358 TRACE2(("Test/Verify/Start hdrive %d\n",t));
2359 break;
2360
2361 case INQUIRY:
2362 TRACE2(("Inquiry hdrive %d devtype %d\n",
2363 t,ha->hdr[t].devtype));
2364 inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
2365 /* you can here set all disks to removable, if you want to do
2366 a flush using the ALLOW_MEDIUM_REMOVAL command */
2367 inq.modif_rmb = 0x00;
2368 if ((ha->hdr[t].devtype & 1) ||
2369 (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
2370 inq.modif_rmb = 0x80;
2371 inq.version = 2;
2372 inq.resp_aenc = 2;
2373 inq.add_length= 32;
2374 strcpy(inq.vendor,ha->oem_name);
2375 sprintf(inq.product,"Host Drive #%02d",t);
2376 strcpy(inq.revision," ");
2377 gdth_copy_internal_data(ha, scp, (char*)&inq, sizeof(gdth_inq_data));
2378 break;
2379
2380 case REQUEST_SENSE:
2381 TRACE2(("Request sense hdrive %d\n",t));
2382 sd.errorcode = 0x70;
2383 sd.segno = 0x00;
2384 sd.key = NO_SENSE;
2385 sd.info = 0;
2386 sd.add_length= 0;
2387 gdth_copy_internal_data(ha, scp, (char*)&sd, sizeof(gdth_sense_data));
2388 break;
2389
2390 case MODE_SENSE:
2391 TRACE2(("Mode sense hdrive %d\n",t));
2392 memset((char*)&mpd,0,sizeof(gdth_modep_data));
2393 mpd.hd.data_length = sizeof(gdth_modep_data);
2394 mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
2395 mpd.hd.bd_length = sizeof(mpd.bd);
2396 mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
2397 mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
2398 mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
2399 gdth_copy_internal_data(ha, scp, (char*)&mpd, sizeof(gdth_modep_data));
2400 break;
2401
2402 case READ_CAPACITY:
2403 TRACE2(("Read capacity hdrive %d\n",t));
2404 if (ha->hdr[t].size > (ulong64)0xffffffff)
2405 rdc.last_block_no = 0xffffffff;
2406 else
2407 rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
2408 rdc.block_length = cpu_to_be32(SECTOR_SIZE);
2409 gdth_copy_internal_data(ha, scp, (char*)&rdc, sizeof(gdth_rdcap_data));
2410 break;
2411
2412 case SERVICE_ACTION_IN:
2413 if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
2414 (ha->cache_feat & GDT_64BIT)) {
2415 gdth_rdcap16_data rdc16;
2416
2417 TRACE2(("Read capacity (16) hdrive %d\n",t));
2418 rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
2419 rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
2420 gdth_copy_internal_data(ha, scp, (char*)&rdc16,
2421 sizeof(gdth_rdcap16_data));
2422 } else {
2423 scp->result = DID_ABORT << 16;
2424 }
2425 break;
2426
2427 default:
2428 TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
2429 break;
2430 }
2431
2432 if (!cmndinfo->wait_for_completion)
2433 cmndinfo->wait_for_completion++;
2434 else
2435 return 1;
2436
2437 return 0;
2438 }
2439
2440 static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, ushort hdrive)
2441 {
2442 register gdth_cmd_str *cmdp;
2443 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
2444 ulong32 cnt, blockcnt;
2445 ulong64 no, blockno;
2446 int i, cmd_index, read_write, sgcnt, mode64;
2447
2448 cmdp = ha->pccb;
2449 TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
2450 scp->cmnd[0],scp->cmd_len,hdrive));
2451
2452 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2453 return 0;
2454
2455 mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
2456 /* test for READ_16, WRITE_16 if !mode64 ? ---
2457 not required, should not occur due to error return on
2458 READ_CAPACITY_16 */
2459
2460 cmdp->Service = CACHESERVICE;
2461 cmdp->RequestBuffer = scp;
2462 /* search free command index */
2463 if (!(cmd_index=gdth_get_cmd_index(ha))) {
2464 TRACE(("GDT: No free command index found\n"));
2465 return 0;
2466 }
2467 /* if it's the first command, set command semaphore */
2468 if (ha->cmd_cnt == 0)
2469 gdth_set_sema0(ha);
2470
2471 /* fill command */
2472 read_write = 0;
2473 if (cmndinfo->OpCode != -1)
2474 cmdp->OpCode = cmndinfo->OpCode; /* special cache cmd. */
2475 else if (scp->cmnd[0] == RESERVE)
2476 cmdp->OpCode = GDT_RESERVE_DRV;
2477 else if (scp->cmnd[0] == RELEASE)
2478 cmdp->OpCode = GDT_RELEASE_DRV;
2479 else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
2480 if (scp->cmnd[4] & 1) /* prevent ? */
2481 cmdp->OpCode = GDT_MOUNT;
2482 else if (scp->cmnd[3] & 1) /* removable drive ? */
2483 cmdp->OpCode = GDT_UNMOUNT;
2484 else
2485 cmdp->OpCode = GDT_FLUSH;
2486 } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
2487 scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
2488 ) {
2489 read_write = 1;
2490 if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
2491 (ha->cache_feat & GDT_WR_THROUGH)))
2492 cmdp->OpCode = GDT_WRITE_THR;
2493 else
2494 cmdp->OpCode = GDT_WRITE;
2495 } else {
2496 read_write = 2;
2497 cmdp->OpCode = GDT_READ;
2498 }
2499
2500 cmdp->BoardNode = LOCALBOARD;
2501 if (mode64) {
2502 cmdp->u.cache64.DeviceNo = hdrive;
2503 cmdp->u.cache64.BlockNo = 1;
2504 cmdp->u.cache64.sg_canz = 0;
2505 } else {
2506 cmdp->u.cache.DeviceNo = hdrive;
2507 cmdp->u.cache.BlockNo = 1;
2508 cmdp->u.cache.sg_canz = 0;
2509 }
2510
2511 if (read_write) {
2512 if (scp->cmd_len == 16) {
2513 memcpy(&no, &scp->cmnd[2], sizeof(ulong64));
2514 blockno = be64_to_cpu(no);
2515 memcpy(&cnt, &scp->cmnd[10], sizeof(ulong32));
2516 blockcnt = be32_to_cpu(cnt);
2517 } else if (scp->cmd_len == 10) {
2518 memcpy(&no, &scp->cmnd[2], sizeof(ulong32));
2519 blockno = be32_to_cpu(no);
2520 memcpy(&cnt, &scp->cmnd[7], sizeof(ushort));
2521 blockcnt = be16_to_cpu(cnt);
2522 } else {
2523 memcpy(&no, &scp->cmnd[0], sizeof(ulong32));
2524 blockno = be32_to_cpu(no) & 0x001fffffUL;
2525 blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
2526 }
2527 if (mode64) {
2528 cmdp->u.cache64.BlockNo = blockno;
2529 cmdp->u.cache64.BlockCnt = blockcnt;
2530 } else {
2531 cmdp->u.cache.BlockNo = (ulong32)blockno;
2532 cmdp->u.cache.BlockCnt = blockcnt;
2533 }
2534
2535 if (scsi_bufflen(scp)) {
2536 cmndinfo->dma_dir = (read_write == 1 ?
2537 PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
2538 sgcnt = pci_map_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
2539 cmndinfo->dma_dir);
2540 if (mode64) {
2541 struct scatterlist *sl;
2542
2543 cmdp->u.cache64.DestAddr= (ulong64)-1;
2544 cmdp->u.cache64.sg_canz = sgcnt;
2545 scsi_for_each_sg(scp, sl, sgcnt, i) {
2546 cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
2547 #ifdef GDTH_DMA_STATISTICS
2548 if (cmdp->u.cache64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
2549 ha->dma64_cnt++;
2550 else
2551 ha->dma32_cnt++;
2552 #endif
2553 cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
2554 }
2555 } else {
2556 struct scatterlist *sl;
2557
2558 cmdp->u.cache.DestAddr= 0xffffffff;
2559 cmdp->u.cache.sg_canz = sgcnt;
2560 scsi_for_each_sg(scp, sl, sgcnt, i) {
2561 cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
2562 #ifdef GDTH_DMA_STATISTICS
2563 ha->dma32_cnt++;
2564 #endif
2565 cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
2566 }
2567 }
2568
2569 #ifdef GDTH_STATISTICS
2570 if (max_sg < (ulong32)sgcnt) {
2571 max_sg = (ulong32)sgcnt;
2572 TRACE3(("GDT: max_sg = %d\n",max_sg));
2573 }
2574 #endif
2575
2576 }
2577 }
2578 /* evaluate command size, check space */
2579 if (mode64) {
2580 TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2581 cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
2582 cmdp->u.cache64.sg_lst[0].sg_ptr,
2583 cmdp->u.cache64.sg_lst[0].sg_len));
2584 TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
2585 cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
2586 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
2587 (ushort)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
2588 } else {
2589 TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2590 cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
2591 cmdp->u.cache.sg_lst[0].sg_ptr,
2592 cmdp->u.cache.sg_lst[0].sg_len));
2593 TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
2594 cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
2595 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
2596 (ushort)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
2597 }
2598 if (ha->cmd_len & 3)
2599 ha->cmd_len += (4 - (ha->cmd_len & 3));
2600
2601 if (ha->cmd_cnt > 0) {
2602 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
2603 ha->ic_all_size) {
2604 TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
2605 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
2606 return 0;
2607 }
2608 }
2609
2610 /* copy command */
2611 gdth_copy_command(ha);
2612 return cmd_index;
2613 }
2614
2615 static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar b)
2616 {
2617 register gdth_cmd_str *cmdp;
2618 ushort i;
2619 dma_addr_t sense_paddr;
2620 int cmd_index, sgcnt, mode64;
2621 unchar t,l;
2622 struct page *page;
2623 ulong offset;
2624 struct gdth_cmndinfo *cmndinfo;
2625
2626 t = scp->device->id;
2627 l = scp->device->lun;
2628 cmdp = ha->pccb;
2629 TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
2630 scp->cmnd[0],b,t,l));
2631
2632 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2633 return 0;
2634
2635 mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
2636
2637 cmdp->Service = SCSIRAWSERVICE;
2638 cmdp->RequestBuffer = scp;
2639 /* search free command index */
2640 if (!(cmd_index=gdth_get_cmd_index(ha))) {
2641 TRACE(("GDT: No free command index found\n"));
2642 return 0;
2643 }
2644 /* if it's the first command, set command semaphore */
2645 if (ha->cmd_cnt == 0)
2646 gdth_set_sema0(ha);
2647
2648 cmndinfo = gdth_cmnd_priv(scp);
2649 /* fill command */
2650 if (cmndinfo->OpCode != -1) {
2651 cmdp->OpCode = cmndinfo->OpCode; /* special raw cmd. */
2652 cmdp->BoardNode = LOCALBOARD;
2653 if (mode64) {
2654 cmdp->u.raw64.direction = (cmndinfo->phase >> 8);
2655 TRACE2(("special raw cmd 0x%x param 0x%x\n",
2656 cmdp->OpCode, cmdp->u.raw64.direction));
2657 /* evaluate command size */
2658 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
2659 } else {
2660 cmdp->u.raw.direction = (cmndinfo->phase >> 8);
2661 TRACE2(("special raw cmd 0x%x param 0x%x\n",
2662 cmdp->OpCode, cmdp->u.raw.direction));
2663 /* evaluate command size */
2664 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
2665 }
2666
2667 } else {
2668 page = virt_to_page(scp->sense_buffer);
2669 offset = (ulong)scp->sense_buffer & ~PAGE_MASK;
2670 sense_paddr = pci_map_page(ha->pdev,page,offset,
2671 16,PCI_DMA_FROMDEVICE);
2672
2673 cmndinfo->sense_paddr = sense_paddr;
2674 cmdp->OpCode = GDT_WRITE; /* always */
2675 cmdp->BoardNode = LOCALBOARD;
2676 if (mode64) {
2677 cmdp->u.raw64.reserved = 0;
2678 cmdp->u.raw64.mdisc_time = 0;
2679 cmdp->u.raw64.mcon_time = 0;
2680 cmdp->u.raw64.clen = scp->cmd_len;
2681 cmdp->u.raw64.target = t;
2682 cmdp->u.raw64.lun = l;
2683 cmdp->u.raw64.bus = b;
2684 cmdp->u.raw64.priority = 0;
2685 cmdp->u.raw64.sdlen = scsi_bufflen(scp);
2686 cmdp->u.raw64.sense_len = 16;
2687 cmdp->u.raw64.sense_data = sense_paddr;
2688 cmdp->u.raw64.direction =
2689 gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
2690 memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
2691 cmdp->u.raw64.sg_ranz = 0;
2692 } else {
2693 cmdp->u.raw.reserved = 0;
2694 cmdp->u.raw.mdisc_time = 0;
2695 cmdp->u.raw.mcon_time = 0;
2696 cmdp->u.raw.clen = scp->cmd_len;
2697 cmdp->u.raw.target = t;
2698 cmdp->u.raw.lun = l;
2699 cmdp->u.raw.bus = b;
2700 cmdp->u.raw.priority = 0;
2701 cmdp->u.raw.link_p = 0;
2702 cmdp->u.raw.sdlen = scsi_bufflen(scp);
2703 cmdp->u.raw.sense_len = 16;
2704 cmdp->u.raw.sense_data = sense_paddr;
2705 cmdp->u.raw.direction =
2706 gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
2707 memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
2708 cmdp->u.raw.sg_ranz = 0;
2709 }
2710
2711 if (scsi_bufflen(scp)) {
2712 cmndinfo->dma_dir = PCI_DMA_BIDIRECTIONAL;
2713 sgcnt = pci_map_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
2714 cmndinfo->dma_dir);
2715 if (mode64) {
2716 struct scatterlist *sl;
2717
2718 cmdp->u.raw64.sdata = (ulong64)-1;
2719 cmdp->u.raw64.sg_ranz = sgcnt;
2720 scsi_for_each_sg(scp, sl, sgcnt, i) {
2721 cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
2722 #ifdef GDTH_DMA_STATISTICS
2723 if (cmdp->u.raw64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
2724 ha->dma64_cnt++;
2725 else
2726 ha->dma32_cnt++;
2727 #endif
2728 cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
2729 }
2730 } else {
2731 struct scatterlist *sl;
2732
2733 cmdp->u.raw.sdata = 0xffffffff;
2734 cmdp->u.raw.sg_ranz = sgcnt;
2735 scsi_for_each_sg(scp, sl, sgcnt, i) {
2736 cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
2737 #ifdef GDTH_DMA_STATISTICS
2738 ha->dma32_cnt++;
2739 #endif
2740 cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
2741 }
2742 }
2743
2744 #ifdef GDTH_STATISTICS
2745 if (max_sg < sgcnt) {
2746 max_sg = sgcnt;
2747 TRACE3(("GDT: max_sg = %d\n",sgcnt));
2748 }
2749 #endif
2750
2751 }
2752 if (mode64) {
2753 TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2754 cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
2755 cmdp->u.raw64.sg_lst[0].sg_ptr,
2756 cmdp->u.raw64.sg_lst[0].sg_len));
2757 /* evaluate command size */
2758 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
2759 (ushort)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
2760 } else {
2761 TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2762 cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
2763 cmdp->u.raw.sg_lst[0].sg_ptr,
2764 cmdp->u.raw.sg_lst[0].sg_len));
2765 /* evaluate command size */
2766 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
2767 (ushort)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
2768 }
2769 }
2770 /* check space */
2771 if (ha->cmd_len & 3)
2772 ha->cmd_len += (4 - (ha->cmd_len & 3));
2773
2774 if (ha->cmd_cnt > 0) {
2775 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
2776 ha->ic_all_size) {
2777 TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
2778 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
2779 return 0;
2780 }
2781 }
2782
2783 /* copy command */
2784 gdth_copy_command(ha);
2785 return cmd_index;
2786 }
2787
2788 static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
2789 {
2790 register gdth_cmd_str *cmdp;
2791 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
2792 int cmd_index;
2793
2794 cmdp= ha->pccb;
2795 TRACE2(("gdth_special_cmd(): "));
2796
2797 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2798 return 0;
2799
2800 *cmdp = *cmndinfo->internal_cmd_str;
2801 cmdp->RequestBuffer = scp;
2802
2803 /* search free command index */
2804 if (!(cmd_index=gdth_get_cmd_index(ha))) {
2805 TRACE(("GDT: No free command index found\n"));
2806 return 0;
2807 }
2808
2809 /* if it's the first command, set command semaphore */
2810 if (ha->cmd_cnt == 0)
2811 gdth_set_sema0(ha);
2812
2813 /* evaluate command size, check space */
2814 if (cmdp->OpCode == GDT_IOCTL) {
2815 TRACE2(("IOCTL\n"));
2816 ha->cmd_len =
2817 GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(ulong64);
2818 } else if (cmdp->Service == CACHESERVICE) {
2819 TRACE2(("cache command %d\n",cmdp->OpCode));
2820 if (ha->cache_feat & GDT_64BIT)
2821 ha->cmd_len =
2822 GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
2823 else
2824 ha->cmd_len =
2825 GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
2826 } else if (cmdp->Service == SCSIRAWSERVICE) {
2827 TRACE2(("raw command %d\n",cmdp->OpCode));
2828 if (ha->raw_feat & GDT_64BIT)
2829 ha->cmd_len =
2830 GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
2831 else
2832 ha->cmd_len =
2833 GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
2834 }
2835
2836 if (ha->cmd_len & 3)
2837 ha->cmd_len += (4 - (ha->cmd_len & 3));
2838
2839 if (ha->cmd_cnt > 0) {
2840 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
2841 ha->ic_all_size) {
2842 TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
2843 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
2844 return 0;
2845 }
2846 }
2847
2848 /* copy command */
2849 gdth_copy_command(ha);
2850 return cmd_index;
2851 }
2852
2853
2854 /* Controller event handling functions */
2855 static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
2856 ushort idx, gdth_evt_data *evt)
2857 {
2858 gdth_evt_str *e;
2859 struct timeval tv;
2860
2861 /* no GDTH_LOCK_HA() ! */
2862 TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
2863 if (source == 0) /* no source -> no event */
2864 return NULL;
2865
2866 if (ebuffer[elastidx].event_source == source &&
2867 ebuffer[elastidx].event_idx == idx &&
2868 ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
2869 !memcmp((char *)&ebuffer[elastidx].event_data.eu,
2870 (char *)&evt->eu, evt->size)) ||
2871 (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
2872 !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
2873 (char *)&evt->event_string)))) {
2874 e = &ebuffer[elastidx];
2875 do_gettimeofday(&tv);
2876 e->last_stamp = tv.tv_sec;
2877 ++e->same_count;
2878 } else {
2879 if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
2880 ++elastidx;
2881 if (elastidx == MAX_EVENTS)
2882 elastidx = 0;
2883 if (elastidx == eoldidx) { /* reached mark ? */
2884 ++eoldidx;
2885 if (eoldidx == MAX_EVENTS)
2886 eoldidx = 0;
2887 }
2888 }
2889 e = &ebuffer[elastidx];
2890 e->event_source = source;
2891 e->event_idx = idx;
2892 do_gettimeofday(&tv);
2893 e->first_stamp = e->last_stamp = tv.tv_sec;
2894 e->same_count = 1;
2895 e->event_data = *evt;
2896 e->application = 0;
2897 }
2898 return e;
2899 }
2900
2901 static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
2902 {
2903 gdth_evt_str *e;
2904 int eindex;
2905 ulong flags;
2906
2907 TRACE2(("gdth_read_event() handle %d\n", handle));
2908 spin_lock_irqsave(&ha->smp_lock, flags);
2909 if (handle == -1)
2910 eindex = eoldidx;
2911 else
2912 eindex = handle;
2913 estr->event_source = 0;
2914
2915 if (eindex >= MAX_EVENTS) {
2916 spin_unlock_irqrestore(&ha->smp_lock, flags);
2917 return eindex;
2918 }
2919 e = &ebuffer[eindex];
2920 if (e->event_source != 0) {
2921 if (eindex != elastidx) {
2922 if (++eindex == MAX_EVENTS)
2923 eindex = 0;
2924 } else {
2925 eindex = -1;
2926 }
2927 memcpy(estr, e, sizeof(gdth_evt_str));
2928 }
2929 spin_unlock_irqrestore(&ha->smp_lock, flags);
2930 return eindex;
2931 }
2932
2933 static void gdth_readapp_event(gdth_ha_str *ha,
2934 unchar application, gdth_evt_str *estr)
2935 {
2936 gdth_evt_str *e;
2937 int eindex;
2938 ulong flags;
2939 unchar found = FALSE;
2940
2941 TRACE2(("gdth_readapp_event() app. %d\n", application));
2942 spin_lock_irqsave(&ha->smp_lock, flags);
2943 eindex = eoldidx;
2944 for (;;) {
2945 e = &ebuffer[eindex];
2946 if (e->event_source == 0)
2947 break;
2948 if ((e->application & application) == 0) {
2949 e->application |= application;
2950 found = TRUE;
2951 break;
2952 }
2953 if (eindex == elastidx)
2954 break;
2955 if (++eindex == MAX_EVENTS)
2956 eindex = 0;
2957 }
2958 if (found)
2959 memcpy(estr, e, sizeof(gdth_evt_str));
2960 else
2961 estr->event_source = 0;
2962 spin_unlock_irqrestore(&ha->smp_lock, flags);
2963 }
2964
2965 static void gdth_clear_events(void)
2966 {
2967 TRACE(("gdth_clear_events()"));
2968
2969 eoldidx = elastidx = 0;
2970 ebuffer[0].event_source = 0;
2971 }
2972
2973
2974 /* SCSI interface functions */
2975
2976 static irqreturn_t __gdth_interrupt(gdth_ha_str *ha,
2977 int gdth_from_wait, int* pIndex)
2978 {
2979 gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
2980 gdt6_dpram_str __iomem *dp6_ptr;
2981 gdt2_dpram_str __iomem *dp2_ptr;
2982 Scsi_Cmnd *scp;
2983 int rval, i;
2984 unchar IStatus;
2985 ushort Service;
2986 ulong flags = 0;
2987 #ifdef INT_COAL
2988 int coalesced = FALSE;
2989 int next = FALSE;
2990 gdth_coal_status *pcs = NULL;
2991 int act_int_coal = 0;
2992 #endif
2993
2994 TRACE(("gdth_interrupt() IRQ %d\n", ha->irq));
2995
2996 /* if polling and not from gdth_wait() -> return */
2997 if (gdth_polling) {
2998 if (!gdth_from_wait) {
2999 return IRQ_HANDLED;
3000 }
3001 }
3002
3003 if (!gdth_polling)
3004 spin_lock_irqsave(&ha->smp_lock, flags);
3005
3006 /* search controller */
3007 IStatus = gdth_get_status(ha);
3008 if (IStatus == 0) {
3009 /* spurious interrupt */
3010 if (!gdth_polling)
3011 spin_unlock_irqrestore(&ha->smp_lock, flags);
3012 return IRQ_HANDLED;
3013 }
3014
3015 #ifdef GDTH_STATISTICS
3016 ++act_ints;
3017 #endif
3018
3019 #ifdef INT_COAL
3020 /* See if the fw is returning coalesced status */
3021 if (IStatus == COALINDEX) {
3022 /* Coalesced status. Setup the initial status
3023 buffer pointer and flags */
3024 pcs = ha->coal_stat;
3025 coalesced = TRUE;
3026 next = TRUE;
3027 }
3028
3029 do {
3030 if (coalesced) {
3031 /* For coalesced requests all status
3032 information is found in the status buffer */
3033 IStatus = (unchar)(pcs->status & 0xff);
3034 }
3035 #endif
3036
3037 if (ha->type == GDT_EISA) {
3038 if (IStatus & 0x80) { /* error flag */
3039 IStatus &= ~0x80;
3040 ha->status = inw(ha->bmic + MAILBOXREG+8);
3041 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3042 } else /* no error */
3043 ha->status = S_OK;
3044 ha->info = inl(ha->bmic + MAILBOXREG+12);
3045 ha->service = inw(ha->bmic + MAILBOXREG+10);
3046 ha->info2 = inl(ha->bmic + MAILBOXREG+4);
3047
3048 outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
3049 outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
3050 } else if (ha->type == GDT_ISA) {
3051 dp2_ptr = ha->brd;
3052 if (IStatus & 0x80) { /* error flag */
3053 IStatus &= ~0x80;
3054 ha->status = readw(&dp2_ptr->u.ic.Status);
3055 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3056 } else /* no error */
3057 ha->status = S_OK;
3058 ha->info = readl(&dp2_ptr->u.ic.Info[0]);
3059 ha->service = readw(&dp2_ptr->u.ic.Service);
3060 ha->info2 = readl(&dp2_ptr->u.ic.Info[1]);
3061
3062 writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
3063 writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
3064 writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
3065 } else if (ha->type == GDT_PCI) {
3066 dp6_ptr = ha->brd;
3067 if (IStatus & 0x80) { /* error flag */
3068 IStatus &= ~0x80;
3069 ha->status = readw(&dp6_ptr->u.ic.Status);
3070 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3071 } else /* no error */
3072 ha->status = S_OK;
3073 ha->info = readl(&dp6_ptr->u.ic.Info[0]);
3074 ha->service = readw(&dp6_ptr->u.ic.Service);
3075 ha->info2 = readl(&dp6_ptr->u.ic.Info[1]);
3076
3077 writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
3078 writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
3079 writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
3080 } else if (ha->type == GDT_PCINEW) {
3081 if (IStatus & 0x80) { /* error flag */
3082 IStatus &= ~0x80;
3083 ha->status = inw(PTR2USHORT(&ha->plx->status));
3084 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3085 } else
3086 ha->status = S_OK;
3087 ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
3088 ha->service = inw(PTR2USHORT(&ha->plx->service));
3089 ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
3090
3091 outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
3092 outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
3093 } else if (ha->type == GDT_PCIMPR) {
3094 dp6m_ptr = ha->brd;
3095 if (IStatus & 0x80) { /* error flag */
3096 IStatus &= ~0x80;
3097 #ifdef INT_COAL
3098 if (coalesced)
3099 ha->status = pcs->ext_status & 0xffff;
3100 else
3101 #endif
3102 ha->status = readw(&dp6m_ptr->i960r.status);
3103 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3104 } else /* no error */
3105 ha->status = S_OK;
3106 #ifdef INT_COAL
3107 /* get information */
3108 if (coalesced) {
3109 ha->info = pcs->info0;
3110 ha->info2 = pcs->info1;
3111 ha->service = (pcs->ext_status >> 16) & 0xffff;
3112 } else
3113 #endif
3114 {
3115 ha->info = readl(&dp6m_ptr->i960r.info[0]);
3116 ha->service = readw(&dp6m_ptr->i960r.service);
3117 ha->info2 = readl(&dp6m_ptr->i960r.info[1]);
3118 }
3119 /* event string */
3120 if (IStatus == ASYNCINDEX) {
3121 if (ha->service != SCREENSERVICE &&
3122 (ha->fw_vers & 0xff) >= 0x1a) {
3123 ha->dvr.severity = readb
3124 (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
3125 for (i = 0; i < 256; ++i) {
3126 ha->dvr.event_string[i] = readb
3127 (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
3128 if (ha->dvr.event_string[i] == 0)
3129 break;
3130 }
3131 }
3132 }
3133 #ifdef INT_COAL
3134 /* Make sure that non coalesced interrupts get cleared
3135 before being handled by gdth_async_event/gdth_sync_event */
3136 if (!coalesced)
3137 #endif
3138 {
3139 writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
3140 writeb(0, &dp6m_ptr->i960r.sema1_reg);
3141 }
3142 } else {
3143 TRACE2(("gdth_interrupt() unknown controller type\n"));
3144 if (!gdth_polling)
3145 spin_unlock_irqrestore(&ha->smp_lock, flags);
3146 return IRQ_HANDLED;
3147 }
3148
3149 TRACE(("gdth_interrupt() index %d stat %d info %d\n",
3150 IStatus,ha->status,ha->info));
3151
3152 if (gdth_from_wait) {
3153 *pIndex = (int)IStatus;
3154 }
3155
3156 if (IStatus == ASYNCINDEX) {
3157 TRACE2(("gdth_interrupt() async. event\n"));
3158 gdth_async_event(ha);
3159 if (!gdth_polling)
3160 spin_unlock_irqrestore(&ha->smp_lock, flags);
3161 gdth_next(ha);
3162 return IRQ_HANDLED;
3163 }
3164
3165 if (IStatus == SPEZINDEX) {
3166 TRACE2(("Service unknown or not initialized !\n"));
3167 ha->dvr.size = sizeof(ha->dvr.eu.driver);
3168 ha->dvr.eu.driver.ionode = ha->hanum;
3169 gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
3170 if (!gdth_polling)
3171 spin_unlock_irqrestore(&ha->smp_lock, flags);
3172 return IRQ_HANDLED;
3173 }
3174 scp = ha->cmd_tab[IStatus-2].cmnd;
3175 Service = ha->cmd_tab[IStatus-2].service;
3176 ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
3177 if (scp == UNUSED_CMND) {
3178 TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
3179 ha->dvr.size = sizeof(ha->dvr.eu.driver);
3180 ha->dvr.eu.driver.ionode = ha->hanum;
3181 ha->dvr.eu.driver.index = IStatus;
3182 gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
3183 if (!gdth_polling)
3184 spin_unlock_irqrestore(&ha->smp_lock, flags);
3185 return IRQ_HANDLED;
3186 }
3187 if (scp == INTERNAL_CMND) {
3188 TRACE(("gdth_interrupt() answer to internal command\n"));
3189 if (!gdth_polling)
3190 spin_unlock_irqrestore(&ha->smp_lock, flags);
3191 return IRQ_HANDLED;
3192 }
3193
3194 TRACE(("gdth_interrupt() sync. status\n"));
3195 rval = gdth_sync_event(ha,Service,IStatus,scp);
3196 if (!gdth_polling)
3197 spin_unlock_irqrestore(&ha->smp_lock, flags);
3198 if (rval == 2) {
3199 gdth_putq(ha, scp, gdth_cmnd_priv(scp)->priority);
3200 } else if (rval == 1) {
3201 gdth_scsi_done(scp);
3202 }
3203
3204 #ifdef INT_COAL
3205 if (coalesced) {
3206 /* go to the next status in the status buffer */
3207 ++pcs;
3208 #ifdef GDTH_STATISTICS
3209 ++act_int_coal;
3210 if (act_int_coal > max_int_coal) {
3211 max_int_coal = act_int_coal;
3212 printk("GDT: max_int_coal = %d\n",(ushort)max_int_coal);
3213 }
3214 #endif
3215 /* see if there is another status */
3216 if (pcs->status == 0)
3217 /* Stop the coalesce loop */
3218 next = FALSE;
3219 }
3220 } while (next);
3221
3222 /* coalescing only for new GDT_PCIMPR controllers available */
3223 if (ha->type == GDT_PCIMPR && coalesced) {
3224 writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
3225 writeb(0, &dp6m_ptr->i960r.sema1_reg);
3226 }
3227 #endif
3228
3229 gdth_next(ha);
3230 return IRQ_HANDLED;
3231 }
3232
3233 static irqreturn_t gdth_interrupt(int irq, void *dev_id)
3234 {
3235 gdth_ha_str *ha = dev_id;
3236
3237 return __gdth_interrupt(ha, false, NULL);
3238 }
3239
3240 static int gdth_sync_event(gdth_ha_str *ha, int service, unchar index,
3241 Scsi_Cmnd *scp)
3242 {
3243 gdth_msg_str *msg;
3244 gdth_cmd_str *cmdp;
3245 unchar b, t;
3246 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
3247
3248 cmdp = ha->pccb;
3249 TRACE(("gdth_sync_event() serv %d status %d\n",
3250 service,ha->status));
3251
3252 if (service == SCREENSERVICE) {
3253 msg = ha->pmsg;
3254 TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
3255 msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
3256 if (msg->msg_len > MSGLEN+1)
3257 msg->msg_len = MSGLEN+1;
3258 if (msg->msg_len)
3259 if (!(msg->msg_answer && msg->msg_ext)) {
3260 msg->msg_text[msg->msg_len] = '\0';
3261 printk("%s",msg->msg_text);
3262 }
3263
3264 if (msg->msg_ext && !msg->msg_answer) {
3265 while (gdth_test_busy(ha))
3266 gdth_delay(0);
3267 cmdp->Service = SCREENSERVICE;
3268 cmdp->RequestBuffer = SCREEN_CMND;
3269 gdth_get_cmd_index(ha);
3270 gdth_set_sema0(ha);
3271 cmdp->OpCode = GDT_READ;
3272 cmdp->BoardNode = LOCALBOARD;
3273 cmdp->u.screen.reserved = 0;
3274 cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
3275 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3276 ha->cmd_offs_dpmem = 0;
3277 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3278 + sizeof(ulong64);
3279 ha->cmd_cnt = 0;
3280 gdth_copy_command(ha);
3281 gdth_release_event(ha);
3282 return 0;
3283 }
3284
3285 if (msg->msg_answer && msg->msg_alen) {
3286 /* default answers (getchar() not possible) */
3287 if (msg->msg_alen == 1) {
3288 msg->msg_alen = 0;
3289 msg->msg_len = 1;
3290 msg->msg_text[0] = 0;
3291 } else {
3292 msg->msg_alen -= 2;
3293 msg->msg_len = 2;
3294 msg->msg_text[0] = 1;
3295 msg->msg_text[1] = 0;
3296 }
3297 msg->msg_ext = 0;
3298 msg->msg_answer = 0;
3299 while (gdth_test_busy(ha))
3300 gdth_delay(0);
3301 cmdp->Service = SCREENSERVICE;
3302 cmdp->RequestBuffer = SCREEN_CMND;
3303 gdth_get_cmd_index(ha);
3304 gdth_set_sema0(ha);
3305 cmdp->OpCode = GDT_WRITE;
3306 cmdp->BoardNode = LOCALBOARD;
3307 cmdp->u.screen.reserved = 0;
3308 cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
3309 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3310 ha->cmd_offs_dpmem = 0;
3311 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3312 + sizeof(ulong64);
3313 ha->cmd_cnt = 0;
3314 gdth_copy_command(ha);
3315 gdth_release_event(ha);
3316 return 0;
3317 }
3318 printk("\n");
3319
3320 } else {
3321 b = scp->device->channel;
3322 t = scp->device->id;
3323 if (cmndinfo->OpCode == -1 && b != ha->virt_bus) {
3324 ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
3325 }
3326 /* cache or raw service */
3327 if (ha->status == S_BSY) {
3328 TRACE2(("Controller busy -> retry !\n"));
3329 if (cmndinfo->OpCode == GDT_MOUNT)
3330 cmndinfo->OpCode = GDT_CLUST_INFO;
3331 /* retry */
3332 return 2;
3333 }
3334 if (scsi_bufflen(scp))
3335 pci_unmap_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
3336 cmndinfo->dma_dir);
3337
3338 if (cmndinfo->sense_paddr)
3339 pci_unmap_page(ha->pdev, cmndinfo->sense_paddr, 16,
3340 PCI_DMA_FROMDEVICE);
3341
3342 if (ha->status == S_OK) {
3343 cmndinfo->status = S_OK;
3344 cmndinfo->info = ha->info;
3345 if (cmndinfo->OpCode != -1) {
3346 TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
3347 cmndinfo->OpCode));
3348 /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
3349 if (cmndinfo->OpCode == GDT_CLUST_INFO) {
3350 ha->hdr[t].cluster_type = (unchar)ha->info;
3351 if (!(ha->hdr[t].cluster_type &
3352 CLUSTER_MOUNTED)) {
3353 /* NOT MOUNTED -> MOUNT */
3354 cmndinfo->OpCode = GDT_MOUNT;
3355 if (ha->hdr[t].cluster_type &
3356 CLUSTER_RESERVED) {
3357 /* cluster drive RESERVED (on the other node) */
3358 cmndinfo->phase = -2; /* reservation conflict */
3359 }
3360 } else {
3361 cmndinfo->OpCode = -1;
3362 }
3363 } else {
3364 if (cmndinfo->OpCode == GDT_MOUNT) {
3365 ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
3366 ha->hdr[t].media_changed = TRUE;
3367 } else if (cmndinfo->OpCode == GDT_UNMOUNT) {
3368 ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
3369 ha->hdr[t].media_changed = TRUE;
3370 }
3371 cmndinfo->OpCode = -1;
3372 }
3373 /* retry */
3374 cmndinfo->priority = HIGH_PRI;
3375 return 2;
3376 } else {
3377 /* RESERVE/RELEASE ? */
3378 if (scp->cmnd[0] == RESERVE) {
3379 ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
3380 } else if (scp->cmnd[0] == RELEASE) {
3381 ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
3382 }
3383 scp->result = DID_OK << 16;
3384 scp->sense_buffer[0] = 0;
3385 }
3386 } else {
3387 cmndinfo->status = ha->status;
3388 cmndinfo->info = ha->info;
3389
3390 if (cmndinfo->OpCode != -1) {
3391 TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
3392 cmndinfo->OpCode, ha->status));
3393 if (cmndinfo->OpCode == GDT_SCAN_START ||
3394 cmndinfo->OpCode == GDT_SCAN_END) {
3395 cmndinfo->OpCode = -1;
3396 /* retry */
3397 cmndinfo->priority = HIGH_PRI;
3398 return 2;
3399 }
3400 memset((char*)scp->sense_buffer,0,16);
3401 scp->sense_buffer[0] = 0x70;
3402 scp->sense_buffer[2] = NOT_READY;
3403 scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
3404 } else if (service == CACHESERVICE) {
3405 if (ha->status == S_CACHE_UNKNOWN &&
3406 (ha->hdr[t].cluster_type &
3407 CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
3408 /* bus reset -> force GDT_CLUST_INFO */
3409 ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
3410 }
3411 memset((char*)scp->sense_buffer,0,16);
3412 if (ha->status == (ushort)S_CACHE_RESERV) {
3413 scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
3414 } else {
3415 scp->sense_buffer[0] = 0x70;
3416 scp->sense_buffer[2] = NOT_READY;
3417 scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
3418 }
3419 if (!cmndinfo->internal_command) {
3420 ha->dvr.size = sizeof(ha->dvr.eu.sync);
3421 ha->dvr.eu.sync.ionode = ha->hanum;
3422 ha->dvr.eu.sync.service = service;
3423 ha->dvr.eu.sync.status = ha->status;
3424 ha->dvr.eu.sync.info = ha->info;
3425 ha->dvr.eu.sync.hostdrive = t;
3426 if (ha->status >= 0x8000)
3427 gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
3428 else
3429 gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
3430 }
3431 } else {
3432 /* sense buffer filled from controller firmware (DMA) */
3433 if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
3434 scp->result = DID_BAD_TARGET << 16;
3435 } else {
3436 scp->result = (DID_OK << 16) | ha->info;
3437 }
3438 }
3439 }
3440 if (!cmndinfo->wait_for_completion)
3441 cmndinfo->wait_for_completion++;
3442 else
3443 return 1;
3444 }
3445
3446 return 0;
3447 }
3448
3449 static char *async_cache_tab[] = {
3450 /* 0*/ "\011\000\002\002\002\004\002\006\004"
3451 "GDT HA %u, service %u, async. status %u/%lu unknown",
3452 /* 1*/ "\011\000\002\002\002\004\002\006\004"
3453 "GDT HA %u, service %u, async. status %u/%lu unknown",
3454 /* 2*/ "\005\000\002\006\004"
3455 "GDT HA %u, Host Drive %lu not ready",
3456 /* 3*/ "\005\000\002\006\004"
3457 "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
3458 /* 4*/ "\005\000\002\006\004"
3459 "GDT HA %u, mirror update on Host Drive %lu failed",
3460 /* 5*/ "\005\000\002\006\004"
3461 "GDT HA %u, Mirror Drive %lu failed",
3462 /* 6*/ "\005\000\002\006\004"
3463 "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
3464 /* 7*/ "\005\000\002\006\004"
3465 "GDT HA %u, Host Drive %lu write protected",
3466 /* 8*/ "\005\000\002\006\004"
3467 "GDT HA %u, media changed in Host Drive %lu",
3468 /* 9*/ "\005\000\002\006\004"
3469 "GDT HA %u, Host Drive %lu is offline",
3470 /*10*/ "\005\000\002\006\004"
3471 "GDT HA %u, media change of Mirror Drive %lu",
3472 /*11*/ "\005\000\002\006\004"
3473 "GDT HA %u, Mirror Drive %lu is write protected",
3474 /*12*/ "\005\000\002\006\004"
3475 "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
3476 /*13*/ "\007\000\002\006\002\010\002"
3477 "GDT HA %u, Array Drive %u: Cache Drive %u failed",
3478 /*14*/ "\005\000\002\006\002"
3479 "GDT HA %u, Array Drive %u: FAIL state entered",
3480 /*15*/ "\005\000\002\006\002"
3481 "GDT HA %u, Array Drive %u: error",
3482 /*16*/ "\007\000\002\006\002\010\002"
3483 "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
3484 /*17*/ "\005\000\002\006\002"
3485 "GDT HA %u, Array Drive %u: parity build failed",
3486 /*18*/ "\005\000\002\006\002"
3487 "GDT HA %u, Array Drive %u: drive rebuild failed",
3488 /*19*/ "\005\000\002\010\002"
3489 "GDT HA %u, Test of Hot Fix %u failed",
3490 /*20*/ "\005\000\002\006\002"
3491 "GDT HA %u, Array Drive %u: drive build finished successfully",
3492 /*21*/ "\005\000\002\006\002"
3493 "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
3494 /*22*/ "\007\000\002\006\002\010\002"
3495 "GDT HA %u, Array Drive %u: Hot Fix %u activated",
3496 /*23*/ "\005\000\002\006\002"
3497 "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
3498 /*24*/ "\005\000\002\010\002"
3499 "GDT HA %u, mirror update on Cache Drive %u completed",
3500 /*25*/ "\005\000\002\010\002"
3501 "GDT HA %u, mirror update on Cache Drive %lu failed",
3502 /*26*/ "\005\000\002\006\002"
3503 "GDT HA %u, Array Drive %u: drive rebuild started",
3504 /*27*/ "\005\000\002\012\001"
3505 "GDT HA %u, Fault bus %u: SHELF OK detected",
3506 /*28*/ "\005\000\002\012\001"
3507 "GDT HA %u, Fault bus %u: SHELF not OK detected",
3508 /*29*/ "\007\000\002\012\001\013\001"
3509 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
3510 /*30*/ "\007\000\002\012\001\013\001"
3511 "GDT HA %u, Fault bus %u, ID %u: new disk detected",
3512 /*31*/ "\007\000\002\012\001\013\001"
3513 "GDT HA %u, Fault bus %u, ID %u: old disk detected",
3514 /*32*/ "\007\000\002\012\001\013\001"
3515 "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
3516 /*33*/ "\007\000\002\012\001\013\001"
3517 "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
3518 /*34*/ "\011\000\002\012\001\013\001\006\004"
3519 "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
3520 /*35*/ "\007\000\002\012\001\013\001"
3521 "GDT HA %u, Fault bus %u, ID %u: disk write protected",
3522 /*36*/ "\007\000\002\012\001\013\001"
3523 "GDT HA %u, Fault bus %u, ID %u: disk not available",
3524 /*37*/ "\007\000\002\012\001\006\004"
3525 "GDT HA %u, Fault bus %u: swap detected (%lu)",
3526 /*38*/ "\007\000\002\012\001\013\001"
3527 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
3528 /*39*/ "\007\000\002\012\001\013\001"
3529 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
3530 /*40*/ "\007\000\002\012\001\013\001"
3531 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
3532 /*41*/ "\007\000\002\012\001\013\001"
3533 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
3534 /*42*/ "\005\000\002\006\002"
3535 "GDT HA %u, Array Drive %u: drive build started",
3536 /*43*/ "\003\000\002"
3537 "GDT HA %u, DRAM parity error detected",
3538 /*44*/ "\005\000\002\006\002"
3539 "GDT HA %u, Mirror Drive %u: update started",
3540 /*45*/ "\007\000\002\006\002\010\002"
3541 "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
3542 /*46*/ "\005\000\002\006\002"
3543 "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
3544 /*47*/ "\005\000\002\006\002"
3545 "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
3546 /*48*/ "\005\000\002\006\002"
3547 "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
3548 /*49*/ "\005\000\002\006\002"
3549 "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
3550 /*50*/ "\007\000\002\012\001\013\001"
3551 "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
3552 /*51*/ "\005\000\002\006\002"
3553 "GDT HA %u, Array Drive %u: expand started",
3554 /*52*/ "\005\000\002\006\002"
3555 "GDT HA %u, Array Drive %u: expand finished successfully",
3556 /*53*/ "\005\000\002\006\002"
3557 "GDT HA %u, Array Drive %u: expand failed",
3558 /*54*/ "\003\000\002"
3559 "GDT HA %u, CPU temperature critical",
3560 /*55*/ "\003\000\002"
3561 "GDT HA %u, CPU temperature OK",
3562 /*56*/ "\005\000\002\006\004"
3563 "GDT HA %u, Host drive %lu created",
3564 /*57*/ "\005\000\002\006\002"
3565 "GDT HA %u, Array Drive %u: expand restarted",
3566 /*58*/ "\005\000\002\006\002"
3567 "GDT HA %u, Array Drive %u: expand stopped",
3568 /*59*/ "\005\000\002\010\002"
3569 "GDT HA %u, Mirror Drive %u: drive build quited",
3570 /*60*/ "\005\000\002\006\002"
3571 "GDT HA %u, Array Drive %u: parity build quited",
3572 /*61*/ "\005\000\002\006\002"
3573 "GDT HA %u, Array Drive %u: drive rebuild quited",
3574 /*62*/ "\005\000\002\006\002"
3575 "GDT HA %u, Array Drive %u: parity verify started",
3576 /*63*/ "\005\000\002\006\002"
3577 "GDT HA %u, Array Drive %u: parity verify done",
3578 /*64*/ "\005\000\002\006\002"
3579 "GDT HA %u, Array Drive %u: parity verify failed",
3580 /*65*/ "\005\000\002\006\002"
3581 "GDT HA %u, Array Drive %u: parity error detected",
3582 /*66*/ "\005\000\002\006\002"
3583 "GDT HA %u, Array Drive %u: parity verify quited",
3584 /*67*/ "\005\000\002\006\002"
3585 "GDT HA %u, Host Drive %u reserved",
3586 /*68*/ "\005\000\002\006\002"
3587 "GDT HA %u, Host Drive %u mounted and released",
3588 /*69*/ "\005\000\002\006\002"
3589 "GDT HA %u, Host Drive %u released",
3590 /*70*/ "\003\000\002"
3591 "GDT HA %u, DRAM error detected and corrected with ECC",
3592 /*71*/ "\003\000\002"
3593 "GDT HA %u, Uncorrectable DRAM error detected with ECC",
3594 /*72*/ "\011\000\002\012\001\013\001\014\001"
3595 "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
3596 /*73*/ "\005\000\002\006\002"
3597 "GDT HA %u, Host drive %u resetted locally",
3598 /*74*/ "\005\000\002\006\002"
3599 "GDT HA %u, Host drive %u resetted remotely",
3600 /*75*/ "\003\000\002"
3601 "GDT HA %u, async. status 75 unknown",
3602 };
3603
3604
3605 static int gdth_async_event(gdth_ha_str *ha)
3606 {
3607 gdth_cmd_str *cmdp;
3608 int cmd_index;
3609
3610 cmdp= ha->pccb;
3611 TRACE2(("gdth_async_event() ha %d serv %d\n",
3612 ha->hanum, ha->service));
3613
3614 if (ha->service == SCREENSERVICE) {
3615 if (ha->status == MSG_REQUEST) {
3616 while (gdth_test_busy(ha))
3617 gdth_delay(0);
3618 cmdp->Service = SCREENSERVICE;
3619 cmdp->RequestBuffer = SCREEN_CMND;
3620 cmd_index = gdth_get_cmd_index(ha);
3621 gdth_set_sema0(ha);
3622 cmdp->OpCode = GDT_READ;
3623 cmdp->BoardNode = LOCALBOARD;
3624 cmdp->u.screen.reserved = 0;
3625 cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
3626 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3627 ha->cmd_offs_dpmem = 0;
3628 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3629 + sizeof(ulong64);
3630 ha->cmd_cnt = 0;
3631 gdth_copy_command(ha);
3632 if (ha->type == GDT_EISA)
3633 printk("[EISA slot %d] ",(ushort)ha->brd_phys);
3634 else if (ha->type == GDT_ISA)
3635 printk("[DPMEM 0x%4X] ",(ushort)ha->brd_phys);
3636 else
3637 printk("[PCI %d/%d] ",(ushort)(ha->brd_phys>>8),
3638 (ushort)((ha->brd_phys>>3)&0x1f));
3639 gdth_release_event(ha);
3640 }
3641
3642 } else {
3643 if (ha->type == GDT_PCIMPR &&
3644 (ha->fw_vers & 0xff) >= 0x1a) {
3645 ha->dvr.size = 0;
3646 ha->dvr.eu.async.ionode = ha->hanum;
3647 ha->dvr.eu.async.status = ha->status;
3648 /* severity and event_string already set! */
3649 } else {
3650 ha->dvr.size = sizeof(ha->dvr.eu.async);
3651 ha->dvr.eu.async.ionode = ha->hanum;
3652 ha->dvr.eu.async.service = ha->service;
3653 ha->dvr.eu.async.status = ha->status;
3654 ha->dvr.eu.async.info = ha->info;
3655 *(ulong32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
3656 }
3657 gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
3658 gdth_log_event( &ha->dvr, NULL );
3659
3660 /* new host drive from expand? */
3661 if (ha->service == CACHESERVICE && ha->status == 56) {
3662 TRACE2(("gdth_async_event(): new host drive %d created\n",
3663 (ushort)ha->info));
3664 /* gdth_analyse_hdrive(hanum, (ushort)ha->info); */
3665 }
3666 }
3667 return 1;
3668 }
3669
3670 static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
3671 {
3672 gdth_stackframe stack;
3673 char *f = NULL;
3674 int i,j;
3675
3676 TRACE2(("gdth_log_event()\n"));
3677 if (dvr->size == 0) {
3678 if (buffer == NULL) {
3679 printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
3680 } else {
3681 sprintf(buffer,"Adapter %d: %s\n",
3682 dvr->eu.async.ionode,dvr->event_string);
3683 }
3684 } else if (dvr->eu.async.service == CACHESERVICE &&
3685 INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
3686 TRACE2(("GDT: Async. event cache service, event no.: %d\n",
3687 dvr->eu.async.status));
3688
3689 f = async_cache_tab[dvr->eu.async.status];
3690
3691 /* i: parameter to push, j: stack element to fill */
3692 for (j=0,i=1; i < f[0]; i+=2) {
3693 switch (f[i+1]) {
3694 case 4:
3695 stack.b[j++] = *(ulong32*)&dvr->eu.stream[(int)f[i]];
3696 break;
3697 case 2:
3698 stack.b[j++] = *(ushort*)&dvr->eu.stream[(int)f[i]];
3699 break;
3700 case 1:
3701 stack.b[j++] = *(unchar*)&dvr->eu.stream[(int)f[i]];
3702 break;
3703 default:
3704 break;
3705 }
3706 }
3707
3708 if (buffer == NULL) {
3709 printk(&f[(int)f[0]],stack);
3710 printk("\n");
3711 } else {
3712 sprintf(buffer,&f[(int)f[0]],stack);
3713 }
3714
3715 } else {
3716 if (buffer == NULL) {
3717 printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
3718 dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
3719 } else {
3720 sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
3721 dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
3722 }
3723 }
3724 }
3725
3726 #ifdef GDTH_STATISTICS
3727 static void gdth_timeout(ulong data)
3728 {
3729 ulong32 i;
3730 Scsi_Cmnd *nscp;
3731 gdth_ha_str *ha;
3732 ulong flags;
3733
3734 BUG_ON(list_empty(&gdth_instances));
3735
3736 ha = list_first_entry(&gdth_instances, gdth_ha_str, list);
3737 spin_lock_irqsave(&ha->smp_lock, flags);
3738
3739 for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
3740 if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
3741 ++act_stats;
3742
3743 for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
3744 ++act_rq;
3745
3746 TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
3747 act_ints, act_ios, act_stats, act_rq));
3748 act_ints = act_ios = 0;
3749
3750 gdth_timer.expires = jiffies + 30 * HZ;
3751 add_timer(&gdth_timer);
3752 spin_unlock_irqrestore(&ha->smp_lock, flags);
3753 }
3754 #endif
3755
3756 static void __init internal_setup(char *str,int *ints)
3757 {
3758 int i, argc;
3759 char *cur_str, *argv;
3760
3761 TRACE2(("internal_setup() str %s ints[0] %d\n",
3762 str ? str:"NULL", ints ? ints[0]:0));
3763
3764 /* read irq[] from ints[] */
3765 if (ints) {
3766 argc = ints[0];
3767 if (argc > 0) {
3768 if (argc > MAXHA)
3769 argc = MAXHA;
3770 for (i = 0; i < argc; ++i)
3771 irq[i] = ints[i+1];
3772 }
3773 }
3774
3775 /* analyse string */
3776 argv = str;
3777 while (argv && (cur_str = strchr(argv, ':'))) {
3778 int val = 0, c = *++cur_str;
3779
3780 if (c == 'n' || c == 'N')
3781 val = 0;
3782 else if (c == 'y' || c == 'Y')
3783 val = 1;
3784 else
3785 val = (int)simple_strtoul(cur_str, NULL, 0);
3786
3787 if (!strncmp(argv, "disable:", 8))
3788 disable = val;
3789 else if (!strncmp(argv, "reserve_mode:", 13))
3790 reserve_mode = val;
3791 else if (!strncmp(argv, "reverse_scan:", 13))
3792 reverse_scan = val;
3793 else if (!strncmp(argv, "hdr_channel:", 12))
3794 hdr_channel = val;
3795 else if (!strncmp(argv, "max_ids:", 8))
3796 max_ids = val;
3797 else if (!strncmp(argv, "rescan:", 7))
3798 rescan = val;
3799 else if (!strncmp(argv, "shared_access:", 14))
3800 shared_access = val;
3801 else if (!strncmp(argv, "probe_eisa_isa:", 15))
3802 probe_eisa_isa = val;
3803 else if (!strncmp(argv, "reserve_list:", 13)) {
3804 reserve_list[0] = val;
3805 for (i = 1; i < MAX_RES_ARGS; i++) {
3806 cur_str = strchr(cur_str, ',');
3807 if (!cur_str)
3808 break;
3809 if (!isdigit((int)*++cur_str)) {
3810 --cur_str;
3811 break;
3812 }
3813 reserve_list[i] =
3814 (int)simple_strtoul(cur_str, NULL, 0);
3815 }
3816 if (!cur_str)
3817 break;
3818 argv = ++cur_str;
3819 continue;
3820 }
3821
3822 if ((argv = strchr(argv, ',')))
3823 ++argv;
3824 }
3825 }
3826
3827 int __init option_setup(char *str)
3828 {
3829 int ints[MAXHA];
3830 char *cur = str;
3831 int i = 1;
3832
3833 TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
3834
3835 while (cur && isdigit(*cur) && i <= MAXHA) {
3836 ints[i++] = simple_strtoul(cur, NULL, 0);
3837 if ((cur = strchr(cur, ',')) != NULL) cur++;
3838 }
3839
3840 ints[0] = i - 1;
3841 internal_setup(cur, ints);
3842 return 1;
3843 }
3844
3845 static const char *gdth_ctr_name(gdth_ha_str *ha)
3846 {
3847 TRACE2(("gdth_ctr_name()\n"));
3848
3849 if (ha->type == GDT_EISA) {
3850 switch (ha->stype) {
3851 case GDT3_ID:
3852 return("GDT3000/3020");
3853 case GDT3A_ID:
3854 return("GDT3000A/3020A/3050A");
3855 case GDT3B_ID:
3856 return("GDT3000B/3010A");
3857 }
3858 } else if (ha->type == GDT_ISA) {
3859 return("GDT2000/2020");
3860 } else if (ha->type == GDT_PCI) {
3861 switch (ha->pdev->device) {
3862 case PCI_DEVICE_ID_VORTEX_GDT60x0:
3863 return("GDT6000/6020/6050");
3864 case PCI_DEVICE_ID_VORTEX_GDT6000B:
3865 return("GDT6000B/6010");
3866 }
3867 }
3868 /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
3869
3870 return("");
3871 }
3872
3873 static const char *gdth_info(struct Scsi_Host *shp)
3874 {
3875 gdth_ha_str *ha = shost_priv(shp);
3876
3877 TRACE2(("gdth_info()\n"));
3878 return ((const char *)ha->binfo.type_string);
3879 }
3880
3881 static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
3882 {
3883 gdth_ha_str *ha = shost_priv(scp->device->host);
3884 int i;
3885 ulong flags;
3886 Scsi_Cmnd *cmnd;
3887 unchar b;
3888
3889 TRACE2(("gdth_eh_bus_reset()\n"));
3890
3891 b = scp->device->channel;
3892
3893 /* clear command tab */
3894 spin_lock_irqsave(&ha->smp_lock, flags);
3895 for (i = 0; i < GDTH_MAXCMDS; ++i) {
3896 cmnd = ha->cmd_tab[i].cmnd;
3897 if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
3898 ha->cmd_tab[i].cmnd = UNUSED_CMND;
3899 }
3900 spin_unlock_irqrestore(&ha->smp_lock, flags);
3901
3902 if (b == ha->virt_bus) {
3903 /* host drives */
3904 for (i = 0; i < MAX_HDRIVES; ++i) {
3905 if (ha->hdr[i].present) {
3906 spin_lock_irqsave(&ha->smp_lock, flags);
3907 gdth_polling = TRUE;
3908 while (gdth_test_busy(ha))
3909 gdth_delay(0);
3910 if (gdth_internal_cmd(ha, CACHESERVICE,
3911 GDT_CLUST_RESET, i, 0, 0))
3912 ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
3913 gdth_polling = FALSE;
3914 spin_unlock_irqrestore(&ha->smp_lock, flags);
3915 }
3916 }
3917 } else {
3918 /* raw devices */
3919 spin_lock_irqsave(&ha->smp_lock, flags);
3920 for (i = 0; i < MAXID; ++i)
3921 ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
3922 gdth_polling = TRUE;
3923 while (gdth_test_busy(ha))
3924 gdth_delay(0);
3925 gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESET_BUS,
3926 BUS_L2P(ha,b), 0, 0);
3927 gdth_polling = FALSE;
3928 spin_unlock_irqrestore(&ha->smp_lock, flags);
3929 }
3930 return SUCCESS;
3931 }
3932
3933 static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
3934 {
3935 unchar b, t;
3936 gdth_ha_str *ha = shost_priv(sdev->host);
3937 struct scsi_device *sd;
3938 unsigned capacity;
3939
3940 sd = sdev;
3941 capacity = cap;
3942 b = sd->channel;
3943 t = sd->id;
3944 TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", ha->hanum, b, t));
3945
3946 if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
3947 /* raw device or host drive without mapping information */
3948 TRACE2(("Evaluate mapping\n"));
3949 gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
3950 } else {
3951 ip[0] = ha->hdr[t].heads;
3952 ip[1] = ha->hdr[t].secs;
3953 ip[2] = capacity / ip[0] / ip[1];
3954 }
3955
3956 TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
3957 ip[0],ip[1],ip[2]));
3958 return 0;
3959 }
3960
3961
3962 static int gdth_queuecommand(struct scsi_cmnd *scp,
3963 void (*done)(struct scsi_cmnd *))
3964 {
3965 gdth_ha_str *ha = shost_priv(scp->device->host);
3966 struct gdth_cmndinfo *cmndinfo;
3967
3968 TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
3969
3970 cmndinfo = gdth_get_cmndinfo(ha);
3971 BUG_ON(!cmndinfo);
3972
3973 scp->scsi_done = done;
3974 gdth_update_timeout(scp, scp->timeout_per_command * 6);
3975 cmndinfo->priority = DEFAULT_PRI;
3976
3977 return __gdth_queuecommand(ha, scp, cmndinfo);
3978 }
3979
3980 static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
3981 struct gdth_cmndinfo *cmndinfo)
3982 {
3983 scp->host_scribble = (unsigned char *)cmndinfo;
3984 cmndinfo->wait_for_completion = 1;
3985 cmndinfo->phase = -1;
3986 cmndinfo->OpCode = -1;
3987
3988 #ifdef GDTH_STATISTICS
3989 ++act_ios;
3990 #endif
3991
3992 gdth_putq(ha, scp, cmndinfo->priority);
3993 gdth_next(ha);
3994 return 0;
3995 }
3996
3997
3998 static int gdth_open(struct inode *inode, struct file *filep)
3999 {
4000 gdth_ha_str *ha;
4001
4002 list_for_each_entry(ha, &gdth_instances, list) {
4003 if (!ha->sdev)
4004 ha->sdev = scsi_get_host_dev(ha->shost);
4005 }
4006
4007 TRACE(("gdth_open()\n"));
4008 return 0;
4009 }
4010
4011 static int gdth_close(struct inode *inode, struct file *filep)
4012 {
4013 TRACE(("gdth_close()\n"));
4014 return 0;
4015 }
4016
4017 static int ioc_event(void __user *arg)
4018 {
4019 gdth_ioctl_event evt;
4020 gdth_ha_str *ha;
4021 ulong flags;
4022
4023 if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)))
4024 return -EFAULT;
4025 ha = gdth_find_ha(evt.ionode);
4026 if (!ha)
4027 return -EFAULT;
4028
4029 if (evt.erase == 0xff) {
4030 if (evt.event.event_source == ES_TEST)
4031 evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
4032 else if (evt.event.event_source == ES_DRIVER)
4033 evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
4034 else if (evt.event.event_source == ES_SYNC)
4035 evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
4036 else
4037 evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
4038 spin_lock_irqsave(&ha->smp_lock, flags);
4039 gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
4040 &evt.event.event_data);
4041 spin_unlock_irqrestore(&ha->smp_lock, flags);
4042 } else if (evt.erase == 0xfe) {
4043 gdth_clear_events();
4044 } else if (evt.erase == 0) {
4045 evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
4046 } else {
4047 gdth_readapp_event(ha, evt.erase, &evt.event);
4048 }
4049 if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
4050 return -EFAULT;
4051 return 0;
4052 }
4053
4054 static int ioc_lockdrv(void __user *arg)
4055 {
4056 gdth_ioctl_lockdrv ldrv;
4057 unchar i, j;
4058 ulong flags;
4059 gdth_ha_str *ha;
4060
4061 if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)))
4062 return -EFAULT;
4063 ha = gdth_find_ha(ldrv.ionode);
4064 if (!ha)
4065 return -EFAULT;
4066
4067 for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
4068 j = ldrv.drives[i];
4069 if (j >= MAX_HDRIVES || !ha->hdr[j].present)
4070 continue;
4071 if (ldrv.lock) {
4072 spin_lock_irqsave(&ha->smp_lock, flags);
4073 ha->hdr[j].lock = 1;
4074 spin_unlock_irqrestore(&ha->smp_lock, flags);
4075 gdth_wait_completion(ha, ha->bus_cnt, j);
4076 gdth_stop_timeout(ha, ha->bus_cnt, j);
4077 } else {
4078 spin_lock_irqsave(&ha->smp_lock, flags);
4079 ha->hdr[j].lock = 0;
4080 spin_unlock_irqrestore(&ha->smp_lock, flags);
4081 gdth_start_timeout(ha, ha->bus_cnt, j);
4082 gdth_next(ha);
4083 }
4084 }
4085 return 0;
4086 }
4087
4088 static int ioc_resetdrv(void __user *arg, char *cmnd)
4089 {
4090 gdth_ioctl_reset res;
4091 gdth_cmd_str cmd;
4092 gdth_ha_str *ha;
4093 int rval;
4094
4095 if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
4096 res.number >= MAX_HDRIVES)
4097 return -EFAULT;
4098 ha = gdth_find_ha(res.ionode);
4099 if (!ha)
4100 return -EFAULT;
4101
4102 if (!ha->hdr[res.number].present)
4103 return 0;
4104 memset(&cmd, 0, sizeof(gdth_cmd_str));
4105 cmd.Service = CACHESERVICE;
4106 cmd.OpCode = GDT_CLUST_RESET;
4107 if (ha->cache_feat & GDT_64BIT)
4108 cmd.u.cache64.DeviceNo = res.number;
4109 else
4110 cmd.u.cache.DeviceNo = res.number;
4111
4112 rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
4113 if (rval < 0)
4114 return rval;
4115 res.status = rval;
4116
4117 if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
4118 return -EFAULT;
4119 return 0;
4120 }
4121
4122 static int ioc_general(void __user *arg, char *cmnd)
4123 {
4124 gdth_ioctl_general gen;
4125 char *buf = NULL;
4126 ulong64 paddr;
4127 gdth_ha_str *ha;
4128 int rval;
4129
4130 if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)))
4131 return -EFAULT;
4132 ha = gdth_find_ha(gen.ionode);
4133 if (!ha)
4134 return -EFAULT;
4135 if (gen.data_len + gen.sense_len != 0) {
4136 if (!(buf = gdth_ioctl_alloc(ha, gen.data_len + gen.sense_len,
4137 FALSE, &paddr)))
4138 return -EFAULT;
4139 if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
4140 gen.data_len + gen.sense_len)) {
4141 gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
4142 return -EFAULT;
4143 }
4144
4145 if (gen.command.OpCode == GDT_IOCTL) {
4146 gen.command.u.ioctl.p_param = paddr;
4147 } else if (gen.command.Service == CACHESERVICE) {
4148 if (ha->cache_feat & GDT_64BIT) {
4149 /* copy elements from 32-bit IOCTL structure */
4150 gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
4151 gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
4152 gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
4153 /* addresses */
4154 if (ha->cache_feat & SCATTER_GATHER) {
4155 gen.command.u.cache64.DestAddr = (ulong64)-1;
4156 gen.command.u.cache64.sg_canz = 1;
4157 gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
4158 gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
4159 gen.command.u.cache64.sg_lst[1].sg_len = 0;
4160 } else {
4161 gen.command.u.cache64.DestAddr = paddr;
4162 gen.command.u.cache64.sg_canz = 0;
4163 }
4164 } else {
4165 if (ha->cache_feat & SCATTER_GATHER) {
4166 gen.command.u.cache.DestAddr = 0xffffffff;
4167 gen.command.u.cache.sg_canz = 1;
4168 gen.command.u.cache.sg_lst[0].sg_ptr = (ulong32)paddr;
4169 gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
4170 gen.command.u.cache.sg_lst[1].sg_len = 0;
4171 } else {
4172 gen.command.u.cache.DestAddr = paddr;
4173 gen.command.u.cache.sg_canz = 0;
4174 }
4175 }
4176 } else if (gen.command.Service == SCSIRAWSERVICE) {
4177 if (ha->raw_feat & GDT_64BIT) {
4178 /* copy elements from 32-bit IOCTL structure */
4179 char cmd[16];
4180 gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
4181 gen.command.u.raw64.bus = gen.command.u.raw.bus;
4182 gen.command.u.raw64.lun = gen.command.u.raw.lun;
4183 gen.command.u.raw64.target = gen.command.u.raw.target;
4184 memcpy(cmd, gen.command.u.raw.cmd, 16);
4185 memcpy(gen.command.u.raw64.cmd, cmd, 16);
4186 gen.command.u.raw64.clen = gen.command.u.raw.clen;
4187 gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
4188 gen.command.u.raw64.direction = gen.command.u.raw.direction;
4189 /* addresses */
4190 if (ha->raw_feat & SCATTER_GATHER) {
4191 gen.command.u.raw64.sdata = (ulong64)-1;
4192 gen.command.u.raw64.sg_ranz = 1;
4193 gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
4194 gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
4195 gen.command.u.raw64.sg_lst[1].sg_len = 0;
4196 } else {
4197 gen.command.u.raw64.sdata = paddr;
4198 gen.command.u.raw64.sg_ranz = 0;
4199 }
4200 gen.command.u.raw64.sense_data = paddr + gen.data_len;
4201 } else {
4202 if (ha->raw_feat & SCATTER_GATHER) {
4203 gen.command.u.raw.sdata = 0xffffffff;
4204 gen.command.u.raw.sg_ranz = 1;
4205 gen.command.u.raw.sg_lst[0].sg_ptr = (ulong32)paddr;
4206 gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
4207 gen.command.u.raw.sg_lst[1].sg_len = 0;
4208 } else {
4209 gen.command.u.raw.sdata = paddr;
4210 gen.command.u.raw.sg_ranz = 0;
4211 }
4212 gen.command.u.raw.sense_data = (ulong32)paddr + gen.data_len;
4213 }
4214 } else {
4215 gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
4216 return -EFAULT;
4217 }
4218 }
4219
4220 rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
4221 if (rval < 0)
4222 return rval;
4223 gen.status = rval;
4224
4225 if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
4226 gen.data_len + gen.sense_len)) {
4227 gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
4228 return -EFAULT;
4229 }
4230 if (copy_to_user(arg, &gen,
4231 sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
4232 gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
4233 return -EFAULT;
4234 }
4235 gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
4236 return 0;
4237 }
4238
4239 static int ioc_hdrlist(void __user *arg, char *cmnd)
4240 {
4241 gdth_ioctl_rescan *rsc;
4242 gdth_cmd_str *cmd;
4243 gdth_ha_str *ha;
4244 unchar i;
4245 int rc = -ENOMEM;
4246 u32 cluster_type = 0;
4247
4248 rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
4249 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
4250 if (!rsc || !cmd)
4251 goto free_fail;
4252
4253 if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
4254 (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
4255 rc = -EFAULT;
4256 goto free_fail;
4257 }
4258 memset(cmd, 0, sizeof(gdth_cmd_str));
4259
4260 for (i = 0; i < MAX_HDRIVES; ++i) {
4261 if (!ha->hdr[i].present) {
4262 rsc->hdr_list[i].bus = 0xff;
4263 continue;
4264 }
4265 rsc->hdr_list[i].bus = ha->virt_bus;
4266 rsc->hdr_list[i].target = i;
4267 rsc->hdr_list[i].lun = 0;
4268 rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
4269 if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
4270 cmd->Service = CACHESERVICE;
4271 cmd->OpCode = GDT_CLUST_INFO;
4272 if (ha->cache_feat & GDT_64BIT)
4273 cmd->u.cache64.DeviceNo = i;
4274 else
4275 cmd->u.cache.DeviceNo = i;
4276 if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
4277 rsc->hdr_list[i].cluster_type = cluster_type;
4278 }
4279 }
4280
4281 if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
4282 rc = -EFAULT;
4283 else
4284 rc = 0;
4285
4286 free_fail:
4287 kfree(rsc);
4288 kfree(cmd);
4289 return rc;
4290 }
4291
4292 static int ioc_rescan(void __user *arg, char *cmnd)
4293 {
4294 gdth_ioctl_rescan *rsc;
4295 gdth_cmd_str *cmd;
4296 ushort i, status, hdr_cnt;
4297 ulong32 info;
4298 int cyls, hds, secs;
4299 int rc = -ENOMEM;
4300 ulong flags;
4301 gdth_ha_str *ha;
4302
4303 rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
4304 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
4305 if (!cmd || !rsc)
4306 goto free_fail;
4307
4308 if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
4309 (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
4310 rc = -EFAULT;
4311 goto free_fail;
4312 }
4313 memset(cmd, 0, sizeof(gdth_cmd_str));
4314
4315 if (rsc->flag == 0) {
4316 /* old method: re-init. cache service */
4317 cmd->Service = CACHESERVICE;
4318 if (ha->cache_feat & GDT_64BIT) {
4319 cmd->OpCode = GDT_X_INIT_HOST;
4320 cmd->u.cache64.DeviceNo = LINUX_OS;
4321 } else {
4322 cmd->OpCode = GDT_INIT;
4323 cmd->u.cache.DeviceNo = LINUX_OS;
4324 }
4325
4326 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4327 i = 0;
4328 hdr_cnt = (status == S_OK ? (ushort)info : 0);
4329 } else {
4330 i = rsc->hdr_no;
4331 hdr_cnt = i + 1;
4332 }
4333
4334 for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
4335 cmd->Service = CACHESERVICE;
4336 cmd->OpCode = GDT_INFO;
4337 if (ha->cache_feat & GDT_64BIT)
4338 cmd->u.cache64.DeviceNo = i;
4339 else
4340 cmd->u.cache.DeviceNo = i;
4341
4342 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4343
4344 spin_lock_irqsave(&ha->smp_lock, flags);
4345 rsc->hdr_list[i].bus = ha->virt_bus;
4346 rsc->hdr_list[i].target = i;
4347 rsc->hdr_list[i].lun = 0;
4348 if (status != S_OK) {
4349 ha->hdr[i].present = FALSE;
4350 } else {
4351 ha->hdr[i].present = TRUE;
4352 ha->hdr[i].size = info;
4353 /* evaluate mapping */
4354 ha->hdr[i].size &= ~SECS32;
4355 gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
4356 ha->hdr[i].heads = hds;
4357 ha->hdr[i].secs = secs;
4358 /* round size */
4359 ha->hdr[i].size = cyls * hds * secs;
4360 }
4361 spin_unlock_irqrestore(&ha->smp_lock, flags);
4362 if (status != S_OK)
4363 continue;
4364
4365 /* extended info, if GDT_64BIT, for drives > 2 TB */
4366 /* but we need ha->info2, not yet stored in scp->SCp */
4367
4368 /* devtype, cluster info, R/W attribs */
4369 cmd->Service = CACHESERVICE;
4370 cmd->OpCode = GDT_DEVTYPE;
4371 if (ha->cache_feat & GDT_64BIT)
4372 cmd->u.cache64.DeviceNo = i;
4373 else
4374 cmd->u.cache.DeviceNo = i;
4375
4376 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4377
4378 spin_lock_irqsave(&ha->smp_lock, flags);
4379 ha->hdr[i].devtype = (status == S_OK ? (ushort)info : 0);
4380 spin_unlock_irqrestore(&ha->smp_lock, flags);
4381
4382 cmd->Service = CACHESERVICE;
4383 cmd->OpCode = GDT_CLUST_INFO;
4384 if (ha->cache_feat & GDT_64BIT)
4385 cmd->u.cache64.DeviceNo = i;
4386 else
4387 cmd->u.cache.DeviceNo = i;
4388
4389 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4390
4391 spin_lock_irqsave(&ha->smp_lock, flags);
4392 ha->hdr[i].cluster_type =
4393 ((status == S_OK && !shared_access) ? (ushort)info : 0);
4394 spin_unlock_irqrestore(&ha->smp_lock, flags);
4395 rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
4396
4397 cmd->Service = CACHESERVICE;
4398 cmd->OpCode = GDT_RW_ATTRIBS;
4399 if (ha->cache_feat & GDT_64BIT)
4400 cmd->u.cache64.DeviceNo = i;
4401 else
4402 cmd->u.cache.DeviceNo = i;
4403
4404 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4405
4406 spin_lock_irqsave(&ha->smp_lock, flags);
4407 ha->hdr[i].rw_attribs = (status == S_OK ? (ushort)info : 0);
4408 spin_unlock_irqrestore(&ha->smp_lock, flags);
4409 }
4410
4411 if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
4412 rc = -EFAULT;
4413 else
4414 rc = 0;
4415
4416 free_fail:
4417 kfree(rsc);
4418 kfree(cmd);
4419 return rc;
4420 }
4421
4422 static int gdth_ioctl(struct inode *inode, struct file *filep,
4423 unsigned int cmd, unsigned long arg)
4424 {
4425 gdth_ha_str *ha;
4426 Scsi_Cmnd *scp;
4427 ulong flags;
4428 char cmnd[MAX_COMMAND_SIZE];
4429 void __user *argp = (void __user *)arg;
4430
4431 memset(cmnd, 0xff, 12);
4432
4433 TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
4434
4435 switch (cmd) {
4436 case GDTIOCTL_CTRCNT:
4437 {
4438 int cnt = gdth_ctr_count;
4439 if (put_user(cnt, (int __user *)argp))
4440 return -EFAULT;
4441 break;
4442 }
4443
4444 case GDTIOCTL_DRVERS:
4445 {
4446 int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
4447 if (put_user(ver, (int __user *)argp))
4448 return -EFAULT;
4449 break;
4450 }
4451
4452 case GDTIOCTL_OSVERS:
4453 {
4454 gdth_ioctl_osvers osv;
4455
4456 osv.version = (unchar)(LINUX_VERSION_CODE >> 16);
4457 osv.subversion = (unchar)(LINUX_VERSION_CODE >> 8);
4458 osv.revision = (ushort)(LINUX_VERSION_CODE & 0xff);
4459 if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
4460 return -EFAULT;
4461 break;
4462 }
4463
4464 case GDTIOCTL_CTRTYPE:
4465 {
4466 gdth_ioctl_ctrtype ctrt;
4467
4468 if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
4469 (NULL == (ha = gdth_find_ha(ctrt.ionode))))
4470 return -EFAULT;
4471
4472 if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
4473 ctrt.type = (unchar)((ha->stype>>20) - 0x10);
4474 } else {
4475 if (ha->type != GDT_PCIMPR) {
4476 ctrt.type = (unchar)((ha->stype<<4) + 6);
4477 } else {
4478 ctrt.type =
4479 (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
4480 if (ha->stype >= 0x300)
4481 ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device;
4482 else
4483 ctrt.ext_type = 0x6000 | ha->stype;
4484 }
4485 ctrt.device_id = ha->pdev->device;
4486 ctrt.sub_device_id = ha->pdev->subsystem_device;
4487 }
4488 ctrt.info = ha->brd_phys;
4489 ctrt.oem_id = ha->oem_id;
4490 if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
4491 return -EFAULT;
4492 break;
4493 }
4494
4495 case GDTIOCTL_GENERAL:
4496 return ioc_general(argp, cmnd);
4497
4498 case GDTIOCTL_EVENT:
4499 return ioc_event(argp);
4500
4501 case GDTIOCTL_LOCKDRV:
4502 return ioc_lockdrv(argp);
4503
4504 case GDTIOCTL_LOCKCHN:
4505 {
4506 gdth_ioctl_lockchn lchn;
4507 unchar i, j;
4508
4509 if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
4510 (NULL == (ha = gdth_find_ha(lchn.ionode))))
4511 return -EFAULT;
4512
4513 i = lchn.channel;
4514 if (i < ha->bus_cnt) {
4515 if (lchn.lock) {
4516 spin_lock_irqsave(&ha->smp_lock, flags);
4517 ha->raw[i].lock = 1;
4518 spin_unlock_irqrestore(&ha->smp_lock, flags);
4519 for (j = 0; j < ha->tid_cnt; ++j) {
4520 gdth_wait_completion(ha, i, j);
4521 gdth_stop_timeout(ha, i, j);
4522 }
4523 } else {
4524 spin_lock_irqsave(&ha->smp_lock, flags);
4525 ha->raw[i].lock = 0;
4526 spin_unlock_irqrestore(&ha->smp_lock, flags);
4527 for (j = 0; j < ha->tid_cnt; ++j) {
4528 gdth_start_timeout(ha, i, j);
4529 gdth_next(ha);
4530 }
4531 }
4532 }
4533 break;
4534 }
4535
4536 case GDTIOCTL_RESCAN:
4537 return ioc_rescan(argp, cmnd);
4538
4539 case GDTIOCTL_HDRLIST:
4540 return ioc_hdrlist(argp, cmnd);
4541
4542 case GDTIOCTL_RESET_BUS:
4543 {
4544 gdth_ioctl_reset res;
4545 int rval;
4546
4547 if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
4548 (NULL == (ha = gdth_find_ha(res.ionode))))
4549 return -EFAULT;
4550
4551 scp = kzalloc(sizeof(*scp), GFP_KERNEL);
4552 if (!scp)
4553 return -ENOMEM;
4554 scp->device = ha->sdev;
4555 scp->cmd_len = 12;
4556 scp->device->channel = res.number;
4557 rval = gdth_eh_bus_reset(scp);
4558 res.status = (rval == SUCCESS ? S_OK : S_GENERR);
4559 kfree(scp);
4560
4561 if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
4562 return -EFAULT;
4563 break;
4564 }
4565
4566 case GDTIOCTL_RESET_DRV:
4567 return ioc_resetdrv(argp, cmnd);
4568
4569 default:
4570 break;
4571 }
4572 return 0;
4573 }
4574
4575
4576 /* flush routine */
4577 static void gdth_flush(gdth_ha_str *ha)
4578 {
4579 int i;
4580 gdth_cmd_str gdtcmd;
4581 char cmnd[MAX_COMMAND_SIZE];
4582 memset(cmnd, 0xff, MAX_COMMAND_SIZE);
4583
4584 TRACE2(("gdth_flush() hanum %d\n", ha->hanum));
4585
4586 for (i = 0; i < MAX_HDRIVES; ++i) {
4587 if (ha->hdr[i].present) {
4588 gdtcmd.BoardNode = LOCALBOARD;
4589 gdtcmd.Service = CACHESERVICE;
4590 gdtcmd.OpCode = GDT_FLUSH;
4591 if (ha->cache_feat & GDT_64BIT) {
4592 gdtcmd.u.cache64.DeviceNo = i;
4593 gdtcmd.u.cache64.BlockNo = 1;
4594 gdtcmd.u.cache64.sg_canz = 0;
4595 } else {
4596 gdtcmd.u.cache.DeviceNo = i;
4597 gdtcmd.u.cache.BlockNo = 1;
4598 gdtcmd.u.cache.sg_canz = 0;
4599 }
4600 TRACE2(("gdth_flush(): flush ha %d drive %d\n", ha->hanum, i));
4601
4602 gdth_execute(ha->shost, &gdtcmd, cmnd, 30, NULL);
4603 }
4604 }
4605 }
4606
4607 /* configure lun */
4608 static int gdth_slave_configure(struct scsi_device *sdev)
4609 {
4610 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
4611 sdev->skip_ms_page_3f = 1;
4612 sdev->skip_ms_page_8 = 1;
4613 return 0;
4614 }
4615
4616 static struct scsi_host_template gdth_template = {
4617 .name = "GDT SCSI Disk Array Controller",
4618 .info = gdth_info,
4619 .queuecommand = gdth_queuecommand,
4620 .eh_bus_reset_handler = gdth_eh_bus_reset,
4621 .slave_configure = gdth_slave_configure,
4622 .bios_param = gdth_bios_param,
4623 .proc_info = gdth_proc_info,
4624 .proc_name = "gdth",
4625 .can_queue = GDTH_MAXCMDS,
4626 .this_id = -1,
4627 .sg_tablesize = GDTH_MAXSG,
4628 .cmd_per_lun = GDTH_MAXC_P_L,
4629 .unchecked_isa_dma = 1,
4630 .use_clustering = ENABLE_CLUSTERING,
4631 };
4632
4633 #ifdef CONFIG_ISA
4634 static int __init gdth_isa_probe_one(ulong32 isa_bios)
4635 {
4636 struct Scsi_Host *shp;
4637 gdth_ha_str *ha;
4638 dma_addr_t scratch_dma_handle = 0;
4639 int error, i;
4640
4641 if (!gdth_search_isa(isa_bios))
4642 return -ENXIO;
4643
4644 shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
4645 if (!shp)
4646 return -ENOMEM;
4647 ha = shost_priv(shp);
4648
4649 error = -ENODEV;
4650 if (!gdth_init_isa(isa_bios,ha))
4651 goto out_host_put;
4652
4653 /* controller found and initialized */
4654 printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
4655 isa_bios, ha->irq, ha->drq);
4656
4657 error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
4658 if (error) {
4659 printk("GDT-ISA: Unable to allocate IRQ\n");
4660 goto out_host_put;
4661 }
4662
4663 error = request_dma(ha->drq, "gdth");
4664 if (error) {
4665 printk("GDT-ISA: Unable to allocate DMA channel\n");
4666 goto out_free_irq;
4667 }
4668
4669 set_dma_mode(ha->drq,DMA_MODE_CASCADE);
4670 enable_dma(ha->drq);
4671 shp->unchecked_isa_dma = 1;
4672 shp->irq = ha->irq;
4673 shp->dma_channel = ha->drq;
4674
4675 ha->hanum = gdth_ctr_count++;
4676 ha->shost = shp;
4677
4678 ha->pccb = &ha->cmdext;
4679 ha->ccb_phys = 0L;
4680 ha->pdev = NULL;
4681
4682 error = -ENOMEM;
4683
4684 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4685 &scratch_dma_handle);
4686 if (!ha->pscratch)
4687 goto out_dec_counters;
4688 ha->scratch_phys = scratch_dma_handle;
4689
4690 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4691 &scratch_dma_handle);
4692 if (!ha->pmsg)
4693 goto out_free_pscratch;
4694 ha->msg_phys = scratch_dma_handle;
4695
4696 #ifdef INT_COAL
4697 ha->coal_stat = pci_alloc_consistent(ha->pdev,
4698 sizeof(gdth_coal_status) * MAXOFFSETS,
4699 &scratch_dma_handle);
4700 if (!ha->coal_stat)
4701 goto out_free_pmsg;
4702 ha->coal_stat_phys = scratch_dma_handle;
4703 #endif
4704
4705 ha->scratch_busy = FALSE;
4706 ha->req_first = NULL;
4707 ha->tid_cnt = MAX_HDRIVES;
4708 if (max_ids > 0 && max_ids < ha->tid_cnt)
4709 ha->tid_cnt = max_ids;
4710 for (i = 0; i < GDTH_MAXCMDS; ++i)
4711 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4712 ha->scan_mode = rescan ? 0x10 : 0;
4713
4714 error = -ENODEV;
4715 if (!gdth_search_drives(ha)) {
4716 printk("GDT-ISA: Error during device scan\n");
4717 goto out_free_coal_stat;
4718 }
4719
4720 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
4721 hdr_channel = ha->bus_cnt;
4722 ha->virt_bus = hdr_channel;
4723
4724 if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
4725 shp->max_cmd_len = 16;
4726
4727 shp->max_id = ha->tid_cnt;
4728 shp->max_lun = MAXLUN;
4729 shp->max_channel = ha->bus_cnt;
4730
4731 spin_lock_init(&ha->smp_lock);
4732 gdth_enable_int(ha);
4733
4734 error = scsi_add_host(shp, NULL);
4735 if (error)
4736 goto out_free_coal_stat;
4737 list_add_tail(&ha->list, &gdth_instances);
4738
4739 scsi_scan_host(shp);
4740
4741 return 0;
4742
4743 out_free_coal_stat:
4744 #ifdef INT_COAL
4745 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
4746 ha->coal_stat, ha->coal_stat_phys);
4747 out_free_pmsg:
4748 #endif
4749 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4750 ha->pmsg, ha->msg_phys);
4751 out_free_pscratch:
4752 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4753 ha->pscratch, ha->scratch_phys);
4754 out_dec_counters:
4755 gdth_ctr_count--;
4756 out_free_irq:
4757 free_irq(ha->irq, ha);
4758 out_host_put:
4759 scsi_host_put(shp);
4760 return error;
4761 }
4762 #endif /* CONFIG_ISA */
4763
4764 #ifdef CONFIG_EISA
4765 static int __init gdth_eisa_probe_one(ushort eisa_slot)
4766 {
4767 struct Scsi_Host *shp;
4768 gdth_ha_str *ha;
4769 dma_addr_t scratch_dma_handle = 0;
4770 int error, i;
4771
4772 if (!gdth_search_eisa(eisa_slot))
4773 return -ENXIO;
4774
4775 shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
4776 if (!shp)
4777 return -ENOMEM;
4778 ha = shost_priv(shp);
4779
4780 error = -ENODEV;
4781 if (!gdth_init_eisa(eisa_slot,ha))
4782 goto out_host_put;
4783
4784 /* controller found and initialized */
4785 printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
4786 eisa_slot >> 12, ha->irq);
4787
4788 error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
4789 if (error) {
4790 printk("GDT-EISA: Unable to allocate IRQ\n");
4791 goto out_host_put;
4792 }
4793
4794 shp->unchecked_isa_dma = 0;
4795 shp->irq = ha->irq;
4796 shp->dma_channel = 0xff;
4797
4798 ha->hanum = gdth_ctr_count++;
4799 ha->shost = shp;
4800
4801 TRACE2(("EISA detect Bus 0: hanum %d\n", ha->hanum));
4802
4803 ha->pccb = &ha->cmdext;
4804 ha->ccb_phys = 0L;
4805
4806 error = -ENOMEM;
4807
4808 ha->pdev = NULL;
4809 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4810 &scratch_dma_handle);
4811 if (!ha->pscratch)
4812 goto out_free_irq;
4813 ha->scratch_phys = scratch_dma_handle;
4814
4815 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4816 &scratch_dma_handle);
4817 if (!ha->pmsg)
4818 goto out_free_pscratch;
4819 ha->msg_phys = scratch_dma_handle;
4820
4821 #ifdef INT_COAL
4822 ha->coal_stat = pci_alloc_consistent(ha->pdev,
4823 sizeof(gdth_coal_status) * MAXOFFSETS,
4824 &scratch_dma_handle);
4825 if (!ha->coal_stat)
4826 goto out_free_pmsg;
4827 ha->coal_stat_phys = scratch_dma_handle;
4828 #endif
4829
4830 ha->ccb_phys = pci_map_single(ha->pdev,ha->pccb,
4831 sizeof(gdth_cmd_str), PCI_DMA_BIDIRECTIONAL);
4832 if (!ha->ccb_phys)
4833 goto out_free_coal_stat;
4834
4835 ha->scratch_busy = FALSE;
4836 ha->req_first = NULL;
4837 ha->tid_cnt = MAX_HDRIVES;
4838 if (max_ids > 0 && max_ids < ha->tid_cnt)
4839 ha->tid_cnt = max_ids;
4840 for (i = 0; i < GDTH_MAXCMDS; ++i)
4841 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4842 ha->scan_mode = rescan ? 0x10 : 0;
4843
4844 if (!gdth_search_drives(ha)) {
4845 printk("GDT-EISA: Error during device scan\n");
4846 error = -ENODEV;
4847 goto out_free_ccb_phys;
4848 }
4849
4850 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
4851 hdr_channel = ha->bus_cnt;
4852 ha->virt_bus = hdr_channel;
4853
4854 if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
4855 shp->max_cmd_len = 16;
4856
4857 shp->max_id = ha->tid_cnt;
4858 shp->max_lun = MAXLUN;
4859 shp->max_channel = ha->bus_cnt;
4860
4861 spin_lock_init(&ha->smp_lock);
4862 gdth_enable_int(ha);
4863
4864 error = scsi_add_host(shp, NULL);
4865 if (error)
4866 goto out_free_coal_stat;
4867 list_add_tail(&ha->list, &gdth_instances);
4868
4869 scsi_scan_host(shp);
4870
4871 return 0;
4872
4873 out_free_ccb_phys:
4874 pci_unmap_single(ha->pdev,ha->ccb_phys, sizeof(gdth_cmd_str),
4875 PCI_DMA_BIDIRECTIONAL);
4876 out_free_coal_stat:
4877 #ifdef INT_COAL
4878 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
4879 ha->coal_stat, ha->coal_stat_phys);
4880 out_free_pmsg:
4881 #endif
4882 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4883 ha->pmsg, ha->msg_phys);
4884 out_free_pscratch:
4885 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4886 ha->pscratch, ha->scratch_phys);
4887 out_free_irq:
4888 free_irq(ha->irq, ha);
4889 gdth_ctr_count--;
4890 out_host_put:
4891 scsi_host_put(shp);
4892 return error;
4893 }
4894 #endif /* CONFIG_EISA */
4895
4896 #ifdef CONFIG_PCI
4897 static int gdth_pci_probe_one(gdth_pci_str *pcistr,
4898 gdth_ha_str **ha_out)
4899 {
4900 struct Scsi_Host *shp;
4901 gdth_ha_str *ha;
4902 dma_addr_t scratch_dma_handle = 0;
4903 int error, i;
4904 struct pci_dev *pdev = pcistr->pdev;
4905
4906 *ha_out = NULL;
4907
4908 shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
4909 if (!shp)
4910 return -ENOMEM;
4911 ha = shost_priv(shp);
4912
4913 error = -ENODEV;
4914 if (!gdth_init_pci(pdev, pcistr, ha))
4915 goto out_host_put;
4916
4917 /* controller found and initialized */
4918 printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
4919 pdev->bus->number,
4920 PCI_SLOT(pdev->devfn),
4921 ha->irq);
4922
4923 error = request_irq(ha->irq, gdth_interrupt,
4924 IRQF_DISABLED|IRQF_SHARED, "gdth", ha);
4925 if (error) {
4926 printk("GDT-PCI: Unable to allocate IRQ\n");
4927 goto out_host_put;
4928 }
4929
4930 shp->unchecked_isa_dma = 0;
4931 shp->irq = ha->irq;
4932 shp->dma_channel = 0xff;
4933
4934 ha->hanum = gdth_ctr_count++;
4935 ha->shost = shp;
4936
4937 ha->pccb = &ha->cmdext;
4938 ha->ccb_phys = 0L;
4939
4940 error = -ENOMEM;
4941
4942 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4943 &scratch_dma_handle);
4944 if (!ha->pscratch)
4945 goto out_free_irq;
4946 ha->scratch_phys = scratch_dma_handle;
4947
4948 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4949 &scratch_dma_handle);
4950 if (!ha->pmsg)
4951 goto out_free_pscratch;
4952 ha->msg_phys = scratch_dma_handle;
4953
4954 #ifdef INT_COAL
4955 ha->coal_stat = pci_alloc_consistent(ha->pdev,
4956 sizeof(gdth_coal_status) * MAXOFFSETS,
4957 &scratch_dma_handle);
4958 if (!ha->coal_stat)
4959 goto out_free_pmsg;
4960 ha->coal_stat_phys = scratch_dma_handle;
4961 #endif
4962
4963 ha->scratch_busy = FALSE;
4964 ha->req_first = NULL;
4965 ha->tid_cnt = pdev->device >= 0x200 ? MAXID : MAX_HDRIVES;
4966 if (max_ids > 0 && max_ids < ha->tid_cnt)
4967 ha->tid_cnt = max_ids;
4968 for (i = 0; i < GDTH_MAXCMDS; ++i)
4969 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4970 ha->scan_mode = rescan ? 0x10 : 0;
4971
4972 error = -ENODEV;
4973 if (!gdth_search_drives(ha)) {
4974 printk("GDT-PCI %d: Error during device scan\n", ha->hanum);
4975 goto out_free_coal_stat;
4976 }
4977
4978 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
4979 hdr_channel = ha->bus_cnt;
4980 ha->virt_bus = hdr_channel;
4981
4982 /* 64-bit DMA only supported from FW >= x.43 */
4983 if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT) ||
4984 !ha->dma64_support) {
4985 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
4986 printk(KERN_WARNING "GDT-PCI %d: "
4987 "Unable to set 32-bit DMA\n", ha->hanum);
4988 goto out_free_coal_stat;
4989 }
4990 } else {
4991 shp->max_cmd_len = 16;
4992 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
4993 printk("GDT-PCI %d: 64-bit DMA enabled\n", ha->hanum);
4994 } else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
4995 printk(KERN_WARNING "GDT-PCI %d: "
4996 "Unable to set 64/32-bit DMA\n", ha->hanum);
4997 goto out_free_coal_stat;
4998 }
4999 }
5000
5001 shp->max_id = ha->tid_cnt;
5002 shp->max_lun = MAXLUN;
5003 shp->max_channel = ha->bus_cnt;
5004
5005 spin_lock_init(&ha->smp_lock);
5006 gdth_enable_int(ha);
5007
5008 error = scsi_add_host(shp, &pdev->dev);
5009 if (error)
5010 goto out_free_coal_stat;
5011 list_add_tail(&ha->list, &gdth_instances);
5012
5013 pci_set_drvdata(ha->pdev, ha);
5014
5015 scsi_scan_host(shp);
5016
5017 *ha_out = ha;
5018
5019 return 0;
5020
5021 out_free_coal_stat:
5022 #ifdef INT_COAL
5023 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
5024 ha->coal_stat, ha->coal_stat_phys);
5025 out_free_pmsg:
5026 #endif
5027 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
5028 ha->pmsg, ha->msg_phys);
5029 out_free_pscratch:
5030 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
5031 ha->pscratch, ha->scratch_phys);
5032 out_free_irq:
5033 free_irq(ha->irq, ha);
5034 gdth_ctr_count--;
5035 out_host_put:
5036 scsi_host_put(shp);
5037 return error;
5038 }
5039 #endif /* CONFIG_PCI */
5040
5041 static void gdth_remove_one(gdth_ha_str *ha)
5042 {
5043 struct Scsi_Host *shp = ha->shost;
5044
5045 TRACE2(("gdth_remove_one()\n"));
5046
5047 scsi_remove_host(shp);
5048
5049 gdth_flush(ha);
5050
5051 if (ha->sdev) {
5052 scsi_free_host_dev(ha->sdev);
5053 ha->sdev = NULL;
5054 }
5055
5056 if (shp->irq)
5057 free_irq(shp->irq,ha);
5058
5059 #ifdef CONFIG_ISA
5060 if (shp->dma_channel != 0xff)
5061 free_dma(shp->dma_channel);
5062 #endif
5063 #ifdef INT_COAL
5064 if (ha->coal_stat)
5065 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
5066 MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
5067 #endif
5068 if (ha->pscratch)
5069 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
5070 ha->pscratch, ha->scratch_phys);
5071 if (ha->pmsg)
5072 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
5073 ha->pmsg, ha->msg_phys);
5074 if (ha->ccb_phys)
5075 pci_unmap_single(ha->pdev,ha->ccb_phys,
5076 sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
5077
5078 scsi_host_put(shp);
5079 }
5080
5081 static int gdth_halt(struct notifier_block *nb, ulong event, void *buf)
5082 {
5083 gdth_ha_str *ha;
5084
5085 TRACE2(("gdth_halt() event %d\n", (int)event));
5086 if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
5087 return NOTIFY_DONE;
5088
5089 list_for_each_entry(ha, &gdth_instances, list)
5090 gdth_flush(ha);
5091
5092 return NOTIFY_OK;
5093 }
5094
5095 static struct notifier_block gdth_notifier = {
5096 gdth_halt, NULL, 0
5097 };
5098
5099 static int __init gdth_init(void)
5100 {
5101 if (disable) {
5102 printk("GDT-HA: Controller driver disabled from"
5103 " command line !\n");
5104 return 0;
5105 }
5106
5107 printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",
5108 GDTH_VERSION_STR);
5109
5110 /* initializations */
5111 gdth_polling = TRUE;
5112 gdth_clear_events();
5113
5114 /* As default we do not probe for EISA or ISA controllers */
5115 if (probe_eisa_isa) {
5116 /* scanning for controllers, at first: ISA controller */
5117 #ifdef CONFIG_ISA
5118 ulong32 isa_bios;
5119 for (isa_bios = 0xc8000UL; isa_bios <= 0xd8000UL;
5120 isa_bios += 0x8000UL)
5121 gdth_isa_probe_one(isa_bios);
5122 #endif
5123 #ifdef CONFIG_EISA
5124 {
5125 ushort eisa_slot;
5126 for (eisa_slot = 0x1000; eisa_slot <= 0x8000;
5127 eisa_slot += 0x1000)
5128 gdth_eisa_probe_one(eisa_slot);
5129 }
5130 #endif
5131 }
5132
5133 #ifdef CONFIG_PCI
5134 /* scanning for PCI controllers */
5135 if (pci_register_driver(&gdth_pci_driver) == 0)
5136 gdth_pci_registered = true;
5137 #endif /* CONFIG_PCI */
5138
5139 TRACE2(("gdth_detect() %d controller detected\n", gdth_ctr_count));
5140
5141 if (list_empty(&gdth_instances))
5142 return -ENODEV;
5143
5144 #ifdef GDTH_STATISTICS
5145 TRACE2(("gdth_detect(): Initializing timer !\n"));
5146 init_timer(&gdth_timer);
5147 gdth_timer.expires = jiffies + HZ;
5148 gdth_timer.data = 0L;
5149 gdth_timer.function = gdth_timeout;
5150 add_timer(&gdth_timer);
5151 #endif
5152 major = register_chrdev(0,"gdth", &gdth_fops);
5153 register_reboot_notifier(&gdth_notifier);
5154 gdth_polling = FALSE;
5155 return 0;
5156 }
5157
5158 static void __exit gdth_exit(void)
5159 {
5160 gdth_ha_str *ha;
5161
5162 unregister_chrdev(major, "gdth");
5163 unregister_reboot_notifier(&gdth_notifier);
5164
5165 #ifdef GDTH_STATISTICS
5166 del_timer_sync(&gdth_timer);
5167 #endif
5168
5169 #ifdef CONFIG_PCI
5170 if (gdth_pci_registered)
5171 pci_unregister_driver(&gdth_pci_driver);
5172 #endif
5173
5174 list_for_each_entry(ha, &gdth_instances, list)
5175 gdth_remove_one(ha);
5176 }
5177
5178 module_init(gdth_init);
5179 module_exit(gdth_exit);
5180
5181 #ifndef MODULE
5182 __setup("gdth=", option_setup);
5183 #endif
Support for the Chinese Samsung S3C2440 based development boards