?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
pciehp: Mask hotplug interrupt at controller release
[linux-2.6/mini2440.git] / drivers / ata / sata_fsl.c
blobfddd346b1d5728c289d1a9a44ae5ab8c2de37412
1 /*
2 * drivers/ata/sata_fsl.c
3 *
4 * Freescale 3.0Gbps SATA device driver
5 *
6 * Author: Ashish Kalra <ashish.kalra@freescale.com>
7 * Li Yang <leoli@freescale.com>
8 *
9 * Copyright (c) 2006-2007 Freescale Semiconductor, Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21
22 #include <scsi/scsi_host.h>
23 #include <scsi/scsi_cmnd.h>
24 #include <linux/libata.h>
25 #include <asm/io.h>
26 #include <linux/of_platform.h>
27
28 /* Controller information */
29 enum {
30 SATA_FSL_QUEUE_DEPTH = 16,
31 SATA_FSL_MAX_PRD = 63,
32 SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1,
33 SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */
34
35 SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
36 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
37 ATA_FLAG_NCQ),
38
39 SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH,
40 SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */
41 SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE),
42
43 /*
44 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and
45 * chained indirect PRDEs upto a max count of 63.
46 * We are allocating an array of 63 PRDEs contigiously, but PRDE#15 will
47 * be setup as an indirect descriptor, pointing to it's next
48 * (contigious) PRDE. Though chained indirect PRDE arrays are
49 * supported,it will be more efficient to use a direct PRDT and
50 * a single chain/link to indirect PRDE array/PRDT.
51 */
52
53 SATA_FSL_CMD_DESC_CFIS_SZ = 32,
54 SATA_FSL_CMD_DESC_SFIS_SZ = 32,
55 SATA_FSL_CMD_DESC_ACMD_SZ = 16,
56 SATA_FSL_CMD_DESC_RSRVD = 16,
57
58 SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ +
59 SATA_FSL_CMD_DESC_SFIS_SZ +
60 SATA_FSL_CMD_DESC_ACMD_SZ +
61 SATA_FSL_CMD_DESC_RSRVD +
62 SATA_FSL_MAX_PRD * 16),
63
64 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT =
65 (SATA_FSL_CMD_DESC_CFIS_SZ +
66 SATA_FSL_CMD_DESC_SFIS_SZ +
67 SATA_FSL_CMD_DESC_ACMD_SZ +
68 SATA_FSL_CMD_DESC_RSRVD),
69
70 SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS),
71 SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE +
72 SATA_FSL_CMD_DESC_AR_SZ),
73
74 /*
75 * MPC8315 has two SATA controllers, SATA1 & SATA2
76 * (one port per controller)
77 * MPC837x has 2/4 controllers, one port per controller
78 */
79
80 SATA_FSL_MAX_PORTS = 1,
81
82 SATA_FSL_IRQ_FLAG = IRQF_SHARED,
83 };
84
85 /*
86 * Host Controller command register set - per port
87 */
88 enum {
89 CQ = 0,
90 CA = 8,
91 CC = 0x10,
92 CE = 0x18,
93 DE = 0x20,
94 CHBA = 0x24,
95 HSTATUS = 0x28,
96 HCONTROL = 0x2C,
97 CQPMP = 0x30,
98 SIGNATURE = 0x34,
99 ICC = 0x38,
100
101 /*
102 * Host Status Register (HStatus) bitdefs
103 */
104 ONLINE = (1 << 31),
105 GOING_OFFLINE = (1 << 30),
106 BIST_ERR = (1 << 29),
107
108 FATAL_ERR_HC_MASTER_ERR = (1 << 18),
109 FATAL_ERR_PARITY_ERR_TX = (1 << 17),
110 FATAL_ERR_PARITY_ERR_RX = (1 << 16),
111 FATAL_ERR_DATA_UNDERRUN = (1 << 13),
112 FATAL_ERR_DATA_OVERRUN = (1 << 12),
113 FATAL_ERR_CRC_ERR_TX = (1 << 11),
114 FATAL_ERR_CRC_ERR_RX = (1 << 10),
115 FATAL_ERR_FIFO_OVRFL_TX = (1 << 9),
116 FATAL_ERR_FIFO_OVRFL_RX = (1 << 8),
117
118 FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR |
119 FATAL_ERR_PARITY_ERR_TX |
120 FATAL_ERR_PARITY_ERR_RX |
121 FATAL_ERR_DATA_UNDERRUN |
122 FATAL_ERR_DATA_OVERRUN |
123 FATAL_ERR_CRC_ERR_TX |
124 FATAL_ERR_CRC_ERR_RX |
125 FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX,
126
127 INT_ON_FATAL_ERR = (1 << 5),
128 INT_ON_PHYRDY_CHG = (1 << 4),
129
130 INT_ON_SIGNATURE_UPDATE = (1 << 3),
131 INT_ON_SNOTIFY_UPDATE = (1 << 2),
132 INT_ON_SINGL_DEVICE_ERR = (1 << 1),
133 INT_ON_CMD_COMPLETE = 1,
134
135 INT_ON_ERROR = INT_ON_FATAL_ERR |
136 INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR,
137
138 /*
139 * Host Control Register (HControl) bitdefs
140 */
141 HCONTROL_ONLINE_PHY_RST = (1 << 31),
142 HCONTROL_FORCE_OFFLINE = (1 << 30),
143 HCONTROL_PARITY_PROT_MOD = (1 << 14),
144 HCONTROL_DPATH_PARITY = (1 << 12),
145 HCONTROL_SNOOP_ENABLE = (1 << 10),
146 HCONTROL_PMP_ATTACHED = (1 << 9),
147 HCONTROL_COPYOUT_STATFIS = (1 << 8),
148 IE_ON_FATAL_ERR = (1 << 5),
149 IE_ON_PHYRDY_CHG = (1 << 4),
150 IE_ON_SIGNATURE_UPDATE = (1 << 3),
151 IE_ON_SNOTIFY_UPDATE = (1 << 2),
152 IE_ON_SINGL_DEVICE_ERR = (1 << 1),
153 IE_ON_CMD_COMPLETE = 1,
154
155 DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG |
156 IE_ON_SIGNATURE_UPDATE |
157 IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE,
158
159 EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31),
160 DATA_SNOOP_ENABLE = (1 << 22),
161 };
162
163 /*
164 * SATA Superset Registers
165 */
166 enum {
167 SSTATUS = 0,
168 SERROR = 4,
169 SCONTROL = 8,
170 SNOTIFY = 0xC,
171 };
172
173 /*
174 * Control Status Register Set
175 */
176 enum {
177 TRANSCFG = 0,
178 TRANSSTATUS = 4,
179 LINKCFG = 8,
180 LINKCFG1 = 0xC,
181 LINKCFG2 = 0x10,
182 LINKSTATUS = 0x14,
183 LINKSTATUS1 = 0x18,
184 PHYCTRLCFG = 0x1C,
185 COMMANDSTAT = 0x20,
186 };
187
188 /* PHY (link-layer) configuration control */
189 enum {
190 PHY_BIST_ENABLE = 0x01,
191 };
192
193 /*
194 * Command Header Table entry, i.e, command slot
195 * 4 Dwords per command slot, command header size == 64 Dwords.
196 */
197 struct cmdhdr_tbl_entry {
198 u32 cda;
199 u32 prde_fis_len;
200 u32 ttl;
201 u32 desc_info;
202 };
203
204 /*
205 * Description information bitdefs
206 */
207 enum {
208 VENDOR_SPECIFIC_BIST = (1 << 10),
209 CMD_DESC_SNOOP_ENABLE = (1 << 9),
210 FPDMA_QUEUED_CMD = (1 << 8),
211 SRST_CMD = (1 << 7),
212 BIST = (1 << 6),
213 ATAPI_CMD = (1 << 5),
214 };
215
216 /*
217 * Command Descriptor
218 */
219 struct command_desc {
220 u8 cfis[8 * 4];
221 u8 sfis[8 * 4];
222 u8 acmd[4 * 4];
223 u8 fill[4 * 4];
224 u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4];
225 u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4];
226 };
227
228 /*
229 * Physical region table descriptor(PRD)
230 */
231
232 struct prde {
233 u32 dba;
234 u8 fill[2 * 4];
235 u32 ddc_and_ext;
236 };
237
238 /*
239 * ata_port private data
240 * This is our per-port instance data.
241 */
242 struct sata_fsl_port_priv {
243 struct cmdhdr_tbl_entry *cmdslot;
244 dma_addr_t cmdslot_paddr;
245 struct command_desc *cmdentry;
246 dma_addr_t cmdentry_paddr;
247 };
248
249 /*
250 * ata_port->host_set private data
251 */
252 struct sata_fsl_host_priv {
253 void __iomem *hcr_base;
254 void __iomem *ssr_base;
255 void __iomem *csr_base;
256 int irq;
257 };
258
259 static inline unsigned int sata_fsl_tag(unsigned int tag,
260 void __iomem *hcr_base)
261 {
262 /* We let libATA core do actual (queue) tag allocation */
263
264 /* all non NCQ/queued commands should have tag#0 */
265 if (ata_tag_internal(tag)) {
266 DPRINTK("mapping internal cmds to tag#0\n");
267 return 0;
268 }
269
270 if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) {
271 DPRINTK("tag %d invalid : out of range\n", tag);
272 return 0;
273 }
274
275 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) {
276 DPRINTK("tag %d invalid : in use!!\n", tag);
277 return 0;
278 }
279
280 return tag;
281 }
282
283 static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp,
284 unsigned int tag, u32 desc_info,
285 u32 data_xfer_len, u8 num_prde,
286 u8 fis_len)
287 {
288 dma_addr_t cmd_descriptor_address;
289
290 cmd_descriptor_address = pp->cmdentry_paddr +
291 tag * SATA_FSL_CMD_DESC_SIZE;
292
293 /* NOTE: both data_xfer_len & fis_len are Dword counts */
294
295 pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address);
296 pp->cmdslot[tag].prde_fis_len =
297 cpu_to_le32((num_prde << 16) | (fis_len << 2));
298 pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03);
299 pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F));
300
301 VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n",
302 pp->cmdslot[tag].cda,
303 pp->cmdslot[tag].prde_fis_len,
304 pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info);
305
306 }
307
308 static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc,
309 u32 *ttl, dma_addr_t cmd_desc_paddr)
310 {
311 struct scatterlist *sg;
312 unsigned int num_prde = 0;
313 u32 ttl_dwords = 0;
314
315 /*
316 * NOTE : direct & indirect prdt's are contigiously allocated
317 */
318 struct prde *prd = (struct prde *)&((struct command_desc *)
319 cmd_desc)->prdt;
320
321 struct prde *prd_ptr_to_indirect_ext = NULL;
322 unsigned indirect_ext_segment_sz = 0;
323 dma_addr_t indirect_ext_segment_paddr;
324 unsigned int si;
325
326 VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc, prd);
327
328 indirect_ext_segment_paddr = cmd_desc_paddr +
329 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16;
330
331 for_each_sg(qc->sg, sg, qc->n_elem, si) {
332 dma_addr_t sg_addr = sg_dma_address(sg);
333 u32 sg_len = sg_dma_len(sg);
334
335 VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%x, sg_len = %d\n",
336 sg_addr, sg_len);
337
338 /* warn if each s/g element is not dword aligned */
339 if (sg_addr & 0x03)
340 ata_port_printk(qc->ap, KERN_ERR,
341 "s/g addr unaligned : 0x%x\n", sg_addr);
342 if (sg_len & 0x03)
343 ata_port_printk(qc->ap, KERN_ERR,
344 "s/g len unaligned : 0x%x\n", sg_len);
345
346 if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) &&
347 sg_next(sg) != NULL) {
348 VPRINTK("setting indirect prde\n");
349 prd_ptr_to_indirect_ext = prd;
350 prd->dba = cpu_to_le32(indirect_ext_segment_paddr);
351 indirect_ext_segment_sz = 0;
352 ++prd;
353 ++num_prde;
354 }
355
356 ttl_dwords += sg_len;
357 prd->dba = cpu_to_le32(sg_addr);
358 prd->ddc_and_ext =
359 cpu_to_le32(DATA_SNOOP_ENABLE | (sg_len & ~0x03));
360
361 VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n",
362 ttl_dwords, prd->dba, prd->ddc_and_ext);
363
364 ++num_prde;
365 ++prd;
366 if (prd_ptr_to_indirect_ext)
367 indirect_ext_segment_sz += sg_len;
368 }
369
370 if (prd_ptr_to_indirect_ext) {
371 /* set indirect extension flag along with indirect ext. size */
372 prd_ptr_to_indirect_ext->ddc_and_ext =
373 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG |
374 DATA_SNOOP_ENABLE |
375 (indirect_ext_segment_sz & ~0x03)));
376 }
377
378 *ttl = ttl_dwords;
379 return num_prde;
380 }
381
382 static void sata_fsl_qc_prep(struct ata_queued_cmd *qc)
383 {
384 struct ata_port *ap = qc->ap;
385 struct sata_fsl_port_priv *pp = ap->private_data;
386 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
387 void __iomem *hcr_base = host_priv->hcr_base;
388 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
389 struct command_desc *cd;
390 u32 desc_info = CMD_DESC_SNOOP_ENABLE;
391 u32 num_prde = 0;
392 u32 ttl_dwords = 0;
393 dma_addr_t cd_paddr;
394
395 cd = (struct command_desc *)pp->cmdentry + tag;
396 cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE;
397
398 ata_tf_to_fis(&qc->tf, 0, 1, (u8 *) &cd->cfis);
399
400 VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n",
401 cd->cfis[0], cd->cfis[1], cd->cfis[2]);
402
403 if (qc->tf.protocol == ATA_PROT_NCQ) {
404 VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n",
405 cd->cfis[3], cd->cfis[11]);
406 }
407
408 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */
409 if (ata_is_atapi(qc->tf.protocol)) {
410 desc_info |= ATAPI_CMD;
411 memset((void *)&cd->acmd, 0, 32);
412 memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len);
413 }
414
415 if (qc->flags & ATA_QCFLAG_DMAMAP)
416 num_prde = sata_fsl_fill_sg(qc, (void *)cd,
417 &ttl_dwords, cd_paddr);
418
419 if (qc->tf.protocol == ATA_PROT_NCQ)
420 desc_info |= FPDMA_QUEUED_CMD;
421
422 sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords,
423 num_prde, 5);
424
425 VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n",
426 desc_info, ttl_dwords, num_prde);
427 }
428
429 static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc)
430 {
431 struct ata_port *ap = qc->ap;
432 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
433 void __iomem *hcr_base = host_priv->hcr_base;
434 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
435
436 VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n",
437 ioread32(CQ + hcr_base),
438 ioread32(CA + hcr_base),
439 ioread32(CE + hcr_base), ioread32(CC + hcr_base));
440
441 /* Simply queue command to the controller/device */
442 iowrite32(1 << tag, CQ + hcr_base);
443
444 VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n",
445 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base));
446
447 VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n",
448 ioread32(CE + hcr_base),
449 ioread32(DE + hcr_base),
450 ioread32(CC + hcr_base),
451 ioread32(COMMANDSTAT + host_priv->csr_base));
452
453 return 0;
454 }
455
456 static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc)
457 {
458 struct sata_fsl_port_priv *pp = qc->ap->private_data;
459 struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data;
460 void __iomem *hcr_base = host_priv->hcr_base;
461 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
462 struct command_desc *cd;
463
464 cd = pp->cmdentry + tag;
465
466 ata_tf_from_fis(cd->sfis, &qc->result_tf);
467 return true;
468 }
469
470 static int sata_fsl_scr_write(struct ata_port *ap, unsigned int sc_reg_in,
471 u32 val)
472 {
473 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
474 void __iomem *ssr_base = host_priv->ssr_base;
475 unsigned int sc_reg;
476
477 switch (sc_reg_in) {
478 case SCR_STATUS:
479 case SCR_ERROR:
480 case SCR_CONTROL:
481 case SCR_ACTIVE:
482 sc_reg = sc_reg_in;
483 break;
484 default:
485 return -EINVAL;
486 }
487
488 VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg);
489
490 iowrite32(val, ssr_base + (sc_reg * 4));
491 return 0;
492 }
493
494 static int sata_fsl_scr_read(struct ata_port *ap, unsigned int sc_reg_in,
495 u32 *val)
496 {
497 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
498 void __iomem *ssr_base = host_priv->ssr_base;
499 unsigned int sc_reg;
500
501 switch (sc_reg_in) {
502 case SCR_STATUS:
503 case SCR_ERROR:
504 case SCR_CONTROL:
505 case SCR_ACTIVE:
506 sc_reg = sc_reg_in;
507 break;
508 default:
509 return -EINVAL;
510 }
511
512 VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg);
513
514 *val = ioread32(ssr_base + (sc_reg * 4));
515 return 0;
516 }
517
518 static void sata_fsl_freeze(struct ata_port *ap)
519 {
520 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
521 void __iomem *hcr_base = host_priv->hcr_base;
522 u32 temp;
523
524 VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n",
525 ioread32(CQ + hcr_base),
526 ioread32(CA + hcr_base),
527 ioread32(CE + hcr_base), ioread32(DE + hcr_base));
528 VPRINTK("CmdStat = 0x%x\n",
529 ioread32(host_priv->csr_base + COMMANDSTAT));
530
531 /* disable interrupts on the controller/port */
532 temp = ioread32(hcr_base + HCONTROL);
533 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
534
535 VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n",
536 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
537 }
538
539 static void sata_fsl_thaw(struct ata_port *ap)
540 {
541 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
542 void __iomem *hcr_base = host_priv->hcr_base;
543 u32 temp;
544
545 /* ack. any pending IRQs for this controller/port */
546 temp = ioread32(hcr_base + HSTATUS);
547
548 VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F));
549
550 if (temp & 0x3F)
551 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
552
553 /* enable interrupts on the controller/port */
554 temp = ioread32(hcr_base + HCONTROL);
555 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
556
557 VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n",
558 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
559 }
560
561 static int sata_fsl_port_start(struct ata_port *ap)
562 {
563 struct device *dev = ap->host->dev;
564 struct sata_fsl_port_priv *pp;
565 int retval;
566 void *mem;
567 dma_addr_t mem_dma;
568 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
569 void __iomem *hcr_base = host_priv->hcr_base;
570 u32 temp;
571
572 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
573 if (!pp)
574 return -ENOMEM;
575
576 mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma,
577 GFP_KERNEL);
578 if (!mem) {
579 kfree(pp);
580 return -ENOMEM;
581 }
582 memset(mem, 0, SATA_FSL_PORT_PRIV_DMA_SZ);
583
584 pp->cmdslot = mem;
585 pp->cmdslot_paddr = mem_dma;
586
587 mem += SATA_FSL_CMD_SLOT_SIZE;
588 mem_dma += SATA_FSL_CMD_SLOT_SIZE;
589
590 pp->cmdentry = mem;
591 pp->cmdentry_paddr = mem_dma;
592
593 ap->private_data = pp;
594
595 VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n",
596 pp->cmdslot_paddr, pp->cmdentry_paddr);
597
598 /* Now, update the CHBA register in host controller cmd register set */
599 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
600
601 /*
602 * Now, we can bring the controller on-line & also initiate
603 * the COMINIT sequence, we simply return here and the boot-probing
604 * & device discovery process is re-initiated by libATA using a
605 * Softreset EH (dummy) session. Hence, boot probing and device
606 * discovey will be part of sata_fsl_softreset() callback.
607 */
608
609 temp = ioread32(hcr_base + HCONTROL);
610 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL);
611
612 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
613 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
614 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA));
615
616 #ifdef CONFIG_MPC8315_DS
617 /*
618 * Workaround for 8315DS board 3gbps link-up issue,
619 * currently limit SATA port to GEN1 speed
620 */
621 sata_fsl_scr_read(ap, SCR_CONTROL, &temp);
622 temp &= ~(0xF << 4);
623 temp |= (0x1 << 4);
624 sata_fsl_scr_write(ap, SCR_CONTROL, temp);
625
626 sata_fsl_scr_read(ap, SCR_CONTROL, &temp);
627 dev_printk(KERN_WARNING, dev, "scr_control, speed limited to %x\n",
628 temp);
629 #endif
630
631 return 0;
632 }
633
634 static void sata_fsl_port_stop(struct ata_port *ap)
635 {
636 struct device *dev = ap->host->dev;
637 struct sata_fsl_port_priv *pp = ap->private_data;
638 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
639 void __iomem *hcr_base = host_priv->hcr_base;
640 u32 temp;
641
642 /*
643 * Force host controller to go off-line, aborting current operations
644 */
645 temp = ioread32(hcr_base + HCONTROL);
646 temp &= ~HCONTROL_ONLINE_PHY_RST;
647 temp |= HCONTROL_FORCE_OFFLINE;
648 iowrite32(temp, hcr_base + HCONTROL);
649
650 /* Poll for controller to go offline - should happen immediately */
651 ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1);
652
653 ap->private_data = NULL;
654 dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ,
655 pp->cmdslot, pp->cmdslot_paddr);
656
657 kfree(pp);
658 }
659
660 static unsigned int sata_fsl_dev_classify(struct ata_port *ap)
661 {
662 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
663 void __iomem *hcr_base = host_priv->hcr_base;
664 struct ata_taskfile tf;
665 u32 temp;
666
667 temp = ioread32(hcr_base + SIGNATURE);
668
669 VPRINTK("raw sig = 0x%x\n", temp);
670 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
671 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
672
673 tf.lbah = (temp >> 24) & 0xff;
674 tf.lbam = (temp >> 16) & 0xff;
675 tf.lbal = (temp >> 8) & 0xff;
676 tf.nsect = temp & 0xff;
677
678 return ata_dev_classify(&tf);
679 }
680
681 static int sata_fsl_prereset(struct ata_linke *link, unsigned long deadline)
682 {
683 /* FIXME: Never skip softreset, sata_fsl_softreset() is
684 * combination of soft and hard resets. sata_fsl_softreset()
685 * needs to be splitted into soft and hard resets.
686 */
687 return 0;
688 }
689
690 static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
691 unsigned long deadline)
692 {
693 struct ata_port *ap = link->ap;
694 struct sata_fsl_port_priv *pp = ap->private_data;
695 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
696 void __iomem *hcr_base = host_priv->hcr_base;
697 u32 temp;
698 struct ata_taskfile tf;
699 u8 *cfis;
700 u32 Serror;
701 int i = 0;
702 unsigned long start_jiffies;
703
704 DPRINTK("in xx_softreset\n");
705
706 try_offline_again:
707 /*
708 * Force host controller to go off-line, aborting current operations
709 */
710 temp = ioread32(hcr_base + HCONTROL);
711 temp &= ~HCONTROL_ONLINE_PHY_RST;
712 iowrite32(temp, hcr_base + HCONTROL);
713
714 /* Poll for controller to go offline */
715 temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 500);
716
717 if (temp & ONLINE) {
718 ata_port_printk(ap, KERN_ERR,
719 "Softreset failed, not off-lined %d\n", i);
720
721 /*
722 * Try to offline controller atleast twice
723 */
724 i++;
725 if (i == 2)
726 goto err;
727 else
728 goto try_offline_again;
729 }
730
731 DPRINTK("softreset, controller off-lined\n");
732 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
733 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
734
735 /*
736 * PHY reset should remain asserted for atleast 1ms
737 */
738 msleep(1);
739
740 /*
741 * Now, bring the host controller online again, this can take time
742 * as PHY reset and communication establishment, 1st D2H FIS and
743 * device signature update is done, on safe side assume 500ms
744 * NOTE : Host online status may be indicated immediately!!
745 */
746
747 temp = ioread32(hcr_base + HCONTROL);
748 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE);
749 iowrite32(temp, hcr_base + HCONTROL);
750
751 temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, 0, 1, 500);
752
753 if (!(temp & ONLINE)) {
754 ata_port_printk(ap, KERN_ERR,
755 "Softreset failed, not on-lined\n");
756 goto err;
757 }
758
759 DPRINTK("softreset, controller off-lined & on-lined\n");
760 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
761 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
762
763 /*
764 * First, wait for the PHYRDY change to occur before waiting for
765 * the signature, and also verify if SStatus indicates device
766 * presence
767 */
768
769 temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0, 1, 500);
770 if ((!(temp & 0x10)) || ata_link_offline(link)) {
771 ata_port_printk(ap, KERN_WARNING,
772 "No Device OR PHYRDY change,Hstatus = 0x%x\n",
773 ioread32(hcr_base + HSTATUS));
774 goto err;
775 }
776
777 /*
778 * Wait for the first D2H from device,i.e,signature update notification
779 */
780 start_jiffies = jiffies;
781 temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0x10,
782 500, jiffies_to_msecs(deadline - start_jiffies));
783
784 if ((temp & 0xFF) != 0x18) {
785 ata_port_printk(ap, KERN_WARNING, "No Signature Update\n");
786 goto err;
787 } else {
788 ata_port_printk(ap, KERN_INFO,
789 "Signature Update detected @ %d msecs\n",
790 jiffies_to_msecs(jiffies - start_jiffies));
791 }
792
793 /*
794 * Send a device reset (SRST) explicitly on command slot #0
795 * Check : will the command queue (reg) be cleared during offlining ??
796 * Also we will be online only if Phy commn. has been established
797 * and device presence has been detected, therefore if we have
798 * reached here, we can send a command to the target device
799 */
800
801 DPRINTK("Sending SRST/device reset\n");
802
803 ata_tf_init(link->device, &tf);
804 cfis = (u8 *) &pp->cmdentry->cfis;
805
806 /* device reset/SRST is a control register update FIS, uses tag0 */
807 sata_fsl_setup_cmd_hdr_entry(pp, 0,
808 SRST_CMD | CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
809
810 tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */
811 ata_tf_to_fis(&tf, 0, 0, cfis);
812
813 DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n",
814 cfis[0], cfis[1], cfis[2], cfis[3]);
815
816 /*
817 * Queue SRST command to the controller/device, ensure that no
818 * other commands are active on the controller/device
819 */
820
821 DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n",
822 ioread32(CQ + hcr_base),
823 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
824
825 iowrite32(0xFFFF, CC + hcr_base);
826 iowrite32(1, CQ + hcr_base);
827
828 temp = ata_wait_register(CQ + hcr_base, 0x1, 0x1, 1, 5000);
829 if (temp & 0x1) {
830 ata_port_printk(ap, KERN_WARNING, "ATA_SRST issue failed\n");
831
832 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
833 ioread32(CQ + hcr_base),
834 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
835
836 sata_fsl_scr_read(ap, SCR_ERROR, &Serror);
837
838 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
839 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
840 DPRINTK("Serror = 0x%x\n", Serror);
841 goto err;
842 }
843
844 msleep(1);
845
846 /*
847 * SATA device enters reset state after receving a Control register
848 * FIS with SRST bit asserted and it awaits another H2D Control reg.
849 * FIS with SRST bit cleared, then the device does internal diags &
850 * initialization, followed by indicating it's initialization status
851 * using ATA signature D2H register FIS to the host controller.
852 */
853
854 sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
855
856 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */
857 ata_tf_to_fis(&tf, 0, 0, cfis);
858
859 iowrite32(1, CQ + hcr_base);
860 msleep(150); /* ?? */
861
862 /*
863 * The above command would have signalled an interrupt on command
864 * complete, which needs special handling, by clearing the Nth
865 * command bit of the CCreg
866 */
867 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
868
869 DPRINTK("SATA FSL : Now checking device signature\n");
870
871 *class = ATA_DEV_NONE;
872
873 /* Verify if SStatus indicates device presence */
874 if (ata_link_online(link)) {
875 /*
876 * if we are here, device presence has been detected,
877 * 1st D2H FIS would have been received, but sfis in
878 * command desc. is not updated, but signature register
879 * would have been updated
880 */
881
882 *class = sata_fsl_dev_classify(ap);
883
884 DPRINTK("class = %d\n", *class);
885 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC));
886 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE));
887 }
888
889 return 0;
890
891 err:
892 return -EIO;
893 }
894
895 static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc)
896 {
897 if (qc->flags & ATA_QCFLAG_FAILED)
898 qc->err_mask |= AC_ERR_OTHER;
899
900 if (qc->err_mask) {
901 /* make DMA engine forget about the failed command */
902
903 }
904 }
905
906 static void sata_fsl_error_intr(struct ata_port *ap)
907 {
908 struct ata_link *link = &ap->link;
909 struct ata_eh_info *ehi = &link->eh_info;
910 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
911 void __iomem *hcr_base = host_priv->hcr_base;
912 u32 hstatus, dereg, cereg = 0, SError = 0;
913 unsigned int err_mask = 0, action = 0;
914 struct ata_queued_cmd *qc;
915 int freeze = 0;
916
917 hstatus = ioread32(hcr_base + HSTATUS);
918 cereg = ioread32(hcr_base + CE);
919
920 ata_ehi_clear_desc(ehi);
921
922 /*
923 * Handle & Clear SError
924 */
925
926 sata_fsl_scr_read(ap, SCR_ERROR, &SError);
927 if (unlikely(SError & 0xFFFF0000)) {
928 sata_fsl_scr_write(ap, SCR_ERROR, SError);
929 err_mask |= AC_ERR_ATA_BUS;
930 }
931
932 DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
933 hstatus, cereg, ioread32(hcr_base + DE), SError);
934
935 /* handle single device errors */
936 if (cereg) {
937 /*
938 * clear the command error, also clears queue to the device
939 * in error, and we can (re)issue commands to this device.
940 * When a device is in error all commands queued into the
941 * host controller and at the device are considered aborted
942 * and the queue for that device is stopped. Now, after
943 * clearing the device error, we can issue commands to the
944 * device to interrogate it to find the source of the error.
945 */
946 dereg = ioread32(hcr_base + DE);
947 iowrite32(dereg, hcr_base + DE);
948 iowrite32(cereg, hcr_base + CE);
949
950 DPRINTK("single device error, CE=0x%x, DE=0x%x\n",
951 ioread32(hcr_base + CE), ioread32(hcr_base + DE));
952 /*
953 * We should consider this as non fatal error, and TF must
954 * be updated as done below.
955 */
956
957 err_mask |= AC_ERR_DEV;
958 }
959
960 /* handle fatal errors */
961 if (hstatus & FATAL_ERROR_DECODE) {
962 err_mask |= AC_ERR_ATA_BUS;
963 action |= ATA_EH_RESET;
964 /* how will fatal error interrupts be completed ?? */
965 freeze = 1;
966 }
967
968 /* Handle PHYRDY change notification */
969 if (hstatus & INT_ON_PHYRDY_CHG) {
970 DPRINTK("SATA FSL: PHYRDY change indication\n");
971
972 /* Setup a soft-reset EH action */
973 ata_ehi_hotplugged(ehi);
974 freeze = 1;
975 }
976
977 /* record error info */
978 qc = ata_qc_from_tag(ap, link->active_tag);
979
980 if (qc)
981 qc->err_mask |= err_mask;
982 else
983 ehi->err_mask |= err_mask;
984
985 ehi->action |= action;
986 ehi->serror |= SError;
987
988 /* freeze or abort */
989 if (freeze)
990 ata_port_freeze(ap);
991 else
992 ata_port_abort(ap);
993 }
994
995 static void sata_fsl_host_intr(struct ata_port *ap)
996 {
997 struct ata_link *link = &ap->link;
998 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
999 void __iomem *hcr_base = host_priv->hcr_base;
1000 u32 hstatus, qc_active = 0;
1001 struct ata_queued_cmd *qc;
1002 u32 SError;
1003
1004 hstatus = ioread32(hcr_base + HSTATUS);
1005
1006 sata_fsl_scr_read(ap, SCR_ERROR, &SError);
1007
1008 if (unlikely(SError & 0xFFFF0000)) {
1009 DPRINTK("serror @host_intr : 0x%x\n", SError);
1010 sata_fsl_error_intr(ap);
1011
1012 }
1013
1014 if (unlikely(hstatus & INT_ON_ERROR)) {
1015 DPRINTK("error interrupt!!\n");
1016 sata_fsl_error_intr(ap);
1017 return;
1018 }
1019
1020 if (link->sactive) { /* only true for NCQ commands */
1021 int i;
1022 /* Read command completed register */
1023 qc_active = ioread32(hcr_base + CC);
1024 /* clear CC bit, this will also complete the interrupt */
1025 iowrite32(qc_active, hcr_base + CC);
1026
1027 DPRINTK("Status of all queues :\n");
1028 DPRINTK("qc_active/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
1029 qc_active, ioread32(hcr_base + CA),
1030 ioread32(hcr_base + CE));
1031
1032 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) {
1033 if (qc_active & (1 << i)) {
1034 qc = ata_qc_from_tag(ap, i);
1035 if (qc)
1036 ata_qc_complete(qc);
1037 DPRINTK
1038 ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n",
1039 i, ioread32(hcr_base + CC),
1040 ioread32(hcr_base + CA));
1041 }
1042 }
1043 return;
1044
1045 } else if (ap->qc_active) {
1046 iowrite32(1, hcr_base + CC);
1047 qc = ata_qc_from_tag(ap, link->active_tag);
1048
1049 DPRINTK("completing non-ncq cmd, tag=%d,CC=0x%x\n",
1050 link->active_tag, ioread32(hcr_base + CC));
1051
1052 if (qc)
1053 ata_qc_complete(qc);
1054 } else {
1055 /* Spurious Interrupt!! */
1056 DPRINTK("spurious interrupt!!, CC = 0x%x\n",
1057 ioread32(hcr_base + CC));
1058 return;
1059 }
1060 }
1061
1062 static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance)
1063 {
1064 struct ata_host *host = dev_instance;
1065 struct sata_fsl_host_priv *host_priv = host->private_data;
1066 void __iomem *hcr_base = host_priv->hcr_base;
1067 u32 interrupt_enables;
1068 unsigned handled = 0;
1069 struct ata_port *ap;
1070
1071 /* ack. any pending IRQs for this controller/port */
1072 interrupt_enables = ioread32(hcr_base + HSTATUS);
1073 interrupt_enables &= 0x3F;
1074
1075 DPRINTK("interrupt status 0x%x\n", interrupt_enables);
1076
1077 if (!interrupt_enables)
1078 return IRQ_NONE;
1079
1080 spin_lock(&host->lock);
1081
1082 /* Assuming one port per host controller */
1083
1084 ap = host->ports[0];
1085 if (ap) {
1086 sata_fsl_host_intr(ap);
1087 } else {
1088 dev_printk(KERN_WARNING, host->dev,
1089 "interrupt on disabled port 0\n");
1090 }
1091
1092 iowrite32(interrupt_enables, hcr_base + HSTATUS);
1093 handled = 1;
1094
1095 spin_unlock(&host->lock);
1096
1097 return IRQ_RETVAL(handled);
1098 }
1099
1100 /*
1101 * Multiple ports are represented by multiple SATA controllers with
1102 * one port per controller
1103 */
1104 static int sata_fsl_init_controller(struct ata_host *host)
1105 {
1106 struct sata_fsl_host_priv *host_priv = host->private_data;
1107 void __iomem *hcr_base = host_priv->hcr_base;
1108 u32 temp;
1109
1110 /*
1111 * NOTE : We cannot bring the controller online before setting
1112 * the CHBA, hence main controller initialization is done as
1113 * part of the port_start() callback
1114 */
1115
1116 /* ack. any pending IRQs for this controller/port */
1117 temp = ioread32(hcr_base + HSTATUS);
1118 if (temp & 0x3F)
1119 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
1120
1121 /* Keep interrupts disabled on the controller */
1122 temp = ioread32(hcr_base + HCONTROL);
1123 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
1124
1125 /* Disable interrupt coalescing control(icc), for the moment */
1126 DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC));
1127 iowrite32(0x01000000, hcr_base + ICC);
1128
1129 /* clear error registers, SError is cleared by libATA */
1130 iowrite32(0x00000FFFF, hcr_base + CE);
1131 iowrite32(0x00000FFFF, hcr_base + DE);
1132
1133 /* initially assuming no Port multiplier, set CQPMP to 0 */
1134 iowrite32(0x0, hcr_base + CQPMP);
1135
1136 /*
1137 * host controller will be brought on-line, during xx_port_start()
1138 * callback, that should also initiate the OOB, COMINIT sequence
1139 */
1140
1141 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
1142 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
1143
1144 return 0;
1145 }
1146
1147 /*
1148 * scsi mid-layer and libata interface structures
1149 */
1150 static struct scsi_host_template sata_fsl_sht = {
1151 ATA_NCQ_SHT("sata_fsl"),
1152 .can_queue = SATA_FSL_QUEUE_DEPTH,
1153 .sg_tablesize = SATA_FSL_MAX_PRD_USABLE,
1154 .dma_boundary = ATA_DMA_BOUNDARY,
1155 };
1156
1157 static const struct ata_port_operations sata_fsl_ops = {
1158 .inherits = &sata_port_ops,
1159
1160 .qc_prep = sata_fsl_qc_prep,
1161 .qc_issue = sata_fsl_qc_issue,
1162 .qc_fill_rtf = sata_fsl_qc_fill_rtf,
1163
1164 .scr_read = sata_fsl_scr_read,
1165 .scr_write = sata_fsl_scr_write,
1166
1167 .freeze = sata_fsl_freeze,
1168 .thaw = sata_fsl_thaw,
1169 .prereset = sata_fsl_prereset,
1170 .softreset = sata_fsl_softreset,
1171 .post_internal_cmd = sata_fsl_post_internal_cmd,
1172
1173 .port_start = sata_fsl_port_start,
1174 .port_stop = sata_fsl_port_stop,
1175 };
1176
1177 static const struct ata_port_info sata_fsl_port_info[] = {
1178 {
1179 .flags = SATA_FSL_HOST_FLAGS,
1180 .pio_mask = 0x1f, /* pio 0-4 */
1181 .udma_mask = 0x7f, /* udma 0-6 */
1182 .port_ops = &sata_fsl_ops,
1183 },
1184 };
1185
1186 static int sata_fsl_probe(struct of_device *ofdev,
1187 const struct of_device_id *match)
1188 {
1189 int retval = 0;
1190 void __iomem *hcr_base = NULL;
1191 void __iomem *ssr_base = NULL;
1192 void __iomem *csr_base = NULL;
1193 struct sata_fsl_host_priv *host_priv = NULL;
1194 int irq;
1195 struct ata_host *host;
1196
1197 struct ata_port_info pi = sata_fsl_port_info[0];
1198 const struct ata_port_info *ppi[] = { &pi, NULL };
1199
1200 dev_printk(KERN_INFO, &ofdev->dev,
1201 "Sata FSL Platform/CSB Driver init\n");
1202
1203 hcr_base = of_iomap(ofdev->node, 0);
1204 if (!hcr_base)
1205 goto error_exit_with_cleanup;
1206
1207 ssr_base = hcr_base + 0x100;
1208 csr_base = hcr_base + 0x140;
1209
1210 DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG));
1211 DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc));
1212 DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE);
1213
1214 host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL);
1215 if (!host_priv)
1216 goto error_exit_with_cleanup;
1217
1218 host_priv->hcr_base = hcr_base;
1219 host_priv->ssr_base = ssr_base;
1220 host_priv->csr_base = csr_base;
1221
1222 irq = irq_of_parse_and_map(ofdev->node, 0);
1223 if (irq < 0) {
1224 dev_printk(KERN_ERR, &ofdev->dev, "invalid irq from platform\n");
1225 goto error_exit_with_cleanup;
1226 }
1227 host_priv->irq = irq;
1228
1229 /* allocate host structure */
1230 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS);
1231
1232 /* host->iomap is not used currently */
1233 host->private_data = host_priv;
1234
1235 /* initialize host controller */
1236 sata_fsl_init_controller(host);
1237
1238 /*
1239 * Now, register with libATA core, this will also initiate the
1240 * device discovery process, invoking our port_start() handler &
1241 * error_handler() to execute a dummy Softreset EH session
1242 */
1243 ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG,
1244 &sata_fsl_sht);
1245
1246 dev_set_drvdata(&ofdev->dev, host);
1247
1248 return 0;
1249
1250 error_exit_with_cleanup:
1251
1252 if (hcr_base)
1253 iounmap(hcr_base);
1254 if (host_priv)
1255 kfree(host_priv);
1256
1257 return retval;
1258 }
1259
1260 static int sata_fsl_remove(struct of_device *ofdev)
1261 {
1262 struct ata_host *host = dev_get_drvdata(&ofdev->dev);
1263 struct sata_fsl_host_priv *host_priv = host->private_data;
1264
1265 ata_host_detach(host);
1266
1267 dev_set_drvdata(&ofdev->dev, NULL);
1268
1269 irq_dispose_mapping(host_priv->irq);
1270 iounmap(host_priv->hcr_base);
1271 kfree(host_priv);
1272
1273 return 0;
1274 }
1275
1276 static struct of_device_id fsl_sata_match[] = {
1277 {
1278 .compatible = "fsl,pq-sata",
1279 },
1280 {},
1281 };
1282
1283 MODULE_DEVICE_TABLE(of, fsl_sata_match);
1284
1285 static struct of_platform_driver fsl_sata_driver = {
1286 .name = "fsl-sata",
1287 .match_table = fsl_sata_match,
1288 .probe = sata_fsl_probe,
1289 .remove = sata_fsl_remove,
1290 };
1291
1292 static int __init sata_fsl_init(void)
1293 {
1294 of_register_platform_driver(&fsl_sata_driver);
1295 return 0;
1296 }
1297
1298 static void __exit sata_fsl_exit(void)
1299 {
1300 of_unregister_platform_driver(&fsl_sata_driver);
1301 }
1302
1303 MODULE_LICENSE("GPL");
1304 MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor");
1305 MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver");
1306 MODULE_VERSION("1.10");
1307
1308 module_init(sata_fsl_init);
1309 module_exit(sata_fsl_exit);
Support for the Chinese Samsung S3C2440 based development boards