include/asm-x86_64/processor.h

   1 /*
   2  * include/asm-x86_64/processor.h
   3  *
   4  * Copyright (C) 1994 Linus Torvalds
   5  */
   6
   7 #ifndef __ASM_X86_64_PROCESSOR_H
   8 #define __ASM_X86_64_PROCESSOR_H
   9
  10 #include <asm/segment.h>
  11 #include <asm/page.h>
  12 #include <asm/types.h>
  13 #include <asm/sigcontext.h>
  14 #include <asm/cpufeature.h>
  15 #include <linux/config.h>
  16 #include <linux/threads.h>
  17 #include <asm/msr.h>
  18 #include <asm/current.h>
  19 #include <asm/system.h>
  20 #include <asm/mmsegment.h>
  21 #include <asm/percpu.h>
  22 #include <linux/personality.h>
  23 #include <linux/cpumask.h>
  24
  25 #define TF_MASK         0x00000100
  26 #define IF_MASK         0x00000200
  27 #define IOPL_MASK       0x00003000
  28 #define NT_MASK         0x00004000
  29 #define VM_MASK         0x00020000
  30 #define AC_MASK         0x00040000
  31 #define VIF_MASK        0x00080000      /* virtual interrupt flag */
  32 #define VIP_MASK        0x00100000      /* virtual interrupt pending */
  33 #define ID_MASK         0x00200000
  34
  35 #define desc_empty(desc) \
  36                (!((desc)->a | (desc)->b))
  37
  38 #define desc_equal(desc1, desc2) \
  39                (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
  40
  41 /*
  42  * Default implementation of macro that returns current
  43  * instruction pointer ("program counter").
  44  */
  45 #define current_text_addr() ({ void *pc; asm volatile("leaq 1f(%%rip),%0\n1:":"=r"(pc)); pc; })
  46
  47 /*
  48  *  CPU type and hardware bug flags. Kept separately for each CPU.
  49  */
  50
  51 struct cpuinfo_x86 {
  52         __u8    x86;            /* CPU family */
  53         __u8    x86_vendor;     /* CPU vendor */
  54         __u8    x86_model;
  55         __u8    x86_mask;
  56         int     cpuid_level;    /* Maximum supported CPUID level, -1=no CPUID */
  57         __u32   x86_capability[NCAPINTS];
  58         char    x86_vendor_id[16];
  59         char    x86_model_id[64];
  60         int     x86_cache_size;  /* in KB */
  61         int     x86_clflush_size;
  62         int     x86_cache_alignment;
  63         int     x86_tlbsize;    /* number of 4K pages in DTLB/ITLB combined(in pages)*/
  64         __u8    x86_virt_bits, x86_phys_bits;
  65         __u8    x86_max_cores;  /* cpuid returned max cores value */
  66         __u32   x86_power;
  67         __u32   extended_cpuid_level;   /* Max extended CPUID function supported */
  68         unsigned long loops_per_jiffy;
  69 #ifdef CONFIG_SMP
  70         cpumask_t llc_shared_map;       /* cpus sharing the last level cache */
  71 #endif
  72         __u8    apicid;
  73         __u8    booted_cores;   /* number of cores as seen by OS */
  74 } ____cacheline_aligned;
  75
  76 #define X86_VENDOR_INTEL 0
  77 #define X86_VENDOR_CYRIX 1
  78 #define X86_VENDOR_AMD 2
  79 #define X86_VENDOR_UMC 3
  80 #define X86_VENDOR_NEXGEN 4
  81 #define X86_VENDOR_CENTAUR 5
  82 #define X86_VENDOR_RISE 6
  83 #define X86_VENDOR_TRANSMETA 7
  84 #define X86_VENDOR_NUM 8
  85 #define X86_VENDOR_UNKNOWN 0xff
  86
  87 #ifdef CONFIG_SMP
  88 extern struct cpuinfo_x86 cpu_data[];
  89 #define current_cpu_data cpu_data[smp_processor_id()]
  90 #else
  91 #define cpu_data (&boot_cpu_data)
  92 #define current_cpu_data boot_cpu_data
  93 #endif
  94
  95 extern char ignore_irq13;
  96
  97 extern void identify_cpu(struct cpuinfo_x86 *);
  98 extern void print_cpu_info(struct cpuinfo_x86 *);
  99 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 100
 101 /*
 102  * EFLAGS bits
 103  */
 104 #define X86_EFLAGS_CF   0x00000001 /* Carry Flag */
 105 #define X86_EFLAGS_PF   0x00000004 /* Parity Flag */
 106 #define X86_EFLAGS_AF   0x00000010 /* Auxillary carry Flag */
 107 #define X86_EFLAGS_ZF   0x00000040 /* Zero Flag */
 108 #define X86_EFLAGS_SF   0x00000080 /* Sign Flag */
 109 #define X86_EFLAGS_TF   0x00000100 /* Trap Flag */
 110 #define X86_EFLAGS_IF   0x00000200 /* Interrupt Flag */
 111 #define X86_EFLAGS_DF   0x00000400 /* Direction Flag */
 112 #define X86_EFLAGS_OF   0x00000800 /* Overflow Flag */
 113 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
 114 #define X86_EFLAGS_NT   0x00004000 /* Nested Task */
 115 #define X86_EFLAGS_RF   0x00010000 /* Resume Flag */
 116 #define X86_EFLAGS_VM   0x00020000 /* Virtual Mode */
 117 #define X86_EFLAGS_AC   0x00040000 /* Alignment Check */
 118 #define X86_EFLAGS_VIF  0x00080000 /* Virtual Interrupt Flag */
 119 #define X86_EFLAGS_VIP  0x00100000 /* Virtual Interrupt Pending */
 120 #define X86_EFLAGS_ID   0x00200000 /* CPUID detection flag */
 121
 122 /*
 123  * Intel CPU features in CR4
 124  */
 125 #define X86_CR4_VME             0x0001  /* enable vm86 extensions */
 126 #define X86_CR4_PVI             0x0002  /* virtual interrupts flag enable */
 127 #define X86_CR4_TSD             0x0004  /* disable time stamp at ipl 3 */
 128 #define X86_CR4_DE              0x0008  /* enable debugging extensions */
 129 #define X86_CR4_PSE             0x0010  /* enable page size extensions */
 130 #define X86_CR4_PAE             0x0020  /* enable physical address extensions */
 131 #define X86_CR4_MCE             0x0040  /* Machine check enable */
 132 #define X86_CR4_PGE             0x0080  /* enable global pages */
 133 #define X86_CR4_PCE             0x0100  /* enable performance counters at ipl 3 */
 134 #define X86_CR4_OSFXSR          0x0200  /* enable fast FPU save and restore */
 135 #define X86_CR4_OSXMMEXCPT      0x0400  /* enable unmasked SSE exceptions */
 136
 137 /*
 138  * Save the cr4 feature set we're using (ie
 139  * Pentium 4MB enable and PPro Global page
 140  * enable), so that any CPU's that boot up
 141  * after us can get the correct flags.
 142  */
 143 extern unsigned long mmu_cr4_features;
 144
 145 static inline void set_in_cr4 (unsigned long mask)
 146 {
 147         mmu_cr4_features |= mask;
 148         __asm__("movq %%cr4,%%rax\n\t"
 149                 "orq %0,%%rax\n\t"
 150                 "movq %%rax,%%cr4\n"
 151                 : : "irg" (mask)
 152                 :"ax");
 153 }
 154
 155 static inline void clear_in_cr4 (unsigned long mask)
 156 {
 157         mmu_cr4_features &= ~mask;
 158         __asm__("movq %%cr4,%%rax\n\t"
 159                 "andq %0,%%rax\n\t"
 160                 "movq %%rax,%%cr4\n"
 161                 : : "irg" (~mask)
 162                 :"ax");
 163 }
 164
 165
 166 /*
 167  * User space process size. 47bits minus one guard page.
 168  */
 169 #define TASK_SIZE64     (0x800000000000UL - 4096)
 170
 171 /* This decides where the kernel will search for a free chunk of vm
 172  * space during mmap's.
 173  */
 174 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? 0xc0000000 : 0xFFFFe000)
 175
 176 #define TASK_SIZE               (test_thread_flag(TIF_IA32) ? IA32_PAGE_OFFSET : TASK_SIZE64)
 177 #define TASK_SIZE_OF(child)     ((test_tsk_thread_flag(child, TIF_IA32)) ? IA32_PAGE_OFFSET : TASK_SIZE64)
 178
 179 #define TASK_UNMAPPED_BASE      PAGE_ALIGN(TASK_SIZE/3)
 180
 181 /*
 182  * Size of io_bitmap.
 183  */
 184 #define IO_BITMAP_BITS  65536
 185 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
 186 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
 187 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
 188 #define INVALID_IO_BITMAP_OFFSET 0x8000
 189
 190 struct i387_fxsave_struct {
 191         u16     cwd;
 192         u16     swd;
 193         u16     twd;
 194         u16     fop;
 195         u64     rip;
 196         u64     rdp;
 197         u32     mxcsr;
 198         u32     mxcsr_mask;
 199         u32     st_space[32];   /* 8*16 bytes for each FP-reg = 128 bytes */
 200         u32     xmm_space[64];  /* 16*16 bytes for each XMM-reg = 128 bytes */
 201         u32     padding[24];
 202 } __attribute__ ((aligned (16)));
 203
 204 union i387_union {
 205         struct i387_fxsave_struct       fxsave;
 206 };
 207
 208 struct tss_struct {
 209         u32 reserved1;
 210         u64 rsp0;
 211         u64 rsp1;
 212         u64 rsp2;
 213         u64 reserved2;
 214         u64 ist[7];
 215         u32 reserved3;
 216         u32 reserved4;
 217         u16 reserved5;
 218         u16 io_bitmap_base;
 219         /*
 220          * The extra 1 is there because the CPU will access an
 221          * additional byte beyond the end of the IO permission
 222          * bitmap. The extra byte must be all 1 bits, and must
 223          * be within the limit. Thus we have:
 224          *
 225          * 128 bytes, the bitmap itself, for ports 0..0x3ff
 226          * 8 bytes, for an extra "long" of ~0UL
 227          */
 228         unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
 229 } __attribute__((packed)) ____cacheline_aligned;
 230
 231 extern struct cpuinfo_x86 boot_cpu_data;
 232 DECLARE_PER_CPU(struct tss_struct,init_tss);
 233
 234 #ifdef CONFIG_X86_VSMP
 235 #define ARCH_MIN_TASKALIGN      (1 << INTERNODE_CACHE_SHIFT)
 236 #define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
 237 #else
 238 #define ARCH_MIN_TASKALIGN      16
 239 #define ARCH_MIN_MMSTRUCT_ALIGN 0
 240 #endif
 241
 242 struct thread_struct {
 243         unsigned long   rsp0;
 244         unsigned long   rsp;
 245         unsigned long   userrsp;        /* Copy from PDA */
 246         unsigned long   fs;
 247         unsigned long   gs;
 248         unsigned short  es, ds, fsindex, gsindex;
 249 /* Hardware debugging registers */
 250         unsigned long   debugreg0;
 251         unsigned long   debugreg1;
 252         unsigned long   debugreg2;
 253         unsigned long   debugreg3;
 254         unsigned long   debugreg6;
 255         unsigned long   debugreg7;
 256 /* fault info */
 257         unsigned long   cr2, trap_no, error_code;
 258 /* floating point info */
 259         union i387_union        i387  __attribute__((aligned(16)));
 260 /* IO permissions. the bitmap could be moved into the GDT, that would make
 261    switch faster for a limited number of ioperm using tasks. -AK */
 262         int             ioperm;
 263         unsigned long   *io_bitmap_ptr;
 264         unsigned io_bitmap_max;
 265 /* cached TLS descriptors. */
 266         u64 tls_array[GDT_ENTRY_TLS_ENTRIES];
 267 } __attribute__((aligned(16)));
 268
 269 #define INIT_THREAD  { \
 270         .rsp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 271 }
 272
 273 #define INIT_TSS  { \
 274         .rsp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 275 }
 276
 277 #define INIT_MMAP \
 278 { &init_mm, 0, 0, NULL, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL }
 279
 280 #define start_thread(regs,new_rip,new_rsp) do { \
 281         asm volatile("movl %0,%%fs; movl %0,%%es; movl %0,%%ds": :"r" (0));      \
 282         load_gs_index(0);                                                       \
 283         (regs)->rip = (new_rip);                                                 \
 284         (regs)->rsp = (new_rsp);                                                 \
 285         write_pda(oldrsp, (new_rsp));                                            \
 286         (regs)->cs = __USER_CS;                                                  \
 287         (regs)->ss = __USER_DS;                                                  \
 288         (regs)->eflags = 0x200;                                                  \
 289         set_fs(USER_DS);                                                         \
 290 } while(0)
 291
 292 #define get_debugreg(var, register)                             \
 293                 __asm__("movq %%db" #register ", %0"            \
 294                         :"=r" (var))
 295 #define set_debugreg(value, register)                   \
 296                 __asm__("movq %0,%%db" #register                \
 297                         : /* no output */                       \
 298                         :"r" (value))
 299
 300 struct task_struct;
 301 struct mm_struct;
 302
 303 /* Free all resources held by a thread. */
 304 extern void release_thread(struct task_struct *);
 305
 306 /* Prepare to copy thread state - unlazy all lazy status */
 307 extern void prepare_to_copy(struct task_struct *tsk);
 308
 309 /*
 310  * create a kernel thread without removing it from tasklists
 311  */
 312 extern long kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
 313
 314 /*
 315  * Return saved PC of a blocked thread.
 316  * What is this good for? it will be always the scheduler or ret_from_fork.
 317  */
 318 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.rsp - 8))
 319
 320 extern unsigned long get_wchan(struct task_struct *p);
 321 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.rsp0 - 1)
 322 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->rip)
 323 #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
 324
 325
 326 struct microcode_header {
 327         unsigned int hdrver;
 328         unsigned int rev;
 329         unsigned int date;
 330         unsigned int sig;
 331         unsigned int cksum;
 332         unsigned int ldrver;
 333         unsigned int pf;
 334         unsigned int datasize;
 335         unsigned int totalsize;
 336         unsigned int reserved[3];
 337 };
 338
 339 struct microcode {
 340         struct microcode_header hdr;
 341         unsigned int bits[0];
 342 };
 343
 344 typedef struct microcode microcode_t;
 345 typedef struct microcode_header microcode_header_t;
 346
 347 /* microcode format is extended from prescott processors */
 348 struct extended_signature {
 349         unsigned int sig;
 350         unsigned int pf;
 351         unsigned int cksum;
 352 };
 353
 354 struct extended_sigtable {
 355         unsigned int count;
 356         unsigned int cksum;
 357         unsigned int reserved[3];
 358         struct extended_signature sigs[0];
 359 };
 360
 361
 362 #define ASM_NOP1 K8_NOP1
 363 #define ASM_NOP2 K8_NOP2
 364 #define ASM_NOP3 K8_NOP3
 365 #define ASM_NOP4 K8_NOP4
 366 #define ASM_NOP5 K8_NOP5
 367 #define ASM_NOP6 K8_NOP6
 368 #define ASM_NOP7 K8_NOP7
 369 #define ASM_NOP8 K8_NOP8
 370
 371 /* Opteron nops */
 372 #define K8_NOP1 ".byte 0x90\n"
 373 #define K8_NOP2 ".byte 0x66,0x90\n"
 374 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
 375 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
 376 #define K8_NOP5 K8_NOP3 K8_NOP2
 377 #define K8_NOP6 K8_NOP3 K8_NOP3
 378 #define K8_NOP7 K8_NOP4 K8_NOP3
 379 #define K8_NOP8 K8_NOP4 K8_NOP4
 380
 381 #define ASM_NOP_MAX 8
 382
 383 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
 384 static inline void rep_nop(void)
 385 {
 386         __asm__ __volatile__("rep;nop": : :"memory");
 387 }
 388
 389 /* Stop speculative execution */
 390 static inline void sync_core(void)
 391 {
 392         int tmp;
 393         asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
 394 }
 395
 396 #define cpu_has_fpu 1
 397
 398 #define ARCH_HAS_PREFETCH
 399 static inline void prefetch(void *x)
 400 {
 401         asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
 402 }
 403
 404 #define ARCH_HAS_PREFETCHW 1
 405 static inline void prefetchw(void *x)
 406 {
 407         alternative_input("prefetcht0 (%1)",
 408                           "prefetchw (%1)",
 409                           X86_FEATURE_3DNOW,
 410                           "r" (x));
 411 }
 412
 413 #define ARCH_HAS_SPINLOCK_PREFETCH 1
 414
 415 #define spin_lock_prefetch(x)  prefetchw(x)
 416
 417 #define cpu_relax()   rep_nop()
 418
 419 /*
 420  *      NSC/Cyrix CPU configuration register indexes
 421  */
 422 #define CX86_CCR0 0xc0
 423 #define CX86_CCR1 0xc1
 424 #define CX86_CCR2 0xc2
 425 #define CX86_CCR3 0xc3
 426 #define CX86_CCR4 0xe8
 427 #define CX86_CCR5 0xe9
 428 #define CX86_CCR6 0xea
 429 #define CX86_CCR7 0xeb
 430 #define CX86_DIR0 0xfe
 431 #define CX86_DIR1 0xff
 432 #define CX86_ARR_BASE 0xc4
 433 #define CX86_RCR_BASE 0xdc
 434
 435 /*
 436  *      NSC/Cyrix CPU indexed register access macros
 437  */
 438
 439 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
 440
 441 #define setCx86(reg, data) do { \
 442         outb((reg), 0x22); \
 443         outb((data), 0x23); \
 444 } while (0)
 445
 446 static inline void serialize_cpu(void)
 447 {
 448         __asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx");
 449 }
 450
 451 static inline void __monitor(const void *eax, unsigned long ecx,
 452                 unsigned long edx)
 453 {
 454         /* "monitor %eax,%ecx,%edx;" */
 455         asm volatile(
 456                 ".byte 0x0f,0x01,0xc8;"
 457                 : :"a" (eax), "c" (ecx), "d"(edx));
 458 }
 459
 460 static inline void __mwait(unsigned long eax, unsigned long ecx)
 461 {
 462         /* "mwait %eax,%ecx;" */
 463         asm volatile(
 464                 ".byte 0x0f,0x01,0xc9;"
 465                 : :"a" (eax), "c" (ecx));
 466 }
 467
 468 #define stack_current() \
 469 ({                                                              \
 470         struct thread_info *ti;                                 \
 471         asm("andq %%rsp,%0; ":"=r" (ti) : "0" (CURRENT_MASK));  \
 472         ti->task;                                       \
 473 })
 474
 475 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
 476
 477 extern unsigned long boot_option_idle_override;
 478 /* Boot loader type from the setup header */
 479 extern int bootloader_type;
 480
 481 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
 482
 483 #endif /* __ASM_X86_64_PROCESSOR_H */