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Ath5k: unify resets
[linux-2.6/mini2440.git] / drivers / pcmcia / au1000_pb1x00.c
blobaa1cd4d3aa292c4e840a4b09471b6068a81f9385
1 /*
2 *
3 * Alchemy Semi Pb1x00 boards specific pcmcia routines.
4 *
5 * Copyright 2002 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ppopov@mvista.com or source@mvista.com
8 *
9 * ########################################################################
10 *
11 * This program is free software; you can distribute it and/or modify it
12 * under the terms of the GNU General Public License (Version 2) as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
23 */
24 #include <linux/module.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/ioport.h>
28 #include <linux/kernel.h>
29 #include <linux/tqueue.h>
30 #include <linux/timer.h>
31 #include <linux/mm.h>
32 #include <linux/proc_fs.h>
33 #include <linux/types.h>
34
35 #include <pcmcia/cs_types.h>
36 #include <pcmcia/cs.h>
37 #include <pcmcia/ss.h>
38 #include <pcmcia/cistpl.h>
39 #include <pcmcia/bus_ops.h>
40 #include "cs_internal.h"
41
42 #include <asm/io.h>
43 #include <asm/irq.h>
44 #include <asm/system.h>
45
46 #include <asm/au1000.h>
47 #include <asm/au1000_pcmcia.h>
48
49 #define debug(fmt, arg...) do { } while (0)
50
51 #ifdef CONFIG_MIPS_PB1000
52 #include <asm/pb1000.h>
53 #define PCMCIA_IRQ AU1000_GPIO_15
54 #elif defined (CONFIG_MIPS_PB1500)
55 #include <asm/pb1500.h>
56 #define PCMCIA_IRQ AU1500_GPIO_203
57 #elif defined (CONFIG_MIPS_PB1100)
58 #include <asm/pb1100.h>
59 #define PCMCIA_IRQ AU1000_GPIO_11
60 #endif
61
62 static int pb1x00_pcmcia_init(struct pcmcia_init *init)
63 {
64 #ifdef CONFIG_MIPS_PB1000
65 u16 pcr;
66 pcr = PCR_SLOT_0_RST | PCR_SLOT_1_RST;
67
68 au_writel(0x8000, PB1000_MDR); /* clear pcmcia interrupt */
69 au_sync_delay(100);
70 au_writel(0x4000, PB1000_MDR); /* enable pcmcia interrupt */
71 au_sync();
72
73 pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,0);
74 pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,1);
75 au_writel(pcr, PB1000_PCR);
76 au_sync_delay(20);
77
78 return PCMCIA_NUM_SOCKS;
79
80 #else /* fixme -- take care of the Pb1500 at some point */
81
82 u16 pcr;
83 pcr = au_readw(PCMCIA_BOARD_REG) & ~0xf; /* turn off power */
84 pcr &= ~(PC_DEASSERT_RST | PC_DRV_EN);
85 au_writew(pcr, PCMCIA_BOARD_REG);
86 au_sync_delay(500);
87 return PCMCIA_NUM_SOCKS;
88 #endif
89 }
90
91 static int pb1x00_pcmcia_shutdown(void)
92 {
93 #ifdef CONFIG_MIPS_PB1000
94 u16 pcr;
95 pcr = PCR_SLOT_0_RST | PCR_SLOT_1_RST;
96 pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,0);
97 pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,1);
98 au_writel(pcr, PB1000_PCR);
99 au_sync_delay(20);
100 return 0;
101 #else
102 u16 pcr;
103 pcr = au_readw(PCMCIA_BOARD_REG) & ~0xf; /* turn off power */
104 pcr &= ~(PC_DEASSERT_RST | PC_DRV_EN);
105 au_writew(pcr, PCMCIA_BOARD_REG);
106 au_sync_delay(2);
107 return 0;
108 #endif
109 }
110
111 static int
112 pb1x00_pcmcia_socket_state(unsigned sock, struct pcmcia_state *state)
113 {
114 u32 inserted0, inserted1;
115 u16 vs0, vs1;
116
117 #ifdef CONFIG_MIPS_PB1000
118 vs0 = vs1 = (u16)au_readl(PB1000_ACR1);
119 inserted0 = !(vs0 & (ACR1_SLOT_0_CD1 | ACR1_SLOT_0_CD2));
120 inserted1 = !(vs1 & (ACR1_SLOT_1_CD1 | ACR1_SLOT_1_CD2));
121 vs0 = (vs0 >> 4) & 0x3;
122 vs1 = (vs1 >> 12) & 0x3;
123 #else
124 vs0 = (au_readw(BOARD_STATUS_REG) >> 4) & 0x3;
125 #ifdef CONFIG_MIPS_PB1500
126 inserted0 = !((au_readl(GPIO2_PINSTATE) >> 1) & 0x1); /* gpio 201 */
127 #else /* Pb1100 */
128 inserted0 = !((au_readl(SYS_PINSTATERD) >> 9) & 0x1); /* gpio 9 */
129 #endif
130 inserted1 = 0;
131 #endif
132
133 state->ready = 0;
134 state->vs_Xv = 0;
135 state->vs_3v = 0;
136 state->detect = 0;
137
138 if (sock == 0) {
139 if (inserted0) {
140 switch (vs0) {
141 case 0:
142 case 2:
143 state->vs_3v=1;
144 break;
145 case 3: /* 5V */
146 break;
147 default:
148 /* return without setting 'detect' */
149 printk(KERN_ERR "pb1x00 bad VS (%d)\n",
150 vs0);
151 return 0;
152 }
153 state->detect = 1;
154 }
155 }
156 else {
157 if (inserted1) {
158 switch (vs1) {
159 case 0:
160 case 2:
161 state->vs_3v=1;
162 break;
163 case 3: /* 5V */
164 break;
165 default:
166 /* return without setting 'detect' */
167 printk(KERN_ERR "pb1x00 bad VS (%d)\n",
168 vs1);
169 return 0;
170 }
171 state->detect = 1;
172 }
173 }
174
175 if (state->detect) {
176 state->ready = 1;
177 }
178
179 state->bvd1=1;
180 state->bvd2=1;
181 state->wrprot=0;
182 return 1;
183 }
184
185
186 static int pb1x00_pcmcia_get_irq_info(struct pcmcia_irq_info *info)
187 {
188
189 if(info->sock > PCMCIA_MAX_SOCK) return -1;
190
191 /*
192 * Even in the case of the Pb1000, both sockets are connected
193 * to the same irq line.
194 */
195 info->irq = PCMCIA_IRQ;
196
197 return 0;
198 }
199
200
201 static int
202 pb1x00_pcmcia_configure_socket(const struct pcmcia_configure *configure)
203 {
204 u16 pcr;
205
206 if(configure->sock > PCMCIA_MAX_SOCK) return -1;
207
208 #ifdef CONFIG_MIPS_PB1000
209 pcr = au_readl(PB1000_PCR);
210
211 if (configure->sock == 0) {
212 pcr &= ~(PCR_SLOT_0_VCC0 | PCR_SLOT_0_VCC1 |
213 PCR_SLOT_0_VPP0 | PCR_SLOT_0_VPP1);
214 }
215 else {
216 pcr &= ~(PCR_SLOT_1_VCC0 | PCR_SLOT_1_VCC1 |
217 PCR_SLOT_1_VPP0 | PCR_SLOT_1_VPP1);
218 }
219
220 pcr &= ~PCR_SLOT_0_RST;
221 debug("Vcc %dV Vpp %dV, pcr %x\n",
222 configure->vcc, configure->vpp, pcr);
223 switch(configure->vcc){
224 case 0: /* Vcc 0 */
225 switch(configure->vpp) {
226 case 0:
227 pcr |= SET_VCC_VPP(VCC_HIZ,VPP_GND,
228 configure->sock);
229 break;
230 case 12:
231 pcr |= SET_VCC_VPP(VCC_HIZ,VPP_12V,
232 configure->sock);
233 break;
234 case 50:
235 pcr |= SET_VCC_VPP(VCC_HIZ,VPP_5V,
236 configure->sock);
237 break;
238 case 33:
239 pcr |= SET_VCC_VPP(VCC_HIZ,VPP_3V,
240 configure->sock);
241 break;
242 default:
243 pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,
244 configure->sock);
245 printk("%s: bad Vcc/Vpp (%d:%d)\n",
246 __func__,
247 configure->vcc,
248 configure->vpp);
249 break;
250 }
251 break;
252 case 50: /* Vcc 5V */
253 switch(configure->vpp) {
254 case 0:
255 pcr |= SET_VCC_VPP(VCC_5V,VPP_GND,
256 configure->sock);
257 break;
258 case 50:
259 pcr |= SET_VCC_VPP(VCC_5V,VPP_5V,
260 configure->sock);
261 break;
262 case 12:
263 pcr |= SET_VCC_VPP(VCC_5V,VPP_12V,
264 configure->sock);
265 break;
266 case 33:
267 pcr |= SET_VCC_VPP(VCC_5V,VPP_3V,
268 configure->sock);
269 break;
270 default:
271 pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,
272 configure->sock);
273 printk("%s: bad Vcc/Vpp (%d:%d)\n",
274 __func__,
275 configure->vcc,
276 configure->vpp);
277 break;
278 }
279 break;
280 case 33: /* Vcc 3.3V */
281 switch(configure->vpp) {
282 case 0:
283 pcr |= SET_VCC_VPP(VCC_3V,VPP_GND,
284 configure->sock);
285 break;
286 case 50:
287 pcr |= SET_VCC_VPP(VCC_3V,VPP_5V,
288 configure->sock);
289 break;
290 case 12:
291 pcr |= SET_VCC_VPP(VCC_3V,VPP_12V,
292 configure->sock);
293 break;
294 case 33:
295 pcr |= SET_VCC_VPP(VCC_3V,VPP_3V,
296 configure->sock);
297 break;
298 default:
299 pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,
300 configure->sock);
301 printk("%s: bad Vcc/Vpp (%d:%d)\n",
302 __func__,
303 configure->vcc,
304 configure->vpp);
305 break;
306 }
307 break;
308 default: /* what's this ? */
309 pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,configure->sock);
310 printk(KERN_ERR "%s: bad Vcc %d\n",
311 __func__, configure->vcc);
312 break;
313 }
314
315 if (configure->sock == 0) {
316 pcr &= ~(PCR_SLOT_0_RST);
317 if (configure->reset)
318 pcr |= PCR_SLOT_0_RST;
319 }
320 else {
321 pcr &= ~(PCR_SLOT_1_RST);
322 if (configure->reset)
323 pcr |= PCR_SLOT_1_RST;
324 }
325 au_writel(pcr, PB1000_PCR);
326 au_sync_delay(300);
327
328 #else
329
330 pcr = au_readw(PCMCIA_BOARD_REG) & ~0xf;
331
332 debug("Vcc %dV Vpp %dV, pcr %x, reset %d\n",
333 configure->vcc, configure->vpp, pcr, configure->reset);
334
335
336 switch(configure->vcc){
337 case 0: /* Vcc 0 */
338 pcr |= SET_VCC_VPP(0,0);
339 break;
340 case 50: /* Vcc 5V */
341 switch(configure->vpp) {
342 case 0:
343 pcr |= SET_VCC_VPP(2,0);
344 break;
345 case 50:
346 pcr |= SET_VCC_VPP(2,1);
347 break;
348 case 12:
349 pcr |= SET_VCC_VPP(2,2);
350 break;
351 case 33:
352 default:
353 pcr |= SET_VCC_VPP(0,0);
354 printk("%s: bad Vcc/Vpp (%d:%d)\n",
355 __func__,
356 configure->vcc,
357 configure->vpp);
358 break;
359 }
360 break;
361 case 33: /* Vcc 3.3V */
362 switch(configure->vpp) {
363 case 0:
364 pcr |= SET_VCC_VPP(1,0);
365 break;
366 case 12:
367 pcr |= SET_VCC_VPP(1,2);
368 break;
369 case 33:
370 pcr |= SET_VCC_VPP(1,1);
371 break;
372 case 50:
373 default:
374 pcr |= SET_VCC_VPP(0,0);
375 printk("%s: bad Vcc/Vpp (%d:%d)\n",
376 __func__,
377 configure->vcc,
378 configure->vpp);
379 break;
380 }
381 break;
382 default: /* what's this ? */
383 pcr |= SET_VCC_VPP(0,0);
384 printk(KERN_ERR "%s: bad Vcc %d\n",
385 __func__, configure->vcc);
386 break;
387 }
388
389 au_writew(pcr, PCMCIA_BOARD_REG);
390 au_sync_delay(300);
391
392 if (!configure->reset) {
393 pcr |= PC_DRV_EN;
394 au_writew(pcr, PCMCIA_BOARD_REG);
395 au_sync_delay(100);
396 pcr |= PC_DEASSERT_RST;
397 au_writew(pcr, PCMCIA_BOARD_REG);
398 au_sync_delay(100);
399 }
400 else {
401 pcr &= ~(PC_DEASSERT_RST | PC_DRV_EN);
402 au_writew(pcr, PCMCIA_BOARD_REG);
403 au_sync_delay(100);
404 }
405 #endif
406 return 0;
407 }
408
409
410 struct pcmcia_low_level pb1x00_pcmcia_ops = {
411 pb1x00_pcmcia_init,
412 pb1x00_pcmcia_shutdown,
413 pb1x00_pcmcia_socket_state,
414 pb1x00_pcmcia_get_irq_info,
415 pb1x00_pcmcia_configure_socket
416 };
Support for the Chinese Samsung S3C2440 based development boards