arch/mips/kernel/i8259.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Code to handle x86 style IRQs plus some generic interrupt stuff.
   7  *
   8  * Copyright (C) 1992 Linus Torvalds
   9  * Copyright (C) 1994 - 2000 Ralf Baechle
  10  */
  11 #include <linux/delay.h>
  12 #include <linux/init.h>
  13 #include <linux/ioport.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/kernel.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/sysdev.h>
  18
  19 #include <asm/i8259.h>
  20 #include <asm/io.h>
  21
  22 /*
  23  * This is the 'legacy' 8259A Programmable Interrupt Controller,
  24  * present in the majority of PC/AT boxes.
  25  * plus some generic x86 specific things if generic specifics makes
  26  * any sense at all.
  27  * this file should become arch/i386/kernel/irq.c when the old irq.c
  28  * moves to arch independent land
  29  */
  30
  31 static int i8259A_auto_eoi = -1;
  32 DEFINE_SPINLOCK(i8259A_lock);
  33 /* some platforms call this... */
  34 void mask_and_ack_8259A(unsigned int);
  35
  36 static struct irq_chip i8259A_chip = {
  37         .name           = "XT-PIC",
  38         .mask           = disable_8259A_irq,
  39         .disable        = disable_8259A_irq,
  40         .unmask         = enable_8259A_irq,
  41         .mask_ack       = mask_and_ack_8259A,
  42 };
  43
  44 /*
  45  * 8259A PIC functions to handle ISA devices:
  46  */
  47
  48 /*
  49  * This contains the irq mask for both 8259A irq controllers,
  50  */
  51 static unsigned int cached_irq_mask = 0xffff;
  52
  53 #define cached_master_mask      (cached_irq_mask)
  54 #define cached_slave_mask       (cached_irq_mask >> 8)
  55
  56 void disable_8259A_irq(unsigned int irq)
  57 {
  58         unsigned int mask;
  59         unsigned long flags;
  60
  61         irq -= I8259A_IRQ_BASE;
  62         mask = 1 << irq;
  63         spin_lock_irqsave(&i8259A_lock, flags);
  64         cached_irq_mask |= mask;
  65         if (irq & 8)
  66                 outb(cached_slave_mask, PIC_SLAVE_IMR);
  67         else
  68                 outb(cached_master_mask, PIC_MASTER_IMR);
  69         spin_unlock_irqrestore(&i8259A_lock, flags);
  70 }
  71
  72 void enable_8259A_irq(unsigned int irq)
  73 {
  74         unsigned int mask;
  75         unsigned long flags;
  76
  77         irq -= I8259A_IRQ_BASE;
  78         mask = ~(1 << irq);
  79         spin_lock_irqsave(&i8259A_lock, flags);
  80         cached_irq_mask &= mask;
  81         if (irq & 8)
  82                 outb(cached_slave_mask, PIC_SLAVE_IMR);
  83         else
  84                 outb(cached_master_mask, PIC_MASTER_IMR);
  85         spin_unlock_irqrestore(&i8259A_lock, flags);
  86 }
  87
  88 int i8259A_irq_pending(unsigned int irq)
  89 {
  90         unsigned int mask;
  91         unsigned long flags;
  92         int ret;
  93
  94         irq -= I8259A_IRQ_BASE;
  95         mask = 1 << irq;
  96         spin_lock_irqsave(&i8259A_lock, flags);
  97         if (irq < 8)
  98                 ret = inb(PIC_MASTER_CMD) & mask;
  99         else
 100                 ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
 101         spin_unlock_irqrestore(&i8259A_lock, flags);
 102
 103         return ret;
 104 }
 105
 106 void make_8259A_irq(unsigned int irq)
 107 {
 108         disable_irq_nosync(irq);
 109         set_irq_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
 110         enable_irq(irq);
 111 }
 112
 113 /*
 114  * This function assumes to be called rarely. Switching between
 115  * 8259A registers is slow.
 116  * This has to be protected by the irq controller spinlock
 117  * before being called.
 118  */
 119 static inline int i8259A_irq_real(unsigned int irq)
 120 {
 121         int value;
 122         int irqmask = 1 << irq;
 123
 124         if (irq < 8) {
 125                 outb(0x0B,PIC_MASTER_CMD);      /* ISR register */
 126                 value = inb(PIC_MASTER_CMD) & irqmask;
 127                 outb(0x0A,PIC_MASTER_CMD);      /* back to the IRR register */
 128                 return value;
 129         }
 130         outb(0x0B,PIC_SLAVE_CMD);       /* ISR register */
 131         value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
 132         outb(0x0A,PIC_SLAVE_CMD);       /* back to the IRR register */
 133         return value;
 134 }
 135
 136 /*
 137  * Careful! The 8259A is a fragile beast, it pretty
 138  * much _has_ to be done exactly like this (mask it
 139  * first, _then_ send the EOI, and the order of EOI
 140  * to the two 8259s is important!
 141  */
 142 void mask_and_ack_8259A(unsigned int irq)
 143 {
 144         unsigned int irqmask;
 145         unsigned long flags;
 146
 147         irq -= I8259A_IRQ_BASE;
 148         irqmask = 1 << irq;
 149         spin_lock_irqsave(&i8259A_lock, flags);
 150         /*
 151          * Lightweight spurious IRQ detection. We do not want
 152          * to overdo spurious IRQ handling - it's usually a sign
 153          * of hardware problems, so we only do the checks we can
 154          * do without slowing down good hardware unnecessarily.
 155          *
 156          * Note that IRQ7 and IRQ15 (the two spurious IRQs
 157          * usually resulting from the 8259A-1|2 PICs) occur
 158          * even if the IRQ is masked in the 8259A. Thus we
 159          * can check spurious 8259A IRQs without doing the
 160          * quite slow i8259A_irq_real() call for every IRQ.
 161          * This does not cover 100% of spurious interrupts,
 162          * but should be enough to warn the user that there
 163          * is something bad going on ...
 164          */
 165         if (cached_irq_mask & irqmask)
 166                 goto spurious_8259A_irq;
 167         cached_irq_mask |= irqmask;
 168
 169 handle_real_irq:
 170         if (irq & 8) {
 171                 inb(PIC_SLAVE_IMR);     /* DUMMY - (do we need this?) */
 172                 outb(cached_slave_mask, PIC_SLAVE_IMR);
 173                 outb(0x60+(irq&7),PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
 174                 outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
 175         } else {
 176                 inb(PIC_MASTER_IMR);    /* DUMMY - (do we need this?) */
 177                 outb(cached_master_mask, PIC_MASTER_IMR);
 178                 outb(0x60+irq,PIC_MASTER_CMD);  /* 'Specific EOI to master */
 179         }
 180 #ifdef CONFIG_MIPS_MT_SMTC
 181         if (irq_hwmask[irq] & ST0_IM)
 182                 set_c0_status(irq_hwmask[irq] & ST0_IM);
 183 #endif /* CONFIG_MIPS_MT_SMTC */
 184         spin_unlock_irqrestore(&i8259A_lock, flags);
 185         return;
 186
 187 spurious_8259A_irq:
 188         /*
 189          * this is the slow path - should happen rarely.
 190          */
 191         if (i8259A_irq_real(irq))
 192                 /*
 193                  * oops, the IRQ _is_ in service according to the
 194                  * 8259A - not spurious, go handle it.
 195                  */
 196                 goto handle_real_irq;
 197
 198         {
 199                 static int spurious_irq_mask;
 200                 /*
 201                  * At this point we can be sure the IRQ is spurious,
 202                  * lets ACK and report it. [once per IRQ]
 203                  */
 204                 if (!(spurious_irq_mask & irqmask)) {
 205                         printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
 206                         spurious_irq_mask |= irqmask;
 207                 }
 208                 atomic_inc(&irq_err_count);
 209                 /*
 210                  * Theoretically we do not have to handle this IRQ,
 211                  * but in Linux this does not cause problems and is
 212                  * simpler for us.
 213                  */
 214                 goto handle_real_irq;
 215         }
 216 }
 217
 218 static int i8259A_resume(struct sys_device *dev)
 219 {
 220         if (i8259A_auto_eoi >= 0)
 221                 init_8259A(i8259A_auto_eoi);
 222         return 0;
 223 }
 224
 225 static int i8259A_shutdown(struct sys_device *dev)
 226 {
 227         /* Put the i8259A into a quiescent state that
 228          * the kernel initialization code can get it
 229          * out of.
 230          */
 231         if (i8259A_auto_eoi >= 0) {
 232                 outb(0xff, PIC_MASTER_IMR);     /* mask all of 8259A-1 */
 233                 outb(0xff, PIC_SLAVE_IMR);      /* mask all of 8259A-1 */
 234         }
 235         return 0;
 236 }
 237
 238 static struct sysdev_class i8259_sysdev_class = {
 239         set_kset_name("i8259"),
 240         .resume = i8259A_resume,
 241         .shutdown = i8259A_shutdown,
 242 };
 243
 244 static struct sys_device device_i8259A = {
 245         .id     = 0,
 246         .cls    = &i8259_sysdev_class,
 247 };
 248
 249 static int __init i8259A_init_sysfs(void)
 250 {
 251         int error = sysdev_class_register(&i8259_sysdev_class);
 252         if (!error)
 253                 error = sysdev_register(&device_i8259A);
 254         return error;
 255 }
 256
 257 device_initcall(i8259A_init_sysfs);
 258
 259 void init_8259A(int auto_eoi)
 260 {
 261         unsigned long flags;
 262
 263         i8259A_auto_eoi = auto_eoi;
 264
 265         spin_lock_irqsave(&i8259A_lock, flags);
 266
 267         outb(0xff, PIC_MASTER_IMR);     /* mask all of 8259A-1 */
 268         outb(0xff, PIC_SLAVE_IMR);      /* mask all of 8259A-2 */
 269
 270         /*
 271          * outb_p - this has to work on a wide range of PC hardware.
 272          */
 273         outb_p(0x11, PIC_MASTER_CMD);   /* ICW1: select 8259A-1 init */
 274         outb_p(I8259A_IRQ_BASE + 0, PIC_MASTER_IMR);    /* ICW2: 8259A-1 IR0 mapped to I8259A_IRQ_BASE + 0x00 */
 275         outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);   /* 8259A-1 (the master) has a slave on IR2 */
 276         if (auto_eoi)   /* master does Auto EOI */
 277                 outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
 278         else            /* master expects normal EOI */
 279                 outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
 280
 281         outb_p(0x11, PIC_SLAVE_CMD);    /* ICW1: select 8259A-2 init */
 282         outb_p(I8259A_IRQ_BASE + 8, PIC_SLAVE_IMR);     /* ICW2: 8259A-2 IR0 mapped to I8259A_IRQ_BASE + 0x08 */
 283         outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR);  /* 8259A-2 is a slave on master's IR2 */
 284         outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
 285         if (auto_eoi)
 286                 /*
 287                  * In AEOI mode we just have to mask the interrupt
 288                  * when acking.
 289                  */
 290                 i8259A_chip.mask_ack = disable_8259A_irq;
 291         else
 292                 i8259A_chip.mask_ack = mask_and_ack_8259A;
 293
 294         udelay(100);            /* wait for 8259A to initialize */
 295
 296         outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
 297         outb(cached_slave_mask, PIC_SLAVE_IMR);   /* restore slave IRQ mask */
 298
 299         spin_unlock_irqrestore(&i8259A_lock, flags);
 300 }
 301
 302 /*
 303  * IRQ2 is cascade interrupt to second interrupt controller
 304  */
 305 static struct irqaction irq2 = {
 306         no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL
 307 };
 308
 309 static struct resource pic1_io_resource = {
 310         .name = "pic1",
 311         .start = PIC_MASTER_CMD,
 312         .end = PIC_MASTER_IMR,
 313         .flags = IORESOURCE_BUSY
 314 };
 315
 316 static struct resource pic2_io_resource = {
 317         .name = "pic2",
 318         .start = PIC_SLAVE_CMD,
 319         .end = PIC_SLAVE_IMR,
 320         .flags = IORESOURCE_BUSY
 321 };
 322
 323 /*
 324  * On systems with i8259-style interrupt controllers we assume for
 325  * driver compatibility reasons interrupts 0 - 15 to be the i8259
 326  * interrupts even if the hardware uses a different interrupt numbering.
 327  */
 328 void __init init_i8259_irqs (void)
 329 {
 330         int i;
 331
 332         insert_resource(&ioport_resource, &pic1_io_resource);
 333         insert_resource(&ioport_resource, &pic2_io_resource);
 334
 335         init_8259A(0);
 336
 337         for (i = I8259A_IRQ_BASE; i < I8259A_IRQ_BASE + 16; i++)
 338                 set_irq_chip_and_handler(i, &i8259A_chip, handle_level_irq);
 339
 340         setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2);
 341 }