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drivers/char/mem.c: memory_open() cleanup: lookup minor device number from devlist
[linux-2.6/mini2440.git] / drivers / net / 8139too.c
blob8ae72ec14456d4dc2e31141777a1bf35776fc78a
1 /*
2
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
7
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
11
12 -----<snip>-----
13
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41 Contributors:
42
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
45
46 Tigran Aivazian - bug fixes, skbuff free cleanup
47
48 Martin Mares - suggestions for PCI cleanup
49
50 David S. Miller - PCI DMA and softnet updates
51
52 Ernst Gill - fixes ported from BSD driver
53
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
56
57 Gerard Sharp - bug fix, testing and feedback
58
59 David Ford - Rx ring wrap fix
60
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
63
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
66
67 Santiago Garcia Mantinan - testing and feedback
68
69 Jens David - 2.2.x kernel backports
70
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
73
74 Jean-Jacques Michel - bug fix
75
76 Tobias Ringström - Rx interrupt status checking suggestion
77
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
80
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
82
83 Robert Kuebel - Save kernel thread from dying on any signal.
84
85 Submitting bug reports:
86
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
89
90 */
91
92 #define DRV_NAME "8139too"
93 #define DRV_VERSION "0.9.28"
94
95
96 #include <linux/module.h>
97 #include <linux/kernel.h>
98 #include <linux/compiler.h>
99 #include <linux/pci.h>
100 #include <linux/init.h>
101 #include <linux/netdevice.h>
102 #include <linux/etherdevice.h>
103 #include <linux/rtnetlink.h>
104 #include <linux/delay.h>
105 #include <linux/ethtool.h>
106 #include <linux/mii.h>
107 #include <linux/completion.h>
108 #include <linux/crc32.h>
109 #include <linux/io.h>
110 #include <linux/uaccess.h>
111 #include <asm/irq.h>
112
113 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
114 #define PFX DRV_NAME ": "
115
116 /* Default Message level */
117 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
118 NETIF_MSG_PROBE | \
119 NETIF_MSG_LINK)
120
121
122 /* define to 1, 2 or 3 to enable copious debugging info */
123 #define RTL8139_DEBUG 0
124
125 /* define to 1 to disable lightweight runtime debugging checks */
126 #undef RTL8139_NDEBUG
127
128
129 #ifdef RTL8139_NDEBUG
130 # define assert(expr) do {} while (0)
131 #else
132 # define assert(expr) \
133 if(unlikely(!(expr))) { \
134 pr_err("Assertion failed! %s,%s,%s,line=%d\n", \
135 #expr, __FILE__, __func__, __LINE__); \
136 }
137 #endif
138
139
140 /* A few user-configurable values. */
141 /* media options */
142 #define MAX_UNITS 8
143 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
144 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
145
146 /* Whether to use MMIO or PIO. Default to MMIO. */
147 #ifdef CONFIG_8139TOO_PIO
148 static int use_io = 1;
149 #else
150 static int use_io = 0;
151 #endif
152
153 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
154 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
155 static int multicast_filter_limit = 32;
156
157 /* bitmapped message enable number */
158 static int debug = -1;
159
160 /*
161 * Receive ring size
162 * Warning: 64K ring has hardware issues and may lock up.
163 */
164 #if defined(CONFIG_SH_DREAMCAST)
165 #define RX_BUF_IDX 0 /* 8K ring */
166 #else
167 #define RX_BUF_IDX 2 /* 32K ring */
168 #endif
169 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
170 #define RX_BUF_PAD 16
171 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
172
173 #if RX_BUF_LEN == 65536
174 #define RX_BUF_TOT_LEN RX_BUF_LEN
175 #else
176 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
177 #endif
178
179 /* Number of Tx descriptor registers. */
180 #define NUM_TX_DESC 4
181
182 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
183 #define MAX_ETH_FRAME_SIZE 1536
184
185 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
186 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
187 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
188
189 /* PCI Tuning Parameters
190 Threshold is bytes transferred to chip before transmission starts. */
191 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
192
193 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
194 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
195 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
196 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
197 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
198
199 /* Operational parameters that usually are not changed. */
200 /* Time in jiffies before concluding the transmitter is hung. */
201 #define TX_TIMEOUT (6*HZ)
202
203
204 enum {
205 HAS_MII_XCVR = 0x010000,
206 HAS_CHIP_XCVR = 0x020000,
207 HAS_LNK_CHNG = 0x040000,
208 };
209
210 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
211 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
212 #define RTL_MIN_IO_SIZE 0x80
213 #define RTL8139B_IO_SIZE 256
214
215 #define RTL8129_CAPS HAS_MII_XCVR
216 #define RTL8139_CAPS (HAS_CHIP_XCVR|HAS_LNK_CHNG)
217
218 typedef enum {
219 RTL8139 = 0,
220 RTL8129,
221 } board_t;
222
223
224 /* indexed by board_t, above */
225 static const struct {
226 const char *name;
227 u32 hw_flags;
228 } board_info[] __devinitdata = {
229 { "RealTek RTL8139", RTL8139_CAPS },
230 { "RealTek RTL8129", RTL8129_CAPS },
231 };
232
233
234 static struct pci_device_id rtl8139_pci_tbl[] = {
235 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
236 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
237 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
238 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
239 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
240 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
241 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
242 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
243 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254
255 #ifdef CONFIG_SH_SECUREEDGE5410
256 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
257 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
258 #endif
259 #ifdef CONFIG_8139TOO_8129
260 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
261 #endif
262
263 /* some crazy cards report invalid vendor ids like
264 * 0x0001 here. The other ids are valid and constant,
265 * so we simply don't match on the main vendor id.
266 */
267 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
268 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
269 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
270
271 {0,}
272 };
273 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
274
275 static struct {
276 const char str[ETH_GSTRING_LEN];
277 } ethtool_stats_keys[] = {
278 { "early_rx" },
279 { "tx_buf_mapped" },
280 { "tx_timeouts" },
281 { "rx_lost_in_ring" },
282 };
283
284 /* The rest of these values should never change. */
285
286 /* Symbolic offsets to registers. */
287 enum RTL8139_registers {
288 MAC0 = 0, /* Ethernet hardware address. */
289 MAR0 = 8, /* Multicast filter. */
290 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
291 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
292 RxBuf = 0x30,
293 ChipCmd = 0x37,
294 RxBufPtr = 0x38,
295 RxBufAddr = 0x3A,
296 IntrMask = 0x3C,
297 IntrStatus = 0x3E,
298 TxConfig = 0x40,
299 RxConfig = 0x44,
300 Timer = 0x48, /* A general-purpose counter. */
301 RxMissed = 0x4C, /* 24 bits valid, write clears. */
302 Cfg9346 = 0x50,
303 Config0 = 0x51,
304 Config1 = 0x52,
305 TimerInt = 0x54,
306 MediaStatus = 0x58,
307 Config3 = 0x59,
308 Config4 = 0x5A, /* absent on RTL-8139A */
309 HltClk = 0x5B,
310 MultiIntr = 0x5C,
311 TxSummary = 0x60,
312 BasicModeCtrl = 0x62,
313 BasicModeStatus = 0x64,
314 NWayAdvert = 0x66,
315 NWayLPAR = 0x68,
316 NWayExpansion = 0x6A,
317 /* Undocumented registers, but required for proper operation. */
318 FIFOTMS = 0x70, /* FIFO Control and test. */
319 CSCR = 0x74, /* Chip Status and Configuration Register. */
320 PARA78 = 0x78,
321 FlashReg = 0xD4, /* Communication with Flash ROM, four bytes. */
322 PARA7c = 0x7c, /* Magic transceiver parameter register. */
323 Config5 = 0xD8, /* absent on RTL-8139A */
324 };
325
326 enum ClearBitMasks {
327 MultiIntrClear = 0xF000,
328 ChipCmdClear = 0xE2,
329 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
330 };
331
332 enum ChipCmdBits {
333 CmdReset = 0x10,
334 CmdRxEnb = 0x08,
335 CmdTxEnb = 0x04,
336 RxBufEmpty = 0x01,
337 };
338
339 /* Interrupt register bits, using my own meaningful names. */
340 enum IntrStatusBits {
341 PCIErr = 0x8000,
342 PCSTimeout = 0x4000,
343 RxFIFOOver = 0x40,
344 RxUnderrun = 0x20,
345 RxOverflow = 0x10,
346 TxErr = 0x08,
347 TxOK = 0x04,
348 RxErr = 0x02,
349 RxOK = 0x01,
350
351 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
352 };
353
354 enum TxStatusBits {
355 TxHostOwns = 0x2000,
356 TxUnderrun = 0x4000,
357 TxStatOK = 0x8000,
358 TxOutOfWindow = 0x20000000,
359 TxAborted = 0x40000000,
360 TxCarrierLost = 0x80000000,
361 };
362 enum RxStatusBits {
363 RxMulticast = 0x8000,
364 RxPhysical = 0x4000,
365 RxBroadcast = 0x2000,
366 RxBadSymbol = 0x0020,
367 RxRunt = 0x0010,
368 RxTooLong = 0x0008,
369 RxCRCErr = 0x0004,
370 RxBadAlign = 0x0002,
371 RxStatusOK = 0x0001,
372 };
373
374 /* Bits in RxConfig. */
375 enum rx_mode_bits {
376 AcceptErr = 0x20,
377 AcceptRunt = 0x10,
378 AcceptBroadcast = 0x08,
379 AcceptMulticast = 0x04,
380 AcceptMyPhys = 0x02,
381 AcceptAllPhys = 0x01,
382 };
383
384 /* Bits in TxConfig. */
385 enum tx_config_bits {
386 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
387 TxIFGShift = 24,
388 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
389 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
390 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
391 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
392
393 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
394 TxCRC = (1 << 16), /* DISABLE Tx pkt CRC append */
395 TxClearAbt = (1 << 0), /* Clear abort (WO) */
396 TxDMAShift = 8, /* DMA burst value (0-7) is shifted X many bits */
397 TxRetryShift = 4, /* TXRR value (0-15) is shifted X many bits */
398
399 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
400 };
401
402 /* Bits in Config1 */
403 enum Config1Bits {
404 Cfg1_PM_Enable = 0x01,
405 Cfg1_VPD_Enable = 0x02,
406 Cfg1_PIO = 0x04,
407 Cfg1_MMIO = 0x08,
408 LWAKE = 0x10, /* not on 8139, 8139A */
409 Cfg1_Driver_Load = 0x20,
410 Cfg1_LED0 = 0x40,
411 Cfg1_LED1 = 0x80,
412 SLEEP = (1 << 1), /* only on 8139, 8139A */
413 PWRDN = (1 << 0), /* only on 8139, 8139A */
414 };
415
416 /* Bits in Config3 */
417 enum Config3Bits {
418 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
419 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
420 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
421 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
422 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
423 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
424 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
425 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
426 };
427
428 /* Bits in Config4 */
429 enum Config4Bits {
430 LWPTN = (1 << 2), /* not on 8139, 8139A */
431 };
432
433 /* Bits in Config5 */
434 enum Config5Bits {
435 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
436 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
437 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
438 Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */
439 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
440 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
441 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
442 };
443
444 enum RxConfigBits {
445 /* rx fifo threshold */
446 RxCfgFIFOShift = 13,
447 RxCfgFIFONone = (7 << RxCfgFIFOShift),
448
449 /* Max DMA burst */
450 RxCfgDMAShift = 8,
451 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
452
453 /* rx ring buffer length */
454 RxCfgRcv8K = 0,
455 RxCfgRcv16K = (1 << 11),
456 RxCfgRcv32K = (1 << 12),
457 RxCfgRcv64K = (1 << 11) | (1 << 12),
458
459 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
460 RxNoWrap = (1 << 7),
461 };
462
463 /* Twister tuning parameters from RealTek.
464 Completely undocumented, but required to tune bad links on some boards. */
465 enum CSCRBits {
466 CSCR_LinkOKBit = 0x0400,
467 CSCR_LinkChangeBit = 0x0800,
468 CSCR_LinkStatusBits = 0x0f000,
469 CSCR_LinkDownOffCmd = 0x003c0,
470 CSCR_LinkDownCmd = 0x0f3c0,
471 };
472
473 enum Cfg9346Bits {
474 Cfg9346_Lock = 0x00,
475 Cfg9346_Unlock = 0xC0,
476 };
477
478 typedef enum {
479 CH_8139 = 0,
480 CH_8139_K,
481 CH_8139A,
482 CH_8139A_G,
483 CH_8139B,
484 CH_8130,
485 CH_8139C,
486 CH_8100,
487 CH_8100B_8139D,
488 CH_8101,
489 } chip_t;
490
491 enum chip_flags {
492 HasHltClk = (1 << 0),
493 HasLWake = (1 << 1),
494 };
495
496 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
497 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
498 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
499
500 /* directly indexed by chip_t, above */
501 static const struct {
502 const char *name;
503 u32 version; /* from RTL8139C/RTL8139D docs */
504 u32 flags;
505 } rtl_chip_info[] = {
506 { "RTL-8139",
507 HW_REVID(1, 0, 0, 0, 0, 0, 0),
508 HasHltClk,
509 },
510
511 { "RTL-8139 rev K",
512 HW_REVID(1, 1, 0, 0, 0, 0, 0),
513 HasHltClk,
514 },
515
516 { "RTL-8139A",
517 HW_REVID(1, 1, 1, 0, 0, 0, 0),
518 HasHltClk, /* XXX undocumented? */
519 },
520
521 { "RTL-8139A rev G",
522 HW_REVID(1, 1, 1, 0, 0, 1, 0),
523 HasHltClk, /* XXX undocumented? */
524 },
525
526 { "RTL-8139B",
527 HW_REVID(1, 1, 1, 1, 0, 0, 0),
528 HasLWake,
529 },
530
531 { "RTL-8130",
532 HW_REVID(1, 1, 1, 1, 1, 0, 0),
533 HasLWake,
534 },
535
536 { "RTL-8139C",
537 HW_REVID(1, 1, 1, 0, 1, 0, 0),
538 HasLWake,
539 },
540
541 { "RTL-8100",
542 HW_REVID(1, 1, 1, 1, 0, 1, 0),
543 HasLWake,
544 },
545
546 { "RTL-8100B/8139D",
547 HW_REVID(1, 1, 1, 0, 1, 0, 1),
548 HasHltClk /* XXX undocumented? */
549 | HasLWake,
550 },
551
552 { "RTL-8101",
553 HW_REVID(1, 1, 1, 0, 1, 1, 1),
554 HasLWake,
555 },
556 };
557
558 struct rtl_extra_stats {
559 unsigned long early_rx;
560 unsigned long tx_buf_mapped;
561 unsigned long tx_timeouts;
562 unsigned long rx_lost_in_ring;
563 };
564
565 struct rtl8139_private {
566 void __iomem *mmio_addr;
567 int drv_flags;
568 struct pci_dev *pci_dev;
569 u32 msg_enable;
570 struct napi_struct napi;
571 struct net_device *dev;
572
573 unsigned char *rx_ring;
574 unsigned int cur_rx; /* RX buf index of next pkt */
575 dma_addr_t rx_ring_dma;
576
577 unsigned int tx_flag;
578 unsigned long cur_tx;
579 unsigned long dirty_tx;
580 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
581 unsigned char *tx_bufs; /* Tx bounce buffer region. */
582 dma_addr_t tx_bufs_dma;
583
584 signed char phys[4]; /* MII device addresses. */
585
586 /* Twister tune state. */
587 char twistie, twist_row, twist_col;
588
589 unsigned int watchdog_fired : 1;
590 unsigned int default_port : 4; /* Last dev->if_port value. */
591 unsigned int have_thread : 1;
592
593 spinlock_t lock;
594 spinlock_t rx_lock;
595
596 chip_t chipset;
597 u32 rx_config;
598 struct rtl_extra_stats xstats;
599
600 struct delayed_work thread;
601
602 struct mii_if_info mii;
603 unsigned int regs_len;
604 unsigned long fifo_copy_timeout;
605 };
606
607 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
608 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
609 MODULE_LICENSE("GPL");
610 MODULE_VERSION(DRV_VERSION);
611
612 module_param(use_io, int, 0);
613 MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO");
614 module_param(multicast_filter_limit, int, 0);
615 module_param_array(media, int, NULL, 0);
616 module_param_array(full_duplex, int, NULL, 0);
617 module_param(debug, int, 0);
618 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
619 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
620 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
621 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
622
623 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
624 static int rtl8139_open (struct net_device *dev);
625 static int mdio_read (struct net_device *dev, int phy_id, int location);
626 static void mdio_write (struct net_device *dev, int phy_id, int location,
627 int val);
628 static void rtl8139_start_thread(struct rtl8139_private *tp);
629 static void rtl8139_tx_timeout (struct net_device *dev);
630 static void rtl8139_init_ring (struct net_device *dev);
631 static int rtl8139_start_xmit (struct sk_buff *skb,
632 struct net_device *dev);
633 #ifdef CONFIG_NET_POLL_CONTROLLER
634 static void rtl8139_poll_controller(struct net_device *dev);
635 #endif
636 static int rtl8139_set_mac_address(struct net_device *dev, void *p);
637 static int rtl8139_poll(struct napi_struct *napi, int budget);
638 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);
639 static int rtl8139_close (struct net_device *dev);
640 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
641 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
642 static void rtl8139_set_rx_mode (struct net_device *dev);
643 static void __set_rx_mode (struct net_device *dev);
644 static void rtl8139_hw_start (struct net_device *dev);
645 static void rtl8139_thread (struct work_struct *work);
646 static void rtl8139_tx_timeout_task(struct work_struct *work);
647 static const struct ethtool_ops rtl8139_ethtool_ops;
648
649 /* write MMIO register, with flush */
650 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
651 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
652 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
653 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
654
655 /* write MMIO register */
656 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg))
657 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg))
658 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg))
659
660 /* read MMIO register */
661 #define RTL_R8(reg) ioread8 (ioaddr + (reg))
662 #define RTL_R16(reg) ioread16 (ioaddr + (reg))
663 #define RTL_R32(reg) ((unsigned long) ioread32 (ioaddr + (reg)))
664
665
666 static const u16 rtl8139_intr_mask =
667 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
668 TxErr | TxOK | RxErr | RxOK;
669
670 static const u16 rtl8139_norx_intr_mask =
671 PCIErr | PCSTimeout | RxUnderrun |
672 TxErr | TxOK | RxErr ;
673
674 #if RX_BUF_IDX == 0
675 static const unsigned int rtl8139_rx_config =
676 RxCfgRcv8K | RxNoWrap |
677 (RX_FIFO_THRESH << RxCfgFIFOShift) |
678 (RX_DMA_BURST << RxCfgDMAShift);
679 #elif RX_BUF_IDX == 1
680 static const unsigned int rtl8139_rx_config =
681 RxCfgRcv16K | RxNoWrap |
682 (RX_FIFO_THRESH << RxCfgFIFOShift) |
683 (RX_DMA_BURST << RxCfgDMAShift);
684 #elif RX_BUF_IDX == 2
685 static const unsigned int rtl8139_rx_config =
686 RxCfgRcv32K | RxNoWrap |
687 (RX_FIFO_THRESH << RxCfgFIFOShift) |
688 (RX_DMA_BURST << RxCfgDMAShift);
689 #elif RX_BUF_IDX == 3
690 static const unsigned int rtl8139_rx_config =
691 RxCfgRcv64K |
692 (RX_FIFO_THRESH << RxCfgFIFOShift) |
693 (RX_DMA_BURST << RxCfgDMAShift);
694 #else
695 #error "Invalid configuration for 8139_RXBUF_IDX"
696 #endif
697
698 static const unsigned int rtl8139_tx_config =
699 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
700
701 static void __rtl8139_cleanup_dev (struct net_device *dev)
702 {
703 struct rtl8139_private *tp = netdev_priv(dev);
704 struct pci_dev *pdev;
705
706 assert (dev != NULL);
707 assert (tp->pci_dev != NULL);
708 pdev = tp->pci_dev;
709
710 if (tp->mmio_addr)
711 pci_iounmap (pdev, tp->mmio_addr);
712
713 /* it's ok to call this even if we have no regions to free */
714 pci_release_regions (pdev);
715
716 free_netdev(dev);
717 pci_set_drvdata (pdev, NULL);
718 }
719
720
721 static void rtl8139_chip_reset (void __iomem *ioaddr)
722 {
723 int i;
724
725 /* Soft reset the chip. */
726 RTL_W8 (ChipCmd, CmdReset);
727
728 /* Check that the chip has finished the reset. */
729 for (i = 1000; i > 0; i--) {
730 barrier();
731 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
732 break;
733 udelay (10);
734 }
735 }
736
737
738 static __devinit struct net_device * rtl8139_init_board (struct pci_dev *pdev)
739 {
740 void __iomem *ioaddr;
741 struct net_device *dev;
742 struct rtl8139_private *tp;
743 u8 tmp8;
744 int rc, disable_dev_on_err = 0;
745 unsigned int i;
746 unsigned long pio_start, pio_end, pio_flags, pio_len;
747 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
748 u32 version;
749
750 assert (pdev != NULL);
751
752 /* dev and priv zeroed in alloc_etherdev */
753 dev = alloc_etherdev (sizeof (*tp));
754 if (dev == NULL) {
755 dev_err(&pdev->dev, "Unable to alloc new net device\n");
756 return ERR_PTR(-ENOMEM);
757 }
758 SET_NETDEV_DEV(dev, &pdev->dev);
759
760 tp = netdev_priv(dev);
761 tp->pci_dev = pdev;
762
763 /* enable device (incl. PCI PM wakeup and hotplug setup) */
764 rc = pci_enable_device (pdev);
765 if (rc)
766 goto err_out;
767
768 pio_start = pci_resource_start (pdev, 0);
769 pio_end = pci_resource_end (pdev, 0);
770 pio_flags = pci_resource_flags (pdev, 0);
771 pio_len = pci_resource_len (pdev, 0);
772
773 mmio_start = pci_resource_start (pdev, 1);
774 mmio_end = pci_resource_end (pdev, 1);
775 mmio_flags = pci_resource_flags (pdev, 1);
776 mmio_len = pci_resource_len (pdev, 1);
777
778 /* set this immediately, we need to know before
779 * we talk to the chip directly */
780 pr_debug("PIO region size == 0x%02lX\n", pio_len);
781 pr_debug("MMIO region size == 0x%02lX\n", mmio_len);
782
783 retry:
784 if (use_io) {
785 /* make sure PCI base addr 0 is PIO */
786 if (!(pio_flags & IORESOURCE_IO)) {
787 dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");
788 rc = -ENODEV;
789 goto err_out;
790 }
791 /* check for weird/broken PCI region reporting */
792 if (pio_len < RTL_MIN_IO_SIZE) {
793 dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n");
794 rc = -ENODEV;
795 goto err_out;
796 }
797 } else {
798 /* make sure PCI base addr 1 is MMIO */
799 if (!(mmio_flags & IORESOURCE_MEM)) {
800 dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");
801 rc = -ENODEV;
802 goto err_out;
803 }
804 if (mmio_len < RTL_MIN_IO_SIZE) {
805 dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n");
806 rc = -ENODEV;
807 goto err_out;
808 }
809 }
810
811 rc = pci_request_regions (pdev, DRV_NAME);
812 if (rc)
813 goto err_out;
814 disable_dev_on_err = 1;
815
816 /* enable PCI bus-mastering */
817 pci_set_master (pdev);
818
819 if (use_io) {
820 ioaddr = pci_iomap(pdev, 0, 0);
821 if (!ioaddr) {
822 dev_err(&pdev->dev, "cannot map PIO, aborting\n");
823 rc = -EIO;
824 goto err_out;
825 }
826 dev->base_addr = pio_start;
827 tp->regs_len = pio_len;
828 } else {
829 /* ioremap MMIO region */
830 ioaddr = pci_iomap(pdev, 1, 0);
831 if (ioaddr == NULL) {
832 dev_err(&pdev->dev, "cannot remap MMIO, trying PIO\n");
833 pci_release_regions(pdev);
834 use_io = 1;
835 goto retry;
836 }
837 dev->base_addr = (long) ioaddr;
838 tp->regs_len = mmio_len;
839 }
840 tp->mmio_addr = ioaddr;
841
842 /* Bring old chips out of low-power mode. */
843 RTL_W8 (HltClk, 'R');
844
845 /* check for missing/broken hardware */
846 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
847 dev_err(&pdev->dev, "Chip not responding, ignoring board\n");
848 rc = -EIO;
849 goto err_out;
850 }
851
852 /* identify chip attached to board */
853 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
854 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
855 if (version == rtl_chip_info[i].version) {
856 tp->chipset = i;
857 goto match;
858 }
859
860 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
861 dev_dbg(&pdev->dev, "unknown chip version, assuming RTL-8139\n");
862 dev_dbg(&pdev->dev, "TxConfig = 0x%lx\n", RTL_R32 (TxConfig));
863 tp->chipset = 0;
864
865 match:
866 pr_debug("chipset id (%d) == index %d, '%s'\n",
867 version, i, rtl_chip_info[i].name);
868
869 if (tp->chipset >= CH_8139B) {
870 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
871 pr_debug("PCI PM wakeup\n");
872 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
873 (tmp8 & LWAKE))
874 new_tmp8 &= ~LWAKE;
875 new_tmp8 |= Cfg1_PM_Enable;
876 if (new_tmp8 != tmp8) {
877 RTL_W8 (Cfg9346, Cfg9346_Unlock);
878 RTL_W8 (Config1, tmp8);
879 RTL_W8 (Cfg9346, Cfg9346_Lock);
880 }
881 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
882 tmp8 = RTL_R8 (Config4);
883 if (tmp8 & LWPTN) {
884 RTL_W8 (Cfg9346, Cfg9346_Unlock);
885 RTL_W8 (Config4, tmp8 & ~LWPTN);
886 RTL_W8 (Cfg9346, Cfg9346_Lock);
887 }
888 }
889 } else {
890 pr_debug("Old chip wakeup\n");
891 tmp8 = RTL_R8 (Config1);
892 tmp8 &= ~(SLEEP | PWRDN);
893 RTL_W8 (Config1, tmp8);
894 }
895
896 rtl8139_chip_reset (ioaddr);
897
898 return dev;
899
900 err_out:
901 __rtl8139_cleanup_dev (dev);
902 if (disable_dev_on_err)
903 pci_disable_device (pdev);
904 return ERR_PTR(rc);
905 }
906
907 static const struct net_device_ops rtl8139_netdev_ops = {
908 .ndo_open = rtl8139_open,
909 .ndo_stop = rtl8139_close,
910 .ndo_get_stats = rtl8139_get_stats,
911 .ndo_validate_addr = eth_validate_addr,
912 .ndo_set_mac_address = rtl8139_set_mac_address,
913 .ndo_start_xmit = rtl8139_start_xmit,
914 .ndo_set_multicast_list = rtl8139_set_rx_mode,
915 .ndo_do_ioctl = netdev_ioctl,
916 .ndo_tx_timeout = rtl8139_tx_timeout,
917 #ifdef CONFIG_NET_POLL_CONTROLLER
918 .ndo_poll_controller = rtl8139_poll_controller,
919 #endif
920 };
921
922 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
923 const struct pci_device_id *ent)
924 {
925 struct net_device *dev = NULL;
926 struct rtl8139_private *tp;
927 int i, addr_len, option;
928 void __iomem *ioaddr;
929 static int board_idx = -1;
930
931 assert (pdev != NULL);
932 assert (ent != NULL);
933
934 board_idx++;
935
936 /* when we're built into the kernel, the driver version message
937 * is only printed if at least one 8139 board has been found
938 */
939 #ifndef MODULE
940 {
941 static int printed_version;
942 if (!printed_version++)
943 pr_info(RTL8139_DRIVER_NAME "\n");
944 }
945 #endif
946
947 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
948 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {
949 dev_info(&pdev->dev,
950 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n",
951 pdev->vendor, pdev->device, pdev->revision);
952 return -ENODEV;
953 }
954
955 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
956 pdev->device == PCI_DEVICE_ID_REALTEK_8139 &&
957 pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS &&
958 pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) {
959 pr_info("8139too: OQO Model 2 detected. Forcing PIO\n");
960 use_io = 1;
961 }
962
963 dev = rtl8139_init_board (pdev);
964 if (IS_ERR(dev))
965 return PTR_ERR(dev);
966
967 assert (dev != NULL);
968 tp = netdev_priv(dev);
969 tp->dev = dev;
970
971 ioaddr = tp->mmio_addr;
972 assert (ioaddr != NULL);
973
974 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
975 for (i = 0; i < 3; i++)
976 ((__le16 *) (dev->dev_addr))[i] =
977 cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len));
978 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
979
980 /* The Rtl8139-specific entries in the device structure. */
981 dev->netdev_ops = &rtl8139_netdev_ops;
982 dev->ethtool_ops = &rtl8139_ethtool_ops;
983 dev->watchdog_timeo = TX_TIMEOUT;
984 netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);
985
986 /* note: the hardware is not capable of sg/csum/highdma, however
987 * through the use of skb_copy_and_csum_dev we enable these
988 * features
989 */
990 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
991
992 dev->irq = pdev->irq;
993
994 /* tp zeroed and aligned in alloc_etherdev */
995 tp = netdev_priv(dev);
996
997 /* note: tp->chipset set in rtl8139_init_board */
998 tp->drv_flags = board_info[ent->driver_data].hw_flags;
999 tp->mmio_addr = ioaddr;
1000 tp->msg_enable =
1001 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1002 spin_lock_init (&tp->lock);
1003 spin_lock_init (&tp->rx_lock);
1004 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1005 tp->mii.dev = dev;
1006 tp->mii.mdio_read = mdio_read;
1007 tp->mii.mdio_write = mdio_write;
1008 tp->mii.phy_id_mask = 0x3f;
1009 tp->mii.reg_num_mask = 0x1f;
1010
1011 /* dev is fully set up and ready to use now */
1012 pr_debug("about to register device named %s (%p)...\n", dev->name, dev);
1013 i = register_netdev (dev);
1014 if (i) goto err_out;
1015
1016 pci_set_drvdata (pdev, dev);
1017
1018 pr_info("%s: %s at 0x%lx, %pM, IRQ %d\n",
1019 dev->name,
1020 board_info[ent->driver_data].name,
1021 dev->base_addr,
1022 dev->dev_addr,
1023 dev->irq);
1024
1025 pr_debug("%s: Identified 8139 chip type '%s'\n",
1026 dev->name, rtl_chip_info[tp->chipset].name);
1027
1028 /* Find the connected MII xcvrs.
1029 Doing this in open() would allow detecting external xcvrs later, but
1030 takes too much time. */
1031 #ifdef CONFIG_8139TOO_8129
1032 if (tp->drv_flags & HAS_MII_XCVR) {
1033 int phy, phy_idx = 0;
1034 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1035 int mii_status = mdio_read(dev, phy, 1);
1036 if (mii_status != 0xffff && mii_status != 0x0000) {
1037 u16 advertising = mdio_read(dev, phy, 4);
1038 tp->phys[phy_idx++] = phy;
1039 pr_info("%s: MII transceiver %d status 0x%4.4x advertising %4.4x.\n",
1040 dev->name, phy, mii_status, advertising);
1041 }
1042 }
1043 if (phy_idx == 0) {
1044 pr_info("%s: No MII transceivers found! Assuming SYM transceiver.\n",
1045 dev->name);
1046 tp->phys[0] = 32;
1047 }
1048 } else
1049 #endif
1050 tp->phys[0] = 32;
1051 tp->mii.phy_id = tp->phys[0];
1052
1053 /* The lower four bits are the media type. */
1054 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1055 if (option > 0) {
1056 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1057 tp->default_port = option & 0xFF;
1058 if (tp->default_port)
1059 tp->mii.force_media = 1;
1060 }
1061 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1062 tp->mii.full_duplex = full_duplex[board_idx];
1063 if (tp->mii.full_duplex) {
1064 pr_info("%s: Media type forced to Full Duplex.\n", dev->name);
1065 /* Changing the MII-advertised media because might prevent
1066 re-connection. */
1067 tp->mii.force_media = 1;
1068 }
1069 if (tp->default_port) {
1070 pr_info(" Forcing %dMbps %s-duplex operation.\n",
1071 (option & 0x20 ? 100 : 10),
1072 (option & 0x10 ? "full" : "half"));
1073 mdio_write(dev, tp->phys[0], 0,
1074 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1075 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1076 }
1077
1078 /* Put the chip into low-power mode. */
1079 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1080 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1081
1082 return 0;
1083
1084 err_out:
1085 __rtl8139_cleanup_dev (dev);
1086 pci_disable_device (pdev);
1087 return i;
1088 }
1089
1090
1091 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1092 {
1093 struct net_device *dev = pci_get_drvdata (pdev);
1094
1095 assert (dev != NULL);
1096
1097 flush_scheduled_work();
1098
1099 unregister_netdev (dev);
1100
1101 __rtl8139_cleanup_dev (dev);
1102 pci_disable_device (pdev);
1103 }
1104
1105
1106 /* Serial EEPROM section. */
1107
1108 /* EEPROM_Ctrl bits. */
1109 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1110 #define EE_CS 0x08 /* EEPROM chip select. */
1111 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1112 #define EE_WRITE_0 0x00
1113 #define EE_WRITE_1 0x02
1114 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1115 #define EE_ENB (0x80 | EE_CS)
1116
1117 /* Delay between EEPROM clock transitions.
1118 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1119 */
1120
1121 #define eeprom_delay() (void)RTL_R32(Cfg9346)
1122
1123 /* The EEPROM commands include the alway-set leading bit. */
1124 #define EE_WRITE_CMD (5)
1125 #define EE_READ_CMD (6)
1126 #define EE_ERASE_CMD (7)
1127
1128 static int __devinit read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1129 {
1130 int i;
1131 unsigned retval = 0;
1132 int read_cmd = location | (EE_READ_CMD << addr_len);
1133
1134 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
1135 RTL_W8 (Cfg9346, EE_ENB);
1136 eeprom_delay ();
1137
1138 /* Shift the read command bits out. */
1139 for (i = 4 + addr_len; i >= 0; i--) {
1140 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1141 RTL_W8 (Cfg9346, EE_ENB | dataval);
1142 eeprom_delay ();
1143 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
1144 eeprom_delay ();
1145 }
1146 RTL_W8 (Cfg9346, EE_ENB);
1147 eeprom_delay ();
1148
1149 for (i = 16; i > 0; i--) {
1150 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
1151 eeprom_delay ();
1152 retval =
1153 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
1154 0);
1155 RTL_W8 (Cfg9346, EE_ENB);
1156 eeprom_delay ();
1157 }
1158
1159 /* Terminate the EEPROM access. */
1160 RTL_W8 (Cfg9346, ~EE_CS);
1161 eeprom_delay ();
1162
1163 return retval;
1164 }
1165
1166 /* MII serial management: mostly bogus for now. */
1167 /* Read and write the MII management registers using software-generated
1168 serial MDIO protocol.
1169 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1170 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1171 "overclocking" issues. */
1172 #define MDIO_DIR 0x80
1173 #define MDIO_DATA_OUT 0x04
1174 #define MDIO_DATA_IN 0x02
1175 #define MDIO_CLK 0x01
1176 #define MDIO_WRITE0 (MDIO_DIR)
1177 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1178
1179 #define mdio_delay() RTL_R8(Config4)
1180
1181
1182 static const char mii_2_8139_map[8] = {
1183 BasicModeCtrl,
1184 BasicModeStatus,
1185 0,
1186 0,
1187 NWayAdvert,
1188 NWayLPAR,
1189 NWayExpansion,
1190 0
1191 };
1192
1193
1194 #ifdef CONFIG_8139TOO_8129
1195 /* Syncronize the MII management interface by shifting 32 one bits out. */
1196 static void mdio_sync (void __iomem *ioaddr)
1197 {
1198 int i;
1199
1200 for (i = 32; i >= 0; i--) {
1201 RTL_W8 (Config4, MDIO_WRITE1);
1202 mdio_delay ();
1203 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
1204 mdio_delay ();
1205 }
1206 }
1207 #endif
1208
1209 static int mdio_read (struct net_device *dev, int phy_id, int location)
1210 {
1211 struct rtl8139_private *tp = netdev_priv(dev);
1212 int retval = 0;
1213 #ifdef CONFIG_8139TOO_8129
1214 void __iomem *ioaddr = tp->mmio_addr;
1215 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1216 int i;
1217 #endif
1218
1219 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1220 void __iomem *ioaddr = tp->mmio_addr;
1221 return location < 8 && mii_2_8139_map[location] ?
1222 RTL_R16 (mii_2_8139_map[location]) : 0;
1223 }
1224
1225 #ifdef CONFIG_8139TOO_8129
1226 mdio_sync (ioaddr);
1227 /* Shift the read command bits out. */
1228 for (i = 15; i >= 0; i--) {
1229 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1230
1231 RTL_W8 (Config4, MDIO_DIR | dataval);
1232 mdio_delay ();
1233 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
1234 mdio_delay ();
1235 }
1236
1237 /* Read the two transition, 16 data, and wire-idle bits. */
1238 for (i = 19; i > 0; i--) {
1239 RTL_W8 (Config4, 0);
1240 mdio_delay ();
1241 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
1242 RTL_W8 (Config4, MDIO_CLK);
1243 mdio_delay ();
1244 }
1245 #endif
1246
1247 return (retval >> 1) & 0xffff;
1248 }
1249
1250
1251 static void mdio_write (struct net_device *dev, int phy_id, int location,
1252 int value)
1253 {
1254 struct rtl8139_private *tp = netdev_priv(dev);
1255 #ifdef CONFIG_8139TOO_8129
1256 void __iomem *ioaddr = tp->mmio_addr;
1257 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1258 int i;
1259 #endif
1260
1261 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1262 void __iomem *ioaddr = tp->mmio_addr;
1263 if (location == 0) {
1264 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1265 RTL_W16 (BasicModeCtrl, value);
1266 RTL_W8 (Cfg9346, Cfg9346_Lock);
1267 } else if (location < 8 && mii_2_8139_map[location])
1268 RTL_W16 (mii_2_8139_map[location], value);
1269 return;
1270 }
1271
1272 #ifdef CONFIG_8139TOO_8129
1273 mdio_sync (ioaddr);
1274
1275 /* Shift the command bits out. */
1276 for (i = 31; i >= 0; i--) {
1277 int dataval =
1278 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1279 RTL_W8 (Config4, dataval);
1280 mdio_delay ();
1281 RTL_W8 (Config4, dataval | MDIO_CLK);
1282 mdio_delay ();
1283 }
1284 /* Clear out extra bits. */
1285 for (i = 2; i > 0; i--) {
1286 RTL_W8 (Config4, 0);
1287 mdio_delay ();
1288 RTL_W8 (Config4, MDIO_CLK);
1289 mdio_delay ();
1290 }
1291 #endif
1292 }
1293
1294
1295 static int rtl8139_open (struct net_device *dev)
1296 {
1297 struct rtl8139_private *tp = netdev_priv(dev);
1298 int retval;
1299 void __iomem *ioaddr = tp->mmio_addr;
1300
1301 retval = request_irq (dev->irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev);
1302 if (retval)
1303 return retval;
1304
1305 tp->tx_bufs = dma_alloc_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1306 &tp->tx_bufs_dma, GFP_KERNEL);
1307 tp->rx_ring = dma_alloc_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1308 &tp->rx_ring_dma, GFP_KERNEL);
1309 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1310 free_irq(dev->irq, dev);
1311
1312 if (tp->tx_bufs)
1313 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1314 tp->tx_bufs, tp->tx_bufs_dma);
1315 if (tp->rx_ring)
1316 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1317 tp->rx_ring, tp->rx_ring_dma);
1318
1319 return -ENOMEM;
1320
1321 }
1322
1323 napi_enable(&tp->napi);
1324
1325 tp->mii.full_duplex = tp->mii.force_media;
1326 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1327
1328 rtl8139_init_ring (dev);
1329 rtl8139_hw_start (dev);
1330 netif_start_queue (dev);
1331
1332 if (netif_msg_ifup(tp))
1333 pr_debug("%s: rtl8139_open() ioaddr %#llx IRQ %d"
1334 " GP Pins %2.2x %s-duplex.\n", dev->name,
1335 (unsigned long long)pci_resource_start (tp->pci_dev, 1),
1336 dev->irq, RTL_R8 (MediaStatus),
1337 tp->mii.full_duplex ? "full" : "half");
1338
1339 rtl8139_start_thread(tp);
1340
1341 return 0;
1342 }
1343
1344
1345 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1346 {
1347 struct rtl8139_private *tp = netdev_priv(dev);
1348
1349 if (tp->phys[0] >= 0) {
1350 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1351 }
1352 }
1353
1354 /* Start the hardware at open or resume. */
1355 static void rtl8139_hw_start (struct net_device *dev)
1356 {
1357 struct rtl8139_private *tp = netdev_priv(dev);
1358 void __iomem *ioaddr = tp->mmio_addr;
1359 u32 i;
1360 u8 tmp;
1361
1362 /* Bring old chips out of low-power mode. */
1363 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1364 RTL_W8 (HltClk, 'R');
1365
1366 rtl8139_chip_reset (ioaddr);
1367
1368 /* unlock Config[01234] and BMCR register writes */
1369 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1370 /* Restore our idea of the MAC address. */
1371 RTL_W32_F (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1372 RTL_W32_F (MAC0 + 4, le16_to_cpu (*(__le16 *) (dev->dev_addr + 4)));
1373
1374 tp->cur_rx = 0;
1375
1376 /* init Rx ring buffer DMA address */
1377 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1378
1379 /* Must enable Tx/Rx before setting transfer thresholds! */
1380 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1381
1382 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1383 RTL_W32 (RxConfig, tp->rx_config);
1384 RTL_W32 (TxConfig, rtl8139_tx_config);
1385
1386 rtl_check_media (dev, 1);
1387
1388 if (tp->chipset >= CH_8139B) {
1389 /* Disable magic packet scanning, which is enabled
1390 * when PM is enabled in Config1. It can be reenabled
1391 * via ETHTOOL_SWOL if desired. */
1392 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1393 }
1394
1395 pr_debug("init buffer addresses\n");
1396
1397 /* Lock Config[01234] and BMCR register writes */
1398 RTL_W8 (Cfg9346, Cfg9346_Lock);
1399
1400 /* init Tx buffer DMA addresses */
1401 for (i = 0; i < NUM_TX_DESC; i++)
1402 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1403
1404 RTL_W32 (RxMissed, 0);
1405
1406 rtl8139_set_rx_mode (dev);
1407
1408 /* no early-rx interrupts */
1409 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1410
1411 /* make sure RxTx has started */
1412 tmp = RTL_R8 (ChipCmd);
1413 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1414 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1415
1416 /* Enable all known interrupts by setting the interrupt mask. */
1417 RTL_W16 (IntrMask, rtl8139_intr_mask);
1418 }
1419
1420
1421 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1422 static void rtl8139_init_ring (struct net_device *dev)
1423 {
1424 struct rtl8139_private *tp = netdev_priv(dev);
1425 int i;
1426
1427 tp->cur_rx = 0;
1428 tp->cur_tx = 0;
1429 tp->dirty_tx = 0;
1430
1431 for (i = 0; i < NUM_TX_DESC; i++)
1432 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1433 }
1434
1435
1436 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1437 static int next_tick = 3 * HZ;
1438
1439 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1440 static inline void rtl8139_tune_twister (struct net_device *dev,
1441 struct rtl8139_private *tp) {}
1442 #else
1443 enum TwisterParamVals {
1444 PARA78_default = 0x78fa8388,
1445 PARA7c_default = 0xcb38de43, /* param[0][3] */
1446 PARA7c_xxx = 0xcb38de43,
1447 };
1448
1449 static const unsigned long param[4][4] = {
1450 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1451 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1452 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1453 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1454 };
1455
1456 static void rtl8139_tune_twister (struct net_device *dev,
1457 struct rtl8139_private *tp)
1458 {
1459 int linkcase;
1460 void __iomem *ioaddr = tp->mmio_addr;
1461
1462 /* This is a complicated state machine to configure the "twister" for
1463 impedance/echos based on the cable length.
1464 All of this is magic and undocumented.
1465 */
1466 switch (tp->twistie) {
1467 case 1:
1468 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1469 /* We have link beat, let us tune the twister. */
1470 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1471 tp->twistie = 2; /* Change to state 2. */
1472 next_tick = HZ / 10;
1473 } else {
1474 /* Just put in some reasonable defaults for when beat returns. */
1475 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1476 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1477 RTL_W32 (PARA78, PARA78_default);
1478 RTL_W32 (PARA7c, PARA7c_default);
1479 tp->twistie = 0; /* Bail from future actions. */
1480 }
1481 break;
1482 case 2:
1483 /* Read how long it took to hear the echo. */
1484 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1485 if (linkcase == 0x7000)
1486 tp->twist_row = 3;
1487 else if (linkcase == 0x3000)
1488 tp->twist_row = 2;
1489 else if (linkcase == 0x1000)
1490 tp->twist_row = 1;
1491 else
1492 tp->twist_row = 0;
1493 tp->twist_col = 0;
1494 tp->twistie = 3; /* Change to state 2. */
1495 next_tick = HZ / 10;
1496 break;
1497 case 3:
1498 /* Put out four tuning parameters, one per 100msec. */
1499 if (tp->twist_col == 0)
1500 RTL_W16 (FIFOTMS, 0);
1501 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1502 [(int) tp->twist_col]);
1503 next_tick = HZ / 10;
1504 if (++tp->twist_col >= 4) {
1505 /* For short cables we are done.
1506 For long cables (row == 3) check for mistune. */
1507 tp->twistie =
1508 (tp->twist_row == 3) ? 4 : 0;
1509 }
1510 break;
1511 case 4:
1512 /* Special case for long cables: check for mistune. */
1513 if ((RTL_R16 (CSCR) &
1514 CSCR_LinkStatusBits) == 0x7000) {
1515 tp->twistie = 0;
1516 break;
1517 } else {
1518 RTL_W32 (PARA7c, 0xfb38de03);
1519 tp->twistie = 5;
1520 next_tick = HZ / 10;
1521 }
1522 break;
1523 case 5:
1524 /* Retune for shorter cable (column 2). */
1525 RTL_W32 (FIFOTMS, 0x20);
1526 RTL_W32 (PARA78, PARA78_default);
1527 RTL_W32 (PARA7c, PARA7c_default);
1528 RTL_W32 (FIFOTMS, 0x00);
1529 tp->twist_row = 2;
1530 tp->twist_col = 0;
1531 tp->twistie = 3;
1532 next_tick = HZ / 10;
1533 break;
1534
1535 default:
1536 /* do nothing */
1537 break;
1538 }
1539 }
1540 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1541
1542 static inline void rtl8139_thread_iter (struct net_device *dev,
1543 struct rtl8139_private *tp,
1544 void __iomem *ioaddr)
1545 {
1546 int mii_lpa;
1547
1548 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1549
1550 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1551 int duplex = (mii_lpa & LPA_100FULL)
1552 || (mii_lpa & 0x01C0) == 0x0040;
1553 if (tp->mii.full_duplex != duplex) {
1554 tp->mii.full_duplex = duplex;
1555
1556 if (mii_lpa) {
1557 pr_info("%s: Setting %s-duplex based on MII #%d link"
1558 " partner ability of %4.4x.\n",
1559 dev->name,
1560 tp->mii.full_duplex ? "full" : "half",
1561 tp->phys[0], mii_lpa);
1562 } else {
1563 pr_info("%s: media is unconnected, link down, or incompatible connection\n",
1564 dev->name);
1565 }
1566 #if 0
1567 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1568 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1569 RTL_W8 (Cfg9346, Cfg9346_Lock);
1570 #endif
1571 }
1572 }
1573
1574 next_tick = HZ * 60;
1575
1576 rtl8139_tune_twister (dev, tp);
1577
1578 pr_debug("%s: Media selection tick, Link partner %4.4x.\n",
1579 dev->name, RTL_R16 (NWayLPAR));
1580 pr_debug("%s: Other registers are IntMask %4.4x IntStatus %4.4x\n",
1581 dev->name, RTL_R16 (IntrMask), RTL_R16 (IntrStatus));
1582 pr_debug("%s: Chip config %2.2x %2.2x.\n",
1583 dev->name, RTL_R8 (Config0),
1584 RTL_R8 (Config1));
1585 }
1586
1587 static void rtl8139_thread (struct work_struct *work)
1588 {
1589 struct rtl8139_private *tp =
1590 container_of(work, struct rtl8139_private, thread.work);
1591 struct net_device *dev = tp->mii.dev;
1592 unsigned long thr_delay = next_tick;
1593
1594 rtnl_lock();
1595
1596 if (!netif_running(dev))
1597 goto out_unlock;
1598
1599 if (tp->watchdog_fired) {
1600 tp->watchdog_fired = 0;
1601 rtl8139_tx_timeout_task(work);
1602 } else
1603 rtl8139_thread_iter(dev, tp, tp->mmio_addr);
1604
1605 if (tp->have_thread)
1606 schedule_delayed_work(&tp->thread, thr_delay);
1607 out_unlock:
1608 rtnl_unlock ();
1609 }
1610
1611 static void rtl8139_start_thread(struct rtl8139_private *tp)
1612 {
1613 tp->twistie = 0;
1614 if (tp->chipset == CH_8139_K)
1615 tp->twistie = 1;
1616 else if (tp->drv_flags & HAS_LNK_CHNG)
1617 return;
1618
1619 tp->have_thread = 1;
1620 tp->watchdog_fired = 0;
1621
1622 schedule_delayed_work(&tp->thread, next_tick);
1623 }
1624
1625 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1626 {
1627 tp->cur_tx = 0;
1628 tp->dirty_tx = 0;
1629
1630 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1631 }
1632
1633 static void rtl8139_tx_timeout_task (struct work_struct *work)
1634 {
1635 struct rtl8139_private *tp =
1636 container_of(work, struct rtl8139_private, thread.work);
1637 struct net_device *dev = tp->mii.dev;
1638 void __iomem *ioaddr = tp->mmio_addr;
1639 int i;
1640 u8 tmp8;
1641
1642 pr_debug("%s: Transmit timeout, status %2.2x %4.4x %4.4x media %2.2x.\n",
1643 dev->name, RTL_R8 (ChipCmd),
1644 RTL_R16(IntrStatus), RTL_R16(IntrMask), RTL_R8(MediaStatus));
1645 /* Emit info to figure out what went wrong. */
1646 pr_debug("%s: Tx queue start entry %ld dirty entry %ld.\n",
1647 dev->name, tp->cur_tx, tp->dirty_tx);
1648 for (i = 0; i < NUM_TX_DESC; i++)
1649 pr_debug("%s: Tx descriptor %d is %8.8lx.%s\n",
1650 dev->name, i, RTL_R32 (TxStatus0 + (i * 4)),
1651 i == tp->dirty_tx % NUM_TX_DESC ?
1652 " (queue head)" : "");
1653
1654 tp->xstats.tx_timeouts++;
1655
1656 /* disable Tx ASAP, if not already */
1657 tmp8 = RTL_R8 (ChipCmd);
1658 if (tmp8 & CmdTxEnb)
1659 RTL_W8 (ChipCmd, CmdRxEnb);
1660
1661 spin_lock_bh(&tp->rx_lock);
1662 /* Disable interrupts by clearing the interrupt mask. */
1663 RTL_W16 (IntrMask, 0x0000);
1664
1665 /* Stop a shared interrupt from scavenging while we are. */
1666 spin_lock_irq(&tp->lock);
1667 rtl8139_tx_clear (tp);
1668 spin_unlock_irq(&tp->lock);
1669
1670 /* ...and finally, reset everything */
1671 if (netif_running(dev)) {
1672 rtl8139_hw_start (dev);
1673 netif_wake_queue (dev);
1674 }
1675 spin_unlock_bh(&tp->rx_lock);
1676 }
1677
1678 static void rtl8139_tx_timeout (struct net_device *dev)
1679 {
1680 struct rtl8139_private *tp = netdev_priv(dev);
1681
1682 tp->watchdog_fired = 1;
1683 if (!tp->have_thread) {
1684 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1685 schedule_delayed_work(&tp->thread, next_tick);
1686 }
1687 }
1688
1689 static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1690 {
1691 struct rtl8139_private *tp = netdev_priv(dev);
1692 void __iomem *ioaddr = tp->mmio_addr;
1693 unsigned int entry;
1694 unsigned int len = skb->len;
1695 unsigned long flags;
1696
1697 /* Calculate the next Tx descriptor entry. */
1698 entry = tp->cur_tx % NUM_TX_DESC;
1699
1700 /* Note: the chip doesn't have auto-pad! */
1701 if (likely(len < TX_BUF_SIZE)) {
1702 if (len < ETH_ZLEN)
1703 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1704 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1705 dev_kfree_skb(skb);
1706 } else {
1707 dev_kfree_skb(skb);
1708 dev->stats.tx_dropped++;
1709 return 0;
1710 }
1711
1712 spin_lock_irqsave(&tp->lock, flags);
1713 /*
1714 * Writing to TxStatus triggers a DMA transfer of the data
1715 * copied to tp->tx_buf[entry] above. Use a memory barrier
1716 * to make sure that the device sees the updated data.
1717 */
1718 wmb();
1719 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1720 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1721
1722 dev->trans_start = jiffies;
1723
1724 tp->cur_tx++;
1725
1726 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1727 netif_stop_queue (dev);
1728 spin_unlock_irqrestore(&tp->lock, flags);
1729
1730 if (netif_msg_tx_queued(tp))
1731 pr_debug("%s: Queued Tx packet size %u to slot %d.\n",
1732 dev->name, len, entry);
1733
1734 return 0;
1735 }
1736
1737
1738 static void rtl8139_tx_interrupt (struct net_device *dev,
1739 struct rtl8139_private *tp,
1740 void __iomem *ioaddr)
1741 {
1742 unsigned long dirty_tx, tx_left;
1743
1744 assert (dev != NULL);
1745 assert (ioaddr != NULL);
1746
1747 dirty_tx = tp->dirty_tx;
1748 tx_left = tp->cur_tx - dirty_tx;
1749 while (tx_left > 0) {
1750 int entry = dirty_tx % NUM_TX_DESC;
1751 int txstatus;
1752
1753 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1754
1755 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1756 break; /* It still hasn't been Txed */
1757
1758 /* Note: TxCarrierLost is always asserted at 100mbps. */
1759 if (txstatus & (TxOutOfWindow | TxAborted)) {
1760 /* There was an major error, log it. */
1761 if (netif_msg_tx_err(tp))
1762 pr_debug("%s: Transmit error, Tx status %8.8x.\n",
1763 dev->name, txstatus);
1764 dev->stats.tx_errors++;
1765 if (txstatus & TxAborted) {
1766 dev->stats.tx_aborted_errors++;
1767 RTL_W32 (TxConfig, TxClearAbt);
1768 RTL_W16 (IntrStatus, TxErr);
1769 wmb();
1770 }
1771 if (txstatus & TxCarrierLost)
1772 dev->stats.tx_carrier_errors++;
1773 if (txstatus & TxOutOfWindow)
1774 dev->stats.tx_window_errors++;
1775 } else {
1776 if (txstatus & TxUnderrun) {
1777 /* Add 64 to the Tx FIFO threshold. */
1778 if (tp->tx_flag < 0x00300000)
1779 tp->tx_flag += 0x00020000;
1780 dev->stats.tx_fifo_errors++;
1781 }
1782 dev->stats.collisions += (txstatus >> 24) & 15;
1783 dev->stats.tx_bytes += txstatus & 0x7ff;
1784 dev->stats.tx_packets++;
1785 }
1786
1787 dirty_tx++;
1788 tx_left--;
1789 }
1790
1791 #ifndef RTL8139_NDEBUG
1792 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1793 pr_err("%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
1794 dev->name, dirty_tx, tp->cur_tx);
1795 dirty_tx += NUM_TX_DESC;
1796 }
1797 #endif /* RTL8139_NDEBUG */
1798
1799 /* only wake the queue if we did work, and the queue is stopped */
1800 if (tp->dirty_tx != dirty_tx) {
1801 tp->dirty_tx = dirty_tx;
1802 mb();
1803 netif_wake_queue (dev);
1804 }
1805 }
1806
1807
1808 /* TODO: clean this up! Rx reset need not be this intensive */
1809 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1810 struct rtl8139_private *tp, void __iomem *ioaddr)
1811 {
1812 u8 tmp8;
1813 #ifdef CONFIG_8139_OLD_RX_RESET
1814 int tmp_work;
1815 #endif
1816
1817 if (netif_msg_rx_err (tp))
1818 pr_debug("%s: Ethernet frame had errors, status %8.8x.\n",
1819 dev->name, rx_status);
1820 dev->stats.rx_errors++;
1821 if (!(rx_status & RxStatusOK)) {
1822 if (rx_status & RxTooLong) {
1823 pr_debug("%s: Oversized Ethernet frame, status %4.4x!\n",
1824 dev->name, rx_status);
1825 /* A.C.: The chip hangs here. */
1826 }
1827 if (rx_status & (RxBadSymbol | RxBadAlign))
1828 dev->stats.rx_frame_errors++;
1829 if (rx_status & (RxRunt | RxTooLong))
1830 dev->stats.rx_length_errors++;
1831 if (rx_status & RxCRCErr)
1832 dev->stats.rx_crc_errors++;
1833 } else {
1834 tp->xstats.rx_lost_in_ring++;
1835 }
1836
1837 #ifndef CONFIG_8139_OLD_RX_RESET
1838 tmp8 = RTL_R8 (ChipCmd);
1839 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1840 RTL_W8 (ChipCmd, tmp8);
1841 RTL_W32 (RxConfig, tp->rx_config);
1842 tp->cur_rx = 0;
1843 #else
1844 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1845
1846 /* disable receive */
1847 RTL_W8_F (ChipCmd, CmdTxEnb);
1848 tmp_work = 200;
1849 while (--tmp_work > 0) {
1850 udelay(1);
1851 tmp8 = RTL_R8 (ChipCmd);
1852 if (!(tmp8 & CmdRxEnb))
1853 break;
1854 }
1855 if (tmp_work <= 0)
1856 pr_warning(PFX "rx stop wait too long\n");
1857 /* restart receive */
1858 tmp_work = 200;
1859 while (--tmp_work > 0) {
1860 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1861 udelay(1);
1862 tmp8 = RTL_R8 (ChipCmd);
1863 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1864 break;
1865 }
1866 if (tmp_work <= 0)
1867 pr_warning(PFX "tx/rx enable wait too long\n");
1868
1869 /* and reinitialize all rx related registers */
1870 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1871 /* Must enable Tx/Rx before setting transfer thresholds! */
1872 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1873
1874 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1875 RTL_W32 (RxConfig, tp->rx_config);
1876 tp->cur_rx = 0;
1877
1878 pr_debug("init buffer addresses\n");
1879
1880 /* Lock Config[01234] and BMCR register writes */
1881 RTL_W8 (Cfg9346, Cfg9346_Lock);
1882
1883 /* init Rx ring buffer DMA address */
1884 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1885
1886 /* A.C.: Reset the multicast list. */
1887 __set_rx_mode (dev);
1888 #endif
1889 }
1890
1891 #if RX_BUF_IDX == 3
1892 static inline void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1893 u32 offset, unsigned int size)
1894 {
1895 u32 left = RX_BUF_LEN - offset;
1896
1897 if (size > left) {
1898 skb_copy_to_linear_data(skb, ring + offset, left);
1899 skb_copy_to_linear_data_offset(skb, left, ring, size - left);
1900 } else
1901 skb_copy_to_linear_data(skb, ring + offset, size);
1902 }
1903 #endif
1904
1905 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1906 {
1907 void __iomem *ioaddr = tp->mmio_addr;
1908 u16 status;
1909
1910 status = RTL_R16 (IntrStatus) & RxAckBits;
1911
1912 /* Clear out errors and receive interrupts */
1913 if (likely(status != 0)) {
1914 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1915 tp->dev->stats.rx_errors++;
1916 if (status & RxFIFOOver)
1917 tp->dev->stats.rx_fifo_errors++;
1918 }
1919 RTL_W16_F (IntrStatus, RxAckBits);
1920 }
1921 }
1922
1923 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1924 int budget)
1925 {
1926 void __iomem *ioaddr = tp->mmio_addr;
1927 int received = 0;
1928 unsigned char *rx_ring = tp->rx_ring;
1929 unsigned int cur_rx = tp->cur_rx;
1930 unsigned int rx_size = 0;
1931
1932 pr_debug("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
1933 " free to %4.4x, Cmd %2.2x.\n", dev->name, (u16)cur_rx,
1934 RTL_R16 (RxBufAddr),
1935 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
1936
1937 while (netif_running(dev) && received < budget
1938 && (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1939 u32 ring_offset = cur_rx % RX_BUF_LEN;
1940 u32 rx_status;
1941 unsigned int pkt_size;
1942 struct sk_buff *skb;
1943
1944 rmb();
1945
1946 /* read size+status of next frame from DMA ring buffer */
1947 rx_status = le32_to_cpu (*(__le32 *) (rx_ring + ring_offset));
1948 rx_size = rx_status >> 16;
1949 pkt_size = rx_size - 4;
1950
1951 if (netif_msg_rx_status(tp))
1952 pr_debug("%s: rtl8139_rx() status %4.4x, size %4.4x,"
1953 " cur %4.4x.\n", dev->name, rx_status,
1954 rx_size, cur_rx);
1955 #if RTL8139_DEBUG > 2
1956 {
1957 int i;
1958 pr_debug("%s: Frame contents ", dev->name);
1959 for (i = 0; i < 70; i++)
1960 pr_cont(" %2.2x",
1961 rx_ring[ring_offset + i]);
1962 pr_cont(".\n");
1963 }
1964 #endif
1965
1966 /* Packet copy from FIFO still in progress.
1967 * Theoretically, this should never happen
1968 * since EarlyRx is disabled.
1969 */
1970 if (unlikely(rx_size == 0xfff0)) {
1971 if (!tp->fifo_copy_timeout)
1972 tp->fifo_copy_timeout = jiffies + 2;
1973 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
1974 pr_debug("%s: hung FIFO. Reset.", dev->name);
1975 rx_size = 0;
1976 goto no_early_rx;
1977 }
1978 if (netif_msg_intr(tp)) {
1979 pr_debug("%s: fifo copy in progress.",
1980 dev->name);
1981 }
1982 tp->xstats.early_rx++;
1983 break;
1984 }
1985
1986 no_early_rx:
1987 tp->fifo_copy_timeout = 0;
1988
1989 /* If Rx err or invalid rx_size/rx_status received
1990 * (which happens if we get lost in the ring),
1991 * Rx process gets reset, so we abort any further
1992 * Rx processing.
1993 */
1994 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
1995 (rx_size < 8) ||
1996 (!(rx_status & RxStatusOK)))) {
1997 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
1998 received = -1;
1999 goto out;
2000 }
2001
2002 /* Malloc up new buffer, compatible with net-2e. */
2003 /* Omit the four octet CRC from the length. */
2004
2005 skb = netdev_alloc_skb(dev, pkt_size + NET_IP_ALIGN);
2006 if (likely(skb)) {
2007 skb_reserve (skb, NET_IP_ALIGN); /* 16 byte align the IP fields. */
2008 #if RX_BUF_IDX == 3
2009 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
2010 #else
2011 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size);
2012 #endif
2013 skb_put (skb, pkt_size);
2014
2015 skb->protocol = eth_type_trans (skb, dev);
2016
2017 dev->stats.rx_bytes += pkt_size;
2018 dev->stats.rx_packets++;
2019
2020 netif_receive_skb (skb);
2021 } else {
2022 if (net_ratelimit())
2023 pr_warning("%s: Memory squeeze, dropping packet.\n",
2024 dev->name);
2025 dev->stats.rx_dropped++;
2026 }
2027 received++;
2028
2029 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2030 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2031
2032 rtl8139_isr_ack(tp);
2033 }
2034
2035 if (unlikely(!received || rx_size == 0xfff0))
2036 rtl8139_isr_ack(tp);
2037
2038 pr_debug("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
2039 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
2040 RTL_R16 (RxBufAddr),
2041 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
2042
2043 tp->cur_rx = cur_rx;
2044
2045 /*
2046 * The receive buffer should be mostly empty.
2047 * Tell NAPI to reenable the Rx irq.
2048 */
2049 if (tp->fifo_copy_timeout)
2050 received = budget;
2051
2052 out:
2053 return received;
2054 }
2055
2056
2057 static void rtl8139_weird_interrupt (struct net_device *dev,
2058 struct rtl8139_private *tp,
2059 void __iomem *ioaddr,
2060 int status, int link_changed)
2061 {
2062 pr_debug("%s: Abnormal interrupt, status %8.8x.\n",
2063 dev->name, status);
2064
2065 assert (dev != NULL);
2066 assert (tp != NULL);
2067 assert (ioaddr != NULL);
2068
2069 /* Update the error count. */
2070 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2071 RTL_W32 (RxMissed, 0);
2072
2073 if ((status & RxUnderrun) && link_changed &&
2074 (tp->drv_flags & HAS_LNK_CHNG)) {
2075 rtl_check_media(dev, 0);
2076 status &= ~RxUnderrun;
2077 }
2078
2079 if (status & (RxUnderrun | RxErr))
2080 dev->stats.rx_errors++;
2081
2082 if (status & PCSTimeout)
2083 dev->stats.rx_length_errors++;
2084 if (status & RxUnderrun)
2085 dev->stats.rx_fifo_errors++;
2086 if (status & PCIErr) {
2087 u16 pci_cmd_status;
2088 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2089 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2090
2091 pr_err("%s: PCI Bus error %4.4x.\n",
2092 dev->name, pci_cmd_status);
2093 }
2094 }
2095
2096 static int rtl8139_poll(struct napi_struct *napi, int budget)
2097 {
2098 struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi);
2099 struct net_device *dev = tp->dev;
2100 void __iomem *ioaddr = tp->mmio_addr;
2101 int work_done;
2102
2103 spin_lock(&tp->rx_lock);
2104 work_done = 0;
2105 if (likely(RTL_R16(IntrStatus) & RxAckBits))
2106 work_done += rtl8139_rx(dev, tp, budget);
2107
2108 if (work_done < budget) {
2109 unsigned long flags;
2110 /*
2111 * Order is important since data can get interrupted
2112 * again when we think we are done.
2113 */
2114 spin_lock_irqsave(&tp->lock, flags);
2115 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2116 __napi_complete(napi);
2117 spin_unlock_irqrestore(&tp->lock, flags);
2118 }
2119 spin_unlock(&tp->rx_lock);
2120
2121 return work_done;
2122 }
2123
2124 /* The interrupt handler does all of the Rx thread work and cleans up
2125 after the Tx thread. */
2126 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance)
2127 {
2128 struct net_device *dev = (struct net_device *) dev_instance;
2129 struct rtl8139_private *tp = netdev_priv(dev);
2130 void __iomem *ioaddr = tp->mmio_addr;
2131 u16 status, ackstat;
2132 int link_changed = 0; /* avoid bogus "uninit" warning */
2133 int handled = 0;
2134
2135 spin_lock (&tp->lock);
2136 status = RTL_R16 (IntrStatus);
2137
2138 /* shared irq? */
2139 if (unlikely((status & rtl8139_intr_mask) == 0))
2140 goto out;
2141
2142 handled = 1;
2143
2144 /* h/w no longer present (hotplug?) or major error, bail */
2145 if (unlikely(status == 0xFFFF))
2146 goto out;
2147
2148 /* close possible race's with dev_close */
2149 if (unlikely(!netif_running(dev))) {
2150 RTL_W16 (IntrMask, 0);
2151 goto out;
2152 }
2153
2154 /* Acknowledge all of the current interrupt sources ASAP, but
2155 an first get an additional status bit from CSCR. */
2156 if (unlikely(status & RxUnderrun))
2157 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2158
2159 ackstat = status & ~(RxAckBits | TxErr);
2160 if (ackstat)
2161 RTL_W16 (IntrStatus, ackstat);
2162
2163 /* Receive packets are processed by poll routine.
2164 If not running start it now. */
2165 if (status & RxAckBits){
2166 if (napi_schedule_prep(&tp->napi)) {
2167 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2168 __napi_schedule(&tp->napi);
2169 }
2170 }
2171
2172 /* Check uncommon events with one test. */
2173 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2174 rtl8139_weird_interrupt (dev, tp, ioaddr,
2175 status, link_changed);
2176
2177 if (status & (TxOK | TxErr)) {
2178 rtl8139_tx_interrupt (dev, tp, ioaddr);
2179 if (status & TxErr)
2180 RTL_W16 (IntrStatus, TxErr);
2181 }
2182 out:
2183 spin_unlock (&tp->lock);
2184
2185 pr_debug("%s: exiting interrupt, intr_status=%#4.4x.\n",
2186 dev->name, RTL_R16 (IntrStatus));
2187 return IRQ_RETVAL(handled);
2188 }
2189
2190 #ifdef CONFIG_NET_POLL_CONTROLLER
2191 /*
2192 * Polling receive - used by netconsole and other diagnostic tools
2193 * to allow network i/o with interrupts disabled.
2194 */
2195 static void rtl8139_poll_controller(struct net_device *dev)
2196 {
2197 disable_irq(dev->irq);
2198 rtl8139_interrupt(dev->irq, dev);
2199 enable_irq(dev->irq);
2200 }
2201 #endif
2202
2203 static int rtl8139_set_mac_address(struct net_device *dev, void *p)
2204 {
2205 struct rtl8139_private *tp = netdev_priv(dev);
2206 void __iomem *ioaddr = tp->mmio_addr;
2207 struct sockaddr *addr = p;
2208
2209 if (!is_valid_ether_addr(addr->sa_data))
2210 return -EADDRNOTAVAIL;
2211
2212 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2213
2214 spin_lock_irq(&tp->lock);
2215
2216 RTL_W8_F(Cfg9346, Cfg9346_Unlock);
2217 RTL_W32_F(MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
2218 RTL_W32_F(MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
2219 RTL_W8_F(Cfg9346, Cfg9346_Lock);
2220
2221 spin_unlock_irq(&tp->lock);
2222
2223 return 0;
2224 }
2225
2226 static int rtl8139_close (struct net_device *dev)
2227 {
2228 struct rtl8139_private *tp = netdev_priv(dev);
2229 void __iomem *ioaddr = tp->mmio_addr;
2230 unsigned long flags;
2231
2232 netif_stop_queue(dev);
2233 napi_disable(&tp->napi);
2234
2235 if (netif_msg_ifdown(tp))
2236 pr_debug("%s: Shutting down ethercard, status was 0x%4.4x.\n",
2237 dev->name, RTL_R16 (IntrStatus));
2238
2239 spin_lock_irqsave (&tp->lock, flags);
2240
2241 /* Stop the chip's Tx and Rx DMA processes. */
2242 RTL_W8 (ChipCmd, 0);
2243
2244 /* Disable interrupts by clearing the interrupt mask. */
2245 RTL_W16 (IntrMask, 0);
2246
2247 /* Update the error counts. */
2248 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2249 RTL_W32 (RxMissed, 0);
2250
2251 spin_unlock_irqrestore (&tp->lock, flags);
2252
2253 free_irq (dev->irq, dev);
2254
2255 rtl8139_tx_clear (tp);
2256
2257 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
2258 tp->rx_ring, tp->rx_ring_dma);
2259 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
2260 tp->tx_bufs, tp->tx_bufs_dma);
2261 tp->rx_ring = NULL;
2262 tp->tx_bufs = NULL;
2263
2264 /* Green! Put the chip in low-power mode. */
2265 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2266
2267 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2268 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2269
2270 return 0;
2271 }
2272
2273
2274 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2275 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2276 other threads or interrupts aren't messing with the 8139. */
2277 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2278 {
2279 struct rtl8139_private *tp = netdev_priv(dev);
2280 void __iomem *ioaddr = tp->mmio_addr;
2281
2282 spin_lock_irq(&tp->lock);
2283 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
2284 u8 cfg3 = RTL_R8 (Config3);
2285 u8 cfg5 = RTL_R8 (Config5);
2286
2287 wol->supported = WAKE_PHY | WAKE_MAGIC
2288 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2289
2290 wol->wolopts = 0;
2291 if (cfg3 & Cfg3_LinkUp)
2292 wol->wolopts |= WAKE_PHY;
2293 if (cfg3 & Cfg3_Magic)
2294 wol->wolopts |= WAKE_MAGIC;
2295 /* (KON)FIXME: See how netdev_set_wol() handles the
2296 following constants. */
2297 if (cfg5 & Cfg5_UWF)
2298 wol->wolopts |= WAKE_UCAST;
2299 if (cfg5 & Cfg5_MWF)
2300 wol->wolopts |= WAKE_MCAST;
2301 if (cfg5 & Cfg5_BWF)
2302 wol->wolopts |= WAKE_BCAST;
2303 }
2304 spin_unlock_irq(&tp->lock);
2305 }
2306
2307
2308 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2309 that wol points to kernel memory and other threads or interrupts
2310 aren't messing with the 8139. */
2311 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2312 {
2313 struct rtl8139_private *tp = netdev_priv(dev);
2314 void __iomem *ioaddr = tp->mmio_addr;
2315 u32 support;
2316 u8 cfg3, cfg5;
2317
2318 support = ((rtl_chip_info[tp->chipset].flags & HasLWake)
2319 ? (WAKE_PHY | WAKE_MAGIC
2320 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2321 : 0);
2322 if (wol->wolopts & ~support)
2323 return -EINVAL;
2324
2325 spin_lock_irq(&tp->lock);
2326 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2327 if (wol->wolopts & WAKE_PHY)
2328 cfg3 |= Cfg3_LinkUp;
2329 if (wol->wolopts & WAKE_MAGIC)
2330 cfg3 |= Cfg3_Magic;
2331 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2332 RTL_W8 (Config3, cfg3);
2333 RTL_W8 (Cfg9346, Cfg9346_Lock);
2334
2335 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2336 /* (KON)FIXME: These are untested. We may have to set the
2337 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2338 documentation. */
2339 if (wol->wolopts & WAKE_UCAST)
2340 cfg5 |= Cfg5_UWF;
2341 if (wol->wolopts & WAKE_MCAST)
2342 cfg5 |= Cfg5_MWF;
2343 if (wol->wolopts & WAKE_BCAST)
2344 cfg5 |= Cfg5_BWF;
2345 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2346 spin_unlock_irq(&tp->lock);
2347
2348 return 0;
2349 }
2350
2351 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2352 {
2353 struct rtl8139_private *tp = netdev_priv(dev);
2354 strcpy(info->driver, DRV_NAME);
2355 strcpy(info->version, DRV_VERSION);
2356 strcpy(info->bus_info, pci_name(tp->pci_dev));
2357 info->regdump_len = tp->regs_len;
2358 }
2359
2360 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2361 {
2362 struct rtl8139_private *tp = netdev_priv(dev);
2363 spin_lock_irq(&tp->lock);
2364 mii_ethtool_gset(&tp->mii, cmd);
2365 spin_unlock_irq(&tp->lock);
2366 return 0;
2367 }
2368
2369 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2370 {
2371 struct rtl8139_private *tp = netdev_priv(dev);
2372 int rc;
2373 spin_lock_irq(&tp->lock);
2374 rc = mii_ethtool_sset(&tp->mii, cmd);
2375 spin_unlock_irq(&tp->lock);
2376 return rc;
2377 }
2378
2379 static int rtl8139_nway_reset(struct net_device *dev)
2380 {
2381 struct rtl8139_private *tp = netdev_priv(dev);
2382 return mii_nway_restart(&tp->mii);
2383 }
2384
2385 static u32 rtl8139_get_link(struct net_device *dev)
2386 {
2387 struct rtl8139_private *tp = netdev_priv(dev);
2388 return mii_link_ok(&tp->mii);
2389 }
2390
2391 static u32 rtl8139_get_msglevel(struct net_device *dev)
2392 {
2393 struct rtl8139_private *tp = netdev_priv(dev);
2394 return tp->msg_enable;
2395 }
2396
2397 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2398 {
2399 struct rtl8139_private *tp = netdev_priv(dev);
2400 tp->msg_enable = datum;
2401 }
2402
2403 static int rtl8139_get_regs_len(struct net_device *dev)
2404 {
2405 struct rtl8139_private *tp;
2406 /* TODO: we are too slack to do reg dumping for pio, for now */
2407 if (use_io)
2408 return 0;
2409 tp = netdev_priv(dev);
2410 return tp->regs_len;
2411 }
2412
2413 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2414 {
2415 struct rtl8139_private *tp;
2416
2417 /* TODO: we are too slack to do reg dumping for pio, for now */
2418 if (use_io)
2419 return;
2420 tp = netdev_priv(dev);
2421
2422 regs->version = RTL_REGS_VER;
2423
2424 spin_lock_irq(&tp->lock);
2425 memcpy_fromio(regbuf, tp->mmio_addr, regs->len);
2426 spin_unlock_irq(&tp->lock);
2427 }
2428
2429 static int rtl8139_get_sset_count(struct net_device *dev, int sset)
2430 {
2431 switch (sset) {
2432 case ETH_SS_STATS:
2433 return RTL_NUM_STATS;
2434 default:
2435 return -EOPNOTSUPP;
2436 }
2437 }
2438
2439 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2440 {
2441 struct rtl8139_private *tp = netdev_priv(dev);
2442
2443 data[0] = tp->xstats.early_rx;
2444 data[1] = tp->xstats.tx_buf_mapped;
2445 data[2] = tp->xstats.tx_timeouts;
2446 data[3] = tp->xstats.rx_lost_in_ring;
2447 }
2448
2449 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2450 {
2451 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2452 }
2453
2454 static const struct ethtool_ops rtl8139_ethtool_ops = {
2455 .get_drvinfo = rtl8139_get_drvinfo,
2456 .get_settings = rtl8139_get_settings,
2457 .set_settings = rtl8139_set_settings,
2458 .get_regs_len = rtl8139_get_regs_len,
2459 .get_regs = rtl8139_get_regs,
2460 .nway_reset = rtl8139_nway_reset,
2461 .get_link = rtl8139_get_link,
2462 .get_msglevel = rtl8139_get_msglevel,
2463 .set_msglevel = rtl8139_set_msglevel,
2464 .get_wol = rtl8139_get_wol,
2465 .set_wol = rtl8139_set_wol,
2466 .get_strings = rtl8139_get_strings,
2467 .get_sset_count = rtl8139_get_sset_count,
2468 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2469 };
2470
2471 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2472 {
2473 struct rtl8139_private *tp = netdev_priv(dev);
2474 int rc;
2475
2476 if (!netif_running(dev))
2477 return -EINVAL;
2478
2479 spin_lock_irq(&tp->lock);
2480 rc = generic_mii_ioctl(&tp->mii, if_mii(rq), cmd, NULL);
2481 spin_unlock_irq(&tp->lock);
2482
2483 return rc;
2484 }
2485
2486
2487 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2488 {
2489 struct rtl8139_private *tp = netdev_priv(dev);
2490 void __iomem *ioaddr = tp->mmio_addr;
2491 unsigned long flags;
2492
2493 if (netif_running(dev)) {
2494 spin_lock_irqsave (&tp->lock, flags);
2495 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2496 RTL_W32 (RxMissed, 0);
2497 spin_unlock_irqrestore (&tp->lock, flags);
2498 }
2499
2500 return &dev->stats;
2501 }
2502
2503 /* Set or clear the multicast filter for this adaptor.
2504 This routine is not state sensitive and need not be SMP locked. */
2505
2506 static void __set_rx_mode (struct net_device *dev)
2507 {
2508 struct rtl8139_private *tp = netdev_priv(dev);
2509 void __iomem *ioaddr = tp->mmio_addr;
2510 u32 mc_filter[2]; /* Multicast hash filter */
2511 int i, rx_mode;
2512 u32 tmp;
2513
2514 pr_debug("%s: rtl8139_set_rx_mode(%4.4x) done -- Rx config %8.8lx.\n",
2515 dev->name, dev->flags, RTL_R32 (RxConfig));
2516
2517 /* Note: do not reorder, GCC is clever about common statements. */
2518 if (dev->flags & IFF_PROMISC) {
2519 rx_mode =
2520 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2521 AcceptAllPhys;
2522 mc_filter[1] = mc_filter[0] = 0xffffffff;
2523 } else if ((dev->mc_count > multicast_filter_limit)
2524 || (dev->flags & IFF_ALLMULTI)) {
2525 /* Too many to filter perfectly -- accept all multicasts. */
2526 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2527 mc_filter[1] = mc_filter[0] = 0xffffffff;
2528 } else {
2529 struct dev_mc_list *mclist;
2530 rx_mode = AcceptBroadcast | AcceptMyPhys;
2531 mc_filter[1] = mc_filter[0] = 0;
2532 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2533 i++, mclist = mclist->next) {
2534 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2535
2536 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2537 rx_mode |= AcceptMulticast;
2538 }
2539 }
2540
2541 /* We can safely update without stopping the chip. */
2542 tmp = rtl8139_rx_config | rx_mode;
2543 if (tp->rx_config != tmp) {
2544 RTL_W32_F (RxConfig, tmp);
2545 tp->rx_config = tmp;
2546 }
2547 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2548 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2549 }
2550
2551 static void rtl8139_set_rx_mode (struct net_device *dev)
2552 {
2553 unsigned long flags;
2554 struct rtl8139_private *tp = netdev_priv(dev);
2555
2556 spin_lock_irqsave (&tp->lock, flags);
2557 __set_rx_mode(dev);
2558 spin_unlock_irqrestore (&tp->lock, flags);
2559 }
2560
2561 #ifdef CONFIG_PM
2562
2563 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
2564 {
2565 struct net_device *dev = pci_get_drvdata (pdev);
2566 struct rtl8139_private *tp = netdev_priv(dev);
2567 void __iomem *ioaddr = tp->mmio_addr;
2568 unsigned long flags;
2569
2570 pci_save_state (pdev);
2571
2572 if (!netif_running (dev))
2573 return 0;
2574
2575 netif_device_detach (dev);
2576
2577 spin_lock_irqsave (&tp->lock, flags);
2578
2579 /* Disable interrupts, stop Tx and Rx. */
2580 RTL_W16 (IntrMask, 0);
2581 RTL_W8 (ChipCmd, 0);
2582
2583 /* Update the error counts. */
2584 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2585 RTL_W32 (RxMissed, 0);
2586
2587 spin_unlock_irqrestore (&tp->lock, flags);
2588
2589 pci_set_power_state (pdev, PCI_D3hot);
2590
2591 return 0;
2592 }
2593
2594
2595 static int rtl8139_resume (struct pci_dev *pdev)
2596 {
2597 struct net_device *dev = pci_get_drvdata (pdev);
2598
2599 pci_restore_state (pdev);
2600 if (!netif_running (dev))
2601 return 0;
2602 pci_set_power_state (pdev, PCI_D0);
2603 rtl8139_init_ring (dev);
2604 rtl8139_hw_start (dev);
2605 netif_device_attach (dev);
2606 return 0;
2607 }
2608
2609 #endif /* CONFIG_PM */
2610
2611
2612 static struct pci_driver rtl8139_pci_driver = {
2613 .name = DRV_NAME,
2614 .id_table = rtl8139_pci_tbl,
2615 .probe = rtl8139_init_one,
2616 .remove = __devexit_p(rtl8139_remove_one),
2617 #ifdef CONFIG_PM
2618 .suspend = rtl8139_suspend,
2619 .resume = rtl8139_resume,
2620 #endif /* CONFIG_PM */
2621 };
2622
2623
2624 static int __init rtl8139_init_module (void)
2625 {
2626 /* when we're a module, we always print a version message,
2627 * even if no 8139 board is found.
2628 */
2629 #ifdef MODULE
2630 pr_info(RTL8139_DRIVER_NAME "\n");
2631 #endif
2632
2633 return pci_register_driver(&rtl8139_pci_driver);
2634 }
2635
2636
2637 static void __exit rtl8139_cleanup_module (void)
2638 {
2639 pci_unregister_driver (&rtl8139_pci_driver);
2640 }
2641
2642
2643 module_init(rtl8139_init_module);
2644 module_exit(rtl8139_cleanup_module);
Support for the Chinese Samsung S3C2440 based development boards