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pcmcia: convert fmvj18x driver to internal net_device_stats
[linux-2.6/mini2440.git] / drivers / net / r8169.c
blob06c535222666be7e1c5a0f933268cec7b58052a0
1 /*
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26
27 #include <asm/system.h>
28 #include <asm/io.h>
29 #include <asm/irq.h>
30
31 #define RTL8169_VERSION "2.3LK-NAPI"
32 #define MODULENAME "r8169"
33 #define PFX MODULENAME ": "
34
35 #ifdef RTL8169_DEBUG
36 #define assert(expr) \
37 if (!(expr)) { \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39 #expr,__FILE__,__func__,__LINE__); \
40 }
41 #define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
43 #else
44 #define assert(expr) do {} while (0)
45 #define dprintk(fmt, args...) do {} while (0)
46 #endif /* RTL8169_DEBUG */
47
48 #define R8169_MSG_DEFAULT \
49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
50
51 #define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
53
54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55 static const int max_interrupt_work = 20;
56
57 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
59 static const int multicast_filter_limit = 32;
60
61 /* MAC address length */
62 #define MAC_ADDR_LEN 6
63
64 #define MAX_READ_REQUEST_SHIFT 12
65 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
66 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
67 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
68 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
69 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
70 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
72
73 #define R8169_REGS_SIZE 256
74 #define R8169_NAPI_WEIGHT 64
75 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
78 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
80
81 #define RTL8169_TX_TIMEOUT (6*HZ)
82 #define RTL8169_PHY_TIMEOUT (10*HZ)
83
84 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
85 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
86 #define RTL_EEPROM_SIG_ADDR 0x0000
87
88 /* write/read MMIO register */
89 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
90 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
91 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
92 #define RTL_R8(reg) readb (ioaddr + (reg))
93 #define RTL_R16(reg) readw (ioaddr + (reg))
94 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
95
96 enum mac_version {
97 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
98 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
99 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
100 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
101 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
102 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
103 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
104 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
105 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
106 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
107 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
108 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
109 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
110 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
111 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
112 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
113 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
114 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
115 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
116 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
117 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
118 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
119 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
120 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
121 RTL_GIGA_MAC_VER_25 = 0x19 // 8168D
122 };
123
124 #define _R(NAME,MAC,MASK) \
125 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
126
127 static const struct {
128 const char *name;
129 u8 mac_version;
130 u32 RxConfigMask; /* Clears the bits supported by this chip */
131 } rtl_chip_info[] = {
132 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
133 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
134 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
135 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
136 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
137 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
138 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
139 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
140 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
141 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
142 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
144 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
145 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
146 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
147 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
148 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
149 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
153 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
154 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
155 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
156 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880) // PCI-E
157 };
158 #undef _R
159
160 enum cfg_version {
161 RTL_CFG_0 = 0x00,
162 RTL_CFG_1,
163 RTL_CFG_2
164 };
165
166 static void rtl_hw_start_8169(struct net_device *);
167 static void rtl_hw_start_8168(struct net_device *);
168 static void rtl_hw_start_8101(struct net_device *);
169
170 static struct pci_device_id rtl8169_pci_tbl[] = {
171 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
172 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
173 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
175 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
176 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
177 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
178 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
179 { PCI_VENDOR_ID_LINKSYS, 0x1032,
180 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
181 { 0x0001, 0x8168,
182 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
183 {0,},
184 };
185
186 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
187
188 static int rx_copybreak = 200;
189 static int use_dac;
190 static struct {
191 u32 msg_enable;
192 } debug = { -1 };
193
194 enum rtl_registers {
195 MAC0 = 0, /* Ethernet hardware address. */
196 MAC4 = 4,
197 MAR0 = 8, /* Multicast filter. */
198 CounterAddrLow = 0x10,
199 CounterAddrHigh = 0x14,
200 TxDescStartAddrLow = 0x20,
201 TxDescStartAddrHigh = 0x24,
202 TxHDescStartAddrLow = 0x28,
203 TxHDescStartAddrHigh = 0x2c,
204 FLASH = 0x30,
205 ERSR = 0x36,
206 ChipCmd = 0x37,
207 TxPoll = 0x38,
208 IntrMask = 0x3c,
209 IntrStatus = 0x3e,
210 TxConfig = 0x40,
211 RxConfig = 0x44,
212 RxMissed = 0x4c,
213 Cfg9346 = 0x50,
214 Config0 = 0x51,
215 Config1 = 0x52,
216 Config2 = 0x53,
217 Config3 = 0x54,
218 Config4 = 0x55,
219 Config5 = 0x56,
220 MultiIntr = 0x5c,
221 PHYAR = 0x60,
222 PHYstatus = 0x6c,
223 RxMaxSize = 0xda,
224 CPlusCmd = 0xe0,
225 IntrMitigate = 0xe2,
226 RxDescAddrLow = 0xe4,
227 RxDescAddrHigh = 0xe8,
228 EarlyTxThres = 0xec,
229 FuncEvent = 0xf0,
230 FuncEventMask = 0xf4,
231 FuncPresetState = 0xf8,
232 FuncForceEvent = 0xfc,
233 };
234
235 enum rtl8110_registers {
236 TBICSR = 0x64,
237 TBI_ANAR = 0x68,
238 TBI_LPAR = 0x6a,
239 };
240
241 enum rtl8168_8101_registers {
242 CSIDR = 0x64,
243 CSIAR = 0x68,
244 #define CSIAR_FLAG 0x80000000
245 #define CSIAR_WRITE_CMD 0x80000000
246 #define CSIAR_BYTE_ENABLE 0x0f
247 #define CSIAR_BYTE_ENABLE_SHIFT 12
248 #define CSIAR_ADDR_MASK 0x0fff
249
250 EPHYAR = 0x80,
251 #define EPHYAR_FLAG 0x80000000
252 #define EPHYAR_WRITE_CMD 0x80000000
253 #define EPHYAR_REG_MASK 0x1f
254 #define EPHYAR_REG_SHIFT 16
255 #define EPHYAR_DATA_MASK 0xffff
256 DBG_REG = 0xd1,
257 #define FIX_NAK_1 (1 << 4)
258 #define FIX_NAK_2 (1 << 3)
259 };
260
261 enum rtl_register_content {
262 /* InterruptStatusBits */
263 SYSErr = 0x8000,
264 PCSTimeout = 0x4000,
265 SWInt = 0x0100,
266 TxDescUnavail = 0x0080,
267 RxFIFOOver = 0x0040,
268 LinkChg = 0x0020,
269 RxOverflow = 0x0010,
270 TxErr = 0x0008,
271 TxOK = 0x0004,
272 RxErr = 0x0002,
273 RxOK = 0x0001,
274
275 /* RxStatusDesc */
276 RxFOVF = (1 << 23),
277 RxRWT = (1 << 22),
278 RxRES = (1 << 21),
279 RxRUNT = (1 << 20),
280 RxCRC = (1 << 19),
281
282 /* ChipCmdBits */
283 CmdReset = 0x10,
284 CmdRxEnb = 0x08,
285 CmdTxEnb = 0x04,
286 RxBufEmpty = 0x01,
287
288 /* TXPoll register p.5 */
289 HPQ = 0x80, /* Poll cmd on the high prio queue */
290 NPQ = 0x40, /* Poll cmd on the low prio queue */
291 FSWInt = 0x01, /* Forced software interrupt */
292
293 /* Cfg9346Bits */
294 Cfg9346_Lock = 0x00,
295 Cfg9346_Unlock = 0xc0,
296
297 /* rx_mode_bits */
298 AcceptErr = 0x20,
299 AcceptRunt = 0x10,
300 AcceptBroadcast = 0x08,
301 AcceptMulticast = 0x04,
302 AcceptMyPhys = 0x02,
303 AcceptAllPhys = 0x01,
304
305 /* RxConfigBits */
306 RxCfgFIFOShift = 13,
307 RxCfgDMAShift = 8,
308
309 /* TxConfigBits */
310 TxInterFrameGapShift = 24,
311 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
312
313 /* Config1 register p.24 */
314 LEDS1 = (1 << 7),
315 LEDS0 = (1 << 6),
316 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
317 Speed_down = (1 << 4),
318 MEMMAP = (1 << 3),
319 IOMAP = (1 << 2),
320 VPD = (1 << 1),
321 PMEnable = (1 << 0), /* Power Management Enable */
322
323 /* Config2 register p. 25 */
324 PCI_Clock_66MHz = 0x01,
325 PCI_Clock_33MHz = 0x00,
326
327 /* Config3 register p.25 */
328 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
329 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
330 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
331
332 /* Config5 register p.27 */
333 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
334 MWF = (1 << 5), /* Accept Multicast wakeup frame */
335 UWF = (1 << 4), /* Accept Unicast wakeup frame */
336 LanWake = (1 << 1), /* LanWake enable/disable */
337 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
338
339 /* TBICSR p.28 */
340 TBIReset = 0x80000000,
341 TBILoopback = 0x40000000,
342 TBINwEnable = 0x20000000,
343 TBINwRestart = 0x10000000,
344 TBILinkOk = 0x02000000,
345 TBINwComplete = 0x01000000,
346
347 /* CPlusCmd p.31 */
348 EnableBist = (1 << 15), // 8168 8101
349 Mac_dbgo_oe = (1 << 14), // 8168 8101
350 Normal_mode = (1 << 13), // unused
351 Force_half_dup = (1 << 12), // 8168 8101
352 Force_rxflow_en = (1 << 11), // 8168 8101
353 Force_txflow_en = (1 << 10), // 8168 8101
354 Cxpl_dbg_sel = (1 << 9), // 8168 8101
355 ASF = (1 << 8), // 8168 8101
356 PktCntrDisable = (1 << 7), // 8168 8101
357 Mac_dbgo_sel = 0x001c, // 8168
358 RxVlan = (1 << 6),
359 RxChkSum = (1 << 5),
360 PCIDAC = (1 << 4),
361 PCIMulRW = (1 << 3),
362 INTT_0 = 0x0000, // 8168
363 INTT_1 = 0x0001, // 8168
364 INTT_2 = 0x0002, // 8168
365 INTT_3 = 0x0003, // 8168
366
367 /* rtl8169_PHYstatus */
368 TBI_Enable = 0x80,
369 TxFlowCtrl = 0x40,
370 RxFlowCtrl = 0x20,
371 _1000bpsF = 0x10,
372 _100bps = 0x08,
373 _10bps = 0x04,
374 LinkStatus = 0x02,
375 FullDup = 0x01,
376
377 /* _TBICSRBit */
378 TBILinkOK = 0x02000000,
379
380 /* DumpCounterCommand */
381 CounterDump = 0x8,
382 };
383
384 enum desc_status_bit {
385 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
386 RingEnd = (1 << 30), /* End of descriptor ring */
387 FirstFrag = (1 << 29), /* First segment of a packet */
388 LastFrag = (1 << 28), /* Final segment of a packet */
389
390 /* Tx private */
391 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
392 MSSShift = 16, /* MSS value position */
393 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
394 IPCS = (1 << 18), /* Calculate IP checksum */
395 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
396 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
397 TxVlanTag = (1 << 17), /* Add VLAN tag */
398
399 /* Rx private */
400 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
401 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
402
403 #define RxProtoUDP (PID1)
404 #define RxProtoTCP (PID0)
405 #define RxProtoIP (PID1 | PID0)
406 #define RxProtoMask RxProtoIP
407
408 IPFail = (1 << 16), /* IP checksum failed */
409 UDPFail = (1 << 15), /* UDP/IP checksum failed */
410 TCPFail = (1 << 14), /* TCP/IP checksum failed */
411 RxVlanTag = (1 << 16), /* VLAN tag available */
412 };
413
414 #define RsvdMask 0x3fffc000
415
416 struct TxDesc {
417 __le32 opts1;
418 __le32 opts2;
419 __le64 addr;
420 };
421
422 struct RxDesc {
423 __le32 opts1;
424 __le32 opts2;
425 __le64 addr;
426 };
427
428 struct ring_info {
429 struct sk_buff *skb;
430 u32 len;
431 u8 __pad[sizeof(void *) - sizeof(u32)];
432 };
433
434 enum features {
435 RTL_FEATURE_WOL = (1 << 0),
436 RTL_FEATURE_MSI = (1 << 1),
437 RTL_FEATURE_GMII = (1 << 2),
438 };
439
440 struct rtl8169_counters {
441 __le64 tx_packets;
442 __le64 rx_packets;
443 __le64 tx_errors;
444 __le32 rx_errors;
445 __le16 rx_missed;
446 __le16 align_errors;
447 __le32 tx_one_collision;
448 __le32 tx_multi_collision;
449 __le64 rx_unicast;
450 __le64 rx_broadcast;
451 __le32 rx_multicast;
452 __le16 tx_aborted;
453 __le16 tx_underun;
454 };
455
456 struct rtl8169_private {
457 void __iomem *mmio_addr; /* memory map physical address */
458 struct pci_dev *pci_dev; /* Index of PCI device */
459 struct net_device *dev;
460 struct napi_struct napi;
461 spinlock_t lock; /* spin lock flag */
462 u32 msg_enable;
463 int chipset;
464 int mac_version;
465 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
466 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
467 u32 dirty_rx;
468 u32 dirty_tx;
469 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
470 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
471 dma_addr_t TxPhyAddr;
472 dma_addr_t RxPhyAddr;
473 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
474 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
475 unsigned align;
476 unsigned rx_buf_sz;
477 struct timer_list timer;
478 u16 cp_cmd;
479 u16 intr_event;
480 u16 napi_event;
481 u16 intr_mask;
482 int phy_auto_nego_reg;
483 int phy_1000_ctrl_reg;
484 #ifdef CONFIG_R8169_VLAN
485 struct vlan_group *vlgrp;
486 #endif
487 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
488 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
489 void (*phy_reset_enable)(void __iomem *);
490 void (*hw_start)(struct net_device *);
491 unsigned int (*phy_reset_pending)(void __iomem *);
492 unsigned int (*link_ok)(void __iomem *);
493 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
494 int pcie_cap;
495 struct delayed_work task;
496 unsigned features;
497
498 struct mii_if_info mii;
499 struct rtl8169_counters counters;
500 };
501
502 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
503 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
504 module_param(rx_copybreak, int, 0);
505 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
506 module_param(use_dac, int, 0);
507 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
508 module_param_named(debug, debug.msg_enable, int, 0);
509 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
510 MODULE_LICENSE("GPL");
511 MODULE_VERSION(RTL8169_VERSION);
512
513 static int rtl8169_open(struct net_device *dev);
514 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
515 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
516 static int rtl8169_init_ring(struct net_device *dev);
517 static void rtl_hw_start(struct net_device *dev);
518 static int rtl8169_close(struct net_device *dev);
519 static void rtl_set_rx_mode(struct net_device *dev);
520 static void rtl8169_tx_timeout(struct net_device *dev);
521 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
522 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
523 void __iomem *, u32 budget);
524 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
525 static void rtl8169_down(struct net_device *dev);
526 static void rtl8169_rx_clear(struct rtl8169_private *tp);
527 static int rtl8169_poll(struct napi_struct *napi, int budget);
528
529 static const unsigned int rtl8169_rx_config =
530 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
531
532 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
533 {
534 int i;
535
536 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
537
538 for (i = 20; i > 0; i--) {
539 /*
540 * Check if the RTL8169 has completed writing to the specified
541 * MII register.
542 */
543 if (!(RTL_R32(PHYAR) & 0x80000000))
544 break;
545 udelay(25);
546 }
547 }
548
549 static int mdio_read(void __iomem *ioaddr, int reg_addr)
550 {
551 int i, value = -1;
552
553 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
554
555 for (i = 20; i > 0; i--) {
556 /*
557 * Check if the RTL8169 has completed retrieving data from
558 * the specified MII register.
559 */
560 if (RTL_R32(PHYAR) & 0x80000000) {
561 value = RTL_R32(PHYAR) & 0xffff;
562 break;
563 }
564 udelay(25);
565 }
566 return value;
567 }
568
569 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
570 {
571 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
572 }
573
574 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
575 int val)
576 {
577 struct rtl8169_private *tp = netdev_priv(dev);
578 void __iomem *ioaddr = tp->mmio_addr;
579
580 mdio_write(ioaddr, location, val);
581 }
582
583 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
584 {
585 struct rtl8169_private *tp = netdev_priv(dev);
586 void __iomem *ioaddr = tp->mmio_addr;
587
588 return mdio_read(ioaddr, location);
589 }
590
591 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
592 {
593 unsigned int i;
594
595 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
596 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
597
598 for (i = 0; i < 100; i++) {
599 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
600 break;
601 udelay(10);
602 }
603 }
604
605 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
606 {
607 u16 value = 0xffff;
608 unsigned int i;
609
610 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
611
612 for (i = 0; i < 100; i++) {
613 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
614 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
615 break;
616 }
617 udelay(10);
618 }
619
620 return value;
621 }
622
623 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
624 {
625 unsigned int i;
626
627 RTL_W32(CSIDR, value);
628 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
629 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
630
631 for (i = 0; i < 100; i++) {
632 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
633 break;
634 udelay(10);
635 }
636 }
637
638 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
639 {
640 u32 value = ~0x00;
641 unsigned int i;
642
643 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
644 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
645
646 for (i = 0; i < 100; i++) {
647 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
648 value = RTL_R32(CSIDR);
649 break;
650 }
651 udelay(10);
652 }
653
654 return value;
655 }
656
657 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
658 {
659 RTL_W16(IntrMask, 0x0000);
660
661 RTL_W16(IntrStatus, 0xffff);
662 }
663
664 static void rtl8169_asic_down(void __iomem *ioaddr)
665 {
666 RTL_W8(ChipCmd, 0x00);
667 rtl8169_irq_mask_and_ack(ioaddr);
668 RTL_R16(CPlusCmd);
669 }
670
671 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
672 {
673 return RTL_R32(TBICSR) & TBIReset;
674 }
675
676 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
677 {
678 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
679 }
680
681 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
682 {
683 return RTL_R32(TBICSR) & TBILinkOk;
684 }
685
686 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
687 {
688 return RTL_R8(PHYstatus) & LinkStatus;
689 }
690
691 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
692 {
693 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
694 }
695
696 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
697 {
698 unsigned int val;
699
700 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
701 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
702 }
703
704 static void rtl8169_check_link_status(struct net_device *dev,
705 struct rtl8169_private *tp,
706 void __iomem *ioaddr)
707 {
708 unsigned long flags;
709
710 spin_lock_irqsave(&tp->lock, flags);
711 if (tp->link_ok(ioaddr)) {
712 netif_carrier_on(dev);
713 if (netif_msg_ifup(tp))
714 printk(KERN_INFO PFX "%s: link up\n", dev->name);
715 } else {
716 if (netif_msg_ifdown(tp))
717 printk(KERN_INFO PFX "%s: link down\n", dev->name);
718 netif_carrier_off(dev);
719 }
720 spin_unlock_irqrestore(&tp->lock, flags);
721 }
722
723 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
724 {
725 struct rtl8169_private *tp = netdev_priv(dev);
726 void __iomem *ioaddr = tp->mmio_addr;
727 u8 options;
728
729 wol->wolopts = 0;
730
731 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
732 wol->supported = WAKE_ANY;
733
734 spin_lock_irq(&tp->lock);
735
736 options = RTL_R8(Config1);
737 if (!(options & PMEnable))
738 goto out_unlock;
739
740 options = RTL_R8(Config3);
741 if (options & LinkUp)
742 wol->wolopts |= WAKE_PHY;
743 if (options & MagicPacket)
744 wol->wolopts |= WAKE_MAGIC;
745
746 options = RTL_R8(Config5);
747 if (options & UWF)
748 wol->wolopts |= WAKE_UCAST;
749 if (options & BWF)
750 wol->wolopts |= WAKE_BCAST;
751 if (options & MWF)
752 wol->wolopts |= WAKE_MCAST;
753
754 out_unlock:
755 spin_unlock_irq(&tp->lock);
756 }
757
758 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
759 {
760 struct rtl8169_private *tp = netdev_priv(dev);
761 void __iomem *ioaddr = tp->mmio_addr;
762 unsigned int i;
763 static struct {
764 u32 opt;
765 u16 reg;
766 u8 mask;
767 } cfg[] = {
768 { WAKE_ANY, Config1, PMEnable },
769 { WAKE_PHY, Config3, LinkUp },
770 { WAKE_MAGIC, Config3, MagicPacket },
771 { WAKE_UCAST, Config5, UWF },
772 { WAKE_BCAST, Config5, BWF },
773 { WAKE_MCAST, Config5, MWF },
774 { WAKE_ANY, Config5, LanWake }
775 };
776
777 spin_lock_irq(&tp->lock);
778
779 RTL_W8(Cfg9346, Cfg9346_Unlock);
780
781 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
782 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
783 if (wol->wolopts & cfg[i].opt)
784 options |= cfg[i].mask;
785 RTL_W8(cfg[i].reg, options);
786 }
787
788 RTL_W8(Cfg9346, Cfg9346_Lock);
789
790 if (wol->wolopts)
791 tp->features |= RTL_FEATURE_WOL;
792 else
793 tp->features &= ~RTL_FEATURE_WOL;
794 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
795
796 spin_unlock_irq(&tp->lock);
797
798 return 0;
799 }
800
801 static void rtl8169_get_drvinfo(struct net_device *dev,
802 struct ethtool_drvinfo *info)
803 {
804 struct rtl8169_private *tp = netdev_priv(dev);
805
806 strcpy(info->driver, MODULENAME);
807 strcpy(info->version, RTL8169_VERSION);
808 strcpy(info->bus_info, pci_name(tp->pci_dev));
809 }
810
811 static int rtl8169_get_regs_len(struct net_device *dev)
812 {
813 return R8169_REGS_SIZE;
814 }
815
816 static int rtl8169_set_speed_tbi(struct net_device *dev,
817 u8 autoneg, u16 speed, u8 duplex)
818 {
819 struct rtl8169_private *tp = netdev_priv(dev);
820 void __iomem *ioaddr = tp->mmio_addr;
821 int ret = 0;
822 u32 reg;
823
824 reg = RTL_R32(TBICSR);
825 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
826 (duplex == DUPLEX_FULL)) {
827 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
828 } else if (autoneg == AUTONEG_ENABLE)
829 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
830 else {
831 if (netif_msg_link(tp)) {
832 printk(KERN_WARNING "%s: "
833 "incorrect speed setting refused in TBI mode\n",
834 dev->name);
835 }
836 ret = -EOPNOTSUPP;
837 }
838
839 return ret;
840 }
841
842 static int rtl8169_set_speed_xmii(struct net_device *dev,
843 u8 autoneg, u16 speed, u8 duplex)
844 {
845 struct rtl8169_private *tp = netdev_priv(dev);
846 void __iomem *ioaddr = tp->mmio_addr;
847 int auto_nego, giga_ctrl;
848
849 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
850 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
851 ADVERTISE_100HALF | ADVERTISE_100FULL);
852 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
853 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
854
855 if (autoneg == AUTONEG_ENABLE) {
856 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
857 ADVERTISE_100HALF | ADVERTISE_100FULL);
858 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
859 } else {
860 if (speed == SPEED_10)
861 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
862 else if (speed == SPEED_100)
863 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
864 else if (speed == SPEED_1000)
865 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
866
867 if (duplex == DUPLEX_HALF)
868 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
869
870 if (duplex == DUPLEX_FULL)
871 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
872
873 /* This tweak comes straight from Realtek's driver. */
874 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
875 ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
876 (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
877 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
878 }
879 }
880
881 /* The 8100e/8101e/8102e do Fast Ethernet only. */
882 if ((tp->mac_version == RTL_GIGA_MAC_VER_07) ||
883 (tp->mac_version == RTL_GIGA_MAC_VER_08) ||
884 (tp->mac_version == RTL_GIGA_MAC_VER_09) ||
885 (tp->mac_version == RTL_GIGA_MAC_VER_10) ||
886 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
887 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
888 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
889 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
890 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
891 netif_msg_link(tp)) {
892 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
893 dev->name);
894 }
895 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
896 }
897
898 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
899
900 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
901 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
902 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
903 /*
904 * Wake up the PHY.
905 * Vendor specific (0x1f) and reserved (0x0e) MII registers.
906 */
907 mdio_write(ioaddr, 0x1f, 0x0000);
908 mdio_write(ioaddr, 0x0e, 0x0000);
909 }
910
911 tp->phy_auto_nego_reg = auto_nego;
912 tp->phy_1000_ctrl_reg = giga_ctrl;
913
914 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
915 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
916 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
917 return 0;
918 }
919
920 static int rtl8169_set_speed(struct net_device *dev,
921 u8 autoneg, u16 speed, u8 duplex)
922 {
923 struct rtl8169_private *tp = netdev_priv(dev);
924 int ret;
925
926 ret = tp->set_speed(dev, autoneg, speed, duplex);
927
928 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
929 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
930
931 return ret;
932 }
933
934 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
935 {
936 struct rtl8169_private *tp = netdev_priv(dev);
937 unsigned long flags;
938 int ret;
939
940 spin_lock_irqsave(&tp->lock, flags);
941 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
942 spin_unlock_irqrestore(&tp->lock, flags);
943
944 return ret;
945 }
946
947 static u32 rtl8169_get_rx_csum(struct net_device *dev)
948 {
949 struct rtl8169_private *tp = netdev_priv(dev);
950
951 return tp->cp_cmd & RxChkSum;
952 }
953
954 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
955 {
956 struct rtl8169_private *tp = netdev_priv(dev);
957 void __iomem *ioaddr = tp->mmio_addr;
958 unsigned long flags;
959
960 spin_lock_irqsave(&tp->lock, flags);
961
962 if (data)
963 tp->cp_cmd |= RxChkSum;
964 else
965 tp->cp_cmd &= ~RxChkSum;
966
967 RTL_W16(CPlusCmd, tp->cp_cmd);
968 RTL_R16(CPlusCmd);
969
970 spin_unlock_irqrestore(&tp->lock, flags);
971
972 return 0;
973 }
974
975 #ifdef CONFIG_R8169_VLAN
976
977 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
978 struct sk_buff *skb)
979 {
980 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
981 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
982 }
983
984 static void rtl8169_vlan_rx_register(struct net_device *dev,
985 struct vlan_group *grp)
986 {
987 struct rtl8169_private *tp = netdev_priv(dev);
988 void __iomem *ioaddr = tp->mmio_addr;
989 unsigned long flags;
990
991 spin_lock_irqsave(&tp->lock, flags);
992 tp->vlgrp = grp;
993 if (tp->vlgrp)
994 tp->cp_cmd |= RxVlan;
995 else
996 tp->cp_cmd &= ~RxVlan;
997 RTL_W16(CPlusCmd, tp->cp_cmd);
998 RTL_R16(CPlusCmd);
999 spin_unlock_irqrestore(&tp->lock, flags);
1000 }
1001
1002 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1003 struct sk_buff *skb)
1004 {
1005 u32 opts2 = le32_to_cpu(desc->opts2);
1006 struct vlan_group *vlgrp = tp->vlgrp;
1007 int ret;
1008
1009 if (vlgrp && (opts2 & RxVlanTag)) {
1010 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
1011 ret = 0;
1012 } else
1013 ret = -1;
1014 desc->opts2 = 0;
1015 return ret;
1016 }
1017
1018 #else /* !CONFIG_R8169_VLAN */
1019
1020 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1021 struct sk_buff *skb)
1022 {
1023 return 0;
1024 }
1025
1026 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1027 struct sk_buff *skb)
1028 {
1029 return -1;
1030 }
1031
1032 #endif
1033
1034 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1035 {
1036 struct rtl8169_private *tp = netdev_priv(dev);
1037 void __iomem *ioaddr = tp->mmio_addr;
1038 u32 status;
1039
1040 cmd->supported =
1041 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1042 cmd->port = PORT_FIBRE;
1043 cmd->transceiver = XCVR_INTERNAL;
1044
1045 status = RTL_R32(TBICSR);
1046 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1047 cmd->autoneg = !!(status & TBINwEnable);
1048
1049 cmd->speed = SPEED_1000;
1050 cmd->duplex = DUPLEX_FULL; /* Always set */
1051
1052 return 0;
1053 }
1054
1055 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1056 {
1057 struct rtl8169_private *tp = netdev_priv(dev);
1058
1059 return mii_ethtool_gset(&tp->mii, cmd);
1060 }
1061
1062 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1063 {
1064 struct rtl8169_private *tp = netdev_priv(dev);
1065 unsigned long flags;
1066 int rc;
1067
1068 spin_lock_irqsave(&tp->lock, flags);
1069
1070 rc = tp->get_settings(dev, cmd);
1071
1072 spin_unlock_irqrestore(&tp->lock, flags);
1073 return rc;
1074 }
1075
1076 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1077 void *p)
1078 {
1079 struct rtl8169_private *tp = netdev_priv(dev);
1080 unsigned long flags;
1081
1082 if (regs->len > R8169_REGS_SIZE)
1083 regs->len = R8169_REGS_SIZE;
1084
1085 spin_lock_irqsave(&tp->lock, flags);
1086 memcpy_fromio(p, tp->mmio_addr, regs->len);
1087 spin_unlock_irqrestore(&tp->lock, flags);
1088 }
1089
1090 static u32 rtl8169_get_msglevel(struct net_device *dev)
1091 {
1092 struct rtl8169_private *tp = netdev_priv(dev);
1093
1094 return tp->msg_enable;
1095 }
1096
1097 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1098 {
1099 struct rtl8169_private *tp = netdev_priv(dev);
1100
1101 tp->msg_enable = value;
1102 }
1103
1104 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1105 "tx_packets",
1106 "rx_packets",
1107 "tx_errors",
1108 "rx_errors",
1109 "rx_missed",
1110 "align_errors",
1111 "tx_single_collisions",
1112 "tx_multi_collisions",
1113 "unicast",
1114 "broadcast",
1115 "multicast",
1116 "tx_aborted",
1117 "tx_underrun",
1118 };
1119
1120 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1121 {
1122 switch (sset) {
1123 case ETH_SS_STATS:
1124 return ARRAY_SIZE(rtl8169_gstrings);
1125 default:
1126 return -EOPNOTSUPP;
1127 }
1128 }
1129
1130 static void rtl8169_update_counters(struct net_device *dev)
1131 {
1132 struct rtl8169_private *tp = netdev_priv(dev);
1133 void __iomem *ioaddr = tp->mmio_addr;
1134 struct rtl8169_counters *counters;
1135 dma_addr_t paddr;
1136 u32 cmd;
1137 int wait = 1000;
1138
1139 /*
1140 * Some chips are unable to dump tally counters when the receiver
1141 * is disabled.
1142 */
1143 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1144 return;
1145
1146 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1147 if (!counters)
1148 return;
1149
1150 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1151 cmd = (u64)paddr & DMA_32BIT_MASK;
1152 RTL_W32(CounterAddrLow, cmd);
1153 RTL_W32(CounterAddrLow, cmd | CounterDump);
1154
1155 while (wait--) {
1156 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1157 /* copy updated counters */
1158 memcpy(&tp->counters, counters, sizeof(*counters));
1159 break;
1160 }
1161 udelay(10);
1162 }
1163
1164 RTL_W32(CounterAddrLow, 0);
1165 RTL_W32(CounterAddrHigh, 0);
1166
1167 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1168 }
1169
1170 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1171 struct ethtool_stats *stats, u64 *data)
1172 {
1173 struct rtl8169_private *tp = netdev_priv(dev);
1174
1175 ASSERT_RTNL();
1176
1177 rtl8169_update_counters(dev);
1178
1179 data[0] = le64_to_cpu(tp->counters.tx_packets);
1180 data[1] = le64_to_cpu(tp->counters.rx_packets);
1181 data[2] = le64_to_cpu(tp->counters.tx_errors);
1182 data[3] = le32_to_cpu(tp->counters.rx_errors);
1183 data[4] = le16_to_cpu(tp->counters.rx_missed);
1184 data[5] = le16_to_cpu(tp->counters.align_errors);
1185 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1186 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1187 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1188 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1189 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1190 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1191 data[12] = le16_to_cpu(tp->counters.tx_underun);
1192 }
1193
1194 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1195 {
1196 switch(stringset) {
1197 case ETH_SS_STATS:
1198 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1199 break;
1200 }
1201 }
1202
1203 static const struct ethtool_ops rtl8169_ethtool_ops = {
1204 .get_drvinfo = rtl8169_get_drvinfo,
1205 .get_regs_len = rtl8169_get_regs_len,
1206 .get_link = ethtool_op_get_link,
1207 .get_settings = rtl8169_get_settings,
1208 .set_settings = rtl8169_set_settings,
1209 .get_msglevel = rtl8169_get_msglevel,
1210 .set_msglevel = rtl8169_set_msglevel,
1211 .get_rx_csum = rtl8169_get_rx_csum,
1212 .set_rx_csum = rtl8169_set_rx_csum,
1213 .set_tx_csum = ethtool_op_set_tx_csum,
1214 .set_sg = ethtool_op_set_sg,
1215 .set_tso = ethtool_op_set_tso,
1216 .get_regs = rtl8169_get_regs,
1217 .get_wol = rtl8169_get_wol,
1218 .set_wol = rtl8169_set_wol,
1219 .get_strings = rtl8169_get_strings,
1220 .get_sset_count = rtl8169_get_sset_count,
1221 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1222 };
1223
1224 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1225 int bitnum, int bitval)
1226 {
1227 int val;
1228
1229 val = mdio_read(ioaddr, reg);
1230 val = (bitval == 1) ?
1231 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
1232 mdio_write(ioaddr, reg, val & 0xffff);
1233 }
1234
1235 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1236 void __iomem *ioaddr)
1237 {
1238 /*
1239 * The driver currently handles the 8168Bf and the 8168Be identically
1240 * but they can be identified more specifically through the test below
1241 * if needed:
1242 *
1243 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1244 *
1245 * Same thing for the 8101Eb and the 8101Ec:
1246 *
1247 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1248 */
1249 const struct {
1250 u32 mask;
1251 u32 val;
1252 int mac_version;
1253 } mac_info[] = {
1254 /* 8168D family. */
1255 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_25 },
1256
1257 /* 8168C family. */
1258 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 },
1259 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1260 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1261 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1262 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1263 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1264 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1265 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1266 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1267
1268 /* 8168B family. */
1269 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1270 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1271 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1272 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1273
1274 /* 8101 family. */
1275 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1276 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1277 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1278 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1279 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1280 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1281 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1282 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1283 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1284 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1285 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1286 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1287 /* FIXME: where did these entries come from ? -- FR */
1288 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1289 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1290
1291 /* 8110 family. */
1292 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1293 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1294 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1295 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1296 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1297 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1298
1299 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1300 }, *p = mac_info;
1301 u32 reg;
1302
1303 reg = RTL_R32(TxConfig);
1304 while ((reg & p->mask) != p->val)
1305 p++;
1306 tp->mac_version = p->mac_version;
1307
1308 if (p->mask == 0x00000000) {
1309 struct pci_dev *pdev = tp->pci_dev;
1310
1311 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1312 }
1313 }
1314
1315 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1316 {
1317 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1318 }
1319
1320 struct phy_reg {
1321 u16 reg;
1322 u16 val;
1323 };
1324
1325 static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1326 {
1327 while (len-- > 0) {
1328 mdio_write(ioaddr, regs->reg, regs->val);
1329 regs++;
1330 }
1331 }
1332
1333 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1334 {
1335 struct {
1336 u16 regs[5]; /* Beware of bit-sign propagation */
1337 } phy_magic[5] = { {
1338 { 0x0000, //w 4 15 12 0
1339 0x00a1, //w 3 15 0 00a1
1340 0x0008, //w 2 15 0 0008
1341 0x1020, //w 1 15 0 1020
1342 0x1000 } },{ //w 0 15 0 1000
1343 { 0x7000, //w 4 15 12 7
1344 0xff41, //w 3 15 0 ff41
1345 0xde60, //w 2 15 0 de60
1346 0x0140, //w 1 15 0 0140
1347 0x0077 } },{ //w 0 15 0 0077
1348 { 0xa000, //w 4 15 12 a
1349 0xdf01, //w 3 15 0 df01
1350 0xdf20, //w 2 15 0 df20
1351 0xff95, //w 1 15 0 ff95
1352 0xfa00 } },{ //w 0 15 0 fa00
1353 { 0xb000, //w 4 15 12 b
1354 0xff41, //w 3 15 0 ff41
1355 0xde20, //w 2 15 0 de20
1356 0x0140, //w 1 15 0 0140
1357 0x00bb } },{ //w 0 15 0 00bb
1358 { 0xf000, //w 4 15 12 f
1359 0xdf01, //w 3 15 0 df01
1360 0xdf20, //w 2 15 0 df20
1361 0xff95, //w 1 15 0 ff95
1362 0xbf00 } //w 0 15 0 bf00
1363 }
1364 }, *p = phy_magic;
1365 unsigned int i;
1366
1367 mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1
1368 mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000
1369 mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7
1370 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1371
1372 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1373 int val, pos = 4;
1374
1375 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1376 mdio_write(ioaddr, pos, val);
1377 while (--pos >= 0)
1378 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1379 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1380 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1381 }
1382 mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1383 }
1384
1385 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1386 {
1387 struct phy_reg phy_reg_init[] = {
1388 { 0x1f, 0x0002 },
1389 { 0x01, 0x90d0 },
1390 { 0x1f, 0x0000 }
1391 };
1392
1393 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1394 }
1395
1396 static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1397 {
1398 struct phy_reg phy_reg_init[] = {
1399 { 0x10, 0xf41b },
1400 { 0x1f, 0x0000 }
1401 };
1402
1403 mdio_write(ioaddr, 0x1f, 0x0001);
1404 mdio_patch(ioaddr, 0x16, 1 << 0);
1405
1406 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1407 }
1408
1409 static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1410 {
1411 struct phy_reg phy_reg_init[] = {
1412 { 0x1f, 0x0001 },
1413 { 0x10, 0xf41b },
1414 { 0x1f, 0x0000 }
1415 };
1416
1417 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1418 }
1419
1420 static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
1421 {
1422 struct phy_reg phy_reg_init[] = {
1423 { 0x1f, 0x0000 },
1424 { 0x1d, 0x0f00 },
1425 { 0x1f, 0x0002 },
1426 { 0x0c, 0x1ec8 },
1427 { 0x1f, 0x0000 }
1428 };
1429
1430 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1431 }
1432
1433 static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1434 {
1435 struct phy_reg phy_reg_init[] = {
1436 { 0x1f, 0x0001 },
1437 { 0x1d, 0x3d98 },
1438 { 0x1f, 0x0000 }
1439 };
1440
1441 mdio_write(ioaddr, 0x1f, 0x0000);
1442 mdio_patch(ioaddr, 0x14, 1 << 5);
1443 mdio_patch(ioaddr, 0x0d, 1 << 5);
1444
1445 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1446 }
1447
1448 static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
1449 {
1450 struct phy_reg phy_reg_init[] = {
1451 { 0x1f, 0x0001 },
1452 { 0x12, 0x2300 },
1453 { 0x1f, 0x0002 },
1454 { 0x00, 0x88d4 },
1455 { 0x01, 0x82b1 },
1456 { 0x03, 0x7002 },
1457 { 0x08, 0x9e30 },
1458 { 0x09, 0x01f0 },
1459 { 0x0a, 0x5500 },
1460 { 0x0c, 0x00c8 },
1461 { 0x1f, 0x0003 },
1462 { 0x12, 0xc096 },
1463 { 0x16, 0x000a },
1464 { 0x1f, 0x0000 },
1465 { 0x1f, 0x0000 },
1466 { 0x09, 0x2000 },
1467 { 0x09, 0x0000 }
1468 };
1469
1470 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1471
1472 mdio_patch(ioaddr, 0x14, 1 << 5);
1473 mdio_patch(ioaddr, 0x0d, 1 << 5);
1474 mdio_write(ioaddr, 0x1f, 0x0000);
1475 }
1476
1477 static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
1478 {
1479 struct phy_reg phy_reg_init[] = {
1480 { 0x1f, 0x0001 },
1481 { 0x12, 0x2300 },
1482 { 0x03, 0x802f },
1483 { 0x02, 0x4f02 },
1484 { 0x01, 0x0409 },
1485 { 0x00, 0xf099 },
1486 { 0x04, 0x9800 },
1487 { 0x04, 0x9000 },
1488 { 0x1d, 0x3d98 },
1489 { 0x1f, 0x0002 },
1490 { 0x0c, 0x7eb8 },
1491 { 0x06, 0x0761 },
1492 { 0x1f, 0x0003 },
1493 { 0x16, 0x0f0a },
1494 { 0x1f, 0x0000 }
1495 };
1496
1497 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1498
1499 mdio_patch(ioaddr, 0x16, 1 << 0);
1500 mdio_patch(ioaddr, 0x14, 1 << 5);
1501 mdio_patch(ioaddr, 0x0d, 1 << 5);
1502 mdio_write(ioaddr, 0x1f, 0x0000);
1503 }
1504
1505 static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1506 {
1507 struct phy_reg phy_reg_init[] = {
1508 { 0x1f, 0x0001 },
1509 { 0x12, 0x2300 },
1510 { 0x1d, 0x3d98 },
1511 { 0x1f, 0x0002 },
1512 { 0x0c, 0x7eb8 },
1513 { 0x06, 0x5461 },
1514 { 0x1f, 0x0003 },
1515 { 0x16, 0x0f0a },
1516 { 0x1f, 0x0000 }
1517 };
1518
1519 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1520
1521 mdio_patch(ioaddr, 0x16, 1 << 0);
1522 mdio_patch(ioaddr, 0x14, 1 << 5);
1523 mdio_patch(ioaddr, 0x0d, 1 << 5);
1524 mdio_write(ioaddr, 0x1f, 0x0000);
1525 }
1526
1527 static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1528 {
1529 rtl8168c_3_hw_phy_config(ioaddr);
1530 }
1531
1532 static void rtl8168d_hw_phy_config(void __iomem *ioaddr)
1533 {
1534 struct phy_reg phy_reg_init_0[] = {
1535 { 0x1f, 0x0001 },
1536 { 0x09, 0x2770 },
1537 { 0x08, 0x04d0 },
1538 { 0x0b, 0xad15 },
1539 { 0x0c, 0x5bf0 },
1540 { 0x1c, 0xf101 },
1541 { 0x1f, 0x0003 },
1542 { 0x14, 0x94d7 },
1543 { 0x12, 0xf4d6 },
1544 { 0x09, 0xca0f },
1545 { 0x1f, 0x0002 },
1546 { 0x0b, 0x0b10 },
1547 { 0x0c, 0xd1f7 },
1548 { 0x1f, 0x0002 },
1549 { 0x06, 0x5461 },
1550 { 0x1f, 0x0002 },
1551 { 0x05, 0x6662 },
1552 { 0x1f, 0x0000 },
1553 { 0x14, 0x0060 },
1554 { 0x1f, 0x0000 },
1555 { 0x0d, 0xf8a0 },
1556 { 0x1f, 0x0005 },
1557 { 0x05, 0xffc2 }
1558 };
1559
1560 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
1561
1562 if (mdio_read(ioaddr, 0x06) == 0xc400) {
1563 struct phy_reg phy_reg_init_1[] = {
1564 { 0x1f, 0x0005 },
1565 { 0x01, 0x0300 },
1566 { 0x1f, 0x0000 },
1567 { 0x11, 0x401c },
1568 { 0x16, 0x4100 },
1569 { 0x1f, 0x0005 },
1570 { 0x07, 0x0010 },
1571 { 0x05, 0x83dc },
1572 { 0x06, 0x087d },
1573 { 0x05, 0x8300 },
1574 { 0x06, 0x0101 },
1575 { 0x06, 0x05f8 },
1576 { 0x06, 0xf9fa },
1577 { 0x06, 0xfbef },
1578 { 0x06, 0x79e2 },
1579 { 0x06, 0x835f },
1580 { 0x06, 0xe0f8 },
1581 { 0x06, 0x9ae1 },
1582 { 0x06, 0xf89b },
1583 { 0x06, 0xef31 },
1584 { 0x06, 0x3b65 },
1585 { 0x06, 0xaa07 },
1586 { 0x06, 0x81e4 },
1587 { 0x06, 0xf89a },
1588 { 0x06, 0xe5f8 },
1589 { 0x06, 0x9baf },
1590 { 0x06, 0x06ae },
1591 { 0x05, 0x83dc },
1592 { 0x06, 0x8300 },
1593 };
1594
1595 rtl_phy_write(ioaddr, phy_reg_init_1,
1596 ARRAY_SIZE(phy_reg_init_1));
1597 }
1598
1599 mdio_write(ioaddr, 0x1f, 0x0000);
1600 }
1601
1602 static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
1603 {
1604 struct phy_reg phy_reg_init[] = {
1605 { 0x1f, 0x0003 },
1606 { 0x08, 0x441d },
1607 { 0x01, 0x9100 },
1608 { 0x1f, 0x0000 }
1609 };
1610
1611 mdio_write(ioaddr, 0x1f, 0x0000);
1612 mdio_patch(ioaddr, 0x11, 1 << 12);
1613 mdio_patch(ioaddr, 0x19, 1 << 13);
1614
1615 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1616 }
1617
1618 static void rtl_hw_phy_config(struct net_device *dev)
1619 {
1620 struct rtl8169_private *tp = netdev_priv(dev);
1621 void __iomem *ioaddr = tp->mmio_addr;
1622
1623 rtl8169_print_mac_version(tp);
1624
1625 switch (tp->mac_version) {
1626 case RTL_GIGA_MAC_VER_01:
1627 break;
1628 case RTL_GIGA_MAC_VER_02:
1629 case RTL_GIGA_MAC_VER_03:
1630 rtl8169s_hw_phy_config(ioaddr);
1631 break;
1632 case RTL_GIGA_MAC_VER_04:
1633 rtl8169sb_hw_phy_config(ioaddr);
1634 break;
1635 case RTL_GIGA_MAC_VER_07:
1636 case RTL_GIGA_MAC_VER_08:
1637 case RTL_GIGA_MAC_VER_09:
1638 rtl8102e_hw_phy_config(ioaddr);
1639 break;
1640 case RTL_GIGA_MAC_VER_11:
1641 rtl8168bb_hw_phy_config(ioaddr);
1642 break;
1643 case RTL_GIGA_MAC_VER_12:
1644 rtl8168bef_hw_phy_config(ioaddr);
1645 break;
1646 case RTL_GIGA_MAC_VER_17:
1647 rtl8168bef_hw_phy_config(ioaddr);
1648 break;
1649 case RTL_GIGA_MAC_VER_18:
1650 rtl8168cp_1_hw_phy_config(ioaddr);
1651 break;
1652 case RTL_GIGA_MAC_VER_19:
1653 rtl8168c_1_hw_phy_config(ioaddr);
1654 break;
1655 case RTL_GIGA_MAC_VER_20:
1656 rtl8168c_2_hw_phy_config(ioaddr);
1657 break;
1658 case RTL_GIGA_MAC_VER_21:
1659 rtl8168c_3_hw_phy_config(ioaddr);
1660 break;
1661 case RTL_GIGA_MAC_VER_22:
1662 rtl8168c_4_hw_phy_config(ioaddr);
1663 break;
1664 case RTL_GIGA_MAC_VER_23:
1665 case RTL_GIGA_MAC_VER_24:
1666 rtl8168cp_2_hw_phy_config(ioaddr);
1667 break;
1668 case RTL_GIGA_MAC_VER_25:
1669 rtl8168d_hw_phy_config(ioaddr);
1670 break;
1671
1672 default:
1673 break;
1674 }
1675 }
1676
1677 static void rtl8169_phy_timer(unsigned long __opaque)
1678 {
1679 struct net_device *dev = (struct net_device *)__opaque;
1680 struct rtl8169_private *tp = netdev_priv(dev);
1681 struct timer_list *timer = &tp->timer;
1682 void __iomem *ioaddr = tp->mmio_addr;
1683 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1684
1685 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1686
1687 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1688 return;
1689
1690 spin_lock_irq(&tp->lock);
1691
1692 if (tp->phy_reset_pending(ioaddr)) {
1693 /*
1694 * A busy loop could burn quite a few cycles on nowadays CPU.
1695 * Let's delay the execution of the timer for a few ticks.
1696 */
1697 timeout = HZ/10;
1698 goto out_mod_timer;
1699 }
1700
1701 if (tp->link_ok(ioaddr))
1702 goto out_unlock;
1703
1704 if (netif_msg_link(tp))
1705 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1706
1707 tp->phy_reset_enable(ioaddr);
1708
1709 out_mod_timer:
1710 mod_timer(timer, jiffies + timeout);
1711 out_unlock:
1712 spin_unlock_irq(&tp->lock);
1713 }
1714
1715 static inline void rtl8169_delete_timer(struct net_device *dev)
1716 {
1717 struct rtl8169_private *tp = netdev_priv(dev);
1718 struct timer_list *timer = &tp->timer;
1719
1720 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1721 return;
1722
1723 del_timer_sync(timer);
1724 }
1725
1726 static inline void rtl8169_request_timer(struct net_device *dev)
1727 {
1728 struct rtl8169_private *tp = netdev_priv(dev);
1729 struct timer_list *timer = &tp->timer;
1730
1731 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1732 return;
1733
1734 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1735 }
1736
1737 #ifdef CONFIG_NET_POLL_CONTROLLER
1738 /*
1739 * Polling 'interrupt' - used by things like netconsole to send skbs
1740 * without having to re-enable interrupts. It's not called while
1741 * the interrupt routine is executing.
1742 */
1743 static void rtl8169_netpoll(struct net_device *dev)
1744 {
1745 struct rtl8169_private *tp = netdev_priv(dev);
1746 struct pci_dev *pdev = tp->pci_dev;
1747
1748 disable_irq(pdev->irq);
1749 rtl8169_interrupt(pdev->irq, dev);
1750 enable_irq(pdev->irq);
1751 }
1752 #endif
1753
1754 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1755 void __iomem *ioaddr)
1756 {
1757 iounmap(ioaddr);
1758 pci_release_regions(pdev);
1759 pci_disable_device(pdev);
1760 free_netdev(dev);
1761 }
1762
1763 static void rtl8169_phy_reset(struct net_device *dev,
1764 struct rtl8169_private *tp)
1765 {
1766 void __iomem *ioaddr = tp->mmio_addr;
1767 unsigned int i;
1768
1769 tp->phy_reset_enable(ioaddr);
1770 for (i = 0; i < 100; i++) {
1771 if (!tp->phy_reset_pending(ioaddr))
1772 return;
1773 msleep(1);
1774 }
1775 if (netif_msg_link(tp))
1776 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1777 }
1778
1779 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1780 {
1781 void __iomem *ioaddr = tp->mmio_addr;
1782
1783 rtl_hw_phy_config(dev);
1784
1785 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1786 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1787 RTL_W8(0x82, 0x01);
1788 }
1789
1790 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1791
1792 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1793 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1794
1795 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1796 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1797 RTL_W8(0x82, 0x01);
1798 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1799 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1800 }
1801
1802 rtl8169_phy_reset(dev, tp);
1803
1804 /*
1805 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1806 * only 8101. Don't panic.
1807 */
1808 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1809
1810 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1811 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1812 }
1813
1814 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1815 {
1816 void __iomem *ioaddr = tp->mmio_addr;
1817 u32 high;
1818 u32 low;
1819
1820 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1821 high = addr[4] | (addr[5] << 8);
1822
1823 spin_lock_irq(&tp->lock);
1824
1825 RTL_W8(Cfg9346, Cfg9346_Unlock);
1826 RTL_W32(MAC0, low);
1827 RTL_W32(MAC4, high);
1828 RTL_W8(Cfg9346, Cfg9346_Lock);
1829
1830 spin_unlock_irq(&tp->lock);
1831 }
1832
1833 static int rtl_set_mac_address(struct net_device *dev, void *p)
1834 {
1835 struct rtl8169_private *tp = netdev_priv(dev);
1836 struct sockaddr *addr = p;
1837
1838 if (!is_valid_ether_addr(addr->sa_data))
1839 return -EADDRNOTAVAIL;
1840
1841 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1842
1843 rtl_rar_set(tp, dev->dev_addr);
1844
1845 return 0;
1846 }
1847
1848 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1849 {
1850 struct rtl8169_private *tp = netdev_priv(dev);
1851 struct mii_ioctl_data *data = if_mii(ifr);
1852
1853 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
1854 }
1855
1856 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
1857 {
1858 switch (cmd) {
1859 case SIOCGMIIPHY:
1860 data->phy_id = 32; /* Internal PHY */
1861 return 0;
1862
1863 case SIOCGMIIREG:
1864 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1865 return 0;
1866
1867 case SIOCSMIIREG:
1868 if (!capable(CAP_NET_ADMIN))
1869 return -EPERM;
1870 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1871 return 0;
1872 }
1873 return -EOPNOTSUPP;
1874 }
1875
1876 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
1877 {
1878 return -EOPNOTSUPP;
1879 }
1880
1881 static const struct rtl_cfg_info {
1882 void (*hw_start)(struct net_device *);
1883 unsigned int region;
1884 unsigned int align;
1885 u16 intr_event;
1886 u16 napi_event;
1887 unsigned features;
1888 } rtl_cfg_infos [] = {
1889 [RTL_CFG_0] = {
1890 .hw_start = rtl_hw_start_8169,
1891 .region = 1,
1892 .align = 0,
1893 .intr_event = SYSErr | LinkChg | RxOverflow |
1894 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1895 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1896 .features = RTL_FEATURE_GMII
1897 },
1898 [RTL_CFG_1] = {
1899 .hw_start = rtl_hw_start_8168,
1900 .region = 2,
1901 .align = 8,
1902 .intr_event = SYSErr | LinkChg | RxOverflow |
1903 TxErr | TxOK | RxOK | RxErr,
1904 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
1905 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI
1906 },
1907 [RTL_CFG_2] = {
1908 .hw_start = rtl_hw_start_8101,
1909 .region = 2,
1910 .align = 8,
1911 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1912 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1913 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1914 .features = RTL_FEATURE_MSI
1915 }
1916 };
1917
1918 /* Cfg9346_Unlock assumed. */
1919 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1920 const struct rtl_cfg_info *cfg)
1921 {
1922 unsigned msi = 0;
1923 u8 cfg2;
1924
1925 cfg2 = RTL_R8(Config2) & ~MSIEnable;
1926 if (cfg->features & RTL_FEATURE_MSI) {
1927 if (pci_enable_msi(pdev)) {
1928 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1929 } else {
1930 cfg2 |= MSIEnable;
1931 msi = RTL_FEATURE_MSI;
1932 }
1933 }
1934 RTL_W8(Config2, cfg2);
1935 return msi;
1936 }
1937
1938 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1939 {
1940 if (tp->features & RTL_FEATURE_MSI) {
1941 pci_disable_msi(pdev);
1942 tp->features &= ~RTL_FEATURE_MSI;
1943 }
1944 }
1945
1946 static const struct net_device_ops rtl8169_netdev_ops = {
1947 .ndo_open = rtl8169_open,
1948 .ndo_stop = rtl8169_close,
1949 .ndo_get_stats = rtl8169_get_stats,
1950 .ndo_start_xmit = rtl8169_start_xmit,
1951 .ndo_tx_timeout = rtl8169_tx_timeout,
1952 .ndo_validate_addr = eth_validate_addr,
1953 .ndo_change_mtu = rtl8169_change_mtu,
1954 .ndo_set_mac_address = rtl_set_mac_address,
1955 .ndo_do_ioctl = rtl8169_ioctl,
1956 .ndo_set_multicast_list = rtl_set_rx_mode,
1957 #ifdef CONFIG_R8169_VLAN
1958 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
1959 #endif
1960 #ifdef CONFIG_NET_POLL_CONTROLLER
1961 .ndo_poll_controller = rtl8169_netpoll,
1962 #endif
1963
1964 };
1965
1966 static int __devinit
1967 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1968 {
1969 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1970 const unsigned int region = cfg->region;
1971 struct rtl8169_private *tp;
1972 struct mii_if_info *mii;
1973 struct net_device *dev;
1974 void __iomem *ioaddr;
1975 unsigned int i;
1976 int rc;
1977
1978 if (netif_msg_drv(&debug)) {
1979 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1980 MODULENAME, RTL8169_VERSION);
1981 }
1982
1983 dev = alloc_etherdev(sizeof (*tp));
1984 if (!dev) {
1985 if (netif_msg_drv(&debug))
1986 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1987 rc = -ENOMEM;
1988 goto out;
1989 }
1990
1991 SET_NETDEV_DEV(dev, &pdev->dev);
1992 dev->netdev_ops = &rtl8169_netdev_ops;
1993 tp = netdev_priv(dev);
1994 tp->dev = dev;
1995 tp->pci_dev = pdev;
1996 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1997
1998 mii = &tp->mii;
1999 mii->dev = dev;
2000 mii->mdio_read = rtl_mdio_read;
2001 mii->mdio_write = rtl_mdio_write;
2002 mii->phy_id_mask = 0x1f;
2003 mii->reg_num_mask = 0x1f;
2004 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
2005
2006 /* enable device (incl. PCI PM wakeup and hotplug setup) */
2007 rc = pci_enable_device(pdev);
2008 if (rc < 0) {
2009 if (netif_msg_probe(tp))
2010 dev_err(&pdev->dev, "enable failure\n");
2011 goto err_out_free_dev_1;
2012 }
2013
2014 rc = pci_set_mwi(pdev);
2015 if (rc < 0)
2016 goto err_out_disable_2;
2017
2018 /* make sure PCI base addr 1 is MMIO */
2019 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
2020 if (netif_msg_probe(tp)) {
2021 dev_err(&pdev->dev,
2022 "region #%d not an MMIO resource, aborting\n",
2023 region);
2024 }
2025 rc = -ENODEV;
2026 goto err_out_mwi_3;
2027 }
2028
2029 /* check for weird/broken PCI region reporting */
2030 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
2031 if (netif_msg_probe(tp)) {
2032 dev_err(&pdev->dev,
2033 "Invalid PCI region size(s), aborting\n");
2034 }
2035 rc = -ENODEV;
2036 goto err_out_mwi_3;
2037 }
2038
2039 rc = pci_request_regions(pdev, MODULENAME);
2040 if (rc < 0) {
2041 if (netif_msg_probe(tp))
2042 dev_err(&pdev->dev, "could not request regions.\n");
2043 goto err_out_mwi_3;
2044 }
2045
2046 tp->cp_cmd = PCIMulRW | RxChkSum;
2047
2048 if ((sizeof(dma_addr_t) > 4) &&
2049 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
2050 tp->cp_cmd |= PCIDAC;
2051 dev->features |= NETIF_F_HIGHDMA;
2052 } else {
2053 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2054 if (rc < 0) {
2055 if (netif_msg_probe(tp)) {
2056 dev_err(&pdev->dev,
2057 "DMA configuration failed.\n");
2058 }
2059 goto err_out_free_res_4;
2060 }
2061 }
2062
2063 pci_set_master(pdev);
2064
2065 /* ioremap MMIO region */
2066 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
2067 if (!ioaddr) {
2068 if (netif_msg_probe(tp))
2069 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
2070 rc = -EIO;
2071 goto err_out_free_res_4;
2072 }
2073
2074 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2075 if (!tp->pcie_cap && netif_msg_probe(tp))
2076 dev_info(&pdev->dev, "no PCI Express capability\n");
2077
2078 /* Unneeded ? Don't mess with Mrs. Murphy. */
2079 rtl8169_irq_mask_and_ack(ioaddr);
2080
2081 /* Soft reset the chip. */
2082 RTL_W8(ChipCmd, CmdReset);
2083
2084 /* Check that the chip has finished the reset. */
2085 for (i = 0; i < 100; i++) {
2086 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2087 break;
2088 msleep_interruptible(1);
2089 }
2090
2091 /* Identify chip attached to board */
2092 rtl8169_get_mac_version(tp, ioaddr);
2093
2094 rtl8169_print_mac_version(tp);
2095
2096 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
2097 if (tp->mac_version == rtl_chip_info[i].mac_version)
2098 break;
2099 }
2100 if (i == ARRAY_SIZE(rtl_chip_info)) {
2101 /* Unknown chip: assume array element #0, original RTL-8169 */
2102 if (netif_msg_probe(tp)) {
2103 dev_printk(KERN_DEBUG, &pdev->dev,
2104 "unknown chip version, assuming %s\n",
2105 rtl_chip_info[0].name);
2106 }
2107 i = 0;
2108 }
2109 tp->chipset = i;
2110
2111 RTL_W8(Cfg9346, Cfg9346_Unlock);
2112 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
2113 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
2114 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
2115 tp->features |= RTL_FEATURE_WOL;
2116 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
2117 tp->features |= RTL_FEATURE_WOL;
2118 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
2119 RTL_W8(Cfg9346, Cfg9346_Lock);
2120
2121 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
2122 (RTL_R8(PHYstatus) & TBI_Enable)) {
2123 tp->set_speed = rtl8169_set_speed_tbi;
2124 tp->get_settings = rtl8169_gset_tbi;
2125 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
2126 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
2127 tp->link_ok = rtl8169_tbi_link_ok;
2128 tp->do_ioctl = rtl_tbi_ioctl;
2129
2130 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
2131 } else {
2132 tp->set_speed = rtl8169_set_speed_xmii;
2133 tp->get_settings = rtl8169_gset_xmii;
2134 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
2135 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
2136 tp->link_ok = rtl8169_xmii_link_ok;
2137 tp->do_ioctl = rtl_xmii_ioctl;
2138 }
2139
2140 spin_lock_init(&tp->lock);
2141
2142 tp->mmio_addr = ioaddr;
2143
2144 /* Get MAC address */
2145 for (i = 0; i < MAC_ADDR_LEN; i++)
2146 dev->dev_addr[i] = RTL_R8(MAC0 + i);
2147 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2148
2149 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
2150 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
2151 dev->irq = pdev->irq;
2152 dev->base_addr = (unsigned long) ioaddr;
2153
2154 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
2155
2156 #ifdef CONFIG_R8169_VLAN
2157 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2158 #endif
2159
2160 tp->intr_mask = 0xffff;
2161 tp->align = cfg->align;
2162 tp->hw_start = cfg->hw_start;
2163 tp->intr_event = cfg->intr_event;
2164 tp->napi_event = cfg->napi_event;
2165
2166 init_timer(&tp->timer);
2167 tp->timer.data = (unsigned long) dev;
2168 tp->timer.function = rtl8169_phy_timer;
2169
2170 rc = register_netdev(dev);
2171 if (rc < 0)
2172 goto err_out_msi_5;
2173
2174 pci_set_drvdata(pdev, dev);
2175
2176 if (netif_msg_probe(tp)) {
2177 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
2178
2179 printk(KERN_INFO "%s: %s at 0x%lx, "
2180 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
2181 "XID %08x IRQ %d\n",
2182 dev->name,
2183 rtl_chip_info[tp->chipset].name,
2184 dev->base_addr,
2185 dev->dev_addr[0], dev->dev_addr[1],
2186 dev->dev_addr[2], dev->dev_addr[3],
2187 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
2188 }
2189
2190 rtl8169_init_phy(dev, tp);
2191 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
2192
2193 out:
2194 return rc;
2195
2196 err_out_msi_5:
2197 rtl_disable_msi(pdev, tp);
2198 iounmap(ioaddr);
2199 err_out_free_res_4:
2200 pci_release_regions(pdev);
2201 err_out_mwi_3:
2202 pci_clear_mwi(pdev);
2203 err_out_disable_2:
2204 pci_disable_device(pdev);
2205 err_out_free_dev_1:
2206 free_netdev(dev);
2207 goto out;
2208 }
2209
2210 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
2211 {
2212 struct net_device *dev = pci_get_drvdata(pdev);
2213 struct rtl8169_private *tp = netdev_priv(dev);
2214
2215 flush_scheduled_work();
2216
2217 unregister_netdev(dev);
2218 rtl_disable_msi(pdev, tp);
2219 rtl8169_release_board(pdev, dev, tp->mmio_addr);
2220 pci_set_drvdata(pdev, NULL);
2221 }
2222
2223 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
2224 struct net_device *dev)
2225 {
2226 unsigned int mtu = dev->mtu;
2227
2228 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
2229 }
2230
2231 static int rtl8169_open(struct net_device *dev)
2232 {
2233 struct rtl8169_private *tp = netdev_priv(dev);
2234 struct pci_dev *pdev = tp->pci_dev;
2235 int retval = -ENOMEM;
2236
2237
2238 rtl8169_set_rxbufsize(tp, dev);
2239
2240 /*
2241 * Rx and Tx desscriptors needs 256 bytes alignment.
2242 * pci_alloc_consistent provides more.
2243 */
2244 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
2245 &tp->TxPhyAddr);
2246 if (!tp->TxDescArray)
2247 goto out;
2248
2249 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
2250 &tp->RxPhyAddr);
2251 if (!tp->RxDescArray)
2252 goto err_free_tx_0;
2253
2254 retval = rtl8169_init_ring(dev);
2255 if (retval < 0)
2256 goto err_free_rx_1;
2257
2258 INIT_DELAYED_WORK(&tp->task, NULL);
2259
2260 smp_mb();
2261
2262 retval = request_irq(dev->irq, rtl8169_interrupt,
2263 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
2264 dev->name, dev);
2265 if (retval < 0)
2266 goto err_release_ring_2;
2267
2268 napi_enable(&tp->napi);
2269
2270 rtl_hw_start(dev);
2271
2272 rtl8169_request_timer(dev);
2273
2274 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2275 out:
2276 return retval;
2277
2278 err_release_ring_2:
2279 rtl8169_rx_clear(tp);
2280 err_free_rx_1:
2281 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2282 tp->RxPhyAddr);
2283 err_free_tx_0:
2284 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2285 tp->TxPhyAddr);
2286 goto out;
2287 }
2288
2289 static void rtl8169_hw_reset(void __iomem *ioaddr)
2290 {
2291 /* Disable interrupts */
2292 rtl8169_irq_mask_and_ack(ioaddr);
2293
2294 /* Reset the chipset */
2295 RTL_W8(ChipCmd, CmdReset);
2296
2297 /* PCI commit */
2298 RTL_R8(ChipCmd);
2299 }
2300
2301 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
2302 {
2303 void __iomem *ioaddr = tp->mmio_addr;
2304 u32 cfg = rtl8169_rx_config;
2305
2306 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2307 RTL_W32(RxConfig, cfg);
2308
2309 /* Set DMA burst size and Interframe Gap Time */
2310 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2311 (InterFrameGap << TxInterFrameGapShift));
2312 }
2313
2314 static void rtl_hw_start(struct net_device *dev)
2315 {
2316 struct rtl8169_private *tp = netdev_priv(dev);
2317 void __iomem *ioaddr = tp->mmio_addr;
2318 unsigned int i;
2319
2320 /* Soft reset the chip. */
2321 RTL_W8(ChipCmd, CmdReset);
2322
2323 /* Check that the chip has finished the reset. */
2324 for (i = 0; i < 100; i++) {
2325 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2326 break;
2327 msleep_interruptible(1);
2328 }
2329
2330 tp->hw_start(dev);
2331
2332 netif_start_queue(dev);
2333 }
2334
2335
2336 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2337 void __iomem *ioaddr)
2338 {
2339 /*
2340 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2341 * register to be written before TxDescAddrLow to work.
2342 * Switching from MMIO to I/O access fixes the issue as well.
2343 */
2344 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2345 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
2346 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2347 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
2348 }
2349
2350 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2351 {
2352 u16 cmd;
2353
2354 cmd = RTL_R16(CPlusCmd);
2355 RTL_W16(CPlusCmd, cmd);
2356 return cmd;
2357 }
2358
2359 static void rtl_set_rx_max_size(void __iomem *ioaddr)
2360 {
2361 /* Low hurts. Let's disable the filtering. */
2362 RTL_W16(RxMaxSize, 16383);
2363 }
2364
2365 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2366 {
2367 struct {
2368 u32 mac_version;
2369 u32 clk;
2370 u32 val;
2371 } cfg2_info [] = {
2372 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2373 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2374 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2375 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2376 }, *p = cfg2_info;
2377 unsigned int i;
2378 u32 clk;
2379
2380 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
2381 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
2382 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2383 RTL_W32(0x7c, p->val);
2384 break;
2385 }
2386 }
2387 }
2388
2389 static void rtl_hw_start_8169(struct net_device *dev)
2390 {
2391 struct rtl8169_private *tp = netdev_priv(dev);
2392 void __iomem *ioaddr = tp->mmio_addr;
2393 struct pci_dev *pdev = tp->pci_dev;
2394
2395 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2396 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2397 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2398 }
2399
2400 RTL_W8(Cfg9346, Cfg9346_Unlock);
2401 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2402 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2403 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2404 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2405 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2406
2407 RTL_W8(EarlyTxThres, EarlyTxThld);
2408
2409 rtl_set_rx_max_size(ioaddr);
2410
2411 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2412 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2413 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2414 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2415 rtl_set_rx_tx_config_registers(tp);
2416
2417 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2418
2419 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2420 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
2421 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2422 "Bit-3 and bit-14 MUST be 1\n");
2423 tp->cp_cmd |= (1 << 14);
2424 }
2425
2426 RTL_W16(CPlusCmd, tp->cp_cmd);
2427
2428 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2429
2430 /*
2431 * Undocumented corner. Supposedly:
2432 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2433 */
2434 RTL_W16(IntrMitigate, 0x0000);
2435
2436 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2437
2438 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2439 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2440 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2441 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2442 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2443 rtl_set_rx_tx_config_registers(tp);
2444 }
2445
2446 RTL_W8(Cfg9346, Cfg9346_Lock);
2447
2448 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2449 RTL_R8(IntrMask);
2450
2451 RTL_W32(RxMissed, 0);
2452
2453 rtl_set_rx_mode(dev);
2454
2455 /* no early-rx interrupts */
2456 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2457
2458 /* Enable all known interrupts by setting the interrupt mask. */
2459 RTL_W16(IntrMask, tp->intr_event);
2460 }
2461
2462 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
2463 {
2464 struct net_device *dev = pci_get_drvdata(pdev);
2465 struct rtl8169_private *tp = netdev_priv(dev);
2466 int cap = tp->pcie_cap;
2467
2468 if (cap) {
2469 u16 ctl;
2470
2471 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2472 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2473 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2474 }
2475 }
2476
2477 static void rtl_csi_access_enable(void __iomem *ioaddr)
2478 {
2479 u32 csi;
2480
2481 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2482 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
2483 }
2484
2485 struct ephy_info {
2486 unsigned int offset;
2487 u16 mask;
2488 u16 bits;
2489 };
2490
2491 static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
2492 {
2493 u16 w;
2494
2495 while (len-- > 0) {
2496 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
2497 rtl_ephy_write(ioaddr, e->offset, w);
2498 e++;
2499 }
2500 }
2501
2502 static void rtl_disable_clock_request(struct pci_dev *pdev)
2503 {
2504 struct net_device *dev = pci_get_drvdata(pdev);
2505 struct rtl8169_private *tp = netdev_priv(dev);
2506 int cap = tp->pcie_cap;
2507
2508 if (cap) {
2509 u16 ctl;
2510
2511 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
2512 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
2513 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
2514 }
2515 }
2516
2517 #define R8168_CPCMD_QUIRK_MASK (\
2518 EnableBist | \
2519 Mac_dbgo_oe | \
2520 Force_half_dup | \
2521 Force_rxflow_en | \
2522 Force_txflow_en | \
2523 Cxpl_dbg_sel | \
2524 ASF | \
2525 PktCntrDisable | \
2526 Mac_dbgo_sel)
2527
2528 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
2529 {
2530 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2531
2532 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2533
2534 rtl_tx_performance_tweak(pdev,
2535 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
2536 }
2537
2538 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
2539 {
2540 rtl_hw_start_8168bb(ioaddr, pdev);
2541
2542 RTL_W8(EarlyTxThres, EarlyTxThld);
2543
2544 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
2545 }
2546
2547 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
2548 {
2549 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
2550
2551 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2552
2553 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2554
2555 rtl_disable_clock_request(pdev);
2556
2557 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2558 }
2559
2560 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
2561 {
2562 static struct ephy_info e_info_8168cp[] = {
2563 { 0x01, 0, 0x0001 },
2564 { 0x02, 0x0800, 0x1000 },
2565 { 0x03, 0, 0x0042 },
2566 { 0x06, 0x0080, 0x0000 },
2567 { 0x07, 0, 0x2000 }
2568 };
2569
2570 rtl_csi_access_enable(ioaddr);
2571
2572 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
2573
2574 __rtl_hw_start_8168cp(ioaddr, pdev);
2575 }
2576
2577 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
2578 {
2579 rtl_csi_access_enable(ioaddr);
2580
2581 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2582
2583 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2584
2585 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2586 }
2587
2588 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
2589 {
2590 rtl_csi_access_enable(ioaddr);
2591
2592 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2593
2594 /* Magic. */
2595 RTL_W8(DBG_REG, 0x20);
2596
2597 RTL_W8(EarlyTxThres, EarlyTxThld);
2598
2599 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2600
2601 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2602 }
2603
2604 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
2605 {
2606 static struct ephy_info e_info_8168c_1[] = {
2607 { 0x02, 0x0800, 0x1000 },
2608 { 0x03, 0, 0x0002 },
2609 { 0x06, 0x0080, 0x0000 }
2610 };
2611
2612 rtl_csi_access_enable(ioaddr);
2613
2614 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2615
2616 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
2617
2618 __rtl_hw_start_8168cp(ioaddr, pdev);
2619 }
2620
2621 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
2622 {
2623 static struct ephy_info e_info_8168c_2[] = {
2624 { 0x01, 0, 0x0001 },
2625 { 0x03, 0x0400, 0x0220 }
2626 };
2627
2628 rtl_csi_access_enable(ioaddr);
2629
2630 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
2631
2632 __rtl_hw_start_8168cp(ioaddr, pdev);
2633 }
2634
2635 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
2636 {
2637 rtl_hw_start_8168c_2(ioaddr, pdev);
2638 }
2639
2640 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
2641 {
2642 rtl_csi_access_enable(ioaddr);
2643
2644 __rtl_hw_start_8168cp(ioaddr, pdev);
2645 }
2646
2647 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
2648 {
2649 rtl_csi_access_enable(ioaddr);
2650
2651 rtl_disable_clock_request(pdev);
2652
2653 RTL_W8(EarlyTxThres, EarlyTxThld);
2654
2655 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2656
2657 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2658 }
2659
2660 static void rtl_hw_start_8168(struct net_device *dev)
2661 {
2662 struct rtl8169_private *tp = netdev_priv(dev);
2663 void __iomem *ioaddr = tp->mmio_addr;
2664 struct pci_dev *pdev = tp->pci_dev;
2665
2666 RTL_W8(Cfg9346, Cfg9346_Unlock);
2667
2668 RTL_W8(EarlyTxThres, EarlyTxThld);
2669
2670 rtl_set_rx_max_size(ioaddr);
2671
2672 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2673
2674 RTL_W16(CPlusCmd, tp->cp_cmd);
2675
2676 RTL_W16(IntrMitigate, 0x5151);
2677
2678 /* Work around for RxFIFO overflow. */
2679 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2680 tp->intr_event |= RxFIFOOver | PCSTimeout;
2681 tp->intr_event &= ~RxOverflow;
2682 }
2683
2684 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2685
2686 rtl_set_rx_mode(dev);
2687
2688 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2689 (InterFrameGap << TxInterFrameGapShift));
2690
2691 RTL_R8(IntrMask);
2692
2693 switch (tp->mac_version) {
2694 case RTL_GIGA_MAC_VER_11:
2695 rtl_hw_start_8168bb(ioaddr, pdev);
2696 break;
2697
2698 case RTL_GIGA_MAC_VER_12:
2699 case RTL_GIGA_MAC_VER_17:
2700 rtl_hw_start_8168bef(ioaddr, pdev);
2701 break;
2702
2703 case RTL_GIGA_MAC_VER_18:
2704 rtl_hw_start_8168cp_1(ioaddr, pdev);
2705 break;
2706
2707 case RTL_GIGA_MAC_VER_19:
2708 rtl_hw_start_8168c_1(ioaddr, pdev);
2709 break;
2710
2711 case RTL_GIGA_MAC_VER_20:
2712 rtl_hw_start_8168c_2(ioaddr, pdev);
2713 break;
2714
2715 case RTL_GIGA_MAC_VER_21:
2716 rtl_hw_start_8168c_3(ioaddr, pdev);
2717 break;
2718
2719 case RTL_GIGA_MAC_VER_22:
2720 rtl_hw_start_8168c_4(ioaddr, pdev);
2721 break;
2722
2723 case RTL_GIGA_MAC_VER_23:
2724 rtl_hw_start_8168cp_2(ioaddr, pdev);
2725 break;
2726
2727 case RTL_GIGA_MAC_VER_24:
2728 rtl_hw_start_8168cp_3(ioaddr, pdev);
2729 break;
2730
2731 case RTL_GIGA_MAC_VER_25:
2732 rtl_hw_start_8168d(ioaddr, pdev);
2733 break;
2734
2735 default:
2736 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
2737 dev->name, tp->mac_version);
2738 break;
2739 }
2740
2741 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2742
2743 RTL_W8(Cfg9346, Cfg9346_Lock);
2744
2745 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2746
2747 RTL_W16(IntrMask, tp->intr_event);
2748 }
2749
2750 #define R810X_CPCMD_QUIRK_MASK (\
2751 EnableBist | \
2752 Mac_dbgo_oe | \
2753 Force_half_dup | \
2754 Force_half_dup | \
2755 Force_txflow_en | \
2756 Cxpl_dbg_sel | \
2757 ASF | \
2758 PktCntrDisable | \
2759 PCIDAC | \
2760 PCIMulRW)
2761
2762 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
2763 {
2764 static struct ephy_info e_info_8102e_1[] = {
2765 { 0x01, 0, 0x6e65 },
2766 { 0x02, 0, 0x091f },
2767 { 0x03, 0, 0xc2f9 },
2768 { 0x06, 0, 0xafb5 },
2769 { 0x07, 0, 0x0e00 },
2770 { 0x19, 0, 0xec80 },
2771 { 0x01, 0, 0x2e65 },
2772 { 0x01, 0, 0x6e65 }
2773 };
2774 u8 cfg1;
2775
2776 rtl_csi_access_enable(ioaddr);
2777
2778 RTL_W8(DBG_REG, FIX_NAK_1);
2779
2780 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2781
2782 RTL_W8(Config1,
2783 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
2784 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2785
2786 cfg1 = RTL_R8(Config1);
2787 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
2788 RTL_W8(Config1, cfg1 & ~LEDS0);
2789
2790 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2791
2792 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2793 }
2794
2795 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
2796 {
2797 rtl_csi_access_enable(ioaddr);
2798
2799 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2800
2801 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
2802 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2803
2804 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2805 }
2806
2807 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
2808 {
2809 rtl_hw_start_8102e_2(ioaddr, pdev);
2810
2811 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
2812 }
2813
2814 static void rtl_hw_start_8101(struct net_device *dev)
2815 {
2816 struct rtl8169_private *tp = netdev_priv(dev);
2817 void __iomem *ioaddr = tp->mmio_addr;
2818 struct pci_dev *pdev = tp->pci_dev;
2819
2820 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2821 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
2822 int cap = tp->pcie_cap;
2823
2824 if (cap) {
2825 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2826 PCI_EXP_DEVCTL_NOSNOOP_EN);
2827 }
2828 }
2829
2830 switch (tp->mac_version) {
2831 case RTL_GIGA_MAC_VER_07:
2832 rtl_hw_start_8102e_1(ioaddr, pdev);
2833 break;
2834
2835 case RTL_GIGA_MAC_VER_08:
2836 rtl_hw_start_8102e_3(ioaddr, pdev);
2837 break;
2838
2839 case RTL_GIGA_MAC_VER_09:
2840 rtl_hw_start_8102e_2(ioaddr, pdev);
2841 break;
2842 }
2843
2844 RTL_W8(Cfg9346, Cfg9346_Unlock);
2845
2846 RTL_W8(EarlyTxThres, EarlyTxThld);
2847
2848 rtl_set_rx_max_size(ioaddr);
2849
2850 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2851
2852 RTL_W16(CPlusCmd, tp->cp_cmd);
2853
2854 RTL_W16(IntrMitigate, 0x0000);
2855
2856 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2857
2858 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2859 rtl_set_rx_tx_config_registers(tp);
2860
2861 RTL_W8(Cfg9346, Cfg9346_Lock);
2862
2863 RTL_R8(IntrMask);
2864
2865 rtl_set_rx_mode(dev);
2866
2867 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2868
2869 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2870
2871 RTL_W16(IntrMask, tp->intr_event);
2872 }
2873
2874 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2875 {
2876 struct rtl8169_private *tp = netdev_priv(dev);
2877 int ret = 0;
2878
2879 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2880 return -EINVAL;
2881
2882 dev->mtu = new_mtu;
2883
2884 if (!netif_running(dev))
2885 goto out;
2886
2887 rtl8169_down(dev);
2888
2889 rtl8169_set_rxbufsize(tp, dev);
2890
2891 ret = rtl8169_init_ring(dev);
2892 if (ret < 0)
2893 goto out;
2894
2895 napi_enable(&tp->napi);
2896
2897 rtl_hw_start(dev);
2898
2899 rtl8169_request_timer(dev);
2900
2901 out:
2902 return ret;
2903 }
2904
2905 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2906 {
2907 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
2908 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2909 }
2910
2911 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2912 struct sk_buff **sk_buff, struct RxDesc *desc)
2913 {
2914 struct pci_dev *pdev = tp->pci_dev;
2915
2916 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2917 PCI_DMA_FROMDEVICE);
2918 dev_kfree_skb(*sk_buff);
2919 *sk_buff = NULL;
2920 rtl8169_make_unusable_by_asic(desc);
2921 }
2922
2923 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2924 {
2925 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2926
2927 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2928 }
2929
2930 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2931 u32 rx_buf_sz)
2932 {
2933 desc->addr = cpu_to_le64(mapping);
2934 wmb();
2935 rtl8169_mark_to_asic(desc, rx_buf_sz);
2936 }
2937
2938 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2939 struct net_device *dev,
2940 struct RxDesc *desc, int rx_buf_sz,
2941 unsigned int align)
2942 {
2943 struct sk_buff *skb;
2944 dma_addr_t mapping;
2945 unsigned int pad;
2946
2947 pad = align ? align : NET_IP_ALIGN;
2948
2949 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2950 if (!skb)
2951 goto err_out;
2952
2953 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2954
2955 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2956 PCI_DMA_FROMDEVICE);
2957
2958 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2959 out:
2960 return skb;
2961
2962 err_out:
2963 rtl8169_make_unusable_by_asic(desc);
2964 goto out;
2965 }
2966
2967 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2968 {
2969 unsigned int i;
2970
2971 for (i = 0; i < NUM_RX_DESC; i++) {
2972 if (tp->Rx_skbuff[i]) {
2973 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2974 tp->RxDescArray + i);
2975 }
2976 }
2977 }
2978
2979 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2980 u32 start, u32 end)
2981 {
2982 u32 cur;
2983
2984 for (cur = start; end - cur != 0; cur++) {
2985 struct sk_buff *skb;
2986 unsigned int i = cur % NUM_RX_DESC;
2987
2988 WARN_ON((s32)(end - cur) < 0);
2989
2990 if (tp->Rx_skbuff[i])
2991 continue;
2992
2993 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2994 tp->RxDescArray + i,
2995 tp->rx_buf_sz, tp->align);
2996 if (!skb)
2997 break;
2998
2999 tp->Rx_skbuff[i] = skb;
3000 }
3001 return cur - start;
3002 }
3003
3004 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
3005 {
3006 desc->opts1 |= cpu_to_le32(RingEnd);
3007 }
3008
3009 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3010 {
3011 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3012 }
3013
3014 static int rtl8169_init_ring(struct net_device *dev)
3015 {
3016 struct rtl8169_private *tp = netdev_priv(dev);
3017
3018 rtl8169_init_ring_indexes(tp);
3019
3020 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
3021 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
3022
3023 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
3024 goto err_out;
3025
3026 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
3027
3028 return 0;
3029
3030 err_out:
3031 rtl8169_rx_clear(tp);
3032 return -ENOMEM;
3033 }
3034
3035 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
3036 struct TxDesc *desc)
3037 {
3038 unsigned int len = tx_skb->len;
3039
3040 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
3041 desc->opts1 = 0x00;
3042 desc->opts2 = 0x00;
3043 desc->addr = 0x00;
3044 tx_skb->len = 0;
3045 }
3046
3047 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3048 {
3049 unsigned int i;
3050
3051 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
3052 unsigned int entry = i % NUM_TX_DESC;
3053 struct ring_info *tx_skb = tp->tx_skb + entry;
3054 unsigned int len = tx_skb->len;
3055
3056 if (len) {
3057 struct sk_buff *skb = tx_skb->skb;
3058
3059 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
3060 tp->TxDescArray + entry);
3061 if (skb) {
3062 dev_kfree_skb(skb);
3063 tx_skb->skb = NULL;
3064 }
3065 tp->dev->stats.tx_dropped++;
3066 }
3067 }
3068 tp->cur_tx = tp->dirty_tx = 0;
3069 }
3070
3071 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
3072 {
3073 struct rtl8169_private *tp = netdev_priv(dev);
3074
3075 PREPARE_DELAYED_WORK(&tp->task, task);
3076 schedule_delayed_work(&tp->task, 4);
3077 }
3078
3079 static void rtl8169_wait_for_quiescence(struct net_device *dev)
3080 {
3081 struct rtl8169_private *tp = netdev_priv(dev);
3082 void __iomem *ioaddr = tp->mmio_addr;
3083
3084 synchronize_irq(dev->irq);
3085
3086 /* Wait for any pending NAPI task to complete */
3087 napi_disable(&tp->napi);
3088
3089 rtl8169_irq_mask_and_ack(ioaddr);
3090
3091 tp->intr_mask = 0xffff;
3092 RTL_W16(IntrMask, tp->intr_event);
3093 napi_enable(&tp->napi);
3094 }
3095
3096 static void rtl8169_reinit_task(struct work_struct *work)
3097 {
3098 struct rtl8169_private *tp =
3099 container_of(work, struct rtl8169_private, task.work);
3100 struct net_device *dev = tp->dev;
3101 int ret;
3102
3103 rtnl_lock();
3104
3105 if (!netif_running(dev))
3106 goto out_unlock;
3107
3108 rtl8169_wait_for_quiescence(dev);
3109 rtl8169_close(dev);
3110
3111 ret = rtl8169_open(dev);
3112 if (unlikely(ret < 0)) {
3113 if (net_ratelimit() && netif_msg_drv(tp)) {
3114 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
3115 " Rescheduling.\n", dev->name, ret);
3116 }
3117 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3118 }
3119
3120 out_unlock:
3121 rtnl_unlock();
3122 }
3123
3124 static void rtl8169_reset_task(struct work_struct *work)
3125 {
3126 struct rtl8169_private *tp =
3127 container_of(work, struct rtl8169_private, task.work);
3128 struct net_device *dev = tp->dev;
3129
3130 rtnl_lock();
3131
3132 if (!netif_running(dev))
3133 goto out_unlock;
3134
3135 rtl8169_wait_for_quiescence(dev);
3136
3137 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
3138 rtl8169_tx_clear(tp);
3139
3140 if (tp->dirty_rx == tp->cur_rx) {
3141 rtl8169_init_ring_indexes(tp);
3142 rtl_hw_start(dev);
3143 netif_wake_queue(dev);
3144 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3145 } else {
3146 if (net_ratelimit() && netif_msg_intr(tp)) {
3147 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
3148 dev->name);
3149 }
3150 rtl8169_schedule_work(dev, rtl8169_reset_task);
3151 }
3152
3153 out_unlock:
3154 rtnl_unlock();
3155 }
3156
3157 static void rtl8169_tx_timeout(struct net_device *dev)
3158 {
3159 struct rtl8169_private *tp = netdev_priv(dev);
3160
3161 rtl8169_hw_reset(tp->mmio_addr);
3162
3163 /* Let's wait a bit while any (async) irq lands on */
3164 rtl8169_schedule_work(dev, rtl8169_reset_task);
3165 }
3166
3167 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
3168 u32 opts1)
3169 {
3170 struct skb_shared_info *info = skb_shinfo(skb);
3171 unsigned int cur_frag, entry;
3172 struct TxDesc * uninitialized_var(txd);
3173
3174 entry = tp->cur_tx;
3175 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
3176 skb_frag_t *frag = info->frags + cur_frag;
3177 dma_addr_t mapping;
3178 u32 status, len;
3179 void *addr;
3180
3181 entry = (entry + 1) % NUM_TX_DESC;
3182
3183 txd = tp->TxDescArray + entry;
3184 len = frag->size;
3185 addr = ((void *) page_address(frag->page)) + frag->page_offset;
3186 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
3187
3188 /* anti gcc 2.95.3 bugware (sic) */
3189 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3190
3191 txd->opts1 = cpu_to_le32(status);
3192 txd->addr = cpu_to_le64(mapping);
3193
3194 tp->tx_skb[entry].len = len;
3195 }
3196
3197 if (cur_frag) {
3198 tp->tx_skb[entry].skb = skb;
3199 txd->opts1 |= cpu_to_le32(LastFrag);
3200 }
3201
3202 return cur_frag;
3203 }
3204
3205 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
3206 {
3207 if (dev->features & NETIF_F_TSO) {
3208 u32 mss = skb_shinfo(skb)->gso_size;
3209
3210 if (mss)
3211 return LargeSend | ((mss & MSSMask) << MSSShift);
3212 }
3213 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3214 const struct iphdr *ip = ip_hdr(skb);
3215
3216 if (ip->protocol == IPPROTO_TCP)
3217 return IPCS | TCPCS;
3218 else if (ip->protocol == IPPROTO_UDP)
3219 return IPCS | UDPCS;
3220 WARN_ON(1); /* we need a WARN() */
3221 }
3222 return 0;
3223 }
3224
3225 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
3226 {
3227 struct rtl8169_private *tp = netdev_priv(dev);
3228 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
3229 struct TxDesc *txd = tp->TxDescArray + entry;
3230 void __iomem *ioaddr = tp->mmio_addr;
3231 dma_addr_t mapping;
3232 u32 status, len;
3233 u32 opts1;
3234 int ret = NETDEV_TX_OK;
3235
3236 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
3237 if (netif_msg_drv(tp)) {
3238 printk(KERN_ERR
3239 "%s: BUG! Tx Ring full when queue awake!\n",
3240 dev->name);
3241 }
3242 goto err_stop;
3243 }
3244
3245 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3246 goto err_stop;
3247
3248 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
3249
3250 frags = rtl8169_xmit_frags(tp, skb, opts1);
3251 if (frags) {
3252 len = skb_headlen(skb);
3253 opts1 |= FirstFrag;
3254 } else {
3255 len = skb->len;
3256 opts1 |= FirstFrag | LastFrag;
3257 tp->tx_skb[entry].skb = skb;
3258 }
3259
3260 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
3261
3262 tp->tx_skb[entry].len = len;
3263 txd->addr = cpu_to_le64(mapping);
3264 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
3265
3266 wmb();
3267
3268 /* anti gcc 2.95.3 bugware (sic) */
3269 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3270 txd->opts1 = cpu_to_le32(status);
3271
3272 dev->trans_start = jiffies;
3273
3274 tp->cur_tx += frags + 1;
3275
3276 smp_wmb();
3277
3278 RTL_W8(TxPoll, NPQ); /* set polling bit */
3279
3280 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
3281 netif_stop_queue(dev);
3282 smp_rmb();
3283 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
3284 netif_wake_queue(dev);
3285 }
3286
3287 out:
3288 return ret;
3289
3290 err_stop:
3291 netif_stop_queue(dev);
3292 ret = NETDEV_TX_BUSY;
3293 dev->stats.tx_dropped++;
3294 goto out;
3295 }
3296
3297 static void rtl8169_pcierr_interrupt(struct net_device *dev)
3298 {
3299 struct rtl8169_private *tp = netdev_priv(dev);
3300 struct pci_dev *pdev = tp->pci_dev;
3301 void __iomem *ioaddr = tp->mmio_addr;
3302 u16 pci_status, pci_cmd;
3303
3304 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3305 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3306
3307 if (netif_msg_intr(tp)) {
3308 printk(KERN_ERR
3309 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
3310 dev->name, pci_cmd, pci_status);
3311 }
3312
3313 /*
3314 * The recovery sequence below admits a very elaborated explanation:
3315 * - it seems to work;
3316 * - I did not see what else could be done;
3317 * - it makes iop3xx happy.
3318 *
3319 * Feel free to adjust to your needs.
3320 */
3321 if (pdev->broken_parity_status)
3322 pci_cmd &= ~PCI_COMMAND_PARITY;
3323 else
3324 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
3325
3326 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
3327
3328 pci_write_config_word(pdev, PCI_STATUS,
3329 pci_status & (PCI_STATUS_DETECTED_PARITY |
3330 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
3331 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
3332
3333 /* The infamous DAC f*ckup only happens at boot time */
3334 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
3335 if (netif_msg_intr(tp))
3336 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
3337 tp->cp_cmd &= ~PCIDAC;
3338 RTL_W16(CPlusCmd, tp->cp_cmd);
3339 dev->features &= ~NETIF_F_HIGHDMA;
3340 }
3341
3342 rtl8169_hw_reset(ioaddr);
3343
3344 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3345 }
3346
3347 static void rtl8169_tx_interrupt(struct net_device *dev,
3348 struct rtl8169_private *tp,
3349 void __iomem *ioaddr)
3350 {
3351 unsigned int dirty_tx, tx_left;
3352
3353 dirty_tx = tp->dirty_tx;
3354 smp_rmb();
3355 tx_left = tp->cur_tx - dirty_tx;
3356
3357 while (tx_left > 0) {
3358 unsigned int entry = dirty_tx % NUM_TX_DESC;
3359 struct ring_info *tx_skb = tp->tx_skb + entry;
3360 u32 len = tx_skb->len;
3361 u32 status;
3362
3363 rmb();
3364 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
3365 if (status & DescOwn)
3366 break;
3367
3368 dev->stats.tx_bytes += len;
3369 dev->stats.tx_packets++;
3370
3371 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
3372
3373 if (status & LastFrag) {
3374 dev_kfree_skb_irq(tx_skb->skb);
3375 tx_skb->skb = NULL;
3376 }
3377 dirty_tx++;
3378 tx_left--;
3379 }
3380
3381 if (tp->dirty_tx != dirty_tx) {
3382 tp->dirty_tx = dirty_tx;
3383 smp_wmb();
3384 if (netif_queue_stopped(dev) &&
3385 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
3386 netif_wake_queue(dev);
3387 }
3388 /*
3389 * 8168 hack: TxPoll requests are lost when the Tx packets are
3390 * too close. Let's kick an extra TxPoll request when a burst
3391 * of start_xmit activity is detected (if it is not detected,
3392 * it is slow enough). -- FR
3393 */
3394 smp_rmb();
3395 if (tp->cur_tx != dirty_tx)
3396 RTL_W8(TxPoll, NPQ);
3397 }
3398 }
3399
3400 static inline int rtl8169_fragmented_frame(u32 status)
3401 {
3402 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
3403 }
3404
3405 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
3406 {
3407 u32 opts1 = le32_to_cpu(desc->opts1);
3408 u32 status = opts1 & RxProtoMask;
3409
3410 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
3411 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
3412 ((status == RxProtoIP) && !(opts1 & IPFail)))
3413 skb->ip_summed = CHECKSUM_UNNECESSARY;
3414 else
3415 skb->ip_summed = CHECKSUM_NONE;
3416 }
3417
3418 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
3419 struct rtl8169_private *tp, int pkt_size,
3420 dma_addr_t addr)
3421 {
3422 struct sk_buff *skb;
3423 bool done = false;
3424
3425 if (pkt_size >= rx_copybreak)
3426 goto out;
3427
3428 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
3429 if (!skb)
3430 goto out;
3431
3432 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
3433 PCI_DMA_FROMDEVICE);
3434 skb_reserve(skb, NET_IP_ALIGN);
3435 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
3436 *sk_buff = skb;
3437 done = true;
3438 out:
3439 return done;
3440 }
3441
3442 static int rtl8169_rx_interrupt(struct net_device *dev,
3443 struct rtl8169_private *tp,
3444 void __iomem *ioaddr, u32 budget)
3445 {
3446 unsigned int cur_rx, rx_left;
3447 unsigned int delta, count;
3448
3449 cur_rx = tp->cur_rx;
3450 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
3451 rx_left = min(rx_left, budget);
3452
3453 for (; rx_left > 0; rx_left--, cur_rx++) {
3454 unsigned int entry = cur_rx % NUM_RX_DESC;
3455 struct RxDesc *desc = tp->RxDescArray + entry;
3456 u32 status;
3457
3458 rmb();
3459 status = le32_to_cpu(desc->opts1);
3460
3461 if (status & DescOwn)
3462 break;
3463 if (unlikely(status & RxRES)) {
3464 if (netif_msg_rx_err(tp)) {
3465 printk(KERN_INFO
3466 "%s: Rx ERROR. status = %08x\n",
3467 dev->name, status);
3468 }
3469 dev->stats.rx_errors++;
3470 if (status & (RxRWT | RxRUNT))
3471 dev->stats.rx_length_errors++;
3472 if (status & RxCRC)
3473 dev->stats.rx_crc_errors++;
3474 if (status & RxFOVF) {
3475 rtl8169_schedule_work(dev, rtl8169_reset_task);
3476 dev->stats.rx_fifo_errors++;
3477 }
3478 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3479 } else {
3480 struct sk_buff *skb = tp->Rx_skbuff[entry];
3481 dma_addr_t addr = le64_to_cpu(desc->addr);
3482 int pkt_size = (status & 0x00001FFF) - 4;
3483 struct pci_dev *pdev = tp->pci_dev;
3484
3485 /*
3486 * The driver does not support incoming fragmented
3487 * frames. They are seen as a symptom of over-mtu
3488 * sized frames.
3489 */
3490 if (unlikely(rtl8169_fragmented_frame(status))) {
3491 dev->stats.rx_dropped++;
3492 dev->stats.rx_length_errors++;
3493 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3494 continue;
3495 }
3496
3497 rtl8169_rx_csum(skb, desc);
3498
3499 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
3500 pci_dma_sync_single_for_device(pdev, addr,
3501 pkt_size, PCI_DMA_FROMDEVICE);
3502 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3503 } else {
3504 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
3505 PCI_DMA_FROMDEVICE);
3506 tp->Rx_skbuff[entry] = NULL;
3507 }
3508
3509 skb_put(skb, pkt_size);
3510 skb->protocol = eth_type_trans(skb, dev);
3511
3512 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
3513 netif_receive_skb(skb);
3514
3515 dev->stats.rx_bytes += pkt_size;
3516 dev->stats.rx_packets++;
3517 }
3518
3519 /* Work around for AMD plateform. */
3520 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
3521 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
3522 desc->opts2 = 0;
3523 cur_rx++;
3524 }
3525 }
3526
3527 count = cur_rx - tp->cur_rx;
3528 tp->cur_rx = cur_rx;
3529
3530 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
3531 if (!delta && count && netif_msg_intr(tp))
3532 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
3533 tp->dirty_rx += delta;
3534
3535 /*
3536 * FIXME: until there is periodic timer to try and refill the ring,
3537 * a temporary shortage may definitely kill the Rx process.
3538 * - disable the asic to try and avoid an overflow and kick it again
3539 * after refill ?
3540 * - how do others driver handle this condition (Uh oh...).
3541 */
3542 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
3543 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
3544
3545 return count;
3546 }
3547
3548 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
3549 {
3550 struct net_device *dev = dev_instance;
3551 struct rtl8169_private *tp = netdev_priv(dev);
3552 void __iomem *ioaddr = tp->mmio_addr;
3553 int handled = 0;
3554 int status;
3555
3556 status = RTL_R16(IntrStatus);
3557
3558 /* hotplug/major error/no more work/shared irq */
3559 if ((status == 0xffff) || !status)
3560 goto out;
3561
3562 handled = 1;
3563
3564 if (unlikely(!netif_running(dev))) {
3565 rtl8169_asic_down(ioaddr);
3566 goto out;
3567 }
3568
3569 status &= tp->intr_mask;
3570 RTL_W16(IntrStatus,
3571 (status & RxFIFOOver) ? (status | RxOverflow) : status);
3572
3573 if (!(status & tp->intr_event))
3574 goto out;
3575
3576 /* Work around for rx fifo overflow */
3577 if (unlikely(status & RxFIFOOver) &&
3578 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
3579 netif_stop_queue(dev);
3580 rtl8169_tx_timeout(dev);
3581 goto out;
3582 }
3583
3584 if (unlikely(status & SYSErr)) {
3585 rtl8169_pcierr_interrupt(dev);
3586 goto out;
3587 }
3588
3589 if (status & LinkChg)
3590 rtl8169_check_link_status(dev, tp, ioaddr);
3591
3592 if (status & tp->napi_event) {
3593 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
3594 tp->intr_mask = ~tp->napi_event;
3595
3596 if (likely(napi_schedule_prep(&tp->napi)))
3597 __napi_schedule(&tp->napi);
3598 else if (netif_msg_intr(tp)) {
3599 printk(KERN_INFO "%s: interrupt %04x in poll\n",
3600 dev->name, status);
3601 }
3602 }
3603 out:
3604 return IRQ_RETVAL(handled);
3605 }
3606
3607 static int rtl8169_poll(struct napi_struct *napi, int budget)
3608 {
3609 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
3610 struct net_device *dev = tp->dev;
3611 void __iomem *ioaddr = tp->mmio_addr;
3612 int work_done;
3613
3614 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
3615 rtl8169_tx_interrupt(dev, tp, ioaddr);
3616
3617 if (work_done < budget) {
3618 napi_complete(napi);
3619 tp->intr_mask = 0xffff;
3620 /*
3621 * 20040426: the barrier is not strictly required but the
3622 * behavior of the irq handler could be less predictable
3623 * without it. Btw, the lack of flush for the posted pci
3624 * write is safe - FR
3625 */
3626 smp_wmb();
3627 RTL_W16(IntrMask, tp->intr_event);
3628 }
3629
3630 return work_done;
3631 }
3632
3633 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
3634 {
3635 struct rtl8169_private *tp = netdev_priv(dev);
3636
3637 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
3638 return;
3639
3640 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
3641 RTL_W32(RxMissed, 0);
3642 }
3643
3644 static void rtl8169_down(struct net_device *dev)
3645 {
3646 struct rtl8169_private *tp = netdev_priv(dev);
3647 void __iomem *ioaddr = tp->mmio_addr;
3648 unsigned int intrmask;
3649
3650 rtl8169_delete_timer(dev);
3651
3652 netif_stop_queue(dev);
3653
3654 napi_disable(&tp->napi);
3655
3656 core_down:
3657 spin_lock_irq(&tp->lock);
3658
3659 rtl8169_asic_down(ioaddr);
3660
3661 rtl8169_rx_missed(dev, ioaddr);
3662
3663 spin_unlock_irq(&tp->lock);
3664
3665 synchronize_irq(dev->irq);
3666
3667 /* Give a racing hard_start_xmit a few cycles to complete. */
3668 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
3669
3670 /*
3671 * And now for the 50k$ question: are IRQ disabled or not ?
3672 *
3673 * Two paths lead here:
3674 * 1) dev->close
3675 * -> netif_running() is available to sync the current code and the
3676 * IRQ handler. See rtl8169_interrupt for details.
3677 * 2) dev->change_mtu
3678 * -> rtl8169_poll can not be issued again and re-enable the
3679 * interruptions. Let's simply issue the IRQ down sequence again.
3680 *
3681 * No loop if hotpluged or major error (0xffff).
3682 */
3683 intrmask = RTL_R16(IntrMask);
3684 if (intrmask && (intrmask != 0xffff))
3685 goto core_down;
3686
3687 rtl8169_tx_clear(tp);
3688
3689 rtl8169_rx_clear(tp);
3690 }
3691
3692 static int rtl8169_close(struct net_device *dev)
3693 {
3694 struct rtl8169_private *tp = netdev_priv(dev);
3695 struct pci_dev *pdev = tp->pci_dev;
3696
3697 /* update counters before going down */
3698 rtl8169_update_counters(dev);
3699
3700 rtl8169_down(dev);
3701
3702 free_irq(dev->irq, dev);
3703
3704 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3705 tp->RxPhyAddr);
3706 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3707 tp->TxPhyAddr);
3708 tp->TxDescArray = NULL;
3709 tp->RxDescArray = NULL;
3710
3711 return 0;
3712 }
3713
3714 static void rtl_set_rx_mode(struct net_device *dev)
3715 {
3716 struct rtl8169_private *tp = netdev_priv(dev);
3717 void __iomem *ioaddr = tp->mmio_addr;
3718 unsigned long flags;
3719 u32 mc_filter[2]; /* Multicast hash filter */
3720 int rx_mode;
3721 u32 tmp = 0;
3722
3723 if (dev->flags & IFF_PROMISC) {
3724 /* Unconditionally log net taps. */
3725 if (netif_msg_link(tp)) {
3726 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3727 dev->name);
3728 }
3729 rx_mode =
3730 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3731 AcceptAllPhys;
3732 mc_filter[1] = mc_filter[0] = 0xffffffff;
3733 } else if ((dev->mc_count > multicast_filter_limit)
3734 || (dev->flags & IFF_ALLMULTI)) {
3735 /* Too many to filter perfectly -- accept all multicasts. */
3736 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3737 mc_filter[1] = mc_filter[0] = 0xffffffff;
3738 } else {
3739 struct dev_mc_list *mclist;
3740 unsigned int i;
3741
3742 rx_mode = AcceptBroadcast | AcceptMyPhys;
3743 mc_filter[1] = mc_filter[0] = 0;
3744 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3745 i++, mclist = mclist->next) {
3746 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3747 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3748 rx_mode |= AcceptMulticast;
3749 }
3750 }
3751
3752 spin_lock_irqsave(&tp->lock, flags);
3753
3754 tmp = rtl8169_rx_config | rx_mode |
3755 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3756
3757 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
3758 u32 data = mc_filter[0];
3759
3760 mc_filter[0] = swab32(mc_filter[1]);
3761 mc_filter[1] = swab32(data);
3762 }
3763
3764 RTL_W32(MAR0 + 0, mc_filter[0]);
3765 RTL_W32(MAR0 + 4, mc_filter[1]);
3766
3767 RTL_W32(RxConfig, tmp);
3768
3769 spin_unlock_irqrestore(&tp->lock, flags);
3770 }
3771
3772 /**
3773 * rtl8169_get_stats - Get rtl8169 read/write statistics
3774 * @dev: The Ethernet Device to get statistics for
3775 *
3776 * Get TX/RX statistics for rtl8169
3777 */
3778 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3779 {
3780 struct rtl8169_private *tp = netdev_priv(dev);
3781 void __iomem *ioaddr = tp->mmio_addr;
3782 unsigned long flags;
3783
3784 if (netif_running(dev)) {
3785 spin_lock_irqsave(&tp->lock, flags);
3786 rtl8169_rx_missed(dev, ioaddr);
3787 spin_unlock_irqrestore(&tp->lock, flags);
3788 }
3789
3790 return &dev->stats;
3791 }
3792
3793 #ifdef CONFIG_PM
3794
3795 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3796 {
3797 struct net_device *dev = pci_get_drvdata(pdev);
3798 struct rtl8169_private *tp = netdev_priv(dev);
3799 void __iomem *ioaddr = tp->mmio_addr;
3800
3801 if (!netif_running(dev))
3802 goto out_pci_suspend;
3803
3804 netif_device_detach(dev);
3805 netif_stop_queue(dev);
3806
3807 spin_lock_irq(&tp->lock);
3808
3809 rtl8169_asic_down(ioaddr);
3810
3811 rtl8169_rx_missed(dev, ioaddr);
3812
3813 spin_unlock_irq(&tp->lock);
3814
3815 out_pci_suspend:
3816 pci_save_state(pdev);
3817 pci_enable_wake(pdev, pci_choose_state(pdev, state),
3818 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
3819 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3820
3821 return 0;
3822 }
3823
3824 static int rtl8169_resume(struct pci_dev *pdev)
3825 {
3826 struct net_device *dev = pci_get_drvdata(pdev);
3827
3828 pci_set_power_state(pdev, PCI_D0);
3829 pci_restore_state(pdev);
3830 pci_enable_wake(pdev, PCI_D0, 0);
3831
3832 if (!netif_running(dev))
3833 goto out;
3834
3835 netif_device_attach(dev);
3836
3837 rtl8169_schedule_work(dev, rtl8169_reset_task);
3838 out:
3839 return 0;
3840 }
3841
3842 static void rtl_shutdown(struct pci_dev *pdev)
3843 {
3844 rtl8169_suspend(pdev, PMSG_SUSPEND);
3845 }
3846
3847 #endif /* CONFIG_PM */
3848
3849 static struct pci_driver rtl8169_pci_driver = {
3850 .name = MODULENAME,
3851 .id_table = rtl8169_pci_tbl,
3852 .probe = rtl8169_init_one,
3853 .remove = __devexit_p(rtl8169_remove_one),
3854 #ifdef CONFIG_PM
3855 .suspend = rtl8169_suspend,
3856 .resume = rtl8169_resume,
3857 .shutdown = rtl_shutdown,
3858 #endif
3859 };
3860
3861 static int __init rtl8169_init_module(void)
3862 {
3863 return pci_register_driver(&rtl8169_pci_driver);
3864 }
3865
3866 static void __exit rtl8169_cleanup_module(void)
3867 {
3868 pci_unregister_driver(&rtl8169_pci_driver);
3869 }
3870
3871 module_init(rtl8169_init_module);
3872 module_exit(rtl8169_cleanup_module);
Support for the Chinese Samsung S3C2440 based development boards