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PCI: Fix oops in pci_vpd_truncate
[linux-2.6/mini2440.git] / drivers / video / pxafb.c
blob84f63205c46d1478ea4519e21b87f404caa6988d
1 /*
2 * linux/drivers/video/pxafb.c
3 *
4 * Copyright (C) 1999 Eric A. Thomas.
5 * Copyright (C) 2004 Jean-Frederic Clere.
6 * Copyright (C) 2004 Ian Campbell.
7 * Copyright (C) 2004 Jeff Lackey.
8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
9 * which in turn is
10 * Based on acornfb.c Copyright (C) Russell King.
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive for
14 * more details.
15 *
16 * Intel PXA250/210 LCD Controller Frame Buffer Driver
17 *
18 * Please direct your questions and comments on this driver to the following
19 * email address:
20 *
21 * linux-arm-kernel@lists.arm.linux.org.uk
22 *
23 * Add support for overlay1 and overlay2 based on pxafb_overlay.c:
24 *
25 * Copyright (C) 2004, Intel Corporation
26 *
27 * 2003/08/27: <yu.tang@intel.com>
28 * 2004/03/10: <stanley.cai@intel.com>
29 * 2004/10/28: <yan.yin@intel.com>
30 *
31 * Copyright (C) 2006-2008 Marvell International Ltd.
32 * All Rights Reserved
33 */
34
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/kernel.h>
38 #include <linux/sched.h>
39 #include <linux/errno.h>
40 #include <linux/string.h>
41 #include <linux/interrupt.h>
42 #include <linux/slab.h>
43 #include <linux/mm.h>
44 #include <linux/fb.h>
45 #include <linux/delay.h>
46 #include <linux/init.h>
47 #include <linux/ioport.h>
48 #include <linux/cpufreq.h>
49 #include <linux/platform_device.h>
50 #include <linux/dma-mapping.h>
51 #include <linux/clk.h>
52 #include <linux/err.h>
53 #include <linux/completion.h>
54 #include <linux/mutex.h>
55 #include <linux/kthread.h>
56 #include <linux/freezer.h>
57
58 #include <mach/hardware.h>
59 #include <asm/io.h>
60 #include <asm/irq.h>
61 #include <asm/div64.h>
62 #include <mach/bitfield.h>
63 #include <mach/pxafb.h>
64
65 /*
66 * Complain if VAR is out of range.
67 */
68 #define DEBUG_VAR 1
69
70 #include "pxafb.h"
71
72 /* Bits which should not be set in machine configuration structures */
73 #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
74 LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
75 LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
76
77 #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
78 LCCR3_PCD | LCCR3_BPP(0xf))
79
80 static int pxafb_activate_var(struct fb_var_screeninfo *var,
81 struct pxafb_info *);
82 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
83 static void setup_base_frame(struct pxafb_info *fbi, int branch);
84 static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
85 unsigned long offset, size_t size);
86
87 static unsigned long video_mem_size = 0;
88
89 static inline unsigned long
90 lcd_readl(struct pxafb_info *fbi, unsigned int off)
91 {
92 return __raw_readl(fbi->mmio_base + off);
93 }
94
95 static inline void
96 lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
97 {
98 __raw_writel(val, fbi->mmio_base + off);
99 }
100
101 static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
102 {
103 unsigned long flags;
104
105 local_irq_save(flags);
106 /*
107 * We need to handle two requests being made at the same time.
108 * There are two important cases:
109 * 1. When we are changing VT (C_REENABLE) while unblanking
110 * (C_ENABLE) We must perform the unblanking, which will
111 * do our REENABLE for us.
112 * 2. When we are blanking, but immediately unblank before
113 * we have blanked. We do the "REENABLE" thing here as
114 * well, just to be sure.
115 */
116 if (fbi->task_state == C_ENABLE && state == C_REENABLE)
117 state = (u_int) -1;
118 if (fbi->task_state == C_DISABLE && state == C_ENABLE)
119 state = C_REENABLE;
120
121 if (state != (u_int)-1) {
122 fbi->task_state = state;
123 schedule_work(&fbi->task);
124 }
125 local_irq_restore(flags);
126 }
127
128 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
129 {
130 chan &= 0xffff;
131 chan >>= 16 - bf->length;
132 return chan << bf->offset;
133 }
134
135 static int
136 pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
137 u_int trans, struct fb_info *info)
138 {
139 struct pxafb_info *fbi = (struct pxafb_info *)info;
140 u_int val;
141
142 if (regno >= fbi->palette_size)
143 return 1;
144
145 if (fbi->fb.var.grayscale) {
146 fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
147 return 0;
148 }
149
150 switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
151 case LCCR4_PAL_FOR_0:
152 val = ((red >> 0) & 0xf800);
153 val |= ((green >> 5) & 0x07e0);
154 val |= ((blue >> 11) & 0x001f);
155 fbi->palette_cpu[regno] = val;
156 break;
157 case LCCR4_PAL_FOR_1:
158 val = ((red << 8) & 0x00f80000);
159 val |= ((green >> 0) & 0x0000fc00);
160 val |= ((blue >> 8) & 0x000000f8);
161 ((u32 *)(fbi->palette_cpu))[regno] = val;
162 break;
163 case LCCR4_PAL_FOR_2:
164 val = ((red << 8) & 0x00fc0000);
165 val |= ((green >> 0) & 0x0000fc00);
166 val |= ((blue >> 8) & 0x000000fc);
167 ((u32 *)(fbi->palette_cpu))[regno] = val;
168 break;
169 case LCCR4_PAL_FOR_3:
170 val = ((red << 8) & 0x00ff0000);
171 val |= ((green >> 0) & 0x0000ff00);
172 val |= ((blue >> 8) & 0x000000ff);
173 ((u32 *)(fbi->palette_cpu))[regno] = val;
174 break;
175 }
176
177 return 0;
178 }
179
180 static int
181 pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
182 u_int trans, struct fb_info *info)
183 {
184 struct pxafb_info *fbi = (struct pxafb_info *)info;
185 unsigned int val;
186 int ret = 1;
187
188 /*
189 * If inverse mode was selected, invert all the colours
190 * rather than the register number. The register number
191 * is what you poke into the framebuffer to produce the
192 * colour you requested.
193 */
194 if (fbi->cmap_inverse) {
195 red = 0xffff - red;
196 green = 0xffff - green;
197 blue = 0xffff - blue;
198 }
199
200 /*
201 * If greyscale is true, then we convert the RGB value
202 * to greyscale no matter what visual we are using.
203 */
204 if (fbi->fb.var.grayscale)
205 red = green = blue = (19595 * red + 38470 * green +
206 7471 * blue) >> 16;
207
208 switch (fbi->fb.fix.visual) {
209 case FB_VISUAL_TRUECOLOR:
210 /*
211 * 16-bit True Colour. We encode the RGB value
212 * according to the RGB bitfield information.
213 */
214 if (regno < 16) {
215 u32 *pal = fbi->fb.pseudo_palette;
216
217 val = chan_to_field(red, &fbi->fb.var.red);
218 val |= chan_to_field(green, &fbi->fb.var.green);
219 val |= chan_to_field(blue, &fbi->fb.var.blue);
220
221 pal[regno] = val;
222 ret = 0;
223 }
224 break;
225
226 case FB_VISUAL_STATIC_PSEUDOCOLOR:
227 case FB_VISUAL_PSEUDOCOLOR:
228 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
229 break;
230 }
231
232 return ret;
233 }
234
235 /* calculate pixel depth, transparency bit included, >=16bpp formats _only_ */
236 static inline int var_to_depth(struct fb_var_screeninfo *var)
237 {
238 return var->red.length + var->green.length +
239 var->blue.length + var->transp.length;
240 }
241
242 /* calculate 4-bit BPP value for LCCR3 and OVLxC1 */
243 static int pxafb_var_to_bpp(struct fb_var_screeninfo *var)
244 {
245 int bpp = -EINVAL;
246
247 switch (var->bits_per_pixel) {
248 case 1: bpp = 0; break;
249 case 2: bpp = 1; break;
250 case 4: bpp = 2; break;
251 case 8: bpp = 3; break;
252 case 16: bpp = 4; break;
253 case 24:
254 switch (var_to_depth(var)) {
255 case 18: bpp = 6; break; /* 18-bits/pixel packed */
256 case 19: bpp = 8; break; /* 19-bits/pixel packed */
257 case 24: bpp = 9; break;
258 }
259 break;
260 case 32:
261 switch (var_to_depth(var)) {
262 case 18: bpp = 5; break; /* 18-bits/pixel unpacked */
263 case 19: bpp = 7; break; /* 19-bits/pixel unpacked */
264 case 25: bpp = 10; break;
265 }
266 break;
267 }
268 return bpp;
269 }
270
271 /*
272 * pxafb_var_to_lccr3():
273 * Convert a bits per pixel value to the correct bit pattern for LCCR3
274 *
275 * NOTE: for PXA27x with overlays support, the LCCR3_PDFOR_x bits have an
276 * implication of the acutal use of transparency bit, which we handle it
277 * here separatedly. See PXA27x Developer's Manual, Section <<7.4.6 Pixel
278 * Formats>> for the valid combination of PDFOR, PAL_FOR for various BPP.
279 *
280 * Transparency for palette pixel formats is not supported at the moment.
281 */
282 static uint32_t pxafb_var_to_lccr3(struct fb_var_screeninfo *var)
283 {
284 int bpp = pxafb_var_to_bpp(var);
285 uint32_t lccr3;
286
287 if (bpp < 0)
288 return 0;
289
290 lccr3 = LCCR3_BPP(bpp);
291
292 switch (var_to_depth(var)) {
293 case 16: lccr3 |= var->transp.length ? LCCR3_PDFOR_3 : 0; break;
294 case 18: lccr3 |= LCCR3_PDFOR_3; break;
295 case 24: lccr3 |= var->transp.length ? LCCR3_PDFOR_2 : LCCR3_PDFOR_3;
296 break;
297 case 19:
298 case 25: lccr3 |= LCCR3_PDFOR_0; break;
299 }
300 return lccr3;
301 }
302
303 #define SET_PIXFMT(v, r, g, b, t) \
304 ({ \
305 (v)->transp.offset = (t) ? (r) + (g) + (b) : 0; \
306 (v)->transp.length = (t) ? (t) : 0; \
307 (v)->blue.length = (b); (v)->blue.offset = 0; \
308 (v)->green.length = (g); (v)->green.offset = (b); \
309 (v)->red.length = (r); (v)->red.offset = (b) + (g); \
310 })
311
312 /* set the RGBT bitfields of fb_var_screeninf according to
313 * var->bits_per_pixel and given depth
314 */
315 static void pxafb_set_pixfmt(struct fb_var_screeninfo *var, int depth)
316 {
317 if (depth == 0)
318 depth = var->bits_per_pixel;
319
320 if (var->bits_per_pixel < 16) {
321 /* indexed pixel formats */
322 var->red.offset = 0; var->red.length = 8;
323 var->green.offset = 0; var->green.length = 8;
324 var->blue.offset = 0; var->blue.length = 8;
325 var->transp.offset = 0; var->transp.length = 8;
326 }
327
328 switch (depth) {
329 case 16: var->transp.length ?
330 SET_PIXFMT(var, 5, 5, 5, 1) : /* RGBT555 */
331 SET_PIXFMT(var, 5, 6, 5, 0); break; /* RGB565 */
332 case 18: SET_PIXFMT(var, 6, 6, 6, 0); break; /* RGB666 */
333 case 19: SET_PIXFMT(var, 6, 6, 6, 1); break; /* RGBT666 */
334 case 24: var->transp.length ?
335 SET_PIXFMT(var, 8, 8, 7, 1) : /* RGBT887 */
336 SET_PIXFMT(var, 8, 8, 8, 0); break; /* RGB888 */
337 case 25: SET_PIXFMT(var, 8, 8, 8, 1); break; /* RGBT888 */
338 }
339 }
340
341 #ifdef CONFIG_CPU_FREQ
342 /*
343 * pxafb_display_dma_period()
344 * Calculate the minimum period (in picoseconds) between two DMA
345 * requests for the LCD controller. If we hit this, it means we're
346 * doing nothing but LCD DMA.
347 */
348 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
349 {
350 /*
351 * Period = pixclock * bits_per_byte * bytes_per_transfer
352 * / memory_bits_per_pixel;
353 */
354 return var->pixclock * 8 * 16 / var->bits_per_pixel;
355 }
356 #endif
357
358 /*
359 * Select the smallest mode that allows the desired resolution to be
360 * displayed. If desired parameters can be rounded up.
361 */
362 static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
363 struct fb_var_screeninfo *var)
364 {
365 struct pxafb_mode_info *mode = NULL;
366 struct pxafb_mode_info *modelist = mach->modes;
367 unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
368 unsigned int i;
369
370 for (i = 0; i < mach->num_modes; i++) {
371 if (modelist[i].xres >= var->xres &&
372 modelist[i].yres >= var->yres &&
373 modelist[i].xres < best_x &&
374 modelist[i].yres < best_y &&
375 modelist[i].bpp >= var->bits_per_pixel) {
376 best_x = modelist[i].xres;
377 best_y = modelist[i].yres;
378 mode = &modelist[i];
379 }
380 }
381
382 return mode;
383 }
384
385 static void pxafb_setmode(struct fb_var_screeninfo *var,
386 struct pxafb_mode_info *mode)
387 {
388 var->xres = mode->xres;
389 var->yres = mode->yres;
390 var->bits_per_pixel = mode->bpp;
391 var->pixclock = mode->pixclock;
392 var->hsync_len = mode->hsync_len;
393 var->left_margin = mode->left_margin;
394 var->right_margin = mode->right_margin;
395 var->vsync_len = mode->vsync_len;
396 var->upper_margin = mode->upper_margin;
397 var->lower_margin = mode->lower_margin;
398 var->sync = mode->sync;
399 var->grayscale = mode->cmap_greyscale;
400
401 /* set the initial RGBA bitfields */
402 pxafb_set_pixfmt(var, mode->depth);
403 }
404
405 static int pxafb_adjust_timing(struct pxafb_info *fbi,
406 struct fb_var_screeninfo *var)
407 {
408 int line_length;
409
410 var->xres = max_t(int, var->xres, MIN_XRES);
411 var->yres = max_t(int, var->yres, MIN_YRES);
412
413 if (!(fbi->lccr0 & LCCR0_LCDT)) {
414 clamp_val(var->hsync_len, 1, 64);
415 clamp_val(var->vsync_len, 1, 64);
416 clamp_val(var->left_margin, 1, 255);
417 clamp_val(var->right_margin, 1, 255);
418 clamp_val(var->upper_margin, 1, 255);
419 clamp_val(var->lower_margin, 1, 255);
420 }
421
422 /* make sure each line is aligned on word boundary */
423 line_length = var->xres * var->bits_per_pixel / 8;
424 line_length = ALIGN(line_length, 4);
425 var->xres = line_length * 8 / var->bits_per_pixel;
426
427 /* we don't support xpan, force xres_virtual to be equal to xres */
428 var->xres_virtual = var->xres;
429
430 if (var->accel_flags & FB_ACCELF_TEXT)
431 var->yres_virtual = fbi->fb.fix.smem_len / line_length;
432 else
433 var->yres_virtual = max(var->yres_virtual, var->yres);
434
435 /* check for limits */
436 if (var->xres > MAX_XRES || var->yres > MAX_YRES)
437 return -EINVAL;
438
439 if (var->yres > var->yres_virtual)
440 return -EINVAL;
441
442 return 0;
443 }
444
445 /*
446 * pxafb_check_var():
447 * Get the video params out of 'var'. If a value doesn't fit, round it up,
448 * if it's too big, return -EINVAL.
449 *
450 * Round up in the following order: bits_per_pixel, xres,
451 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
452 * bitfields, horizontal timing, vertical timing.
453 */
454 static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
455 {
456 struct pxafb_info *fbi = (struct pxafb_info *)info;
457 struct pxafb_mach_info *inf = fbi->dev->platform_data;
458 int err;
459
460 if (inf->fixed_modes) {
461 struct pxafb_mode_info *mode;
462
463 mode = pxafb_getmode(inf, var);
464 if (!mode)
465 return -EINVAL;
466 pxafb_setmode(var, mode);
467 }
468
469 /* do a test conversion to BPP fields to check the color formats */
470 err = pxafb_var_to_bpp(var);
471 if (err < 0)
472 return err;
473
474 pxafb_set_pixfmt(var, var_to_depth(var));
475
476 err = pxafb_adjust_timing(fbi, var);
477 if (err)
478 return err;
479
480 #ifdef CONFIG_CPU_FREQ
481 pr_debug("pxafb: dma period = %d ps\n",
482 pxafb_display_dma_period(var));
483 #endif
484
485 return 0;
486 }
487
488 /*
489 * pxafb_set_par():
490 * Set the user defined part of the display for the specified console
491 */
492 static int pxafb_set_par(struct fb_info *info)
493 {
494 struct pxafb_info *fbi = (struct pxafb_info *)info;
495 struct fb_var_screeninfo *var = &info->var;
496
497 if (var->bits_per_pixel >= 16)
498 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
499 else if (!fbi->cmap_static)
500 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
501 else {
502 /*
503 * Some people have weird ideas about wanting static
504 * pseudocolor maps. I suspect their user space
505 * applications are broken.
506 */
507 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
508 }
509
510 fbi->fb.fix.line_length = var->xres_virtual *
511 var->bits_per_pixel / 8;
512 if (var->bits_per_pixel >= 16)
513 fbi->palette_size = 0;
514 else
515 fbi->palette_size = var->bits_per_pixel == 1 ?
516 4 : 1 << var->bits_per_pixel;
517
518 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
519
520 if (fbi->fb.var.bits_per_pixel >= 16)
521 fb_dealloc_cmap(&fbi->fb.cmap);
522 else
523 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
524
525 pxafb_activate_var(var, fbi);
526
527 return 0;
528 }
529
530 static int pxafb_pan_display(struct fb_var_screeninfo *var,
531 struct fb_info *info)
532 {
533 struct pxafb_info *fbi = (struct pxafb_info *)info;
534 int dma = DMA_MAX + DMA_BASE;
535
536 if (fbi->state != C_ENABLE)
537 return 0;
538
539 setup_base_frame(fbi, 1);
540
541 if (fbi->lccr0 & LCCR0_SDS)
542 lcd_writel(fbi, FBR1, fbi->fdadr[dma + 1] | 0x1);
543
544 lcd_writel(fbi, FBR0, fbi->fdadr[dma] | 0x1);
545 return 0;
546 }
547
548 /*
549 * pxafb_blank():
550 * Blank the display by setting all palette values to zero. Note, the
551 * 16 bpp mode does not really use the palette, so this will not
552 * blank the display in all modes.
553 */
554 static int pxafb_blank(int blank, struct fb_info *info)
555 {
556 struct pxafb_info *fbi = (struct pxafb_info *)info;
557 int i;
558
559 switch (blank) {
560 case FB_BLANK_POWERDOWN:
561 case FB_BLANK_VSYNC_SUSPEND:
562 case FB_BLANK_HSYNC_SUSPEND:
563 case FB_BLANK_NORMAL:
564 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
565 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
566 for (i = 0; i < fbi->palette_size; i++)
567 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
568
569 pxafb_schedule_work(fbi, C_DISABLE);
570 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
571 break;
572
573 case FB_BLANK_UNBLANK:
574 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
575 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
576 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
577 fb_set_cmap(&fbi->fb.cmap, info);
578 pxafb_schedule_work(fbi, C_ENABLE);
579 }
580 return 0;
581 }
582
583 static struct fb_ops pxafb_ops = {
584 .owner = THIS_MODULE,
585 .fb_check_var = pxafb_check_var,
586 .fb_set_par = pxafb_set_par,
587 .fb_pan_display = pxafb_pan_display,
588 .fb_setcolreg = pxafb_setcolreg,
589 .fb_fillrect = cfb_fillrect,
590 .fb_copyarea = cfb_copyarea,
591 .fb_imageblit = cfb_imageblit,
592 .fb_blank = pxafb_blank,
593 };
594
595 #ifdef CONFIG_FB_PXA_OVERLAY
596 static void overlay1fb_setup(struct pxafb_layer *ofb)
597 {
598 int size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
599 unsigned long start = ofb->video_mem_phys;
600 setup_frame_dma(ofb->fbi, DMA_OV1, PAL_NONE, start, size);
601 }
602
603 /* Depending on the enable status of overlay1/2, the DMA should be
604 * updated from FDADRx (when disabled) or FBRx (when enabled).
605 */
606 static void overlay1fb_enable(struct pxafb_layer *ofb)
607 {
608 int enabled = lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN;
609 uint32_t fdadr1 = ofb->fbi->fdadr[DMA_OV1] | (enabled ? 0x1 : 0);
610
611 lcd_writel(ofb->fbi, enabled ? FBR1 : FDADR1, fdadr1);
612 lcd_writel(ofb->fbi, OVL1C2, ofb->control[1]);
613 lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] | OVLxC1_OEN);
614 }
615
616 static void overlay1fb_disable(struct pxafb_layer *ofb)
617 {
618 uint32_t lccr5 = lcd_readl(ofb->fbi, LCCR5);
619
620 lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] & ~OVLxC1_OEN);
621
622 lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(1));
623 lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(1));
624 lcd_writel(ofb->fbi, FBR1, ofb->fbi->fdadr[DMA_OV1] | 0x3);
625
626 if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
627 pr_warning("%s: timeout disabling overlay1\n", __func__);
628
629 lcd_writel(ofb->fbi, LCCR5, lccr5);
630 }
631
632 static void overlay2fb_setup(struct pxafb_layer *ofb)
633 {
634 int size, div = 1, pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
635 unsigned long start[3] = { ofb->video_mem_phys, 0, 0 };
636
637 if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED) {
638 size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
639 setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size);
640 } else {
641 size = ofb->fb.var.xres_virtual * ofb->fb.var.yres_virtual;
642 switch (pfor) {
643 case OVERLAY_FORMAT_YUV444_PLANAR: div = 1; break;
644 case OVERLAY_FORMAT_YUV422_PLANAR: div = 2; break;
645 case OVERLAY_FORMAT_YUV420_PLANAR: div = 4; break;
646 }
647 start[1] = start[0] + size;
648 start[2] = start[1] + size / div;
649 setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size);
650 setup_frame_dma(ofb->fbi, DMA_OV2_Cb, -1, start[1], size / div);
651 setup_frame_dma(ofb->fbi, DMA_OV2_Cr, -1, start[2], size / div);
652 }
653 }
654
655 static void overlay2fb_enable(struct pxafb_layer *ofb)
656 {
657 int pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
658 int enabled = lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN;
659 uint32_t fdadr2 = ofb->fbi->fdadr[DMA_OV2_Y] | (enabled ? 0x1 : 0);
660 uint32_t fdadr3 = ofb->fbi->fdadr[DMA_OV2_Cb] | (enabled ? 0x1 : 0);
661 uint32_t fdadr4 = ofb->fbi->fdadr[DMA_OV2_Cr] | (enabled ? 0x1 : 0);
662
663 if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED)
664 lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
665 else {
666 lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
667 lcd_writel(ofb->fbi, enabled ? FBR3 : FDADR3, fdadr3);
668 lcd_writel(ofb->fbi, enabled ? FBR4 : FDADR4, fdadr4);
669 }
670 lcd_writel(ofb->fbi, OVL2C2, ofb->control[1]);
671 lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] | OVLxC1_OEN);
672 }
673
674 static void overlay2fb_disable(struct pxafb_layer *ofb)
675 {
676 uint32_t lccr5 = lcd_readl(ofb->fbi, LCCR5);
677
678 lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] & ~OVLxC1_OEN);
679
680 lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(2));
681 lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(2));
682 lcd_writel(ofb->fbi, FBR2, ofb->fbi->fdadr[DMA_OV2_Y] | 0x3);
683 lcd_writel(ofb->fbi, FBR3, ofb->fbi->fdadr[DMA_OV2_Cb] | 0x3);
684 lcd_writel(ofb->fbi, FBR4, ofb->fbi->fdadr[DMA_OV2_Cr] | 0x3);
685
686 if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
687 pr_warning("%s: timeout disabling overlay2\n", __func__);
688 }
689
690 static struct pxafb_layer_ops ofb_ops[] = {
691 [0] = {
692 .enable = overlay1fb_enable,
693 .disable = overlay1fb_disable,
694 .setup = overlay1fb_setup,
695 },
696 [1] = {
697 .enable = overlay2fb_enable,
698 .disable = overlay2fb_disable,
699 .setup = overlay2fb_setup,
700 },
701 };
702
703 static int overlayfb_open(struct fb_info *info, int user)
704 {
705 struct pxafb_layer *ofb = (struct pxafb_layer *)info;
706
707 /* no support for framebuffer console on overlay */
708 if (user == 0)
709 return -ENODEV;
710
711 /* allow only one user at a time */
712 if (atomic_inc_and_test(&ofb->usage))
713 return -EBUSY;
714
715 /* unblank the base framebuffer */
716 fb_blank(&ofb->fbi->fb, FB_BLANK_UNBLANK);
717 return 0;
718 }
719
720 static int overlayfb_release(struct fb_info *info, int user)
721 {
722 struct pxafb_layer *ofb = (struct pxafb_layer*) info;
723
724 atomic_dec(&ofb->usage);
725 ofb->ops->disable(ofb);
726
727 free_pages_exact(ofb->video_mem, ofb->video_mem_size);
728 ofb->video_mem = NULL;
729 ofb->video_mem_size = 0;
730 return 0;
731 }
732
733 static int overlayfb_check_var(struct fb_var_screeninfo *var,
734 struct fb_info *info)
735 {
736 struct pxafb_layer *ofb = (struct pxafb_layer *)info;
737 struct fb_var_screeninfo *base_var = &ofb->fbi->fb.var;
738 int xpos, ypos, pfor, bpp;
739
740 xpos = NONSTD_TO_XPOS(var->nonstd);
741 ypos = NONSTD_TO_XPOS(var->nonstd);
742 pfor = NONSTD_TO_PFOR(var->nonstd);
743
744 bpp = pxafb_var_to_bpp(var);
745 if (bpp < 0)
746 return -EINVAL;
747
748 /* no support for YUV format on overlay1 */
749 if (ofb->id == OVERLAY1 && pfor != 0)
750 return -EINVAL;
751
752 /* for YUV packed formats, bpp = 'minimum bpp of YUV components' */
753 switch (pfor) {
754 case OVERLAY_FORMAT_RGB:
755 bpp = pxafb_var_to_bpp(var);
756 if (bpp < 0)
757 return -EINVAL;
758
759 pxafb_set_pixfmt(var, var_to_depth(var));
760 break;
761 case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
762 case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 8; break;
763 case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 4; break;
764 case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 2; break;
765 default:
766 return -EINVAL;
767 }
768
769 /* each line must start at a 32-bit word boundary */
770 if ((xpos * bpp) % 32)
771 return -EINVAL;
772
773 /* xres must align on 32-bit word boundary */
774 var->xres = roundup(var->xres * bpp, 32) / bpp;
775
776 if ((xpos + var->xres > base_var->xres) ||
777 (ypos + var->yres > base_var->yres))
778 return -EINVAL;
779
780 var->xres_virtual = var->xres;
781 var->yres_virtual = max(var->yres, var->yres_virtual);
782 return 0;
783 }
784
785 static int overlayfb_map_video_memory(struct pxafb_layer *ofb)
786 {
787 struct fb_var_screeninfo *var = &ofb->fb.var;
788 int pfor = NONSTD_TO_PFOR(var->nonstd);
789 int size, bpp = 0;
790
791 switch (pfor) {
792 case OVERLAY_FORMAT_RGB: bpp = var->bits_per_pixel; break;
793 case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
794 case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 24; break;
795 case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 16; break;
796 case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 12; break;
797 }
798
799 ofb->fb.fix.line_length = var->xres_virtual * bpp / 8;
800
801 size = PAGE_ALIGN(ofb->fb.fix.line_length * var->yres_virtual);
802
803 /* don't re-allocate if the original video memory is enough */
804 if (ofb->video_mem) {
805 if (ofb->video_mem_size >= size)
806 return 0;
807
808 free_pages_exact(ofb->video_mem, ofb->video_mem_size);
809 }
810
811 ofb->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
812 if (ofb->video_mem == NULL)
813 return -ENOMEM;
814
815 ofb->video_mem_phys = virt_to_phys(ofb->video_mem);
816 ofb->video_mem_size = size;
817
818 ofb->fb.fix.smem_start = ofb->video_mem_phys;
819 ofb->fb.fix.smem_len = ofb->fb.fix.line_length * var->yres_virtual;
820 ofb->fb.screen_base = ofb->video_mem;
821 return 0;
822 }
823
824 static int overlayfb_set_par(struct fb_info *info)
825 {
826 struct pxafb_layer *ofb = (struct pxafb_layer *)info;
827 struct fb_var_screeninfo *var = &info->var;
828 int xpos, ypos, pfor, bpp, ret;
829
830 ret = overlayfb_map_video_memory(ofb);
831 if (ret)
832 return ret;
833
834 bpp = pxafb_var_to_bpp(var);
835 xpos = NONSTD_TO_XPOS(var->nonstd);
836 ypos = NONSTD_TO_XPOS(var->nonstd);
837 pfor = NONSTD_TO_PFOR(var->nonstd);
838
839 ofb->control[0] = OVLxC1_PPL(var->xres) | OVLxC1_LPO(var->yres) |
840 OVLxC1_BPP(bpp);
841 ofb->control[1] = OVLxC2_XPOS(xpos) | OVLxC2_YPOS(ypos);
842
843 if (ofb->id == OVERLAY2)
844 ofb->control[1] |= OVL2C2_PFOR(pfor);
845
846 ofb->ops->setup(ofb);
847 ofb->ops->enable(ofb);
848 return 0;
849 }
850
851 static struct fb_ops overlay_fb_ops = {
852 .owner = THIS_MODULE,
853 .fb_open = overlayfb_open,
854 .fb_release = overlayfb_release,
855 .fb_check_var = overlayfb_check_var,
856 .fb_set_par = overlayfb_set_par,
857 };
858
859 static void __devinit init_pxafb_overlay(struct pxafb_info *fbi,
860 struct pxafb_layer *ofb, int id)
861 {
862 sprintf(ofb->fb.fix.id, "overlay%d", id + 1);
863
864 ofb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
865 ofb->fb.fix.xpanstep = 0;
866 ofb->fb.fix.ypanstep = 1;
867
868 ofb->fb.var.activate = FB_ACTIVATE_NOW;
869 ofb->fb.var.height = -1;
870 ofb->fb.var.width = -1;
871 ofb->fb.var.vmode = FB_VMODE_NONINTERLACED;
872
873 ofb->fb.fbops = &overlay_fb_ops;
874 ofb->fb.flags = FBINFO_FLAG_DEFAULT;
875 ofb->fb.node = -1;
876 ofb->fb.pseudo_palette = NULL;
877
878 ofb->id = id;
879 ofb->ops = &ofb_ops[id];
880 atomic_set(&ofb->usage, 0);
881 ofb->fbi = fbi;
882 init_completion(&ofb->branch_done);
883 }
884
885 static inline int pxafb_overlay_supported(void)
886 {
887 if (cpu_is_pxa27x() || cpu_is_pxa3xx())
888 return 1;
889
890 return 0;
891 }
892
893 static int __devinit pxafb_overlay_init(struct pxafb_info *fbi)
894 {
895 int i, ret;
896
897 if (!pxafb_overlay_supported())
898 return 0;
899
900 for (i = 0; i < 2; i++) {
901 init_pxafb_overlay(fbi, &fbi->overlay[i], i);
902 ret = register_framebuffer(&fbi->overlay[i].fb);
903 if (ret) {
904 dev_err(fbi->dev, "failed to register overlay %d\n", i);
905 return ret;
906 }
907 }
908
909 /* mask all IU/BS/EOF/SOF interrupts */
910 lcd_writel(fbi, LCCR5, ~0);
911
912 /* place overlay(s) on top of base */
913 fbi->lccr0 |= LCCR0_OUC;
914 pr_info("PXA Overlay driver loaded successfully!\n");
915 return 0;
916 }
917
918 static void __devexit pxafb_overlay_exit(struct pxafb_info *fbi)
919 {
920 int i;
921
922 if (!pxafb_overlay_supported())
923 return;
924
925 for (i = 0; i < 2; i++)
926 unregister_framebuffer(&fbi->overlay[i].fb);
927 }
928 #else
929 static inline void pxafb_overlay_init(struct pxafb_info *fbi) {}
930 static inline void pxafb_overlay_exit(struct pxafb_info *fbi) {}
931 #endif /* CONFIG_FB_PXA_OVERLAY */
932
933 /*
934 * Calculate the PCD value from the clock rate (in picoseconds).
935 * We take account of the PPCR clock setting.
936 * From PXA Developer's Manual:
937 *
938 * PixelClock = LCLK
939 * -------------
940 * 2 ( PCD + 1 )
941 *
942 * PCD = LCLK
943 * ------------- - 1
944 * 2(PixelClock)
945 *
946 * Where:
947 * LCLK = LCD/Memory Clock
948 * PCD = LCCR3[7:0]
949 *
950 * PixelClock here is in Hz while the pixclock argument given is the
951 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
952 *
953 * The function get_lclk_frequency_10khz returns LCLK in units of
954 * 10khz. Calling the result of this function lclk gives us the
955 * following
956 *
957 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
958 * -------------------------------------- - 1
959 * 2
960 *
961 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
962 */
963 static inline unsigned int get_pcd(struct pxafb_info *fbi,
964 unsigned int pixclock)
965 {
966 unsigned long long pcd;
967
968 /* FIXME: Need to take into account Double Pixel Clock mode
969 * (DPC) bit? or perhaps set it based on the various clock
970 * speeds */
971 pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
972 pcd *= pixclock;
973 do_div(pcd, 100000000 * 2);
974 /* no need for this, since we should subtract 1 anyway. they cancel */
975 /* pcd += 1; */ /* make up for integer math truncations */
976 return (unsigned int)pcd;
977 }
978
979 /*
980 * Some touchscreens need hsync information from the video driver to
981 * function correctly. We export it here. Note that 'hsync_time' and
982 * the value returned from pxafb_get_hsync_time() is the *reciprocal*
983 * of the hsync period in seconds.
984 */
985 static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
986 {
987 unsigned long htime;
988
989 if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
990 fbi->hsync_time = 0;
991 return;
992 }
993
994 htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
995
996 fbi->hsync_time = htime;
997 }
998
999 unsigned long pxafb_get_hsync_time(struct device *dev)
1000 {
1001 struct pxafb_info *fbi = dev_get_drvdata(dev);
1002
1003 /* If display is blanked/suspended, hsync isn't active */
1004 if (!fbi || (fbi->state != C_ENABLE))
1005 return 0;
1006
1007 return fbi->hsync_time;
1008 }
1009 EXPORT_SYMBOL(pxafb_get_hsync_time);
1010
1011 static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
1012 unsigned long start, size_t size)
1013 {
1014 struct pxafb_dma_descriptor *dma_desc, *pal_desc;
1015 unsigned int dma_desc_off, pal_desc_off;
1016
1017 if (dma < 0 || dma >= DMA_MAX * 2)
1018 return -EINVAL;
1019
1020 dma_desc = &fbi->dma_buff->dma_desc[dma];
1021 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
1022
1023 dma_desc->fsadr = start;
1024 dma_desc->fidr = 0;
1025 dma_desc->ldcmd = size;
1026
1027 if (pal < 0 || pal >= PAL_MAX * 2) {
1028 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1029 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
1030 } else {
1031 pal_desc = &fbi->dma_buff->pal_desc[pal];
1032 pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]);
1033
1034 pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
1035 pal_desc->fidr = 0;
1036
1037 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
1038 pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
1039 else
1040 pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
1041
1042 pal_desc->ldcmd |= LDCMD_PAL;
1043
1044 /* flip back and forth between palette and frame buffer */
1045 pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1046 dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
1047 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
1048 }
1049
1050 return 0;
1051 }
1052
1053 static void setup_base_frame(struct pxafb_info *fbi, int branch)
1054 {
1055 struct fb_var_screeninfo *var = &fbi->fb.var;
1056 struct fb_fix_screeninfo *fix = &fbi->fb.fix;
1057 int nbytes, dma, pal, bpp = var->bits_per_pixel;
1058 unsigned long offset;
1059
1060 dma = DMA_BASE + (branch ? DMA_MAX : 0);
1061 pal = (bpp >= 16) ? PAL_NONE : PAL_BASE + (branch ? PAL_MAX : 0);
1062
1063 nbytes = fix->line_length * var->yres;
1064 offset = fix->line_length * var->yoffset + fbi->video_mem_phys;
1065
1066 if (fbi->lccr0 & LCCR0_SDS) {
1067 nbytes = nbytes / 2;
1068 setup_frame_dma(fbi, dma + 1, PAL_NONE, offset + nbytes, nbytes);
1069 }
1070
1071 setup_frame_dma(fbi, dma, pal, offset, nbytes);
1072 }
1073
1074 #ifdef CONFIG_FB_PXA_SMARTPANEL
1075 static int setup_smart_dma(struct pxafb_info *fbi)
1076 {
1077 struct pxafb_dma_descriptor *dma_desc;
1078 unsigned long dma_desc_off, cmd_buff_off;
1079
1080 dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD];
1081 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]);
1082 cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff);
1083
1084 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1085 dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off;
1086 dma_desc->fidr = 0;
1087 dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t);
1088
1089 fbi->fdadr[DMA_CMD] = dma_desc->fdadr;
1090 return 0;
1091 }
1092
1093 int pxafb_smart_flush(struct fb_info *info)
1094 {
1095 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
1096 uint32_t prsr;
1097 int ret = 0;
1098
1099 /* disable controller until all registers are set up */
1100 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1101
1102 /* 1. make it an even number of commands to align on 32-bit boundary
1103 * 2. add the interrupt command to the end of the chain so we can
1104 * keep track of the end of the transfer
1105 */
1106
1107 while (fbi->n_smart_cmds & 1)
1108 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP;
1109
1110 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT;
1111 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC;
1112 setup_smart_dma(fbi);
1113
1114 /* continue to execute next command */
1115 prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT;
1116 lcd_writel(fbi, PRSR, prsr);
1117
1118 /* stop the processor in case it executed "wait for sync" cmd */
1119 lcd_writel(fbi, CMDCR, 0x0001);
1120
1121 /* don't send interrupts for fifo underruns on channel 6 */
1122 lcd_writel(fbi, LCCR5, LCCR5_IUM(6));
1123
1124 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1125 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1126 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1127 lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
1128 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1129 lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
1130
1131 /* begin sending */
1132 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1133
1134 if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) {
1135 pr_warning("%s: timeout waiting for command done\n",
1136 __func__);
1137 ret = -ETIMEDOUT;
1138 }
1139
1140 /* quick disable */
1141 prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT);
1142 lcd_writel(fbi, PRSR, prsr);
1143 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1144 lcd_writel(fbi, FDADR6, 0);
1145 fbi->n_smart_cmds = 0;
1146 return ret;
1147 }
1148
1149 int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
1150 {
1151 int i;
1152 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
1153
1154 for (i = 0; i < n_cmds; i++, cmds++) {
1155 /* if it is a software delay, flush and delay */
1156 if ((*cmds & 0xff00) == SMART_CMD_DELAY) {
1157 pxafb_smart_flush(info);
1158 mdelay(*cmds & 0xff);
1159 continue;
1160 }
1161
1162 /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
1163 if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
1164 pxafb_smart_flush(info);
1165
1166 fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds;
1167 }
1168
1169 return 0;
1170 }
1171
1172 static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk)
1173 {
1174 unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000);
1175 return (t == 0) ? 1 : t;
1176 }
1177
1178 static void setup_smart_timing(struct pxafb_info *fbi,
1179 struct fb_var_screeninfo *var)
1180 {
1181 struct pxafb_mach_info *inf = fbi->dev->platform_data;
1182 struct pxafb_mode_info *mode = &inf->modes[0];
1183 unsigned long lclk = clk_get_rate(fbi->clk);
1184 unsigned t1, t2, t3, t4;
1185
1186 t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld);
1187 t2 = max(mode->rd_pulse_width, mode->wr_pulse_width);
1188 t3 = mode->op_hold_time;
1189 t4 = mode->cmd_inh_time;
1190
1191 fbi->reg_lccr1 =
1192 LCCR1_DisWdth(var->xres) |
1193 LCCR1_BegLnDel(__smart_timing(t1, lclk)) |
1194 LCCR1_EndLnDel(__smart_timing(t2, lclk)) |
1195 LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
1196
1197 fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
1198 fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk));
1199 fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0;
1200 fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0;
1201
1202 /* FIXME: make this configurable */
1203 fbi->reg_cmdcr = 1;
1204 }
1205
1206 static int pxafb_smart_thread(void *arg)
1207 {
1208 struct pxafb_info *fbi = arg;
1209 struct pxafb_mach_info *inf = fbi->dev->platform_data;
1210
1211 if (!fbi || !inf->smart_update) {
1212 pr_err("%s: not properly initialized, thread terminated\n",
1213 __func__);
1214 return -EINVAL;
1215 }
1216
1217 pr_debug("%s(): task starting\n", __func__);
1218
1219 set_freezable();
1220 while (!kthread_should_stop()) {
1221
1222 if (try_to_freeze())
1223 continue;
1224
1225 mutex_lock(&fbi->ctrlr_lock);
1226
1227 if (fbi->state == C_ENABLE) {
1228 inf->smart_update(&fbi->fb);
1229 complete(&fbi->refresh_done);
1230 }
1231
1232 mutex_unlock(&fbi->ctrlr_lock);
1233
1234 set_current_state(TASK_INTERRUPTIBLE);
1235 schedule_timeout(30 * HZ / 1000);
1236 }
1237
1238 pr_debug("%s(): task ending\n", __func__);
1239 return 0;
1240 }
1241
1242 static int pxafb_smart_init(struct pxafb_info *fbi)
1243 {
1244 if (!(fbi->lccr0 & LCCR0_LCDT))
1245 return 0;
1246
1247 fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
1248 fbi->n_smart_cmds = 0;
1249
1250 init_completion(&fbi->command_done);
1251 init_completion(&fbi->refresh_done);
1252
1253 fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
1254 "lcd_refresh");
1255 if (IS_ERR(fbi->smart_thread)) {
1256 pr_err("%s: unable to create kernel thread\n", __func__);
1257 return PTR_ERR(fbi->smart_thread);
1258 }
1259
1260 return 0;
1261 }
1262 #else
1263 int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
1264 {
1265 return 0;
1266 }
1267
1268 int pxafb_smart_flush(struct fb_info *info)
1269 {
1270 return 0;
1271 }
1272
1273 static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; }
1274 #endif /* CONFIG_FB_PXA_SMARTPANEL */
1275
1276 static void setup_parallel_timing(struct pxafb_info *fbi,
1277 struct fb_var_screeninfo *var)
1278 {
1279 unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
1280
1281 fbi->reg_lccr1 =
1282 LCCR1_DisWdth(var->xres) +
1283 LCCR1_HorSnchWdth(var->hsync_len) +
1284 LCCR1_BegLnDel(var->left_margin) +
1285 LCCR1_EndLnDel(var->right_margin);
1286
1287 /*
1288 * If we have a dual scan LCD, we need to halve
1289 * the YRES parameter.
1290 */
1291 lines_per_panel = var->yres;
1292 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1293 lines_per_panel /= 2;
1294
1295 fbi->reg_lccr2 =
1296 LCCR2_DisHght(lines_per_panel) +
1297 LCCR2_VrtSnchWdth(var->vsync_len) +
1298 LCCR2_BegFrmDel(var->upper_margin) +
1299 LCCR2_EndFrmDel(var->lower_margin);
1300
1301 fbi->reg_lccr3 = fbi->lccr3 |
1302 (var->sync & FB_SYNC_HOR_HIGH_ACT ?
1303 LCCR3_HorSnchH : LCCR3_HorSnchL) |
1304 (var->sync & FB_SYNC_VERT_HIGH_ACT ?
1305 LCCR3_VrtSnchH : LCCR3_VrtSnchL);
1306
1307 if (pcd) {
1308 fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd);
1309 set_hsync_time(fbi, pcd);
1310 }
1311 }
1312
1313 /*
1314 * pxafb_activate_var():
1315 * Configures LCD Controller based on entries in var parameter.
1316 * Settings are only written to the controller if changes were made.
1317 */
1318 static int pxafb_activate_var(struct fb_var_screeninfo *var,
1319 struct pxafb_info *fbi)
1320 {
1321 u_long flags;
1322
1323 /* Update shadow copy atomically */
1324 local_irq_save(flags);
1325
1326 #ifdef CONFIG_FB_PXA_SMARTPANEL
1327 if (fbi->lccr0 & LCCR0_LCDT)
1328 setup_smart_timing(fbi, var);
1329 else
1330 #endif
1331 setup_parallel_timing(fbi, var);
1332
1333 setup_base_frame(fbi, 0);
1334
1335 fbi->reg_lccr0 = fbi->lccr0 |
1336 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
1337 LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
1338
1339 fbi->reg_lccr3 |= pxafb_var_to_lccr3(var);
1340
1341 fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
1342 fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
1343 local_irq_restore(flags);
1344
1345 /*
1346 * Only update the registers if the controller is enabled
1347 * and something has changed.
1348 */
1349 if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) ||
1350 (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
1351 (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
1352 (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
1353 (lcd_readl(fbi, LCCR4) != fbi->reg_lccr4) ||
1354 (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
1355 (lcd_readl(fbi, FDADR1) != fbi->fdadr[1]))
1356 pxafb_schedule_work(fbi, C_REENABLE);
1357
1358 return 0;
1359 }
1360
1361 /*
1362 * NOTE! The following functions are purely helpers for set_ctrlr_state.
1363 * Do not call them directly; set_ctrlr_state does the correct serialisation
1364 * to ensure that things happen in the right way 100% of time time.
1365 * -- rmk
1366 */
1367 static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
1368 {
1369 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
1370
1371 if (fbi->backlight_power)
1372 fbi->backlight_power(on);
1373 }
1374
1375 static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
1376 {
1377 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
1378
1379 if (fbi->lcd_power)
1380 fbi->lcd_power(on, &fbi->fb.var);
1381 }
1382
1383 static void pxafb_enable_controller(struct pxafb_info *fbi)
1384 {
1385 pr_debug("pxafb: Enabling LCD controller\n");
1386 pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
1387 pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
1388 pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
1389 pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
1390 pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
1391 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
1392
1393 /* enable LCD controller clock */
1394 clk_enable(fbi->clk);
1395
1396 if (fbi->lccr0 & LCCR0_LCDT)
1397 return;
1398
1399 /* Sequence from 11.7.10 */
1400 lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
1401 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1402 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1403 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1404 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1405
1406 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1407 lcd_writel(fbi, FDADR1, fbi->fdadr[1]);
1408 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1409 }
1410
1411 static void pxafb_disable_controller(struct pxafb_info *fbi)
1412 {
1413 uint32_t lccr0;
1414
1415 #ifdef CONFIG_FB_PXA_SMARTPANEL
1416 if (fbi->lccr0 & LCCR0_LCDT) {
1417 wait_for_completion_timeout(&fbi->refresh_done,
1418 200 * HZ / 1000);
1419 return;
1420 }
1421 #endif
1422
1423 /* Clear LCD Status Register */
1424 lcd_writel(fbi, LCSR, 0xffffffff);
1425
1426 lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM;
1427 lcd_writel(fbi, LCCR0, lccr0);
1428 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS);
1429
1430 wait_for_completion_timeout(&fbi->disable_done, 200 * HZ / 1000);
1431
1432 /* disable LCD controller clock */
1433 clk_disable(fbi->clk);
1434 }
1435
1436 /*
1437 * pxafb_handle_irq: Handle 'LCD DONE' interrupts.
1438 */
1439 static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
1440 {
1441 struct pxafb_info *fbi = dev_id;
1442 unsigned int lccr0, lcsr, lcsr1;
1443
1444 lcsr = lcd_readl(fbi, LCSR);
1445 if (lcsr & LCSR_LDD) {
1446 lccr0 = lcd_readl(fbi, LCCR0);
1447 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
1448 complete(&fbi->disable_done);
1449 }
1450
1451 #ifdef CONFIG_FB_PXA_SMARTPANEL
1452 if (lcsr & LCSR_CMD_INT)
1453 complete(&fbi->command_done);
1454 #endif
1455 lcd_writel(fbi, LCSR, lcsr);
1456
1457 #ifdef CONFIG_FB_PXA_OVERLAY
1458 lcsr1 = lcd_readl(fbi, LCSR1);
1459 if (lcsr1 & LCSR1_BS(1))
1460 complete(&fbi->overlay[0].branch_done);
1461
1462 if (lcsr1 & LCSR1_BS(2))
1463 complete(&fbi->overlay[1].branch_done);
1464
1465 lcd_writel(fbi, LCSR1, lcsr1);
1466 #endif
1467 return IRQ_HANDLED;
1468 }
1469
1470 /*
1471 * This function must be called from task context only, since it will
1472 * sleep when disabling the LCD controller, or if we get two contending
1473 * processes trying to alter state.
1474 */
1475 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
1476 {
1477 u_int old_state;
1478
1479 mutex_lock(&fbi->ctrlr_lock);
1480
1481 old_state = fbi->state;
1482
1483 /*
1484 * Hack around fbcon initialisation.
1485 */
1486 if (old_state == C_STARTUP && state == C_REENABLE)
1487 state = C_ENABLE;
1488
1489 switch (state) {
1490 case C_DISABLE_CLKCHANGE:
1491 /*
1492 * Disable controller for clock change. If the
1493 * controller is already disabled, then do nothing.
1494 */
1495 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
1496 fbi->state = state;
1497 /* TODO __pxafb_lcd_power(fbi, 0); */
1498 pxafb_disable_controller(fbi);
1499 }
1500 break;
1501
1502 case C_DISABLE_PM:
1503 case C_DISABLE:
1504 /*
1505 * Disable controller
1506 */
1507 if (old_state != C_DISABLE) {
1508 fbi->state = state;
1509 __pxafb_backlight_power(fbi, 0);
1510 __pxafb_lcd_power(fbi, 0);
1511 if (old_state != C_DISABLE_CLKCHANGE)
1512 pxafb_disable_controller(fbi);
1513 }
1514 break;
1515
1516 case C_ENABLE_CLKCHANGE:
1517 /*
1518 * Enable the controller after clock change. Only
1519 * do this if we were disabled for the clock change.
1520 */
1521 if (old_state == C_DISABLE_CLKCHANGE) {
1522 fbi->state = C_ENABLE;
1523 pxafb_enable_controller(fbi);
1524 /* TODO __pxafb_lcd_power(fbi, 1); */
1525 }
1526 break;
1527
1528 case C_REENABLE:
1529 /*
1530 * Re-enable the controller only if it was already
1531 * enabled. This is so we reprogram the control
1532 * registers.
1533 */
1534 if (old_state == C_ENABLE) {
1535 __pxafb_lcd_power(fbi, 0);
1536 pxafb_disable_controller(fbi);
1537 pxafb_enable_controller(fbi);
1538 __pxafb_lcd_power(fbi, 1);
1539 }
1540 break;
1541
1542 case C_ENABLE_PM:
1543 /*
1544 * Re-enable the controller after PM. This is not
1545 * perfect - think about the case where we were doing
1546 * a clock change, and we suspended half-way through.
1547 */
1548 if (old_state != C_DISABLE_PM)
1549 break;
1550 /* fall through */
1551
1552 case C_ENABLE:
1553 /*
1554 * Power up the LCD screen, enable controller, and
1555 * turn on the backlight.
1556 */
1557 if (old_state != C_ENABLE) {
1558 fbi->state = C_ENABLE;
1559 pxafb_enable_controller(fbi);
1560 __pxafb_lcd_power(fbi, 1);
1561 __pxafb_backlight_power(fbi, 1);
1562 }
1563 break;
1564 }
1565 mutex_unlock(&fbi->ctrlr_lock);
1566 }
1567
1568 /*
1569 * Our LCD controller task (which is called when we blank or unblank)
1570 * via keventd.
1571 */
1572 static void pxafb_task(struct work_struct *work)
1573 {
1574 struct pxafb_info *fbi =
1575 container_of(work, struct pxafb_info, task);
1576 u_int state = xchg(&fbi->task_state, -1);
1577
1578 set_ctrlr_state(fbi, state);
1579 }
1580
1581 #ifdef CONFIG_CPU_FREQ
1582 /*
1583 * CPU clock speed change handler. We need to adjust the LCD timing
1584 * parameters when the CPU clock is adjusted by the power management
1585 * subsystem.
1586 *
1587 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
1588 */
1589 static int
1590 pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
1591 {
1592 struct pxafb_info *fbi = TO_INF(nb, freq_transition);
1593 /* TODO struct cpufreq_freqs *f = data; */
1594 u_int pcd;
1595
1596 switch (val) {
1597 case CPUFREQ_PRECHANGE:
1598 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1599 break;
1600
1601 case CPUFREQ_POSTCHANGE:
1602 pcd = get_pcd(fbi, fbi->fb.var.pixclock);
1603 set_hsync_time(fbi, pcd);
1604 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
1605 LCCR3_PixClkDiv(pcd);
1606 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1607 break;
1608 }
1609 return 0;
1610 }
1611
1612 static int
1613 pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
1614 {
1615 struct pxafb_info *fbi = TO_INF(nb, freq_policy);
1616 struct fb_var_screeninfo *var = &fbi->fb.var;
1617 struct cpufreq_policy *policy = data;
1618
1619 switch (val) {
1620 case CPUFREQ_ADJUST:
1621 case CPUFREQ_INCOMPATIBLE:
1622 pr_debug("min dma period: %d ps, "
1623 "new clock %d kHz\n", pxafb_display_dma_period(var),
1624 policy->max);
1625 /* TODO: fill in min/max values */
1626 break;
1627 }
1628 return 0;
1629 }
1630 #endif
1631
1632 #ifdef CONFIG_PM
1633 /*
1634 * Power management hooks. Note that we won't be called from IRQ context,
1635 * unlike the blank functions above, so we may sleep.
1636 */
1637 static int pxafb_suspend(struct platform_device *dev, pm_message_t state)
1638 {
1639 struct pxafb_info *fbi = platform_get_drvdata(dev);
1640
1641 set_ctrlr_state(fbi, C_DISABLE_PM);
1642 return 0;
1643 }
1644
1645 static int pxafb_resume(struct platform_device *dev)
1646 {
1647 struct pxafb_info *fbi = platform_get_drvdata(dev);
1648
1649 set_ctrlr_state(fbi, C_ENABLE_PM);
1650 return 0;
1651 }
1652 #else
1653 #define pxafb_suspend NULL
1654 #define pxafb_resume NULL
1655 #endif
1656
1657 static int __devinit pxafb_init_video_memory(struct pxafb_info *fbi)
1658 {
1659 int size = PAGE_ALIGN(fbi->video_mem_size);
1660
1661 fbi->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
1662 if (fbi->video_mem == NULL)
1663 return -ENOMEM;
1664
1665 fbi->video_mem_phys = virt_to_phys(fbi->video_mem);
1666 fbi->video_mem_size = size;
1667
1668 fbi->fb.fix.smem_start = fbi->video_mem_phys;
1669 fbi->fb.fix.smem_len = fbi->video_mem_size;
1670 fbi->fb.screen_base = fbi->video_mem;
1671
1672 return fbi->video_mem ? 0 : -ENOMEM;
1673 }
1674
1675 static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1676 struct pxafb_mach_info *inf)
1677 {
1678 unsigned int lcd_conn = inf->lcd_conn;
1679 struct pxafb_mode_info *m;
1680 int i;
1681
1682 fbi->cmap_inverse = inf->cmap_inverse;
1683 fbi->cmap_static = inf->cmap_static;
1684 fbi->lccr4 = inf->lccr4;
1685
1686 switch (lcd_conn & LCD_TYPE_MASK) {
1687 case LCD_TYPE_MONO_STN:
1688 fbi->lccr0 = LCCR0_CMS;
1689 break;
1690 case LCD_TYPE_MONO_DSTN:
1691 fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
1692 break;
1693 case LCD_TYPE_COLOR_STN:
1694 fbi->lccr0 = 0;
1695 break;
1696 case LCD_TYPE_COLOR_DSTN:
1697 fbi->lccr0 = LCCR0_SDS;
1698 break;
1699 case LCD_TYPE_COLOR_TFT:
1700 fbi->lccr0 = LCCR0_PAS;
1701 break;
1702 case LCD_TYPE_SMART_PANEL:
1703 fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
1704 break;
1705 default:
1706 /* fall back to backward compatibility way */
1707 fbi->lccr0 = inf->lccr0;
1708 fbi->lccr3 = inf->lccr3;
1709 goto decode_mode;
1710 }
1711
1712 if (lcd_conn == LCD_MONO_STN_8BPP)
1713 fbi->lccr0 |= LCCR0_DPD;
1714
1715 fbi->lccr0 |= (lcd_conn & LCD_ALTERNATE_MAPPING) ? LCCR0_LDDALT : 0;
1716
1717 fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
1718 fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
1719 fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0;
1720
1721 decode_mode:
1722 pxafb_setmode(&fbi->fb.var, &inf->modes[0]);
1723
1724 /* decide video memory size as follows:
1725 * 1. default to mode of maximum resolution
1726 * 2. allow platform to override
1727 * 3. allow module parameter to override
1728 */
1729 for (i = 0, m = &inf->modes[0]; i < inf->num_modes; i++, m++)
1730 fbi->video_mem_size = max_t(size_t, fbi->video_mem_size,
1731 m->xres * m->yres * m->bpp / 8);
1732
1733 if (inf->video_mem_size > fbi->video_mem_size)
1734 fbi->video_mem_size = inf->video_mem_size;
1735
1736 if (video_mem_size > fbi->video_mem_size)
1737 fbi->video_mem_size = video_mem_size;
1738 }
1739
1740 static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
1741 {
1742 struct pxafb_info *fbi;
1743 void *addr;
1744 struct pxafb_mach_info *inf = dev->platform_data;
1745
1746 /* Alloc the pxafb_info and pseudo_palette in one step */
1747 fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1748 if (!fbi)
1749 return NULL;
1750
1751 memset(fbi, 0, sizeof(struct pxafb_info));
1752 fbi->dev = dev;
1753
1754 fbi->clk = clk_get(dev, NULL);
1755 if (IS_ERR(fbi->clk)) {
1756 kfree(fbi);
1757 return NULL;
1758 }
1759
1760 strcpy(fbi->fb.fix.id, PXA_NAME);
1761
1762 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1763 fbi->fb.fix.type_aux = 0;
1764 fbi->fb.fix.xpanstep = 0;
1765 fbi->fb.fix.ypanstep = 1;
1766 fbi->fb.fix.ywrapstep = 0;
1767 fbi->fb.fix.accel = FB_ACCEL_NONE;
1768
1769 fbi->fb.var.nonstd = 0;
1770 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1771 fbi->fb.var.height = -1;
1772 fbi->fb.var.width = -1;
1773 fbi->fb.var.accel_flags = FB_ACCELF_TEXT;
1774 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1775
1776 fbi->fb.fbops = &pxafb_ops;
1777 fbi->fb.flags = FBINFO_DEFAULT;
1778 fbi->fb.node = -1;
1779
1780 addr = fbi;
1781 addr = addr + sizeof(struct pxafb_info);
1782 fbi->fb.pseudo_palette = addr;
1783
1784 fbi->state = C_STARTUP;
1785 fbi->task_state = (u_char)-1;
1786
1787 pxafb_decode_mach_info(fbi, inf);
1788
1789 init_waitqueue_head(&fbi->ctrlr_wait);
1790 INIT_WORK(&fbi->task, pxafb_task);
1791 mutex_init(&fbi->ctrlr_lock);
1792 init_completion(&fbi->disable_done);
1793
1794 return fbi;
1795 }
1796
1797 #ifdef CONFIG_FB_PXA_PARAMETERS
1798 static int __devinit parse_opt_mode(struct device *dev, const char *this_opt)
1799 {
1800 struct pxafb_mach_info *inf = dev->platform_data;
1801
1802 const char *name = this_opt+5;
1803 unsigned int namelen = strlen(name);
1804 int res_specified = 0, bpp_specified = 0;
1805 unsigned int xres = 0, yres = 0, bpp = 0;
1806 int yres_specified = 0;
1807 int i;
1808 for (i = namelen-1; i >= 0; i--) {
1809 switch (name[i]) {
1810 case '-':
1811 namelen = i;
1812 if (!bpp_specified && !yres_specified) {
1813 bpp = simple_strtoul(&name[i+1], NULL, 0);
1814 bpp_specified = 1;
1815 } else
1816 goto done;
1817 break;
1818 case 'x':
1819 if (!yres_specified) {
1820 yres = simple_strtoul(&name[i+1], NULL, 0);
1821 yres_specified = 1;
1822 } else
1823 goto done;
1824 break;
1825 case '0' ... '9':
1826 break;
1827 default:
1828 goto done;
1829 }
1830 }
1831 if (i < 0 && yres_specified) {
1832 xres = simple_strtoul(name, NULL, 0);
1833 res_specified = 1;
1834 }
1835 done:
1836 if (res_specified) {
1837 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1838 inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1839 }
1840 if (bpp_specified)
1841 switch (bpp) {
1842 case 1:
1843 case 2:
1844 case 4:
1845 case 8:
1846 case 16:
1847 inf->modes[0].bpp = bpp;
1848 dev_info(dev, "overriding bit depth: %d\n", bpp);
1849 break;
1850 default:
1851 dev_err(dev, "Depth %d is not valid\n", bpp);
1852 return -EINVAL;
1853 }
1854 return 0;
1855 }
1856
1857 static int __devinit parse_opt(struct device *dev, char *this_opt)
1858 {
1859 struct pxafb_mach_info *inf = dev->platform_data;
1860 struct pxafb_mode_info *mode = &inf->modes[0];
1861 char s[64];
1862
1863 s[0] = '\0';
1864
1865 if (!strncmp(this_opt, "vmem:", 5)) {
1866 video_mem_size = memparse(this_opt + 5, NULL);
1867 } else if (!strncmp(this_opt, "mode:", 5)) {
1868 return parse_opt_mode(dev, this_opt);
1869 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1870 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1871 sprintf(s, "pixclock: %ld\n", mode->pixclock);
1872 } else if (!strncmp(this_opt, "left:", 5)) {
1873 mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1874 sprintf(s, "left: %u\n", mode->left_margin);
1875 } else if (!strncmp(this_opt, "right:", 6)) {
1876 mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1877 sprintf(s, "right: %u\n", mode->right_margin);
1878 } else if (!strncmp(this_opt, "upper:", 6)) {
1879 mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1880 sprintf(s, "upper: %u\n", mode->upper_margin);
1881 } else if (!strncmp(this_opt, "lower:", 6)) {
1882 mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1883 sprintf(s, "lower: %u\n", mode->lower_margin);
1884 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1885 mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1886 sprintf(s, "hsynclen: %u\n", mode->hsync_len);
1887 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1888 mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1889 sprintf(s, "vsynclen: %u\n", mode->vsync_len);
1890 } else if (!strncmp(this_opt, "hsync:", 6)) {
1891 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1892 sprintf(s, "hsync: Active Low\n");
1893 mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1894 } else {
1895 sprintf(s, "hsync: Active High\n");
1896 mode->sync |= FB_SYNC_HOR_HIGH_ACT;
1897 }
1898 } else if (!strncmp(this_opt, "vsync:", 6)) {
1899 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1900 sprintf(s, "vsync: Active Low\n");
1901 mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1902 } else {
1903 sprintf(s, "vsync: Active High\n");
1904 mode->sync |= FB_SYNC_VERT_HIGH_ACT;
1905 }
1906 } else if (!strncmp(this_opt, "dpc:", 4)) {
1907 if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1908 sprintf(s, "double pixel clock: false\n");
1909 inf->lccr3 &= ~LCCR3_DPC;
1910 } else {
1911 sprintf(s, "double pixel clock: true\n");
1912 inf->lccr3 |= LCCR3_DPC;
1913 }
1914 } else if (!strncmp(this_opt, "outputen:", 9)) {
1915 if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1916 sprintf(s, "output enable: active low\n");
1917 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1918 } else {
1919 sprintf(s, "output enable: active high\n");
1920 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1921 }
1922 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1923 if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1924 sprintf(s, "pixel clock polarity: falling edge\n");
1925 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1926 } else {
1927 sprintf(s, "pixel clock polarity: rising edge\n");
1928 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1929 }
1930 } else if (!strncmp(this_opt, "color", 5)) {
1931 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1932 } else if (!strncmp(this_opt, "mono", 4)) {
1933 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1934 } else if (!strncmp(this_opt, "active", 6)) {
1935 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1936 } else if (!strncmp(this_opt, "passive", 7)) {
1937 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1938 } else if (!strncmp(this_opt, "single", 6)) {
1939 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1940 } else if (!strncmp(this_opt, "dual", 4)) {
1941 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1942 } else if (!strncmp(this_opt, "4pix", 4)) {
1943 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1944 } else if (!strncmp(this_opt, "8pix", 4)) {
1945 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1946 } else {
1947 dev_err(dev, "unknown option: %s\n", this_opt);
1948 return -EINVAL;
1949 }
1950
1951 if (s[0] != '\0')
1952 dev_info(dev, "override %s", s);
1953
1954 return 0;
1955 }
1956
1957 static int __devinit pxafb_parse_options(struct device *dev, char *options)
1958 {
1959 char *this_opt;
1960 int ret;
1961
1962 if (!options || !*options)
1963 return 0;
1964
1965 dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1966
1967 /* could be made table driven or similar?... */
1968 while ((this_opt = strsep(&options, ",")) != NULL) {
1969 ret = parse_opt(dev, this_opt);
1970 if (ret)
1971 return ret;
1972 }
1973 return 0;
1974 }
1975
1976 static char g_options[256] __devinitdata = "";
1977
1978 #ifndef MODULE
1979 static int __init pxafb_setup_options(void)
1980 {
1981 char *options = NULL;
1982
1983 if (fb_get_options("pxafb", &options))
1984 return -ENODEV;
1985
1986 if (options)
1987 strlcpy(g_options, options, sizeof(g_options));
1988
1989 return 0;
1990 }
1991 #else
1992 #define pxafb_setup_options() (0)
1993
1994 module_param_string(options, g_options, sizeof(g_options), 0);
1995 MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1996 #endif
1997
1998 #else
1999 #define pxafb_parse_options(...) (0)
2000 #define pxafb_setup_options() (0)
2001 #endif
2002
2003 #ifdef DEBUG_VAR
2004 /* Check for various illegal bit-combinations. Currently only
2005 * a warning is given. */
2006 static void __devinit pxafb_check_options(struct device *dev,
2007 struct pxafb_mach_info *inf)
2008 {
2009 if (inf->lcd_conn)
2010 return;
2011
2012 if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
2013 dev_warn(dev, "machine LCCR0 setting contains "
2014 "illegal bits: %08x\n",
2015 inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
2016 if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
2017 dev_warn(dev, "machine LCCR3 setting contains "
2018 "illegal bits: %08x\n",
2019 inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
2020 if (inf->lccr0 & LCCR0_DPD &&
2021 ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
2022 (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
2023 (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
2024 dev_warn(dev, "Double Pixel Data (DPD) mode is "
2025 "only valid in passive mono"
2026 " single panel mode\n");
2027 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
2028 (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
2029 dev_warn(dev, "Dual panel only valid in passive mode\n");
2030 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
2031 (inf->modes->upper_margin || inf->modes->lower_margin))
2032 dev_warn(dev, "Upper and lower margins must be 0 in "
2033 "passive mode\n");
2034 }
2035 #else
2036 #define pxafb_check_options(...) do {} while (0)
2037 #endif
2038
2039 static int __devinit pxafb_probe(struct platform_device *dev)
2040 {
2041 struct pxafb_info *fbi;
2042 struct pxafb_mach_info *inf;
2043 struct resource *r;
2044 int irq, ret;
2045
2046 dev_dbg(&dev->dev, "pxafb_probe\n");
2047
2048 inf = dev->dev.platform_data;
2049 ret = -ENOMEM;
2050 fbi = NULL;
2051 if (!inf)
2052 goto failed;
2053
2054 ret = pxafb_parse_options(&dev->dev, g_options);
2055 if (ret < 0)
2056 goto failed;
2057
2058 pxafb_check_options(&dev->dev, inf);
2059
2060 dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
2061 inf->modes->xres,
2062 inf->modes->yres,
2063 inf->modes->bpp);
2064 if (inf->modes->xres == 0 ||
2065 inf->modes->yres == 0 ||
2066 inf->modes->bpp == 0) {
2067 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
2068 ret = -EINVAL;
2069 goto failed;
2070 }
2071
2072 fbi = pxafb_init_fbinfo(&dev->dev);
2073 if (!fbi) {
2074 /* only reason for pxafb_init_fbinfo to fail is kmalloc */
2075 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
2076 ret = -ENOMEM;
2077 goto failed;
2078 }
2079
2080 fbi->backlight_power = inf->pxafb_backlight_power;
2081 fbi->lcd_power = inf->pxafb_lcd_power;
2082
2083 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
2084 if (r == NULL) {
2085 dev_err(&dev->dev, "no I/O memory resource defined\n");
2086 ret = -ENODEV;
2087 goto failed_fbi;
2088 }
2089
2090 r = request_mem_region(r->start, r->end - r->start + 1, dev->name);
2091 if (r == NULL) {
2092 dev_err(&dev->dev, "failed to request I/O memory\n");
2093 ret = -EBUSY;
2094 goto failed_fbi;
2095 }
2096
2097 fbi->mmio_base = ioremap(r->start, r->end - r->start + 1);
2098 if (fbi->mmio_base == NULL) {
2099 dev_err(&dev->dev, "failed to map I/O memory\n");
2100 ret = -EBUSY;
2101 goto failed_free_res;
2102 }
2103
2104 fbi->dma_buff_size = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
2105 fbi->dma_buff = dma_alloc_coherent(fbi->dev, fbi->dma_buff_size,
2106 &fbi->dma_buff_phys, GFP_KERNEL);
2107 if (fbi->dma_buff == NULL) {
2108 dev_err(&dev->dev, "failed to allocate memory for DMA\n");
2109 ret = -ENOMEM;
2110 goto failed_free_io;
2111 }
2112
2113 ret = pxafb_init_video_memory(fbi);
2114 if (ret) {
2115 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
2116 ret = -ENOMEM;
2117 goto failed_free_dma;
2118 }
2119
2120 irq = platform_get_irq(dev, 0);
2121 if (irq < 0) {
2122 dev_err(&dev->dev, "no IRQ defined\n");
2123 ret = -ENODEV;
2124 goto failed_free_mem;
2125 }
2126
2127 ret = request_irq(irq, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi);
2128 if (ret) {
2129 dev_err(&dev->dev, "request_irq failed: %d\n", ret);
2130 ret = -EBUSY;
2131 goto failed_free_mem;
2132 }
2133
2134 ret = pxafb_smart_init(fbi);
2135 if (ret) {
2136 dev_err(&dev->dev, "failed to initialize smartpanel\n");
2137 goto failed_free_irq;
2138 }
2139
2140 /*
2141 * This makes sure that our colour bitfield
2142 * descriptors are correctly initialised.
2143 */
2144 ret = pxafb_check_var(&fbi->fb.var, &fbi->fb);
2145 if (ret) {
2146 dev_err(&dev->dev, "failed to get suitable mode\n");
2147 goto failed_free_irq;
2148 }
2149
2150 ret = pxafb_set_par(&fbi->fb);
2151 if (ret) {
2152 dev_err(&dev->dev, "Failed to set parameters\n");
2153 goto failed_free_irq;
2154 }
2155
2156 platform_set_drvdata(dev, fbi);
2157
2158 ret = register_framebuffer(&fbi->fb);
2159 if (ret < 0) {
2160 dev_err(&dev->dev,
2161 "Failed to register framebuffer device: %d\n", ret);
2162 goto failed_free_cmap;
2163 }
2164
2165 pxafb_overlay_init(fbi);
2166
2167 #ifdef CONFIG_CPU_FREQ
2168 fbi->freq_transition.notifier_call = pxafb_freq_transition;
2169 fbi->freq_policy.notifier_call = pxafb_freq_policy;
2170 cpufreq_register_notifier(&fbi->freq_transition,
2171 CPUFREQ_TRANSITION_NOTIFIER);
2172 cpufreq_register_notifier(&fbi->freq_policy,
2173 CPUFREQ_POLICY_NOTIFIER);
2174 #endif
2175
2176 /*
2177 * Ok, now enable the LCD controller
2178 */
2179 set_ctrlr_state(fbi, C_ENABLE);
2180
2181 return 0;
2182
2183 failed_free_cmap:
2184 if (fbi->fb.cmap.len)
2185 fb_dealloc_cmap(&fbi->fb.cmap);
2186 failed_free_irq:
2187 free_irq(irq, fbi);
2188 failed_free_mem:
2189 free_pages_exact(fbi->video_mem, fbi->video_mem_size);
2190 failed_free_dma:
2191 dma_free_coherent(&dev->dev, fbi->dma_buff_size,
2192 fbi->dma_buff, fbi->dma_buff_phys);
2193 failed_free_io:
2194 iounmap(fbi->mmio_base);
2195 failed_free_res:
2196 release_mem_region(r->start, r->end - r->start + 1);
2197 failed_fbi:
2198 clk_put(fbi->clk);
2199 platform_set_drvdata(dev, NULL);
2200 kfree(fbi);
2201 failed:
2202 return ret;
2203 }
2204
2205 static int __devexit pxafb_remove(struct platform_device *dev)
2206 {
2207 struct pxafb_info *fbi = platform_get_drvdata(dev);
2208 struct resource *r;
2209 int irq;
2210 struct fb_info *info;
2211
2212 if (!fbi)
2213 return 0;
2214
2215 info = &fbi->fb;
2216
2217 pxafb_overlay_exit(fbi);
2218 unregister_framebuffer(info);
2219
2220 pxafb_disable_controller(fbi);
2221
2222 if (fbi->fb.cmap.len)
2223 fb_dealloc_cmap(&fbi->fb.cmap);
2224
2225 irq = platform_get_irq(dev, 0);
2226 free_irq(irq, fbi);
2227
2228 free_pages_exact(fbi->video_mem, fbi->video_mem_size);
2229
2230 dma_free_writecombine(&dev->dev, fbi->dma_buff_size,
2231 fbi->dma_buff, fbi->dma_buff_phys);
2232
2233 iounmap(fbi->mmio_base);
2234
2235 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
2236 release_mem_region(r->start, r->end - r->start + 1);
2237
2238 clk_put(fbi->clk);
2239 kfree(fbi);
2240
2241 return 0;
2242 }
2243
2244 static struct platform_driver pxafb_driver = {
2245 .probe = pxafb_probe,
2246 .remove = __devexit_p(pxafb_remove),
2247 .suspend = pxafb_suspend,
2248 .resume = pxafb_resume,
2249 .driver = {
2250 .owner = THIS_MODULE,
2251 .name = "pxa2xx-fb",
2252 },
2253 };
2254
2255 static int __init pxafb_init(void)
2256 {
2257 if (pxafb_setup_options())
2258 return -EINVAL;
2259
2260 return platform_driver_register(&pxafb_driver);
2261 }
2262
2263 static void __exit pxafb_exit(void)
2264 {
2265 platform_driver_unregister(&pxafb_driver);
2266 }
2267
2268 module_init(pxafb_init);
2269 module_exit(pxafb_exit);
2270
2271 MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
2272 MODULE_LICENSE("GPL");
Support for the Chinese Samsung S3C2440 based development boards