2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmar.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/pgalloc.h>
40 #include <asm/proto.h>
41 #include <asm/timex.h>
43 #include <asm/i8259.h>
46 #include <mach_apic.h>
48 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
49 static int disable_apic_timer __cpuinitdata
;
50 static int apic_calibrate_pmtmr __initdata
;
55 /* x2apic enabled before OS handover */
56 int x2apic_preenabled
;
58 /* Local APIC timer works in C2 */
59 int local_apic_timer_c2_ok
;
60 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
63 * Debug level, exported for io_apic.c
65 unsigned int apic_verbosity
;
67 /* Have we found an MP table */
70 static struct resource lapic_resource
= {
72 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
75 static unsigned int calibration_result
;
77 static int lapic_next_event(unsigned long delta
,
78 struct clock_event_device
*evt
);
79 static void lapic_timer_setup(enum clock_event_mode mode
,
80 struct clock_event_device
*evt
);
81 static void lapic_timer_broadcast(cpumask_t mask
);
82 static void apic_pm_activate(void);
85 * The local apic timer can be used for any function which is CPU local.
87 static struct clock_event_device lapic_clockevent
= {
89 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
90 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
92 .set_mode
= lapic_timer_setup
,
93 .set_next_event
= lapic_next_event
,
94 .broadcast
= lapic_timer_broadcast
,
98 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
100 static unsigned long apic_phys
;
102 unsigned long mp_lapic_addr
;
104 unsigned int __cpuinitdata maxcpus
= NR_CPUS
;
106 * Get the LAPIC version
108 static inline int lapic_get_version(void)
110 return GET_APIC_VERSION(apic_read(APIC_LVR
));
114 * Check, if the APIC is integrated or a separate chip
116 static inline int lapic_is_integrated(void)
121 return APIC_INTEGRATED(lapic_get_version());
126 * Check, whether this is a modern or a first generation APIC
128 static int modern_apic(void)
130 /* AMD systems use old APIC versions, so check the CPU */
131 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
132 boot_cpu_data
.x86
>= 0xf)
134 return lapic_get_version() >= 0x14;
138 * Paravirt kernels also might be using these below ops. So we still
139 * use generic apic_read()/apic_write(), which might be pointing to different
140 * ops in PARAVIRT case.
142 void xapic_wait_icr_idle(void)
144 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
148 u32
safe_xapic_wait_icr_idle(void)
155 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
159 } while (timeout
++ < 1000);
164 void xapic_icr_write(u32 low
, u32 id
)
166 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
167 apic_write(APIC_ICR
, low
);
170 u64
xapic_icr_read(void)
174 icr2
= apic_read(APIC_ICR2
);
175 icr1
= apic_read(APIC_ICR
);
177 return icr1
| ((u64
)icr2
<< 32);
180 static struct apic_ops xapic_ops
= {
181 .read
= native_apic_mem_read
,
182 .write
= native_apic_mem_write
,
183 .icr_read
= xapic_icr_read
,
184 .icr_write
= xapic_icr_write
,
185 .wait_icr_idle
= xapic_wait_icr_idle
,
186 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
189 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
190 EXPORT_SYMBOL_GPL(apic_ops
);
192 static void x2apic_wait_icr_idle(void)
194 /* no need to wait for icr idle in x2apic */
198 static u32
safe_x2apic_wait_icr_idle(void)
200 /* no need to wait for icr idle in x2apic */
204 void x2apic_icr_write(u32 low
, u32 id
)
206 wrmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), ((__u64
) id
) << 32 | low
);
209 u64
x2apic_icr_read(void)
213 rdmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), val
);
217 static struct apic_ops x2apic_ops
= {
218 .read
= native_apic_msr_read
,
219 .write
= native_apic_msr_write
,
220 .icr_read
= x2apic_icr_read
,
221 .icr_write
= x2apic_icr_write
,
222 .wait_icr_idle
= x2apic_wait_icr_idle
,
223 .safe_wait_icr_idle
= safe_x2apic_wait_icr_idle
,
227 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
229 void __cpuinit
enable_NMI_through_LVT0(void)
233 /* unmask and set to NMI */
236 /* Level triggered for 82489DX (32bit mode) */
237 if (!lapic_is_integrated())
238 v
|= APIC_LVT_LEVEL_TRIGGER
;
240 apic_write(APIC_LVT0
, v
);
244 * lapic_get_maxlvt - get the maximum number of local vector table entries
246 int lapic_get_maxlvt(void)
250 v
= apic_read(APIC_LVR
);
252 * - we always have APIC integrated on 64bit mode
253 * - 82489DXs do not report # of LVT entries
255 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
262 /* Clock divisor is set to 1 */
263 #define APIC_DIVISOR 1
266 * This function sets up the local APIC timer, with a timeout of
267 * 'clocks' APIC bus clock. During calibration we actually call
268 * this function twice on the boot CPU, once with a bogus timeout
269 * value, second time for real. The other (noncalibrating) CPUs
270 * call this function only once, with the real, calibrated value.
272 * We do reads before writes even if unnecessary, to get around the
273 * P5 APIC double write bug.
275 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
277 unsigned int lvtt_value
, tmp_value
;
279 lvtt_value
= LOCAL_TIMER_VECTOR
;
281 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
282 if (!lapic_is_integrated())
283 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
286 lvtt_value
|= APIC_LVT_MASKED
;
288 apic_write(APIC_LVTT
, lvtt_value
);
293 tmp_value
= apic_read(APIC_TDCR
);
294 apic_write(APIC_TDCR
, (tmp_value
295 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
299 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
303 * Setup extended LVT, AMD specific (K8, family 10h)
305 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
306 * MCE interrupts are supported. Thus MCE offset must be set to 0.
309 #define APIC_EILVT_LVTOFF_MCE 0
310 #define APIC_EILVT_LVTOFF_IBS 1
312 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
314 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
315 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
320 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
322 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
323 return APIC_EILVT_LVTOFF_MCE
;
326 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
328 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
329 return APIC_EILVT_LVTOFF_IBS
;
333 * Program the next event, relative to now
335 static int lapic_next_event(unsigned long delta
,
336 struct clock_event_device
*evt
)
338 apic_write(APIC_TMICT
, delta
);
343 * Setup the lapic timer in periodic or oneshot mode
345 static void lapic_timer_setup(enum clock_event_mode mode
,
346 struct clock_event_device
*evt
)
351 /* Lapic used as dummy for broadcast ? */
352 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
355 local_irq_save(flags
);
358 case CLOCK_EVT_MODE_PERIODIC
:
359 case CLOCK_EVT_MODE_ONESHOT
:
360 __setup_APIC_LVTT(calibration_result
,
361 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
363 case CLOCK_EVT_MODE_UNUSED
:
364 case CLOCK_EVT_MODE_SHUTDOWN
:
365 v
= apic_read(APIC_LVTT
);
366 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
367 apic_write(APIC_LVTT
, v
);
369 case CLOCK_EVT_MODE_RESUME
:
370 /* Nothing to do here */
374 local_irq_restore(flags
);
378 * Local APIC timer broadcast function
380 static void lapic_timer_broadcast(cpumask_t mask
)
383 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
388 * Setup the local APIC timer for this CPU. Copy the initilized values
389 * of the boot CPU and register the clock event in the framework.
391 static void setup_APIC_timer(void)
393 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
395 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
396 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
398 clockevents_register_device(levt
);
402 * In this function we calibrate APIC bus clocks to the external
403 * timer. Unfortunately we cannot use jiffies and the timer irq
404 * to calibrate, since some later bootup code depends on getting
405 * the first irq? Ugh.
407 * We want to do the calibration only once since we
408 * want to have local timer irqs syncron. CPUs connected
409 * by the same APIC bus have the very same bus frequency.
410 * And we want to have irqs off anyways, no accidental
414 #define TICK_COUNT 100000000
416 static int __init
calibrate_APIC_clock(void)
418 unsigned apic
, apic_start
;
419 unsigned long tsc
, tsc_start
;
425 * Put whatever arbitrary (but long enough) timeout
426 * value into the APIC clock, we just want to get the
427 * counter running for calibration.
429 * No interrupt enable !
431 __setup_APIC_LVTT(250000000, 0, 0);
433 apic_start
= apic_read(APIC_TMCCT
);
434 #ifdef CONFIG_X86_PM_TIMER
435 if (apic_calibrate_pmtmr
&& pmtmr_ioport
) {
436 pmtimer_wait(5000); /* 5ms wait */
437 apic
= apic_read(APIC_TMCCT
);
438 result
= (apic_start
- apic
) * 1000L / 5;
445 apic
= apic_read(APIC_TMCCT
);
447 } while ((tsc
- tsc_start
) < TICK_COUNT
&&
448 (apic_start
- apic
) < TICK_COUNT
);
450 result
= (apic_start
- apic
) * 1000L * tsc_khz
/
456 printk(KERN_DEBUG
"APIC timer calibration result %d\n", result
);
458 printk(KERN_INFO
"Detected %d.%03d MHz APIC timer.\n",
459 result
/ 1000 / 1000, result
/ 1000 % 1000);
461 /* Calculate the scaled math multiplication factor */
462 lapic_clockevent
.mult
= div_sc(result
, NSEC_PER_SEC
,
463 lapic_clockevent
.shift
);
464 lapic_clockevent
.max_delta_ns
=
465 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
466 lapic_clockevent
.min_delta_ns
=
467 clockevent_delta2ns(0xF, &lapic_clockevent
);
469 calibration_result
= (result
* APIC_DIVISOR
) / HZ
;
472 * Do a sanity check on the APIC calibration result
474 if (calibration_result
< (1000000 / HZ
)) {
476 "APIC frequency too slow, disabling apic timer\n");
484 * Setup the boot APIC
486 * Calibrate and verify the result.
488 void __init
setup_boot_APIC_clock(void)
491 * The local apic timer can be disabled via the kernel
492 * commandline or from the CPU detection code. Register the lapic
493 * timer as a dummy clock event source on SMP systems, so the
494 * broadcast mechanism is used. On UP systems simply ignore it.
496 if (disable_apic_timer
) {
497 printk(KERN_INFO
"Disabling APIC timer\n");
498 /* No broadcast on UP ! */
499 if (num_possible_cpus() > 1) {
500 lapic_clockevent
.mult
= 1;
506 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
507 "calibrating APIC timer ...\n");
509 if (calibrate_APIC_clock()) {
510 /* No broadcast on UP ! */
511 if (num_possible_cpus() > 1)
517 * If nmi_watchdog is set to IO_APIC, we need the
518 * PIT/HPET going. Otherwise register lapic as a dummy
521 if (nmi_watchdog
!= NMI_IO_APIC
)
522 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
524 printk(KERN_WARNING
"APIC timer registered as dummy,"
525 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
527 /* Setup the lapic or request the broadcast */
531 void __cpuinit
setup_secondary_APIC_clock(void)
537 * The guts of the apic timer interrupt
539 static void local_apic_timer_interrupt(void)
541 int cpu
= smp_processor_id();
542 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
545 * Normally we should not be here till LAPIC has been initialized but
546 * in some cases like kdump, its possible that there is a pending LAPIC
547 * timer interrupt from previous kernel's context and is delivered in
548 * new kernel the moment interrupts are enabled.
550 * Interrupts are enabled early and LAPIC is setup much later, hence
551 * its possible that when we get here evt->event_handler is NULL.
552 * Check for event_handler being NULL and discard the interrupt as
555 if (!evt
->event_handler
) {
557 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
559 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
564 * the NMI deadlock-detector uses this.
566 add_pda(apic_timer_irqs
, 1);
568 evt
->event_handler(evt
);
572 * Local APIC timer interrupt. This is the most natural way for doing
573 * local interrupts, but local timer interrupts can be emulated by
574 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
576 * [ if a single-CPU system runs an SMP kernel then we call the local
577 * interrupt as well. Thus we cannot inline the local irq ... ]
579 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
581 struct pt_regs
*old_regs
= set_irq_regs(regs
);
584 * NOTE! We'd better ACK the irq immediately,
585 * because timer handling can be slow.
589 * update_process_times() expects us to have done irq_enter().
590 * Besides, if we don't timer interrupts ignore the global
591 * interrupt lock, which is the WrongThing (tm) to do.
595 local_apic_timer_interrupt();
598 set_irq_regs(old_regs
);
601 int setup_profiling_timer(unsigned int multiplier
)
608 * Local APIC start and shutdown
612 * clear_local_APIC - shutdown the local APIC
614 * This is called, when a CPU is disabled and before rebooting, so the state of
615 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
616 * leftovers during boot.
618 void clear_local_APIC(void)
623 /* APIC hasn't been mapped yet */
627 maxlvt
= lapic_get_maxlvt();
629 * Masking an LVT entry can trigger a local APIC error
630 * if the vector is zero. Mask LVTERR first to prevent this.
633 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
634 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
637 * Careful: we have to set masks only first to deassert
638 * any level-triggered sources.
640 v
= apic_read(APIC_LVTT
);
641 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
642 v
= apic_read(APIC_LVT0
);
643 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
644 v
= apic_read(APIC_LVT1
);
645 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
647 v
= apic_read(APIC_LVTPC
);
648 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
651 /* lets not touch this if we didn't frob it */
652 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
654 v
= apic_read(APIC_LVTTHMR
);
655 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
659 * Clean APIC state for other OSs:
661 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
662 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
663 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
665 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
667 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
669 /* Integrated APIC (!82489DX) ? */
670 if (lapic_is_integrated()) {
672 /* Clear ESR due to Pentium errata 3AP and 11AP */
673 apic_write(APIC_ESR
, 0);
679 * disable_local_APIC - clear and disable the local APIC
681 void disable_local_APIC(void)
688 * Disable APIC (implies clearing of registers
691 value
= apic_read(APIC_SPIV
);
692 value
&= ~APIC_SPIV_APIC_ENABLED
;
693 apic_write(APIC_SPIV
, value
);
696 void lapic_shutdown(void)
703 local_irq_save(flags
);
705 disable_local_APIC();
707 local_irq_restore(flags
);
711 * This is to verify that we're looking at a real local APIC.
712 * Check these against your board if the CPUs aren't getting
713 * started for no apparent reason.
715 int __init
verify_local_APIC(void)
717 unsigned int reg0
, reg1
;
720 * The version register is read-only in a real APIC.
722 reg0
= apic_read(APIC_LVR
);
723 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
724 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
725 reg1
= apic_read(APIC_LVR
);
726 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
729 * The two version reads above should print the same
730 * numbers. If the second one is different, then we
731 * poke at a non-APIC.
737 * Check if the version looks reasonably.
739 reg1
= GET_APIC_VERSION(reg0
);
740 if (reg1
== 0x00 || reg1
== 0xff)
742 reg1
= lapic_get_maxlvt();
743 if (reg1
< 0x02 || reg1
== 0xff)
747 * The ID register is read/write in a real APIC.
749 reg0
= apic_read(APIC_ID
);
750 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
751 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
752 reg1
= apic_read(APIC_ID
);
753 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
754 apic_write(APIC_ID
, reg0
);
755 if (reg1
!= (reg0
^ APIC_ID_MASK
))
759 * The next two are just to see if we have sane values.
760 * They're only really relevant if we're in Virtual Wire
761 * compatibility mode, but most boxes are anymore.
763 reg0
= apic_read(APIC_LVT0
);
764 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
765 reg1
= apic_read(APIC_LVT1
);
766 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
772 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
774 void __init
sync_Arb_IDs(void)
777 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
780 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
786 apic_wait_icr_idle();
788 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
789 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
790 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
794 * An initial setup of the virtual wire mode.
796 void __init
init_bsp_APIC(void)
801 * Don't do the setup now if we have a SMP BIOS as the
802 * through-I/O-APIC virtual wire mode might be active.
804 if (smp_found_config
|| !cpu_has_apic
)
808 * Do not trust the local APIC being empty at bootup.
815 value
= apic_read(APIC_SPIV
);
816 value
&= ~APIC_VECTOR_MASK
;
817 value
|= APIC_SPIV_APIC_ENABLED
;
820 /* This bit is reserved on P4/Xeon and should be cleared */
821 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
822 (boot_cpu_data
.x86
== 15))
823 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
826 value
|= APIC_SPIV_FOCUS_DISABLED
;
827 value
|= SPURIOUS_APIC_VECTOR
;
828 apic_write(APIC_SPIV
, value
);
831 * Set up the virtual wire mode.
833 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
835 if (!lapic_is_integrated()) /* 82489DX */
836 value
|= APIC_LVT_LEVEL_TRIGGER
;
837 apic_write(APIC_LVT1
, value
);
841 * setup_local_APIC - setup the local APIC
843 void __cpuinit
setup_local_APIC(void)
849 value
= apic_read(APIC_LVR
);
851 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR
& 0x0f) != 0x0f);
854 * Double-check whether this APIC is really registered.
855 * This is meaningless in clustered apic mode, so we skip it.
857 if (!apic_id_registered())
861 * Intel recommends to set DFR, LDR and TPR before enabling
862 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
863 * document number 292116). So here it goes...
868 * Set Task Priority to 'accept all'. We never change this
871 value
= apic_read(APIC_TASKPRI
);
872 value
&= ~APIC_TPRI_MASK
;
873 apic_write(APIC_TASKPRI
, value
);
876 * After a crash, we no longer service the interrupts and a pending
877 * interrupt from previous kernel might still have ISR bit set.
879 * Most probably by now CPU has serviced that pending interrupt and
880 * it might not have done the ack_APIC_irq() because it thought,
881 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
882 * does not clear the ISR bit and cpu thinks it has already serivced
883 * the interrupt. Hence a vector might get locked. It was noticed
884 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
886 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
887 value
= apic_read(APIC_ISR
+ i
*0x10);
888 for (j
= 31; j
>= 0; j
--) {
895 * Now that we are all set up, enable the APIC
897 value
= apic_read(APIC_SPIV
);
898 value
&= ~APIC_VECTOR_MASK
;
902 value
|= APIC_SPIV_APIC_ENABLED
;
904 /* We always use processor focus */
907 * Set spurious IRQ vector
909 value
|= SPURIOUS_APIC_VECTOR
;
910 apic_write(APIC_SPIV
, value
);
915 * set up through-local-APIC on the BP's LINT0. This is not
916 * strictly necessary in pure symmetric-IO mode, but sometimes
917 * we delegate interrupts to the 8259A.
920 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
922 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
923 if (!smp_processor_id() && !value
) {
924 value
= APIC_DM_EXTINT
;
925 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
928 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
929 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
932 apic_write(APIC_LVT0
, value
);
935 * only the BP should see the LINT1 NMI signal, obviously.
937 if (!smp_processor_id())
940 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
941 apic_write(APIC_LVT1
, value
);
945 static void __cpuinit
lapic_setup_esr(void)
947 unsigned maxlvt
= lapic_get_maxlvt();
949 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
);
951 * spec says clear errors after enabling vector.
954 apic_write(APIC_ESR
, 0);
957 void __cpuinit
end_local_APIC_setup(void)
960 setup_apic_nmi_watchdog(NULL
);
964 void check_x2apic(void)
968 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
970 if (msr
& X2APIC_ENABLE
) {
971 printk("x2apic enabled by BIOS, switching to x2apic ops\n");
972 x2apic_preenabled
= x2apic
= 1;
973 apic_ops
= &x2apic_ops
;
977 void enable_x2apic(void)
981 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
982 if (!(msr
& X2APIC_ENABLE
)) {
983 printk("Enabling x2apic\n");
984 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
988 void enable_IR_x2apic(void)
990 #ifdef CONFIG_INTR_REMAP
997 if (!x2apic_preenabled
&& disable_x2apic
) {
999 "Skipped enabling x2apic and Interrupt-remapping "
1000 "because of nox2apic\n");
1004 if (x2apic_preenabled
&& disable_x2apic
)
1005 panic("Bios already enabled x2apic, can't enforce nox2apic");
1007 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1009 "Skipped enabling x2apic and Interrupt-remapping "
1010 "because of skipping io-apic setup\n");
1014 ret
= dmar_table_init();
1017 "dmar_table_init() failed with %d:\n", ret
);
1019 if (x2apic_preenabled
)
1020 panic("x2apic enabled by bios. But IR enabling failed");
1023 "Not enabling x2apic,Intr-remapping\n");
1027 local_irq_save(flags
);
1029 save_mask_IO_APIC_setup();
1031 ret
= enable_intr_remapping(1);
1033 if (ret
&& x2apic_preenabled
) {
1034 local_irq_restore(flags
);
1035 panic("x2apic enabled by bios. But IR enabling failed");
1043 apic_ops
= &x2apic_ops
;
1049 * IR enabling failed
1051 restore_IO_APIC_setup();
1053 reinit_intr_remapped_IO_APIC(x2apic_preenabled
);
1056 local_irq_restore(flags
);
1059 if (!x2apic_preenabled
)
1061 "Enabled x2apic and interrupt-remapping\n");
1064 "Enabled Interrupt-remapping\n");
1067 "Failed to enable Interrupt-remapping and x2apic\n");
1069 if (!cpu_has_x2apic
)
1072 if (x2apic_preenabled
)
1073 panic("x2apic enabled prior OS handover,"
1074 " enable CONFIG_INTR_REMAP");
1076 printk(KERN_INFO
"Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1084 * Detect and enable local APICs on non-SMP boards.
1085 * Original code written by Keir Fraser.
1086 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1087 * not correctly set up (usually the APIC timer won't work etc.)
1089 static int __init
detect_init_APIC(void)
1091 if (!cpu_has_apic
) {
1092 printk(KERN_INFO
"No local APIC present\n");
1096 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1097 boot_cpu_physical_apicid
= 0;
1101 void __init
early_init_lapic_mapping(void)
1103 unsigned long phys_addr
;
1106 * If no local APIC can be found then go out
1107 * : it means there is no mpatable and MADT
1109 if (!smp_found_config
)
1112 phys_addr
= mp_lapic_addr
;
1114 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1115 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1116 APIC_BASE
, phys_addr
);
1119 * Fetch the APIC ID of the BSP in case we have a
1120 * default configuration (or the MP table is broken).
1122 boot_cpu_physical_apicid
= read_apic_id();
1126 * init_apic_mappings - initialize APIC mappings
1128 void __init
init_apic_mappings(void)
1131 boot_cpu_physical_apicid
= read_apic_id();
1136 * If no local APIC can be found then set up a fake all
1137 * zeroes page to simulate the local APIC and another
1138 * one for the IO-APIC.
1140 if (!smp_found_config
&& detect_init_APIC()) {
1141 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1142 apic_phys
= __pa(apic_phys
);
1144 apic_phys
= mp_lapic_addr
;
1146 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1147 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1148 APIC_BASE
, apic_phys
);
1151 * Fetch the APIC ID of the BSP in case we have a
1152 * default configuration (or the MP table is broken).
1154 boot_cpu_physical_apicid
= read_apic_id();
1158 * This initializes the IO-APIC and APIC hardware if this is
1161 int __init
APIC_init_uniprocessor(void)
1164 printk(KERN_INFO
"Apic disabled\n");
1167 if (!cpu_has_apic
) {
1169 printk(KERN_INFO
"Apic disabled by BIOS\n");
1174 setup_apic_routing();
1176 verify_local_APIC();
1180 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1181 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1186 * Now enable IO-APICs, actually call clear_IO_APIC
1187 * We need clear_IO_APIC before enabling vector on BP
1189 if (!skip_ioapic_setup
&& nr_ioapics
)
1192 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1193 localise_nmi_watchdog();
1194 end_local_APIC_setup();
1196 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1200 setup_boot_APIC_clock();
1201 check_nmi_watchdog();
1206 * Local APIC interrupts
1210 * This interrupt should _never_ happen with our APIC/SMP architecture
1212 asmlinkage
void smp_spurious_interrupt(void)
1218 * Check if this really is a spurious interrupt and ACK it
1219 * if it is a vectored one. Just in case...
1220 * Spurious interrupts should not be ACKed.
1222 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1223 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1226 add_pda(irq_spurious_count
, 1);
1231 * This interrupt should never happen with our APIC/SMP architecture
1233 asmlinkage
void smp_error_interrupt(void)
1239 /* First tickle the hardware, only then report what went on. -- REW */
1240 v
= apic_read(APIC_ESR
);
1241 apic_write(APIC_ESR
, 0);
1242 v1
= apic_read(APIC_ESR
);
1244 atomic_inc(&irq_err_count
);
1246 /* Here is what the APIC error bits mean:
1249 2: Send accept error
1250 3: Receive accept error
1252 5: Send illegal vector
1253 6: Received illegal vector
1254 7: Illegal register address
1256 printk(KERN_DEBUG
"APIC error on CPU%d: %02x(%02x)\n",
1257 smp_processor_id(), v
, v1
);
1262 * * connect_bsp_APIC - attach the APIC to the interrupt system
1264 void __init
connect_bsp_APIC(void)
1270 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1271 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1273 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1276 void disconnect_bsp_APIC(int virt_wire_setup
)
1278 /* Go back to Virtual Wire compatibility mode */
1279 unsigned long value
;
1281 /* For the spurious interrupt use vector F, and enable it */
1282 value
= apic_read(APIC_SPIV
);
1283 value
&= ~APIC_VECTOR_MASK
;
1284 value
|= APIC_SPIV_APIC_ENABLED
;
1286 apic_write(APIC_SPIV
, value
);
1288 if (!virt_wire_setup
) {
1290 * For LVT0 make it edge triggered, active high,
1291 * external and enabled
1293 value
= apic_read(APIC_LVT0
);
1294 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1295 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1296 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1297 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1298 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1299 apic_write(APIC_LVT0
, value
);
1302 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1305 /* For LVT1 make it edge triggered, active high, nmi and enabled */
1306 value
= apic_read(APIC_LVT1
);
1307 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1308 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1309 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1310 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1311 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1312 apic_write(APIC_LVT1
, value
);
1315 void __cpuinit
generic_processor_info(int apicid
, int version
)
1320 if (num_processors
>= NR_CPUS
) {
1321 printk(KERN_WARNING
"WARNING: NR_CPUS limit of %i reached."
1322 " Processor ignored.\n", NR_CPUS
);
1326 if (num_processors
>= maxcpus
) {
1327 printk(KERN_WARNING
"WARNING: maxcpus limit of %i reached."
1328 " Processor ignored.\n", maxcpus
);
1333 cpus_complement(tmp_map
, cpu_present_map
);
1334 cpu
= first_cpu(tmp_map
);
1336 physid_set(apicid
, phys_cpu_present_map
);
1337 if (apicid
== boot_cpu_physical_apicid
) {
1339 * x86_bios_cpu_apicid is required to have processors listed
1340 * in same order as logical cpu numbers. Hence the first
1341 * entry is BSP, and so on.
1345 if (apicid
> max_physical_apicid
)
1346 max_physical_apicid
= apicid
;
1348 /* are we being called early in kernel startup? */
1349 if (early_per_cpu_ptr(x86_cpu_to_apicid
)) {
1350 u16
*cpu_to_apicid
= early_per_cpu_ptr(x86_cpu_to_apicid
);
1351 u16
*bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1353 cpu_to_apicid
[cpu
] = apicid
;
1354 bios_cpu_apicid
[cpu
] = apicid
;
1356 per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1357 per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1360 cpu_set(cpu
, cpu_possible_map
);
1361 cpu_set(cpu
, cpu_present_map
);
1364 int hard_smp_processor_id(void)
1366 return read_apic_id();
1376 * 'active' is true if the local APIC was enabled by us and
1377 * not the BIOS; this signifies that we are also responsible
1378 * for disabling it before entering apm/acpi suspend
1381 /* r/w apic fields */
1382 unsigned int apic_id
;
1383 unsigned int apic_taskpri
;
1384 unsigned int apic_ldr
;
1385 unsigned int apic_dfr
;
1386 unsigned int apic_spiv
;
1387 unsigned int apic_lvtt
;
1388 unsigned int apic_lvtpc
;
1389 unsigned int apic_lvt0
;
1390 unsigned int apic_lvt1
;
1391 unsigned int apic_lvterr
;
1392 unsigned int apic_tmict
;
1393 unsigned int apic_tdcr
;
1394 unsigned int apic_thmr
;
1397 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1399 unsigned long flags
;
1402 if (!apic_pm_state
.active
)
1405 maxlvt
= lapic_get_maxlvt();
1407 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1408 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1409 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1410 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1411 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1412 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1414 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1415 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1416 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1417 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1418 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1419 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1420 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1422 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1425 local_irq_save(flags
);
1426 disable_local_APIC();
1427 local_irq_restore(flags
);
1431 static int lapic_resume(struct sys_device
*dev
)
1434 unsigned long flags
;
1437 if (!apic_pm_state
.active
)
1440 maxlvt
= lapic_get_maxlvt();
1442 local_irq_save(flags
);
1444 #ifdef CONFIG_X86_64
1451 * Make sure the APICBASE points to the right address
1453 * FIXME! This will be wrong if we ever support suspend on
1454 * SMP! We'll need to do this as part of the CPU restore!
1456 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1457 l
&= ~MSR_IA32_APICBASE_BASE
;
1458 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1459 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1462 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1463 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1464 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1465 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1466 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1467 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1468 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1469 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1470 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1472 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1475 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1476 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1477 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1478 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1479 apic_write(APIC_ESR
, 0);
1480 apic_read(APIC_ESR
);
1481 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1482 apic_write(APIC_ESR
, 0);
1483 apic_read(APIC_ESR
);
1485 local_irq_restore(flags
);
1491 * This device has no shutdown method - fully functioning local APICs
1492 * are needed on every CPU up until machine_halt/restart/poweroff.
1495 static struct sysdev_class lapic_sysclass
= {
1497 .resume
= lapic_resume
,
1498 .suspend
= lapic_suspend
,
1501 static struct sys_device device_lapic
= {
1503 .cls
= &lapic_sysclass
,
1506 static void __cpuinit
apic_pm_activate(void)
1508 apic_pm_state
.active
= 1;
1511 static int __init
init_lapic_sysfs(void)
1517 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1519 error
= sysdev_class_register(&lapic_sysclass
);
1521 error
= sysdev_register(&device_lapic
);
1524 device_initcall(init_lapic_sysfs
);
1526 #else /* CONFIG_PM */
1528 static void apic_pm_activate(void) { }
1530 #endif /* CONFIG_PM */
1533 * apic_is_clustered_box() -- Check if we can expect good TSC
1535 * Thus far, the major user of this is IBM's Summit2 series:
1537 * Clustered boxes may have unsynced TSC problems if they are
1538 * multi-chassis. Use available data to take a good guess.
1539 * If in doubt, go HPET.
1541 __cpuinit
int apic_is_clustered_box(void)
1543 int i
, clusters
, zeros
;
1545 u16
*bios_cpu_apicid
;
1546 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
1549 * there is not this kind of box with AMD CPU yet.
1550 * Some AMD box with quadcore cpu and 8 sockets apicid
1551 * will be [4, 0x23] or [8, 0x27] could be thought to
1552 * vsmp box still need checking...
1554 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
1557 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1558 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
1560 for (i
= 0; i
< NR_CPUS
; i
++) {
1561 /* are we being called early in kernel startup? */
1562 if (bios_cpu_apicid
) {
1563 id
= bios_cpu_apicid
[i
];
1565 else if (i
< nr_cpu_ids
) {
1567 id
= per_cpu(x86_bios_cpu_apicid
, i
);
1574 if (id
!= BAD_APICID
)
1575 __set_bit(APIC_CLUSTERID(id
), clustermap
);
1578 /* Problem: Partially populated chassis may not have CPUs in some of
1579 * the APIC clusters they have been allocated. Only present CPUs have
1580 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
1581 * Since clusters are allocated sequentially, count zeros only if
1582 * they are bounded by ones.
1586 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
1587 if (test_bit(i
, clustermap
)) {
1588 clusters
+= 1 + zeros
;
1594 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
1595 * not guaranteed to be synced between boards
1597 if (is_vsmp_box() && clusters
> 1)
1601 * If clusters > 2, then should be multi-chassis.
1602 * May have to revisit this when multi-core + hyperthreaded CPUs come
1603 * out, but AFAIK this will work even for them.
1605 return (clusters
> 2);
1608 static __init
int setup_nox2apic(char *str
)
1611 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_X2APIC
);
1614 early_param("nox2apic", setup_nox2apic
);
1618 * APIC command line parameters
1620 static int __init
apic_set_verbosity(char *str
)
1623 skip_ioapic_setup
= 0;
1627 if (strcmp("debug", str
) == 0)
1628 apic_verbosity
= APIC_DEBUG
;
1629 else if (strcmp("verbose", str
) == 0)
1630 apic_verbosity
= APIC_VERBOSE
;
1632 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
1633 " use apic=verbose or apic=debug\n", str
);
1639 early_param("apic", apic_set_verbosity
);
1641 static __init
int setup_disableapic(char *str
)
1644 setup_clear_cpu_cap(X86_FEATURE_APIC
);
1647 early_param("disableapic", setup_disableapic
);
1649 /* same as disableapic, for compatibility */
1650 static __init
int setup_nolapic(char *str
)
1652 return setup_disableapic(str
);
1654 early_param("nolapic", setup_nolapic
);
1656 static int __init
parse_lapic_timer_c2_ok(char *arg
)
1658 local_apic_timer_c2_ok
= 1;
1661 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
1663 static int __init
parse_disable_apic_timer(char *arg
)
1665 disable_apic_timer
= 1;
1668 early_param("noapictimer", parse_disable_apic_timer
);
1670 static int __init
parse_nolapic_timer(char *arg
)
1672 disable_apic_timer
= 1;
1675 early_param("nolapic_timer", parse_nolapic_timer
);
1677 static __init
int setup_apicpmtimer(char *s
)
1679 apic_calibrate_pmtmr
= 1;
1683 __setup("apicpmtimer", setup_apicpmtimer
);
1685 static int __init
lapic_insert_resource(void)
1690 /* Put local APIC into the resource map. */
1691 lapic_resource
.start
= apic_phys
;
1692 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
1693 insert_resource(&iomem_resource
, &lapic_resource
);
1699 * need call insert after e820_reserve_resources()
1700 * that is using request_resource
1702 late_initcall(lapic_insert_resource
);