async: make sure independent async domains can't accidentally entangle
[linux-2.6/mini2440.git] / include / linux / mmc / sdio.h
blob47ba464f5170eb3695d11192b28ee96601ead6b8
1 /*
2 * include/linux/mmc/sdio.h
4 * Copyright 2006-2007 Pierre Ossman
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
12 #ifndef MMC_SDIO_H
13 #define MMC_SDIO_H
15 /* SDIO commands type argument response */
16 #define SD_IO_SEND_OP_COND 5 /* bcr [23:0] OCR R4 */
17 #define SD_IO_RW_DIRECT 52 /* ac [31:0] See below R5 */
18 #define SD_IO_RW_EXTENDED 53 /* adtc [31:0] See below R5 */
21 * SD_IO_RW_DIRECT argument format:
23 * [31] R/W flag
24 * [30:28] Function number
25 * [27] RAW flag
26 * [25:9] Register address
27 * [7:0] Data
31 * SD_IO_RW_EXTENDED argument format:
33 * [31] R/W flag
34 * [30:28] Function number
35 * [27] Block mode
36 * [26] Increment address
37 * [25:9] Register address
38 * [8:0] Byte/block count
42 SDIO status in R5
43 Type
44 e : error bit
45 s : status bit
46 r : detected and set for the actual command response
47 x : detected and set during command execution. the host must poll
48 the card by sending status command in order to read these bits.
49 Clear condition
50 a : according to the card state
51 b : always related to the previous command. Reception of
52 a valid command will clear it (with a delay of one command)
53 c : clear by read
56 #define R5_COM_CRC_ERROR (1 << 15) /* er, b */
57 #define R5_ILLEGAL_COMMAND (1 << 14) /* er, b */
58 #define R5_ERROR (1 << 11) /* erx, c */
59 #define R5_FUNCTION_NUMBER (1 << 9) /* er, c */
60 #define R5_OUT_OF_RANGE (1 << 8) /* er, c */
61 #define R5_STATUS(x) (x & 0xCB00)
62 #define R5_IO_CURRENT_STATE(x) ((x & 0x3000) >> 12) /* s, b */
65 * Card Common Control Registers (CCCR)
68 #define SDIO_CCCR_CCCR 0x00
70 #define SDIO_CCCR_REV_1_00 0 /* CCCR/FBR Version 1.00 */
71 #define SDIO_CCCR_REV_1_10 1 /* CCCR/FBR Version 1.10 */
72 #define SDIO_CCCR_REV_1_20 2 /* CCCR/FBR Version 1.20 */
74 #define SDIO_SDIO_REV_1_00 0 /* SDIO Spec Version 1.00 */
75 #define SDIO_SDIO_REV_1_10 1 /* SDIO Spec Version 1.10 */
76 #define SDIO_SDIO_REV_1_20 2 /* SDIO Spec Version 1.20 */
77 #define SDIO_SDIO_REV_2_00 3 /* SDIO Spec Version 2.00 */
79 #define SDIO_CCCR_SD 0x01
81 #define SDIO_SD_REV_1_01 0 /* SD Physical Spec Version 1.01 */
82 #define SDIO_SD_REV_1_10 1 /* SD Physical Spec Version 1.10 */
83 #define SDIO_SD_REV_2_00 2 /* SD Physical Spec Version 2.00 */
85 #define SDIO_CCCR_IOEx 0x02
86 #define SDIO_CCCR_IORx 0x03
88 #define SDIO_CCCR_IENx 0x04 /* Function/Master Interrupt Enable */
89 #define SDIO_CCCR_INTx 0x05 /* Function Interrupt Pending */
91 #define SDIO_CCCR_ABORT 0x06 /* function abort/card reset */
93 #define SDIO_CCCR_IF 0x07 /* bus interface controls */
95 #define SDIO_BUS_WIDTH_1BIT 0x00
96 #define SDIO_BUS_WIDTH_4BIT 0x02
98 #define SDIO_BUS_CD_DISABLE 0x80 /* disable pull-up on DAT3 (pin 1) */
100 #define SDIO_CCCR_CAPS 0x08
102 #define SDIO_CCCR_CAP_SDC 0x01 /* can do CMD52 while data transfer */
103 #define SDIO_CCCR_CAP_SMB 0x02 /* can do multi-block xfers (CMD53) */
104 #define SDIO_CCCR_CAP_SRW 0x04 /* supports read-wait protocol */
105 #define SDIO_CCCR_CAP_SBS 0x08 /* supports suspend/resume */
106 #define SDIO_CCCR_CAP_S4MI 0x10 /* interrupt during 4-bit CMD53 */
107 #define SDIO_CCCR_CAP_E4MI 0x20 /* enable ints during 4-bit CMD53 */
108 #define SDIO_CCCR_CAP_LSC 0x40 /* low speed card */
109 #define SDIO_CCCR_CAP_4BLS 0x80 /* 4 bit low speed card */
111 #define SDIO_CCCR_CIS 0x09 /* common CIS pointer (3 bytes) */
113 /* Following 4 regs are valid only if SBS is set */
114 #define SDIO_CCCR_SUSPEND 0x0c
115 #define SDIO_CCCR_SELx 0x0d
116 #define SDIO_CCCR_EXECx 0x0e
117 #define SDIO_CCCR_READYx 0x0f
119 #define SDIO_CCCR_BLKSIZE 0x10
121 #define SDIO_CCCR_POWER 0x12
123 #define SDIO_POWER_SMPC 0x01 /* Supports Master Power Control */
124 #define SDIO_POWER_EMPC 0x02 /* Enable Master Power Control */
126 #define SDIO_CCCR_SPEED 0x13
128 #define SDIO_SPEED_SHS 0x01 /* Supports High-Speed mode */
129 #define SDIO_SPEED_EHS 0x02 /* Enable High-Speed mode */
132 * Function Basic Registers (FBR)
135 #define SDIO_FBR_BASE(f) ((f) * 0x100) /* base of function f's FBRs */
137 #define SDIO_FBR_STD_IF 0x00
139 #define SDIO_FBR_SUPPORTS_CSA 0x40 /* supports Code Storage Area */
140 #define SDIO_FBR_ENABLE_CSA 0x80 /* enable Code Storage Area */
142 #define SDIO_FBR_STD_IF_EXT 0x01
144 #define SDIO_FBR_POWER 0x02
146 #define SDIO_FBR_POWER_SPS 0x01 /* Supports Power Selection */
147 #define SDIO_FBR_POWER_EPS 0x02 /* Enable (low) Power Selection */
149 #define SDIO_FBR_CIS 0x09 /* CIS pointer (3 bytes) */
152 #define SDIO_FBR_CSA 0x0C /* CSA pointer (3 bytes) */
154 #define SDIO_FBR_CSA_DATA 0x0F
156 #define SDIO_FBR_BLKSIZE 0x10 /* block size (2 bytes) */
158 #endif