async: make sure independent async domains can't accidentally entangle
[linux-2.6/mini2440.git] / arch / blackfin / mach-common / cache-c.c
blobe6ab1f815123b62e6269f335294ea76378fd530c
1 /*
2 * Blackfin cache control code (simpler control-style functions)
4 * Copyright 2004-2008 Analog Devices Inc.
6 * Enter bugs at http://blackfin.uclinux.org/
8 * Licensed under the GPL-2 or later.
9 */
11 #include <asm/blackfin.h>
13 /* Invalidate the Entire Data cache by
14 * clearing DMC[1:0] bits
16 void blackfin_invalidate_entire_dcache(void)
18 u32 dmem = bfin_read_DMEM_CONTROL();
19 SSYNC();
20 bfin_write_DMEM_CONTROL(dmem & ~0xc);
21 SSYNC();
22 bfin_write_DMEM_CONTROL(dmem);
23 SSYNC();