4 #include <linux/config.h>
5 #include <linux/kernel.h>
6 #include <asm/segment.h>
7 #include <asm/cpufeature.h>
8 #include <linux/bitops.h> /* for LOCK_PREFIX */
12 struct task_struct
; /* one of the stranger aspects of C forward declarations.. */
13 extern struct task_struct
* FASTCALL(__switch_to(struct task_struct
*prev
, struct task_struct
*next
));
15 #define switch_to(prev,next,last) do { \
16 unsigned long esi,edi; \
17 asm volatile("pushl %%ebp\n\t" \
18 "movl %%esp,%0\n\t" /* save ESP */ \
19 "movl %5,%%esp\n\t" /* restore ESP */ \
20 "movl $1f,%1\n\t" /* save EIP */ \
21 "pushl %6\n\t" /* restore EIP */ \
25 :"=m" (prev->thread.esp),"=m" (prev->thread.eip), \
26 "=a" (last),"=S" (esi),"=D" (edi) \
27 :"m" (next->thread.esp),"m" (next->thread.eip), \
28 "2" (prev), "d" (next)); \
31 #define _set_base(addr,base) do { unsigned long __pr; \
32 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
33 "rorl $16,%%edx\n\t" \
43 #define _set_limit(addr,limit) do { unsigned long __lr; \
44 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
45 "rorl $16,%%edx\n\t" \
47 "andb $0xf0,%%dh\n\t" \
56 #define set_base(ldt,base) _set_base( ((char *)&(ldt)) , (base) )
57 #define set_limit(ldt,limit) _set_limit( ((char *)&(ldt)) , ((limit)-1) )
60 * Load a segment. Fall back on loading the zero
61 * segment if something goes wrong..
63 #define loadsegment(seg,value) \
66 "mov %0,%%" #seg "\n" \
68 ".section .fixup,\"ax\"\n" \
71 "popl %%" #seg "\n\t" \
74 ".section __ex_table,\"a\"\n\t" \
81 * Save a segment register away
83 #define savesegment(seg, value) \
84 asm volatile("mov %%" #seg ",%0":"=rm" (value))
87 * Clear and set 'TS' bit respectively
89 #define clts() __asm__ __volatile__ ("clts")
90 #define read_cr0() ({ \
91 unsigned int __dummy; \
92 __asm__ __volatile__( \
97 #define write_cr0(x) \
98 __asm__ __volatile__("movl %0,%%cr0": :"r" (x));
100 #define read_cr2() ({ \
101 unsigned int __dummy; \
102 __asm__ __volatile__( \
103 "movl %%cr2,%0\n\t" \
107 #define write_cr2(x) \
108 __asm__ __volatile__("movl %0,%%cr2": :"r" (x));
110 #define read_cr3() ({ \
111 unsigned int __dummy; \
113 "movl %%cr3,%0\n\t" \
117 #define write_cr3(x) \
118 __asm__ __volatile__("movl %0,%%cr3": :"r" (x));
120 #define read_cr4() ({ \
121 unsigned int __dummy; \
123 "movl %%cr4,%0\n\t" \
128 #define read_cr4_safe() ({ \
129 unsigned int __dummy; \
130 /* This could fault if %cr4 does not exist */ \
131 __asm__("1: movl %%cr4, %0 \n" \
133 ".section __ex_table,\"a\" \n" \
136 : "=r" (__dummy): "0" (0)); \
140 #define write_cr4(x) \
141 __asm__ __volatile__("movl %0,%%cr4": :"r" (x));
142 #define stts() write_cr0(8 | read_cr0())
144 #endif /* __KERNEL__ */
147 __asm__ __volatile__ ("wbinvd": : :"memory");
149 static inline unsigned long get_limit(unsigned long segment
)
151 unsigned long __limit
;
153 :"=r" (__limit
):"r" (segment
));
157 #define nop() __asm__ __volatile__ ("nop")
159 #define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
161 #define tas(ptr) (xchg((ptr),1))
163 struct __xchg_dummy
{ unsigned long a
[100]; };
164 #define __xg(x) ((struct __xchg_dummy *)(x))
167 #ifdef CONFIG_X86_CMPXCHG64
170 * The semantics of XCHGCMP8B are a bit strange, this is why
171 * there is a loop and the loading of %%eax and %%edx has to
172 * be inside. This inlines well in most cases, the cached
173 * cost is around ~38 cycles. (in the future we might want
174 * to do an SIMD/3DNOW!/MMX/FPU 64-bit store here, but that
175 * might have an implicit FPU-save as a cost, so it's not
176 * clear which path to go.)
178 * cmpxchg8b must be used with the lock prefix here to allow
179 * the instruction to be executed atomically, see page 3-102
180 * of the instruction set reference 24319102.pdf. We need
181 * the reader side to see the coherent 64bit value.
183 static inline void __set_64bit (unsigned long long * ptr
,
184 unsigned int low
, unsigned int high
)
186 __asm__
__volatile__ (
188 "movl (%0), %%eax\n\t"
189 "movl 4(%0), %%edx\n\t"
190 "lock cmpxchg8b (%0)\n\t"
196 : "ax","dx","memory");
199 static inline void __set_64bit_constant (unsigned long long *ptr
,
200 unsigned long long value
)
202 __set_64bit(ptr
,(unsigned int)(value
), (unsigned int)((value
)>>32ULL));
204 #define ll_low(x) *(((unsigned int*)&(x))+0)
205 #define ll_high(x) *(((unsigned int*)&(x))+1)
207 static inline void __set_64bit_var (unsigned long long *ptr
,
208 unsigned long long value
)
210 __set_64bit(ptr
,ll_low(value
), ll_high(value
));
213 #define set_64bit(ptr,value) \
214 (__builtin_constant_p(value) ? \
215 __set_64bit_constant(ptr, value) : \
216 __set_64bit_var(ptr, value) )
218 #define _set_64bit(ptr,value) \
219 (__builtin_constant_p(value) ? \
220 __set_64bit(ptr, (unsigned int)(value), (unsigned int)((value)>>32ULL) ) : \
221 __set_64bit(ptr, ll_low(value), ll_high(value)) )
226 * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
227 * Note 2: xchg has side effect, so that attribute volatile is necessary,
228 * but generally the primitive is invalid, *ptr is output argument. --ANK
230 static inline unsigned long __xchg(unsigned long x
, volatile void * ptr
, int size
)
234 __asm__
__volatile__("xchgb %b0,%1"
236 :"m" (*__xg(ptr
)), "0" (x
)
240 __asm__
__volatile__("xchgw %w0,%1"
242 :"m" (*__xg(ptr
)), "0" (x
)
246 __asm__
__volatile__("xchgl %0,%1"
248 :"m" (*__xg(ptr
)), "0" (x
)
256 * Atomic compare and exchange. Compare OLD with MEM, if identical,
257 * store NEW in MEM. Return the initial value in MEM. Success is
258 * indicated by comparing RETURN with OLD.
261 #ifdef CONFIG_X86_CMPXCHG
262 #define __HAVE_ARCH_CMPXCHG 1
263 #define cmpxchg(ptr,o,n)\
264 ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
265 (unsigned long)(n),sizeof(*(ptr))))
268 static inline unsigned long __cmpxchg(volatile void *ptr
, unsigned long old
,
269 unsigned long new, int size
)
274 __asm__
__volatile__(LOCK_PREFIX
"cmpxchgb %b1,%2"
276 : "q"(new), "m"(*__xg(ptr
)), "0"(old
)
280 __asm__
__volatile__(LOCK_PREFIX
"cmpxchgw %w1,%2"
282 : "r"(new), "m"(*__xg(ptr
)), "0"(old
)
286 __asm__
__volatile__(LOCK_PREFIX
"cmpxchgl %1,%2"
288 : "r"(new), "m"(*__xg(ptr
)), "0"(old
)
295 #ifndef CONFIG_X86_CMPXCHG
297 * Building a kernel capable running on 80386. It may be necessary to
298 * simulate the cmpxchg on the 80386 CPU. For that purpose we define
299 * a function for each of the sizes we support.
302 extern unsigned long cmpxchg_386_u8(volatile void *, u8
, u8
);
303 extern unsigned long cmpxchg_386_u16(volatile void *, u16
, u16
);
304 extern unsigned long cmpxchg_386_u32(volatile void *, u32
, u32
);
306 static inline unsigned long cmpxchg_386(volatile void *ptr
, unsigned long old
,
307 unsigned long new, int size
)
311 return cmpxchg_386_u8(ptr
, old
, new);
313 return cmpxchg_386_u16(ptr
, old
, new);
315 return cmpxchg_386_u32(ptr
, old
, new);
320 #define cmpxchg(ptr,o,n) \
322 __typeof__(*(ptr)) __ret; \
323 if (likely(boot_cpu_data.x86 > 3)) \
324 __ret = __cmpxchg((ptr), (unsigned long)(o), \
325 (unsigned long)(n), sizeof(*(ptr))); \
327 __ret = cmpxchg_386((ptr), (unsigned long)(o), \
328 (unsigned long)(n), sizeof(*(ptr))); \
333 #ifdef CONFIG_X86_CMPXCHG64
335 static inline unsigned long long __cmpxchg64(volatile void *ptr
, unsigned long long old
,
336 unsigned long long new)
338 unsigned long long prev
;
339 __asm__
__volatile__(LOCK_PREFIX
"cmpxchg8b %3"
341 : "b"((unsigned long)new),
342 "c"((unsigned long)(new >> 32)),
349 #define cmpxchg64(ptr,o,n)\
350 ((__typeof__(*(ptr)))__cmpxchg64((ptr),(unsigned long long)(o),\
351 (unsigned long long)(n)))
357 __u8
*instr
; /* original instruction */
359 __u8 cpuid
; /* cpuid bit set for replacement */
360 __u8 instrlen
; /* length of original instruction */
361 __u8 replacementlen
; /* length of new instruction, <= instrlen */
367 * Alternative instructions for different CPU types or capabilities.
369 * This allows to use optimized instructions even on generic binary
372 * length of oldinstr must be longer or equal the length of newinstr
373 * It can be padded with nops as needed.
375 * For non barrier like inlines please define new variants
376 * without volatile and memory clobber.
378 #define alternative(oldinstr, newinstr, feature) \
379 asm volatile ("661:\n\t" oldinstr "\n662:\n" \
380 ".section .altinstructions,\"a\"\n" \
382 " .long 661b\n" /* label */ \
383 " .long 663f\n" /* new instruction */ \
384 " .byte %c0\n" /* feature bit */ \
385 " .byte 662b-661b\n" /* sourcelen */ \
386 " .byte 664f-663f\n" /* replacementlen */ \
388 ".section .altinstr_replacement,\"ax\"\n" \
389 "663:\n\t" newinstr "\n664:\n" /* replacement */ \
390 ".previous" :: "i" (feature) : "memory")
393 * Alternative inline assembly with input.
396 * No memory clobber here.
397 * Argument numbers start with 1.
398 * Best is to use constraints that are fixed size (like (%1) ... "r")
399 * If you use variable sized constraints like "m" or "g" in the
400 * replacement maake sure to pad to the worst case length.
402 #define alternative_input(oldinstr, newinstr, feature, input...) \
403 asm volatile ("661:\n\t" oldinstr "\n662:\n" \
404 ".section .altinstructions,\"a\"\n" \
406 " .long 661b\n" /* label */ \
407 " .long 663f\n" /* new instruction */ \
408 " .byte %c0\n" /* feature bit */ \
409 " .byte 662b-661b\n" /* sourcelen */ \
410 " .byte 664f-663f\n" /* replacementlen */ \
412 ".section .altinstr_replacement,\"ax\"\n" \
413 "663:\n\t" newinstr "\n664:\n" /* replacement */ \
414 ".previous" :: "i" (feature), ##input)
417 * Force strict CPU ordering.
418 * And yes, this is required on UP too when we're talking
421 * For now, "wmb()" doesn't actually do anything, as all
422 * Intel CPU's follow what Intel calls a *Processor Order*,
423 * in which all writes are seen in the program order even
426 * I expect future Intel CPU's to have a weaker ordering,
427 * but I'd also expect them to finally get their act together
428 * and add some real memory barriers if so.
430 * Some non intel clones support out of order store. wmb() ceases to be a
436 * Actually only lfence would be needed for mb() because all stores done
437 * by the kernel should be already ordered. But keep a full barrier for now.
440 #define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
441 #define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
444 * read_barrier_depends - Flush all pending reads that subsequents reads
447 * No data-dependent reads from memory-like regions are ever reordered
448 * over this barrier. All reads preceding this primitive are guaranteed
449 * to access memory (but not necessarily other CPUs' caches) before any
450 * reads following this primitive that depend on the data return by
451 * any of the preceding reads. This primitive is much lighter weight than
452 * rmb() on most CPUs, and is never heavier weight than is
455 * These ordering constraints are respected by both the local CPU
458 * Ordering is not guaranteed by anything other than these primitives,
459 * not even by data dependencies. See the documentation for
460 * memory_barrier() for examples and URLs to more information.
462 * For example, the following code would force ordering (the initial
463 * value of "a" is zero, "b" is one, and "p" is "&a"):
471 * read_barrier_depends();
475 * because the read of "*q" depends on the read of "p" and these
476 * two reads are separated by a read_barrier_depends(). However,
477 * the following code, with the same initial values for "a" and "b":
485 * read_barrier_depends();
489 * does not enforce ordering, since there is no data dependency between
490 * the read of "a" and the read of "b". Therefore, on some CPUs, such
491 * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
492 * in cases like thiswhere there are no data dependencies.
495 #define read_barrier_depends() do { } while(0)
497 #ifdef CONFIG_X86_OOSTORE
498 /* Actually there are no OOO store capable CPUs for now that do SSE,
499 but make it already an possibility. */
500 #define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
502 #define wmb() __asm__ __volatile__ ("": : :"memory")
506 #define smp_mb() mb()
507 #define smp_rmb() rmb()
508 #define smp_wmb() wmb()
509 #define smp_read_barrier_depends() read_barrier_depends()
510 #define set_mb(var, value) do { xchg(&var, value); } while (0)
512 #define smp_mb() barrier()
513 #define smp_rmb() barrier()
514 #define smp_wmb() barrier()
515 #define smp_read_barrier_depends() do { } while(0)
516 #define set_mb(var, value) do { var = value; barrier(); } while (0)
519 #define set_wmb(var, value) do { var = value; wmb(); } while (0)
521 /* interrupt control.. */
522 #define local_save_flags(x) do { typecheck(unsigned long,x); __asm__ __volatile__("pushfl ; popl %0":"=g" (x): /* no input */); } while (0)
523 #define local_irq_restore(x) do { typecheck(unsigned long,x); __asm__ __volatile__("pushl %0 ; popfl": /* no output */ :"g" (x):"memory", "cc"); } while (0)
524 #define local_irq_disable() __asm__ __volatile__("cli": : :"memory")
525 #define local_irq_enable() __asm__ __volatile__("sti": : :"memory")
526 /* used in the idle loop; sti takes one instruction cycle to complete */
527 #define safe_halt() __asm__ __volatile__("sti; hlt": : :"memory")
528 /* used when interrupts are already enabled or to shutdown the processor */
529 #define halt() __asm__ __volatile__("hlt": : :"memory")
531 #define irqs_disabled() \
533 unsigned long flags; \
534 local_save_flags(flags); \
538 /* For spinlocks etc */
539 #define local_irq_save(x) __asm__ __volatile__("pushfl ; popl %0 ; cli":"=g" (x): /* no input */ :"memory")
542 * disable hlt during certain critical i/o operations
544 #define HAVE_DISABLE_HLT
545 void disable_hlt(void);
546 void enable_hlt(void);
548 extern int es7000_plat
;
549 void cpu_idle_wait(void);
551 extern unsigned long arch_align_stack(unsigned long sp
);