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[SCSI] sd: remove command-size switching code
[linux-2.6/mini2440.git] / drivers / ata / ata_piix.c
blobe9e32ed6b1a34ccbd0e61dd846622234b07ca2f5
1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
83 */
84
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
94 #include <linux/dmi.h>
95
96 #define DRV_NAME "ata_piix"
97 #define DRV_VERSION "2.12"
98
99 enum {
100 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
101 ICH5_PMR = 0x90, /* port mapping register */
102 ICH5_PCS = 0x92, /* port control and status */
103 PIIX_SIDPR_BAR = 5,
104 PIIX_SIDPR_LEN = 16,
105 PIIX_SIDPR_IDX = 0,
106 PIIX_SIDPR_DATA = 4,
107
108 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
109 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
110
111 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
112 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
113
114 PIIX_80C_PRI = (1 << 5) | (1 << 4),
115 PIIX_80C_SEC = (1 << 7) | (1 << 6),
116
117 /* constants for mapping table */
118 P0 = 0, /* port 0 */
119 P1 = 1, /* port 1 */
120 P2 = 2, /* port 2 */
121 P3 = 3, /* port 3 */
122 IDE = -1, /* IDE */
123 NA = -2, /* not avaliable */
124 RV = -3, /* reserved */
125
126 PIIX_AHCI_DEVICE = 6,
127
128 /* host->flags bits */
129 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
130 };
131
132 enum piix_controller_ids {
133 /* controller IDs */
134 piix_pata_mwdma, /* PIIX3 MWDMA only */
135 piix_pata_33, /* PIIX4 at 33Mhz */
136 ich_pata_33, /* ICH up to UDMA 33 only */
137 ich_pata_66, /* ICH up to 66 Mhz */
138 ich_pata_100, /* ICH up to UDMA 100 */
139 ich5_sata,
140 ich6_sata,
141 ich6m_sata,
142 ich8_sata,
143 ich8_2port_sata,
144 ich8m_apple_sata, /* locks up on second port enable */
145 tolapai_sata,
146 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
147 };
148
149 struct piix_map_db {
150 const u32 mask;
151 const u16 port_enable;
152 const int map[][4];
153 };
154
155 struct piix_host_priv {
156 const int *map;
157 void __iomem *sidpr;
158 };
159
160 static int piix_init_one(struct pci_dev *pdev,
161 const struct pci_device_id *ent);
162 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline);
163 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
164 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
165 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
166 static int ich_pata_cable_detect(struct ata_port *ap);
167 static u8 piix_vmw_bmdma_status(struct ata_port *ap);
168 static int piix_sidpr_scr_read(struct ata_link *link,
169 unsigned int reg, u32 *val);
170 static int piix_sidpr_scr_write(struct ata_link *link,
171 unsigned int reg, u32 val);
172 #ifdef CONFIG_PM
173 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
174 static int piix_pci_device_resume(struct pci_dev *pdev);
175 #endif
176
177 static unsigned int in_module_init = 1;
178
179 static const struct pci_device_id piix_pci_tbl[] = {
180 /* Intel PIIX3 for the 430HX etc */
181 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
182 /* VMware ICH4 */
183 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
184 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
185 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
186 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
187 /* Intel PIIX4 */
188 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
189 /* Intel PIIX4 */
190 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
191 /* Intel PIIX */
192 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
193 /* Intel ICH (i810, i815, i840) UDMA 66*/
194 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
195 /* Intel ICH0 : UDMA 33*/
196 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
197 /* Intel ICH2M */
198 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
199 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
200 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
201 /* Intel ICH3M */
202 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
203 /* Intel ICH3 (E7500/1) UDMA 100 */
204 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
205 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
206 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
207 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
208 /* Intel ICH5 */
209 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
210 /* C-ICH (i810E2) */
211 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
212 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
213 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
214 /* ICH6 (and 6) (i915) UDMA 100 */
215 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
216 /* ICH7/7-R (i945, i975) UDMA 100*/
217 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
218 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
219 /* ICH8 Mobile PATA Controller */
220 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
221
222 /* NOTE: The following PCI ids must be kept in sync with the
223 * list in drivers/pci/quirks.c.
224 */
225
226 /* 82801EB (ICH5) */
227 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
228 /* 82801EB (ICH5) */
229 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
230 /* 6300ESB (ICH5 variant with broken PCS present bits) */
231 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
232 /* 6300ESB pretending RAID */
233 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
234 /* 82801FB/FW (ICH6/ICH6W) */
235 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
236 /* 82801FR/FRW (ICH6R/ICH6RW) */
237 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
238 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
239 * Attach iff the controller is in IDE mode. */
240 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
241 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
242 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
243 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
244 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
245 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
246 /* Enterprise Southbridge 2 (631xESB/632xESB) */
247 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
248 /* SATA Controller 1 IDE (ICH8) */
249 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
250 /* SATA Controller 2 IDE (ICH8) */
251 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
252 /* Mobile SATA Controller IDE (ICH8M), Apple */
253 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
254 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
255 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
256 /* Mobile SATA Controller IDE (ICH8M) */
257 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
258 /* SATA Controller IDE (ICH9) */
259 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
260 /* SATA Controller IDE (ICH9) */
261 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
262 /* SATA Controller IDE (ICH9) */
263 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
264 /* SATA Controller IDE (ICH9M) */
265 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
266 /* SATA Controller IDE (ICH9M) */
267 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
268 /* SATA Controller IDE (ICH9M) */
269 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
270 /* SATA Controller IDE (Tolapai) */
271 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
272 /* SATA Controller IDE (ICH10) */
273 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
274 /* SATA Controller IDE (ICH10) */
275 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
276 /* SATA Controller IDE (ICH10) */
277 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
278 /* SATA Controller IDE (ICH10) */
279 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
280 /* SATA Controller IDE (PCH) */
281 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
282 /* SATA Controller IDE (PCH) */
283 { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
284 /* SATA Controller IDE (PCH) */
285 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
286 /* SATA Controller IDE (PCH) */
287 { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
288 /* SATA Controller IDE (PCH) */
289 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
290 /* SATA Controller IDE (PCH) */
291 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
292 { } /* terminate list */
293 };
294
295 static struct pci_driver piix_pci_driver = {
296 .name = DRV_NAME,
297 .id_table = piix_pci_tbl,
298 .probe = piix_init_one,
299 .remove = ata_pci_remove_one,
300 #ifdef CONFIG_PM
301 .suspend = piix_pci_device_suspend,
302 .resume = piix_pci_device_resume,
303 #endif
304 };
305
306 static struct scsi_host_template piix_sht = {
307 ATA_BMDMA_SHT(DRV_NAME),
308 };
309
310 static struct ata_port_operations piix_pata_ops = {
311 .inherits = &ata_bmdma_port_ops,
312 .cable_detect = ata_cable_40wire,
313 .set_piomode = piix_set_piomode,
314 .set_dmamode = piix_set_dmamode,
315 .prereset = piix_pata_prereset,
316 };
317
318 static struct ata_port_operations piix_vmw_ops = {
319 .inherits = &piix_pata_ops,
320 .bmdma_status = piix_vmw_bmdma_status,
321 };
322
323 static struct ata_port_operations ich_pata_ops = {
324 .inherits = &piix_pata_ops,
325 .cable_detect = ich_pata_cable_detect,
326 .set_dmamode = ich_set_dmamode,
327 };
328
329 static struct ata_port_operations piix_sata_ops = {
330 .inherits = &ata_bmdma_port_ops,
331 };
332
333 static struct ata_port_operations piix_sidpr_sata_ops = {
334 .inherits = &piix_sata_ops,
335 .hardreset = sata_std_hardreset,
336 .scr_read = piix_sidpr_scr_read,
337 .scr_write = piix_sidpr_scr_write,
338 };
339
340 static const struct piix_map_db ich5_map_db = {
341 .mask = 0x7,
342 .port_enable = 0x3,
343 .map = {
344 /* PM PS SM SS MAP */
345 { P0, NA, P1, NA }, /* 000b */
346 { P1, NA, P0, NA }, /* 001b */
347 { RV, RV, RV, RV },
348 { RV, RV, RV, RV },
349 { P0, P1, IDE, IDE }, /* 100b */
350 { P1, P0, IDE, IDE }, /* 101b */
351 { IDE, IDE, P0, P1 }, /* 110b */
352 { IDE, IDE, P1, P0 }, /* 111b */
353 },
354 };
355
356 static const struct piix_map_db ich6_map_db = {
357 .mask = 0x3,
358 .port_enable = 0xf,
359 .map = {
360 /* PM PS SM SS MAP */
361 { P0, P2, P1, P3 }, /* 00b */
362 { IDE, IDE, P1, P3 }, /* 01b */
363 { P0, P2, IDE, IDE }, /* 10b */
364 { RV, RV, RV, RV },
365 },
366 };
367
368 static const struct piix_map_db ich6m_map_db = {
369 .mask = 0x3,
370 .port_enable = 0x5,
371
372 /* Map 01b isn't specified in the doc but some notebooks use
373 * it anyway. MAP 01b have been spotted on both ICH6M and
374 * ICH7M.
375 */
376 .map = {
377 /* PM PS SM SS MAP */
378 { P0, P2, NA, NA }, /* 00b */
379 { IDE, IDE, P1, P3 }, /* 01b */
380 { P0, P2, IDE, IDE }, /* 10b */
381 { RV, RV, RV, RV },
382 },
383 };
384
385 static const struct piix_map_db ich8_map_db = {
386 .mask = 0x3,
387 .port_enable = 0xf,
388 .map = {
389 /* PM PS SM SS MAP */
390 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
391 { RV, RV, RV, RV },
392 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
393 { RV, RV, RV, RV },
394 },
395 };
396
397 static const struct piix_map_db ich8_2port_map_db = {
398 .mask = 0x3,
399 .port_enable = 0x3,
400 .map = {
401 /* PM PS SM SS MAP */
402 { P0, NA, P1, NA }, /* 00b */
403 { RV, RV, RV, RV }, /* 01b */
404 { RV, RV, RV, RV }, /* 10b */
405 { RV, RV, RV, RV },
406 },
407 };
408
409 static const struct piix_map_db ich8m_apple_map_db = {
410 .mask = 0x3,
411 .port_enable = 0x1,
412 .map = {
413 /* PM PS SM SS MAP */
414 { P0, NA, NA, NA }, /* 00b */
415 { RV, RV, RV, RV },
416 { P0, P2, IDE, IDE }, /* 10b */
417 { RV, RV, RV, RV },
418 },
419 };
420
421 static const struct piix_map_db tolapai_map_db = {
422 .mask = 0x3,
423 .port_enable = 0x3,
424 .map = {
425 /* PM PS SM SS MAP */
426 { P0, NA, P1, NA }, /* 00b */
427 { RV, RV, RV, RV }, /* 01b */
428 { RV, RV, RV, RV }, /* 10b */
429 { RV, RV, RV, RV },
430 },
431 };
432
433 static const struct piix_map_db *piix_map_db_table[] = {
434 [ich5_sata] = &ich5_map_db,
435 [ich6_sata] = &ich6_map_db,
436 [ich6m_sata] = &ich6m_map_db,
437 [ich8_sata] = &ich8_map_db,
438 [ich8_2port_sata] = &ich8_2port_map_db,
439 [ich8m_apple_sata] = &ich8m_apple_map_db,
440 [tolapai_sata] = &tolapai_map_db,
441 };
442
443 static struct ata_port_info piix_port_info[] = {
444 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
445 {
446 .flags = PIIX_PATA_FLAGS,
447 .pio_mask = 0x1f, /* pio0-4 */
448 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
449 .port_ops = &piix_pata_ops,
450 },
451
452 [piix_pata_33] = /* PIIX4 at 33MHz */
453 {
454 .flags = PIIX_PATA_FLAGS,
455 .pio_mask = 0x1f, /* pio0-4 */
456 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
457 .udma_mask = ATA_UDMA_MASK_40C,
458 .port_ops = &piix_pata_ops,
459 },
460
461 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
462 {
463 .flags = PIIX_PATA_FLAGS,
464 .pio_mask = 0x1f, /* pio 0-4 */
465 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
466 .udma_mask = ATA_UDMA2, /* UDMA33 */
467 .port_ops = &ich_pata_ops,
468 },
469
470 [ich_pata_66] = /* ICH controllers up to 66MHz */
471 {
472 .flags = PIIX_PATA_FLAGS,
473 .pio_mask = 0x1f, /* pio 0-4 */
474 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
475 .udma_mask = ATA_UDMA4,
476 .port_ops = &ich_pata_ops,
477 },
478
479 [ich_pata_100] =
480 {
481 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
482 .pio_mask = 0x1f, /* pio0-4 */
483 .mwdma_mask = 0x06, /* mwdma1-2 */
484 .udma_mask = ATA_UDMA5, /* udma0-5 */
485 .port_ops = &ich_pata_ops,
486 },
487
488 [ich5_sata] =
489 {
490 .flags = PIIX_SATA_FLAGS,
491 .pio_mask = 0x1f, /* pio0-4 */
492 .mwdma_mask = 0x07, /* mwdma0-2 */
493 .udma_mask = ATA_UDMA6,
494 .port_ops = &piix_sata_ops,
495 },
496
497 [ich6_sata] =
498 {
499 .flags = PIIX_SATA_FLAGS,
500 .pio_mask = 0x1f, /* pio0-4 */
501 .mwdma_mask = 0x07, /* mwdma0-2 */
502 .udma_mask = ATA_UDMA6,
503 .port_ops = &piix_sata_ops,
504 },
505
506 [ich6m_sata] =
507 {
508 .flags = PIIX_SATA_FLAGS,
509 .pio_mask = 0x1f, /* pio0-4 */
510 .mwdma_mask = 0x07, /* mwdma0-2 */
511 .udma_mask = ATA_UDMA6,
512 .port_ops = &piix_sata_ops,
513 },
514
515 [ich8_sata] =
516 {
517 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
518 .pio_mask = 0x1f, /* pio0-4 */
519 .mwdma_mask = 0x07, /* mwdma0-2 */
520 .udma_mask = ATA_UDMA6,
521 .port_ops = &piix_sata_ops,
522 },
523
524 [ich8_2port_sata] =
525 {
526 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
527 .pio_mask = 0x1f, /* pio0-4 */
528 .mwdma_mask = 0x07, /* mwdma0-2 */
529 .udma_mask = ATA_UDMA6,
530 .port_ops = &piix_sata_ops,
531 },
532
533 [tolapai_sata] =
534 {
535 .flags = PIIX_SATA_FLAGS,
536 .pio_mask = 0x1f, /* pio0-4 */
537 .mwdma_mask = 0x07, /* mwdma0-2 */
538 .udma_mask = ATA_UDMA6,
539 .port_ops = &piix_sata_ops,
540 },
541
542 [ich8m_apple_sata] =
543 {
544 .flags = PIIX_SATA_FLAGS,
545 .pio_mask = 0x1f, /* pio0-4 */
546 .mwdma_mask = 0x07, /* mwdma0-2 */
547 .udma_mask = ATA_UDMA6,
548 .port_ops = &piix_sata_ops,
549 },
550
551 [piix_pata_vmw] =
552 {
553 .flags = PIIX_PATA_FLAGS,
554 .pio_mask = 0x1f, /* pio0-4 */
555 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
556 .udma_mask = ATA_UDMA_MASK_40C,
557 .port_ops = &piix_vmw_ops,
558 },
559
560 };
561
562 static struct pci_bits piix_enable_bits[] = {
563 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
564 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
565 };
566
567 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
568 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
569 MODULE_LICENSE("GPL");
570 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
571 MODULE_VERSION(DRV_VERSION);
572
573 struct ich_laptop {
574 u16 device;
575 u16 subvendor;
576 u16 subdevice;
577 };
578
579 /*
580 * List of laptops that use short cables rather than 80 wire
581 */
582
583 static const struct ich_laptop ich_laptop[] = {
584 /* devid, subvendor, subdev */
585 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
586 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
587 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
588 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
589 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
590 { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */
591 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
592 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
593 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
594 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
595 /* end marker */
596 { 0, }
597 };
598
599 /**
600 * ich_pata_cable_detect - Probe host controller cable detect info
601 * @ap: Port for which cable detect info is desired
602 *
603 * Read 80c cable indicator from ATA PCI device's PCI config
604 * register. This register is normally set by firmware (BIOS).
605 *
606 * LOCKING:
607 * None (inherited from caller).
608 */
609
610 static int ich_pata_cable_detect(struct ata_port *ap)
611 {
612 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
613 const struct ich_laptop *lap = &ich_laptop[0];
614 u8 tmp, mask;
615
616 /* Check for specials - Acer Aspire 5602WLMi */
617 while (lap->device) {
618 if (lap->device == pdev->device &&
619 lap->subvendor == pdev->subsystem_vendor &&
620 lap->subdevice == pdev->subsystem_device)
621 return ATA_CBL_PATA40_SHORT;
622
623 lap++;
624 }
625
626 /* check BIOS cable detect results */
627 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
628 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
629 if ((tmp & mask) == 0)
630 return ATA_CBL_PATA40;
631 return ATA_CBL_PATA80;
632 }
633
634 /**
635 * piix_pata_prereset - prereset for PATA host controller
636 * @link: Target link
637 * @deadline: deadline jiffies for the operation
638 *
639 * LOCKING:
640 * None (inherited from caller).
641 */
642 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
643 {
644 struct ata_port *ap = link->ap;
645 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
646
647 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
648 return -ENOENT;
649 return ata_sff_prereset(link, deadline);
650 }
651
652 /**
653 * piix_set_piomode - Initialize host controller PATA PIO timings
654 * @ap: Port whose timings we are configuring
655 * @adev: um
656 *
657 * Set PIO mode for device, in host controller PCI config space.
658 *
659 * LOCKING:
660 * None (inherited from caller).
661 */
662
663 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
664 {
665 unsigned int pio = adev->pio_mode - XFER_PIO_0;
666 struct pci_dev *dev = to_pci_dev(ap->host->dev);
667 unsigned int is_slave = (adev->devno != 0);
668 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
669 unsigned int slave_port = 0x44;
670 u16 master_data;
671 u8 slave_data;
672 u8 udma_enable;
673 int control = 0;
674
675 /*
676 * See Intel Document 298600-004 for the timing programing rules
677 * for ICH controllers.
678 */
679
680 static const /* ISP RTC */
681 u8 timings[][2] = { { 0, 0 },
682 { 0, 0 },
683 { 1, 0 },
684 { 2, 1 },
685 { 2, 3 }, };
686
687 if (pio >= 2)
688 control |= 1; /* TIME1 enable */
689 if (ata_pio_need_iordy(adev))
690 control |= 2; /* IE enable */
691
692 /* Intel specifies that the PPE functionality is for disk only */
693 if (adev->class == ATA_DEV_ATA)
694 control |= 4; /* PPE enable */
695
696 /* PIO configuration clears DTE unconditionally. It will be
697 * programmed in set_dmamode which is guaranteed to be called
698 * after set_piomode if any DMA mode is available.
699 */
700 pci_read_config_word(dev, master_port, &master_data);
701 if (is_slave) {
702 /* clear TIME1|IE1|PPE1|DTE1 */
703 master_data &= 0xff0f;
704 /* Enable SITRE (separate slave timing register) */
705 master_data |= 0x4000;
706 /* enable PPE1, IE1 and TIME1 as needed */
707 master_data |= (control << 4);
708 pci_read_config_byte(dev, slave_port, &slave_data);
709 slave_data &= (ap->port_no ? 0x0f : 0xf0);
710 /* Load the timing nibble for this slave */
711 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
712 << (ap->port_no ? 4 : 0);
713 } else {
714 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
715 master_data &= 0xccf0;
716 /* Enable PPE, IE and TIME as appropriate */
717 master_data |= control;
718 /* load ISP and RCT */
719 master_data |=
720 (timings[pio][0] << 12) |
721 (timings[pio][1] << 8);
722 }
723 pci_write_config_word(dev, master_port, master_data);
724 if (is_slave)
725 pci_write_config_byte(dev, slave_port, slave_data);
726
727 /* Ensure the UDMA bit is off - it will be turned back on if
728 UDMA is selected */
729
730 if (ap->udma_mask) {
731 pci_read_config_byte(dev, 0x48, &udma_enable);
732 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
733 pci_write_config_byte(dev, 0x48, udma_enable);
734 }
735 }
736
737 /**
738 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
739 * @ap: Port whose timings we are configuring
740 * @adev: Drive in question
741 * @udma: udma mode, 0 - 6
742 * @isich: set if the chip is an ICH device
743 *
744 * Set UDMA mode for device, in host controller PCI config space.
745 *
746 * LOCKING:
747 * None (inherited from caller).
748 */
749
750 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
751 {
752 struct pci_dev *dev = to_pci_dev(ap->host->dev);
753 u8 master_port = ap->port_no ? 0x42 : 0x40;
754 u16 master_data;
755 u8 speed = adev->dma_mode;
756 int devid = adev->devno + 2 * ap->port_no;
757 u8 udma_enable = 0;
758
759 static const /* ISP RTC */
760 u8 timings[][2] = { { 0, 0 },
761 { 0, 0 },
762 { 1, 0 },
763 { 2, 1 },
764 { 2, 3 }, };
765
766 pci_read_config_word(dev, master_port, &master_data);
767 if (ap->udma_mask)
768 pci_read_config_byte(dev, 0x48, &udma_enable);
769
770 if (speed >= XFER_UDMA_0) {
771 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
772 u16 udma_timing;
773 u16 ideconf;
774 int u_clock, u_speed;
775
776 /*
777 * UDMA is handled by a combination of clock switching and
778 * selection of dividers
779 *
780 * Handy rule: Odd modes are UDMATIMx 01, even are 02
781 * except UDMA0 which is 00
782 */
783 u_speed = min(2 - (udma & 1), udma);
784 if (udma == 5)
785 u_clock = 0x1000; /* 100Mhz */
786 else if (udma > 2)
787 u_clock = 1; /* 66Mhz */
788 else
789 u_clock = 0; /* 33Mhz */
790
791 udma_enable |= (1 << devid);
792
793 /* Load the CT/RP selection */
794 pci_read_config_word(dev, 0x4A, &udma_timing);
795 udma_timing &= ~(3 << (4 * devid));
796 udma_timing |= u_speed << (4 * devid);
797 pci_write_config_word(dev, 0x4A, udma_timing);
798
799 if (isich) {
800 /* Select a 33/66/100Mhz clock */
801 pci_read_config_word(dev, 0x54, &ideconf);
802 ideconf &= ~(0x1001 << devid);
803 ideconf |= u_clock << devid;
804 /* For ICH or later we should set bit 10 for better
805 performance (WR_PingPong_En) */
806 pci_write_config_word(dev, 0x54, ideconf);
807 }
808 } else {
809 /*
810 * MWDMA is driven by the PIO timings. We must also enable
811 * IORDY unconditionally along with TIME1. PPE has already
812 * been set when the PIO timing was set.
813 */
814 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
815 unsigned int control;
816 u8 slave_data;
817 const unsigned int needed_pio[3] = {
818 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
819 };
820 int pio = needed_pio[mwdma] - XFER_PIO_0;
821
822 control = 3; /* IORDY|TIME1 */
823
824 /* If the drive MWDMA is faster than it can do PIO then
825 we must force PIO into PIO0 */
826
827 if (adev->pio_mode < needed_pio[mwdma])
828 /* Enable DMA timing only */
829 control |= 8; /* PIO cycles in PIO0 */
830
831 if (adev->devno) { /* Slave */
832 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
833 master_data |= control << 4;
834 pci_read_config_byte(dev, 0x44, &slave_data);
835 slave_data &= (ap->port_no ? 0x0f : 0xf0);
836 /* Load the matching timing */
837 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
838 pci_write_config_byte(dev, 0x44, slave_data);
839 } else { /* Master */
840 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
841 and master timing bits */
842 master_data |= control;
843 master_data |=
844 (timings[pio][0] << 12) |
845 (timings[pio][1] << 8);
846 }
847
848 if (ap->udma_mask) {
849 udma_enable &= ~(1 << devid);
850 pci_write_config_word(dev, master_port, master_data);
851 }
852 }
853 /* Don't scribble on 0x48 if the controller does not support UDMA */
854 if (ap->udma_mask)
855 pci_write_config_byte(dev, 0x48, udma_enable);
856 }
857
858 /**
859 * piix_set_dmamode - Initialize host controller PATA DMA timings
860 * @ap: Port whose timings we are configuring
861 * @adev: um
862 *
863 * Set MW/UDMA mode for device, in host controller PCI config space.
864 *
865 * LOCKING:
866 * None (inherited from caller).
867 */
868
869 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
870 {
871 do_pata_set_dmamode(ap, adev, 0);
872 }
873
874 /**
875 * ich_set_dmamode - Initialize host controller PATA DMA timings
876 * @ap: Port whose timings we are configuring
877 * @adev: um
878 *
879 * Set MW/UDMA mode for device, in host controller PCI config space.
880 *
881 * LOCKING:
882 * None (inherited from caller).
883 */
884
885 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
886 {
887 do_pata_set_dmamode(ap, adev, 1);
888 }
889
890 /*
891 * Serial ATA Index/Data Pair Superset Registers access
892 *
893 * Beginning from ICH8, there's a sane way to access SCRs using index
894 * and data register pair located at BAR5 which means that we have
895 * separate SCRs for master and slave. This is handled using libata
896 * slave_link facility.
897 */
898 static const int piix_sidx_map[] = {
899 [SCR_STATUS] = 0,
900 [SCR_ERROR] = 2,
901 [SCR_CONTROL] = 1,
902 };
903
904 static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
905 {
906 struct ata_port *ap = link->ap;
907 struct piix_host_priv *hpriv = ap->host->private_data;
908
909 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
910 hpriv->sidpr + PIIX_SIDPR_IDX);
911 }
912
913 static int piix_sidpr_scr_read(struct ata_link *link,
914 unsigned int reg, u32 *val)
915 {
916 struct piix_host_priv *hpriv = link->ap->host->private_data;
917
918 if (reg >= ARRAY_SIZE(piix_sidx_map))
919 return -EINVAL;
920
921 piix_sidpr_sel(link, reg);
922 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
923 return 0;
924 }
925
926 static int piix_sidpr_scr_write(struct ata_link *link,
927 unsigned int reg, u32 val)
928 {
929 struct piix_host_priv *hpriv = link->ap->host->private_data;
930
931 if (reg >= ARRAY_SIZE(piix_sidx_map))
932 return -EINVAL;
933
934 piix_sidpr_sel(link, reg);
935 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
936 return 0;
937 }
938
939 #ifdef CONFIG_PM
940 static int piix_broken_suspend(void)
941 {
942 static const struct dmi_system_id sysids[] = {
943 {
944 .ident = "TECRA M3",
945 .matches = {
946 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
947 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
948 },
949 },
950 {
951 .ident = "TECRA M3",
952 .matches = {
953 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
954 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
955 },
956 },
957 {
958 .ident = "TECRA M4",
959 .matches = {
960 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
961 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
962 },
963 },
964 {
965 .ident = "TECRA M4",
966 .matches = {
967 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
968 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
969 },
970 },
971 {
972 .ident = "TECRA M5",
973 .matches = {
974 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
975 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
976 },
977 },
978 {
979 .ident = "TECRA M6",
980 .matches = {
981 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
982 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
983 },
984 },
985 {
986 .ident = "TECRA M7",
987 .matches = {
988 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
989 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
990 },
991 },
992 {
993 .ident = "TECRA A8",
994 .matches = {
995 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
996 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
997 },
998 },
999 {
1000 .ident = "Satellite R20",
1001 .matches = {
1002 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1003 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
1004 },
1005 },
1006 {
1007 .ident = "Satellite R25",
1008 .matches = {
1009 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1010 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
1011 },
1012 },
1013 {
1014 .ident = "Satellite U200",
1015 .matches = {
1016 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1017 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
1018 },
1019 },
1020 {
1021 .ident = "Satellite U200",
1022 .matches = {
1023 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1024 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
1025 },
1026 },
1027 {
1028 .ident = "Satellite Pro U200",
1029 .matches = {
1030 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1031 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
1032 },
1033 },
1034 {
1035 .ident = "Satellite U205",
1036 .matches = {
1037 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1038 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
1039 },
1040 },
1041 {
1042 .ident = "SATELLITE U205",
1043 .matches = {
1044 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1045 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
1046 },
1047 },
1048 {
1049 .ident = "Portege M500",
1050 .matches = {
1051 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1052 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
1053 },
1054 },
1055
1056 { } /* terminate list */
1057 };
1058 static const char *oemstrs[] = {
1059 "Tecra M3,",
1060 };
1061 int i;
1062
1063 if (dmi_check_system(sysids))
1064 return 1;
1065
1066 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
1067 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
1068 return 1;
1069
1070 return 0;
1071 }
1072
1073 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1074 {
1075 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1076 unsigned long flags;
1077 int rc = 0;
1078
1079 rc = ata_host_suspend(host, mesg);
1080 if (rc)
1081 return rc;
1082
1083 /* Some braindamaged ACPI suspend implementations expect the
1084 * controller to be awake on entry; otherwise, it burns cpu
1085 * cycles and power trying to do something to the sleeping
1086 * beauty.
1087 */
1088 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
1089 pci_save_state(pdev);
1090
1091 /* mark its power state as "unknown", since we don't
1092 * know if e.g. the BIOS will change its device state
1093 * when we suspend.
1094 */
1095 if (pdev->current_state == PCI_D0)
1096 pdev->current_state = PCI_UNKNOWN;
1097
1098 /* tell resume that it's waking up from broken suspend */
1099 spin_lock_irqsave(&host->lock, flags);
1100 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1101 spin_unlock_irqrestore(&host->lock, flags);
1102 } else
1103 ata_pci_device_do_suspend(pdev, mesg);
1104
1105 return 0;
1106 }
1107
1108 static int piix_pci_device_resume(struct pci_dev *pdev)
1109 {
1110 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1111 unsigned long flags;
1112 int rc;
1113
1114 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1115 spin_lock_irqsave(&host->lock, flags);
1116 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1117 spin_unlock_irqrestore(&host->lock, flags);
1118
1119 pci_set_power_state(pdev, PCI_D0);
1120 pci_restore_state(pdev);
1121
1122 /* PCI device wasn't disabled during suspend. Use
1123 * pci_reenable_device() to avoid affecting the enable
1124 * count.
1125 */
1126 rc = pci_reenable_device(pdev);
1127 if (rc)
1128 dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
1129 "device after resume (%d)\n", rc);
1130 } else
1131 rc = ata_pci_device_do_resume(pdev);
1132
1133 if (rc == 0)
1134 ata_host_resume(host);
1135
1136 return rc;
1137 }
1138 #endif
1139
1140 static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1141 {
1142 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1143 }
1144
1145 #define AHCI_PCI_BAR 5
1146 #define AHCI_GLOBAL_CTL 0x04
1147 #define AHCI_ENABLE (1 << 31)
1148 static int piix_disable_ahci(struct pci_dev *pdev)
1149 {
1150 void __iomem *mmio;
1151 u32 tmp;
1152 int rc = 0;
1153
1154 /* BUG: pci_enable_device has not yet been called. This
1155 * works because this device is usually set up by BIOS.
1156 */
1157
1158 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1159 !pci_resource_len(pdev, AHCI_PCI_BAR))
1160 return 0;
1161
1162 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1163 if (!mmio)
1164 return -ENOMEM;
1165
1166 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1167 if (tmp & AHCI_ENABLE) {
1168 tmp &= ~AHCI_ENABLE;
1169 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1170
1171 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1172 if (tmp & AHCI_ENABLE)
1173 rc = -EIO;
1174 }
1175
1176 pci_iounmap(pdev, mmio);
1177 return rc;
1178 }
1179
1180 /**
1181 * piix_check_450nx_errata - Check for problem 450NX setup
1182 * @ata_dev: the PCI device to check
1183 *
1184 * Check for the present of 450NX errata #19 and errata #25. If
1185 * they are found return an error code so we can turn off DMA
1186 */
1187
1188 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1189 {
1190 struct pci_dev *pdev = NULL;
1191 u16 cfg;
1192 int no_piix_dma = 0;
1193
1194 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1195 /* Look for 450NX PXB. Check for problem configurations
1196 A PCI quirk checks bit 6 already */
1197 pci_read_config_word(pdev, 0x41, &cfg);
1198 /* Only on the original revision: IDE DMA can hang */
1199 if (pdev->revision == 0x00)
1200 no_piix_dma = 1;
1201 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1202 else if (cfg & (1<<14) && pdev->revision < 5)
1203 no_piix_dma = 2;
1204 }
1205 if (no_piix_dma)
1206 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
1207 if (no_piix_dma == 2)
1208 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1209 return no_piix_dma;
1210 }
1211
1212 static void __devinit piix_init_pcs(struct ata_host *host,
1213 const struct piix_map_db *map_db)
1214 {
1215 struct pci_dev *pdev = to_pci_dev(host->dev);
1216 u16 pcs, new_pcs;
1217
1218 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1219
1220 new_pcs = pcs | map_db->port_enable;
1221
1222 if (new_pcs != pcs) {
1223 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1224 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1225 msleep(150);
1226 }
1227 }
1228
1229 static const int *__devinit piix_init_sata_map(struct pci_dev *pdev,
1230 struct ata_port_info *pinfo,
1231 const struct piix_map_db *map_db)
1232 {
1233 const int *map;
1234 int i, invalid_map = 0;
1235 u8 map_value;
1236
1237 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1238
1239 map = map_db->map[map_value & map_db->mask];
1240
1241 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1242 for (i = 0; i < 4; i++) {
1243 switch (map[i]) {
1244 case RV:
1245 invalid_map = 1;
1246 printk(" XX");
1247 break;
1248
1249 case NA:
1250 printk(" --");
1251 break;
1252
1253 case IDE:
1254 WARN_ON((i & 1) || map[i + 1] != IDE);
1255 pinfo[i / 2] = piix_port_info[ich_pata_100];
1256 i++;
1257 printk(" IDE IDE");
1258 break;
1259
1260 default:
1261 printk(" P%d", map[i]);
1262 if (i & 1)
1263 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1264 break;
1265 }
1266 }
1267 printk(" ]\n");
1268
1269 if (invalid_map)
1270 dev_printk(KERN_ERR, &pdev->dev,
1271 "invalid MAP value %u\n", map_value);
1272
1273 return map;
1274 }
1275
1276 static int __devinit piix_init_sidpr(struct ata_host *host)
1277 {
1278 struct pci_dev *pdev = to_pci_dev(host->dev);
1279 struct piix_host_priv *hpriv = host->private_data;
1280 struct ata_link *link0 = &host->ports[0]->link;
1281 u32 scontrol;
1282 int i, rc;
1283
1284 /* check for availability */
1285 for (i = 0; i < 4; i++)
1286 if (hpriv->map[i] == IDE)
1287 return 0;
1288
1289 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1290 return 0;
1291
1292 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1293 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1294 return 0;
1295
1296 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1297 return 0;
1298
1299 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1300
1301 /* SCR access via SIDPR doesn't work on some configurations.
1302 * Give it a test drive by inhibiting power save modes which
1303 * we'll do anyway.
1304 */
1305 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1306
1307 /* if IPM is already 3, SCR access is probably working. Don't
1308 * un-inhibit power save modes as BIOS might have inhibited
1309 * them for a reason.
1310 */
1311 if ((scontrol & 0xf00) != 0x300) {
1312 scontrol |= 0x300;
1313 piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
1314 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1315
1316 if ((scontrol & 0xf00) != 0x300) {
1317 dev_printk(KERN_INFO, host->dev, "SCR access via "
1318 "SIDPR is available but doesn't work\n");
1319 return 0;
1320 }
1321 }
1322
1323 /* okay, SCRs available, set ops and ask libata for slave_link */
1324 for (i = 0; i < 2; i++) {
1325 struct ata_port *ap = host->ports[i];
1326
1327 ap->ops = &piix_sidpr_sata_ops;
1328
1329 if (ap->flags & ATA_FLAG_SLAVE_POSS) {
1330 rc = ata_slave_link_init(ap);
1331 if (rc)
1332 return rc;
1333 }
1334 }
1335
1336 return 0;
1337 }
1338
1339 static void piix_iocfg_bit18_quirk(struct pci_dev *pdev)
1340 {
1341 static const struct dmi_system_id sysids[] = {
1342 {
1343 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1344 * isn't used to boot the system which
1345 * disables the channel.
1346 */
1347 .ident = "M570U",
1348 .matches = {
1349 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1350 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1351 },
1352 },
1353
1354 { } /* terminate list */
1355 };
1356 u32 iocfg;
1357
1358 if (!dmi_check_system(sysids))
1359 return;
1360
1361 /* The datasheet says that bit 18 is NOOP but certain systems
1362 * seem to use it to disable a channel. Clear the bit on the
1363 * affected systems.
1364 */
1365 pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg);
1366 if (iocfg & (1 << 18)) {
1367 dev_printk(KERN_INFO, &pdev->dev,
1368 "applying IOCFG bit18 quirk\n");
1369 iocfg &= ~(1 << 18);
1370 pci_write_config_dword(pdev, PIIX_IOCFG, iocfg);
1371 }
1372 }
1373
1374 /**
1375 * piix_init_one - Register PIIX ATA PCI device with kernel services
1376 * @pdev: PCI device to register
1377 * @ent: Entry in piix_pci_tbl matching with @pdev
1378 *
1379 * Called from kernel PCI layer. We probe for combined mode (sigh),
1380 * and then hand over control to libata, for it to do the rest.
1381 *
1382 * LOCKING:
1383 * Inherited from PCI layer (may sleep).
1384 *
1385 * RETURNS:
1386 * Zero on success, or -ERRNO value.
1387 */
1388
1389 static int __devinit piix_init_one(struct pci_dev *pdev,
1390 const struct pci_device_id *ent)
1391 {
1392 static int printed_version;
1393 struct device *dev = &pdev->dev;
1394 struct ata_port_info port_info[2];
1395 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1396 unsigned long port_flags;
1397 struct ata_host *host;
1398 struct piix_host_priv *hpriv;
1399 int rc;
1400
1401 if (!printed_version++)
1402 dev_printk(KERN_DEBUG, &pdev->dev,
1403 "version " DRV_VERSION "\n");
1404
1405 /* no hotplugging support (FIXME) */
1406 if (!in_module_init)
1407 return -ENODEV;
1408
1409 port_info[0] = piix_port_info[ent->driver_data];
1410 port_info[1] = piix_port_info[ent->driver_data];
1411
1412 port_flags = port_info[0].flags;
1413
1414 /* enable device and prepare host */
1415 rc = pcim_enable_device(pdev);
1416 if (rc)
1417 return rc;
1418
1419 /* ICH6R may be driven by either ata_piix or ahci driver
1420 * regardless of BIOS configuration. Make sure AHCI mode is
1421 * off.
1422 */
1423 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
1424 rc = piix_disable_ahci(pdev);
1425 if (rc)
1426 return rc;
1427 }
1428
1429 /* SATA map init can change port_info, do it before prepping host */
1430 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1431 if (!hpriv)
1432 return -ENOMEM;
1433
1434 if (port_flags & ATA_FLAG_SATA)
1435 hpriv->map = piix_init_sata_map(pdev, port_info,
1436 piix_map_db_table[ent->driver_data]);
1437
1438 rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
1439 if (rc)
1440 return rc;
1441 host->private_data = hpriv;
1442
1443 /* initialize controller */
1444 if (port_flags & ATA_FLAG_SATA) {
1445 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1446 rc = piix_init_sidpr(host);
1447 if (rc)
1448 return rc;
1449 }
1450
1451 /* apply IOCFG bit18 quirk */
1452 piix_iocfg_bit18_quirk(pdev);
1453
1454 /* On ICH5, some BIOSen disable the interrupt using the
1455 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1456 * On ICH6, this bit has the same effect, but only when
1457 * MSI is disabled (and it is disabled, as we don't use
1458 * message-signalled interrupts currently).
1459 */
1460 if (port_flags & PIIX_FLAG_CHECKINTR)
1461 pci_intx(pdev, 1);
1462
1463 if (piix_check_450nx_errata(pdev)) {
1464 /* This writes into the master table but it does not
1465 really matter for this errata as we will apply it to
1466 all the PIIX devices on the board */
1467 host->ports[0]->mwdma_mask = 0;
1468 host->ports[0]->udma_mask = 0;
1469 host->ports[1]->mwdma_mask = 0;
1470 host->ports[1]->udma_mask = 0;
1471 }
1472
1473 pci_set_master(pdev);
1474 return ata_pci_sff_activate_host(host, ata_sff_interrupt, &piix_sht);
1475 }
1476
1477 static int __init piix_init(void)
1478 {
1479 int rc;
1480
1481 DPRINTK("pci_register_driver\n");
1482 rc = pci_register_driver(&piix_pci_driver);
1483 if (rc)
1484 return rc;
1485
1486 in_module_init = 0;
1487
1488 DPRINTK("done\n");
1489 return 0;
1490 }
1491
1492 static void __exit piix_exit(void)
1493 {
1494 pci_unregister_driver(&piix_pci_driver);
1495 }
1496
1497 module_init(piix_init);
1498 module_exit(piix_exit);
Support for the Chinese Samsung S3C2440 based development boards