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x86: fix es7000 compiling
[linux-2.6/mini2440.git] / drivers / video / s3fb.c
blob4dcec48a1d78949e07a78663213e035ec248a5f5
1 /*
2 * linux/drivers/video/s3fb.c -- Frame buffer device driver for S3 Trio/Virge
3 *
4 * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive for
8 * more details.
9 *
10 * Code is based on David Boucher's viafb (http://davesdomain.org.uk/viafb/)
11 * which is based on the code of neofb.
12 */
13
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/errno.h>
17 #include <linux/string.h>
18 #include <linux/mm.h>
19 #include <linux/tty.h>
20 #include <linux/slab.h>
21 #include <linux/delay.h>
22 #include <linux/fb.h>
23 #include <linux/svga.h>
24 #include <linux/init.h>
25 #include <linux/pci.h>
26 #include <linux/console.h> /* Why should fb driver call console functions? because acquire_console_sem() */
27 #include <video/vga.h>
28
29 #ifdef CONFIG_MTRR
30 #include <asm/mtrr.h>
31 #endif
32
33 struct s3fb_info {
34 int chip, rev, mclk_freq;
35 int mtrr_reg;
36 struct vgastate state;
37 struct mutex open_lock;
38 unsigned int ref_count;
39 u32 pseudo_palette[16];
40 };
41
42
43 /* ------------------------------------------------------------------------- */
44
45 static const struct svga_fb_format s3fb_formats[] = {
46 { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
47 FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 16},
48 { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
49 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16},
50 { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 1,
51 FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16},
52 { 8, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
53 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 4, 8},
54 {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0,
55 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4},
56 {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0,
57 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4},
58 {24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
59 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2},
60 {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
61 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2},
62 SVGA_FORMAT_END
63 };
64
65
66 static const struct svga_pll s3_pll = {3, 129, 3, 33, 0, 3,
67 35000, 240000, 14318};
68
69 static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512};
70
71 static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64", "S3 Trio64V+",
72 "S3 Trio64UV+", "S3 Trio64V2/DX", "S3 Trio64V2/GX",
73 "S3 Plato/PX", "S3 Aurora64VP", "S3 Virge",
74 "S3 Virge/VX", "S3 Virge/DX", "S3 Virge/GX",
75 "S3 Virge/GX2", "S3 Virge/GX2P", "S3 Virge/GX2P"};
76
77 #define CHIP_UNKNOWN 0x00
78 #define CHIP_732_TRIO32 0x01
79 #define CHIP_764_TRIO64 0x02
80 #define CHIP_765_TRIO64VP 0x03
81 #define CHIP_767_TRIO64UVP 0x04
82 #define CHIP_775_TRIO64V2_DX 0x05
83 #define CHIP_785_TRIO64V2_GX 0x06
84 #define CHIP_551_PLATO_PX 0x07
85 #define CHIP_M65_AURORA64VP 0x08
86 #define CHIP_325_VIRGE 0x09
87 #define CHIP_988_VIRGE_VX 0x0A
88 #define CHIP_375_VIRGE_DX 0x0B
89 #define CHIP_385_VIRGE_GX 0x0C
90 #define CHIP_356_VIRGE_GX2 0x0D
91 #define CHIP_357_VIRGE_GX2P 0x0E
92 #define CHIP_359_VIRGE_GX2P 0x0F
93
94 #define CHIP_XXX_TRIO 0x80
95 #define CHIP_XXX_TRIO64V2_DXGX 0x81
96 #define CHIP_XXX_VIRGE_DXGX 0x82
97
98 #define CHIP_UNDECIDED_FLAG 0x80
99 #define CHIP_MASK 0xFF
100
101 /* CRT timing register sets */
102
103 static const struct vga_regset s3_h_total_regs[] = {{0x00, 0, 7}, {0x5D, 0, 0}, VGA_REGSET_END};
104 static const struct vga_regset s3_h_display_regs[] = {{0x01, 0, 7}, {0x5D, 1, 1}, VGA_REGSET_END};
105 static const struct vga_regset s3_h_blank_start_regs[] = {{0x02, 0, 7}, {0x5D, 2, 2}, VGA_REGSET_END};
106 static const struct vga_regset s3_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7}, VGA_REGSET_END};
107 static const struct vga_regset s3_h_sync_start_regs[] = {{0x04, 0, 7}, {0x5D, 4, 4}, VGA_REGSET_END};
108 static const struct vga_regset s3_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END};
109
110 static const struct vga_regset s3_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x5E, 0, 0}, VGA_REGSET_END};
111 static const struct vga_regset s3_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x5E, 1, 1}, VGA_REGSET_END};
112 static const struct vga_regset s3_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x5E, 2, 2}, VGA_REGSET_END};
113 static const struct vga_regset s3_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END};
114 static const struct vga_regset s3_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x5E, 4, 4}, VGA_REGSET_END};
115 static const struct vga_regset s3_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END};
116
117 static const struct vga_regset s3_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x5E, 6, 6}, VGA_REGSET_END};
118 static const struct vga_regset s3_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x31, 4, 5}, {0x51, 0, 1}, VGA_REGSET_END};
119 static const struct vga_regset s3_offset_regs[] = {{0x13, 0, 7}, {0x51, 4, 5}, VGA_REGSET_END}; /* set 0x43 bit 2 to 0 */
120
121 static const struct svga_timing_regs s3_timing_regs = {
122 s3_h_total_regs, s3_h_display_regs, s3_h_blank_start_regs,
123 s3_h_blank_end_regs, s3_h_sync_start_regs, s3_h_sync_end_regs,
124 s3_v_total_regs, s3_v_display_regs, s3_v_blank_start_regs,
125 s3_v_blank_end_regs, s3_v_sync_start_regs, s3_v_sync_end_regs,
126 };
127
128
129 /* ------------------------------------------------------------------------- */
130
131 /* Module parameters */
132
133
134 static char *mode_option __devinitdata = "640x480-8@60";
135
136 #ifdef CONFIG_MTRR
137 static int mtrr __devinitdata = 1;
138 #endif
139
140 static int fasttext = 1;
141
142
143 MODULE_AUTHOR("(c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>");
144 MODULE_LICENSE("GPL");
145 MODULE_DESCRIPTION("fbdev driver for S3 Trio/Virge");
146
147 module_param(mode_option, charp, 0444);
148 MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)");
149 module_param_named(mode, mode_option, charp, 0444);
150 MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc) (deprecated)");
151
152 #ifdef CONFIG_MTRR
153 module_param(mtrr, int, 0444);
154 MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");
155 #endif
156
157 module_param(fasttext, int, 0644);
158 MODULE_PARM_DESC(fasttext, "Enable S3 fast text mode (1=enable, 0=disable, default=1)");
159
160
161 /* ------------------------------------------------------------------------- */
162
163 /* Set font in S3 fast text mode */
164
165 static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map)
166 {
167 const u8 *font = map->data;
168 u8 __iomem *fb = (u8 __iomem *) info->screen_base;
169 int i, c;
170
171 if ((map->width != 8) || (map->height != 16) ||
172 (map->depth != 1) || (map->length != 256)) {
173 printk(KERN_ERR "fb%d: unsupported font parameters: width %d, height %d, depth %d, length %d\n",
174 info->node, map->width, map->height, map->depth, map->length);
175 return;
176 }
177
178 fb += 2;
179 for (i = 0; i < map->height; i++) {
180 for (c = 0; c < map->length; c++) {
181 fb_writeb(font[c * map->height + i], fb + c * 4);
182 }
183 fb += 1024;
184 }
185 }
186
187 static struct fb_tile_ops s3fb_tile_ops = {
188 .fb_settile = svga_settile,
189 .fb_tilecopy = svga_tilecopy,
190 .fb_tilefill = svga_tilefill,
191 .fb_tileblit = svga_tileblit,
192 .fb_tilecursor = svga_tilecursor,
193 .fb_get_tilemax = svga_get_tilemax,
194 };
195
196 static struct fb_tile_ops s3fb_fast_tile_ops = {
197 .fb_settile = s3fb_settile_fast,
198 .fb_tilecopy = svga_tilecopy,
199 .fb_tilefill = svga_tilefill,
200 .fb_tileblit = svga_tileblit,
201 .fb_tilecursor = svga_tilecursor,
202 .fb_get_tilemax = svga_get_tilemax,
203 };
204
205
206 /* ------------------------------------------------------------------------- */
207
208 /* image data is MSB-first, fb structure is MSB-first too */
209 static inline u32 expand_color(u32 c)
210 {
211 return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF;
212 }
213
214 /* s3fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */
215 static void s3fb_iplan_imageblit(struct fb_info *info, const struct fb_image *image)
216 {
217 u32 fg = expand_color(image->fg_color);
218 u32 bg = expand_color(image->bg_color);
219 const u8 *src1, *src;
220 u8 __iomem *dst1;
221 u32 __iomem *dst;
222 u32 val;
223 int x, y;
224
225 src1 = image->data;
226 dst1 = info->screen_base + (image->dy * info->fix.line_length)
227 + ((image->dx / 8) * 4);
228
229 for (y = 0; y < image->height; y++) {
230 src = src1;
231 dst = (u32 __iomem *) dst1;
232 for (x = 0; x < image->width; x += 8) {
233 val = *(src++) * 0x01010101;
234 val = (val & fg) | (~val & bg);
235 fb_writel(val, dst++);
236 }
237 src1 += image->width / 8;
238 dst1 += info->fix.line_length;
239 }
240
241 }
242
243 /* s3fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */
244 static void s3fb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
245 {
246 u32 fg = expand_color(rect->color);
247 u8 __iomem *dst1;
248 u32 __iomem *dst;
249 int x, y;
250
251 dst1 = info->screen_base + (rect->dy * info->fix.line_length)
252 + ((rect->dx / 8) * 4);
253
254 for (y = 0; y < rect->height; y++) {
255 dst = (u32 __iomem *) dst1;
256 for (x = 0; x < rect->width; x += 8) {
257 fb_writel(fg, dst++);
258 }
259 dst1 += info->fix.line_length;
260 }
261 }
262
263
264 /* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */
265 static inline u32 expand_pixel(u32 c)
266 {
267 return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) |
268 ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF;
269 }
270
271 /* s3fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */
272 static void s3fb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image)
273 {
274 u32 fg = image->fg_color * 0x11111111;
275 u32 bg = image->bg_color * 0x11111111;
276 const u8 *src1, *src;
277 u8 __iomem *dst1;
278 u32 __iomem *dst;
279 u32 val;
280 int x, y;
281
282 src1 = image->data;
283 dst1 = info->screen_base + (image->dy * info->fix.line_length)
284 + ((image->dx / 8) * 4);
285
286 for (y = 0; y < image->height; y++) {
287 src = src1;
288 dst = (u32 __iomem *) dst1;
289 for (x = 0; x < image->width; x += 8) {
290 val = expand_pixel(*(src++));
291 val = (val & fg) | (~val & bg);
292 fb_writel(val, dst++);
293 }
294 src1 += image->width / 8;
295 dst1 += info->fix.line_length;
296 }
297 }
298
299 static void s3fb_imageblit(struct fb_info *info, const struct fb_image *image)
300 {
301 if ((info->var.bits_per_pixel == 4) && (image->depth == 1)
302 && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) {
303 if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)
304 s3fb_iplan_imageblit(info, image);
305 else
306 s3fb_cfb4_imageblit(info, image);
307 } else
308 cfb_imageblit(info, image);
309 }
310
311 static void s3fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
312 {
313 if ((info->var.bits_per_pixel == 4)
314 && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0)
315 && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES))
316 s3fb_iplan_fillrect(info, rect);
317 else
318 cfb_fillrect(info, rect);
319 }
320
321
322
323 /* ------------------------------------------------------------------------- */
324
325
326 static void s3_set_pixclock(struct fb_info *info, u32 pixclock)
327 {
328 u16 m, n, r;
329 u8 regval;
330 int rv;
331
332 rv = svga_compute_pll(&s3_pll, 1000000000 / pixclock, &m, &n, &r, info->node);
333 if (rv < 0) {
334 printk(KERN_ERR "fb%d: cannot set requested pixclock, keeping old value\n", info->node);
335 return;
336 }
337
338 /* Set VGA misc register */
339 regval = vga_r(NULL, VGA_MIS_R);
340 vga_w(NULL, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
341
342 /* Set S3 clock registers */
343 vga_wseq(NULL, 0x12, ((n - 2) | (r << 5)));
344 vga_wseq(NULL, 0x13, m - 2);
345
346 udelay(1000);
347
348 /* Activate clock - write 0, 1, 0 to seq/15 bit 5 */
349 regval = vga_rseq (NULL, 0x15); /* | 0x80; */
350 vga_wseq(NULL, 0x15, regval & ~(1<<5));
351 vga_wseq(NULL, 0x15, regval | (1<<5));
352 vga_wseq(NULL, 0x15, regval & ~(1<<5));
353 }
354
355
356 /* Open framebuffer */
357
358 static int s3fb_open(struct fb_info *info, int user)
359 {
360 struct s3fb_info *par = info->par;
361
362 mutex_lock(&(par->open_lock));
363 if (par->ref_count == 0) {
364 memset(&(par->state), 0, sizeof(struct vgastate));
365 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;
366 par->state.num_crtc = 0x70;
367 par->state.num_seq = 0x20;
368 save_vga(&(par->state));
369 }
370
371 par->ref_count++;
372 mutex_unlock(&(par->open_lock));
373
374 return 0;
375 }
376
377 /* Close framebuffer */
378
379 static int s3fb_release(struct fb_info *info, int user)
380 {
381 struct s3fb_info *par = info->par;
382
383 mutex_lock(&(par->open_lock));
384 if (par->ref_count == 0) {
385 mutex_unlock(&(par->open_lock));
386 return -EINVAL;
387 }
388
389 if (par->ref_count == 1)
390 restore_vga(&(par->state));
391
392 par->ref_count--;
393 mutex_unlock(&(par->open_lock));
394
395 return 0;
396 }
397
398 /* Validate passed in var */
399
400 static int s3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
401 {
402 struct s3fb_info *par = info->par;
403 int rv, mem, step;
404 u16 m, n, r;
405
406 /* Find appropriate format */
407 rv = svga_match_format (s3fb_formats, var, NULL);
408
409 /* 32bpp mode is not supported on VIRGE VX,
410 24bpp is not supported on others */
411 if ((par->chip == CHIP_988_VIRGE_VX) ? (rv == 7) : (rv == 6))
412 rv = -EINVAL;
413
414 if (rv < 0) {
415 printk(KERN_ERR "fb%d: unsupported mode requested\n", info->node);
416 return rv;
417 }
418
419 /* Do not allow to have real resoulution larger than virtual */
420 if (var->xres > var->xres_virtual)
421 var->xres_virtual = var->xres;
422
423 if (var->yres > var->yres_virtual)
424 var->yres_virtual = var->yres;
425
426 /* Round up xres_virtual to have proper alignment of lines */
427 step = s3fb_formats[rv].xresstep - 1;
428 var->xres_virtual = (var->xres_virtual+step) & ~step;
429
430 /* Check whether have enough memory */
431 mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual;
432 if (mem > info->screen_size) {
433 printk(KERN_ERR "fb%d: not enough framebuffer memory (%d kB requested , %d kB available)\n",
434 info->node, mem >> 10, (unsigned int) (info->screen_size >> 10));
435 return -EINVAL;
436 }
437
438 rv = svga_check_timings (&s3_timing_regs, var, info->node);
439 if (rv < 0) {
440 printk(KERN_ERR "fb%d: invalid timings requested\n", info->node);
441 return rv;
442 }
443
444 rv = svga_compute_pll(&s3_pll, PICOS2KHZ(var->pixclock), &m, &n, &r,
445 info->node);
446 if (rv < 0) {
447 printk(KERN_ERR "fb%d: invalid pixclock value requested\n",
448 info->node);
449 return rv;
450 }
451
452 return 0;
453 }
454
455 /* Set video mode from par */
456
457 static int s3fb_set_par(struct fb_info *info)
458 {
459 struct s3fb_info *par = info->par;
460 u32 value, mode, hmul, offset_value, screen_size, multiplex;
461 u32 bpp = info->var.bits_per_pixel;
462
463 if (bpp != 0) {
464 info->fix.ypanstep = 1;
465 info->fix.line_length = (info->var.xres_virtual * bpp) / 8;
466
467 info->flags &= ~FBINFO_MISC_TILEBLITTING;
468 info->tileops = NULL;
469
470 /* in 4bpp supports 8p wide tiles only, any tiles otherwise */
471 info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0);
472 info->pixmap.blit_y = ~(u32)0;
473
474 offset_value = (info->var.xres_virtual * bpp) / 64;
475 screen_size = info->var.yres_virtual * info->fix.line_length;
476 } else {
477 info->fix.ypanstep = 16;
478 info->fix.line_length = 0;
479
480 info->flags |= FBINFO_MISC_TILEBLITTING;
481 info->tileops = fasttext ? &s3fb_fast_tile_ops : &s3fb_tile_ops;
482
483 /* supports 8x16 tiles only */
484 info->pixmap.blit_x = 1 << (8 - 1);
485 info->pixmap.blit_y = 1 << (16 - 1);
486
487 offset_value = info->var.xres_virtual / 16;
488 screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64;
489 }
490
491 info->var.xoffset = 0;
492 info->var.yoffset = 0;
493 info->var.activate = FB_ACTIVATE_NOW;
494
495 /* Unlock registers */
496 vga_wcrt(NULL, 0x38, 0x48);
497 vga_wcrt(NULL, 0x39, 0xA5);
498 vga_wseq(NULL, 0x08, 0x06);
499 svga_wcrt_mask(0x11, 0x00, 0x80);
500
501 /* Blank screen and turn off sync */
502 svga_wseq_mask(0x01, 0x20, 0x20);
503 svga_wcrt_mask(0x17, 0x00, 0x80);
504
505 /* Set default values */
506 svga_set_default_gfx_regs();
507 svga_set_default_atc_regs();
508 svga_set_default_seq_regs();
509 svga_set_default_crt_regs();
510 svga_wcrt_multi(s3_line_compare_regs, 0xFFFFFFFF);
511 svga_wcrt_multi(s3_start_address_regs, 0);
512
513 /* S3 specific initialization */
514 svga_wcrt_mask(0x58, 0x10, 0x10); /* enable linear framebuffer */
515 svga_wcrt_mask(0x31, 0x08, 0x08); /* enable sequencer access to framebuffer above 256 kB */
516
517 /* svga_wcrt_mask(0x33, 0x08, 0x08); */ /* DDR ? */
518 /* svga_wcrt_mask(0x43, 0x01, 0x01); */ /* DDR ? */
519 svga_wcrt_mask(0x33, 0x00, 0x08); /* no DDR ? */
520 svga_wcrt_mask(0x43, 0x00, 0x01); /* no DDR ? */
521
522 svga_wcrt_mask(0x5D, 0x00, 0x28); // Clear strange HSlen bits
523
524 /* svga_wcrt_mask(0x58, 0x03, 0x03); */
525
526 /* svga_wcrt_mask(0x53, 0x12, 0x13); */ /* enable MMIO */
527 /* svga_wcrt_mask(0x40, 0x08, 0x08); */ /* enable write buffer */
528
529
530 /* Set the offset register */
531 pr_debug("fb%d: offset register : %d\n", info->node, offset_value);
532 svga_wcrt_multi(s3_offset_regs, offset_value);
533
534 vga_wcrt(NULL, 0x54, 0x18); /* M parameter */
535 vga_wcrt(NULL, 0x60, 0xff); /* N parameter */
536 vga_wcrt(NULL, 0x61, 0xff); /* L parameter */
537 vga_wcrt(NULL, 0x62, 0xff); /* L parameter */
538
539 vga_wcrt(NULL, 0x3A, 0x35);
540 svga_wattr(0x33, 0x00);
541
542 if (info->var.vmode & FB_VMODE_DOUBLE)
543 svga_wcrt_mask(0x09, 0x80, 0x80);
544 else
545 svga_wcrt_mask(0x09, 0x00, 0x80);
546
547 if (info->var.vmode & FB_VMODE_INTERLACED)
548 svga_wcrt_mask(0x42, 0x20, 0x20);
549 else
550 svga_wcrt_mask(0x42, 0x00, 0x20);
551
552 /* Disable hardware graphics cursor */
553 svga_wcrt_mask(0x45, 0x00, 0x01);
554 /* Disable Streams engine */
555 svga_wcrt_mask(0x67, 0x00, 0x0C);
556
557 mode = svga_match_format(s3fb_formats, &(info->var), &(info->fix));
558
559 /* S3 virge DX hack */
560 if (par->chip == CHIP_375_VIRGE_DX) {
561 vga_wcrt(NULL, 0x86, 0x80);
562 vga_wcrt(NULL, 0x90, 0x00);
563 }
564
565 /* S3 virge VX hack */
566 if (par->chip == CHIP_988_VIRGE_VX) {
567 vga_wcrt(NULL, 0x50, 0x00);
568 vga_wcrt(NULL, 0x67, 0x50);
569
570 vga_wcrt(NULL, 0x63, (mode <= 2) ? 0x90 : 0x09);
571 vga_wcrt(NULL, 0x66, 0x90);
572 }
573
574 svga_wcrt_mask(0x31, 0x00, 0x40);
575 multiplex = 0;
576 hmul = 1;
577
578 /* Set mode-specific register values */
579 switch (mode) {
580 case 0:
581 pr_debug("fb%d: text mode\n", info->node);
582 svga_set_textmode_vga_regs();
583
584 /* Set additional registers like in 8-bit mode */
585 svga_wcrt_mask(0x50, 0x00, 0x30);
586 svga_wcrt_mask(0x67, 0x00, 0xF0);
587
588 /* Disable enhanced mode */
589 svga_wcrt_mask(0x3A, 0x00, 0x30);
590
591 if (fasttext) {
592 pr_debug("fb%d: high speed text mode set\n", info->node);
593 svga_wcrt_mask(0x31, 0x40, 0x40);
594 }
595 break;
596 case 1:
597 pr_debug("fb%d: 4 bit pseudocolor\n", info->node);
598 vga_wgfx(NULL, VGA_GFX_MODE, 0x40);
599
600 /* Set additional registers like in 8-bit mode */
601 svga_wcrt_mask(0x50, 0x00, 0x30);
602 svga_wcrt_mask(0x67, 0x00, 0xF0);
603
604 /* disable enhanced mode */
605 svga_wcrt_mask(0x3A, 0x00, 0x30);
606 break;
607 case 2:
608 pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node);
609
610 /* Set additional registers like in 8-bit mode */
611 svga_wcrt_mask(0x50, 0x00, 0x30);
612 svga_wcrt_mask(0x67, 0x00, 0xF0);
613
614 /* disable enhanced mode */
615 svga_wcrt_mask(0x3A, 0x00, 0x30);
616 break;
617 case 3:
618 pr_debug("fb%d: 8 bit pseudocolor\n", info->node);
619 if (info->var.pixclock > 20000) {
620 svga_wcrt_mask(0x50, 0x00, 0x30);
621 svga_wcrt_mask(0x67, 0x00, 0xF0);
622 } else {
623 svga_wcrt_mask(0x50, 0x00, 0x30);
624 svga_wcrt_mask(0x67, 0x10, 0xF0);
625 multiplex = 1;
626 }
627 break;
628 case 4:
629 pr_debug("fb%d: 5/5/5 truecolor\n", info->node);
630 if (par->chip == CHIP_988_VIRGE_VX) {
631 if (info->var.pixclock > 20000)
632 svga_wcrt_mask(0x67, 0x20, 0xF0);
633 else
634 svga_wcrt_mask(0x67, 0x30, 0xF0);
635 } else {
636 svga_wcrt_mask(0x50, 0x10, 0x30);
637 svga_wcrt_mask(0x67, 0x30, 0xF0);
638 hmul = 2;
639 }
640 break;
641 case 5:
642 pr_debug("fb%d: 5/6/5 truecolor\n", info->node);
643 if (par->chip == CHIP_988_VIRGE_VX) {
644 if (info->var.pixclock > 20000)
645 svga_wcrt_mask(0x67, 0x40, 0xF0);
646 else
647 svga_wcrt_mask(0x67, 0x50, 0xF0);
648 } else {
649 svga_wcrt_mask(0x50, 0x10, 0x30);
650 svga_wcrt_mask(0x67, 0x50, 0xF0);
651 hmul = 2;
652 }
653 break;
654 case 6:
655 /* VIRGE VX case */
656 pr_debug("fb%d: 8/8/8 truecolor\n", info->node);
657 svga_wcrt_mask(0x67, 0xD0, 0xF0);
658 break;
659 case 7:
660 pr_debug("fb%d: 8/8/8/8 truecolor\n", info->node);
661 svga_wcrt_mask(0x50, 0x30, 0x30);
662 svga_wcrt_mask(0x67, 0xD0, 0xF0);
663 break;
664 default:
665 printk(KERN_ERR "fb%d: unsupported mode - bug\n", info->node);
666 return -EINVAL;
667 }
668
669 if (par->chip != CHIP_988_VIRGE_VX) {
670 svga_wseq_mask(0x15, multiplex ? 0x10 : 0x00, 0x10);
671 svga_wseq_mask(0x18, multiplex ? 0x80 : 0x00, 0x80);
672 }
673
674 s3_set_pixclock(info, info->var.pixclock);
675 svga_set_timings(&s3_timing_regs, &(info->var), hmul, 1,
676 (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1,
677 (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1,
678 hmul, info->node);
679
680 /* Set interlaced mode start/end register */
681 value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len;
682 value = ((value * hmul) / 8) - 5;
683 vga_wcrt(NULL, 0x3C, (value + 1) / 2);
684
685 memset_io(info->screen_base, 0x00, screen_size);
686 /* Device and screen back on */
687 svga_wcrt_mask(0x17, 0x80, 0x80);
688 svga_wseq_mask(0x01, 0x00, 0x20);
689
690 return 0;
691 }
692
693 /* Set a colour register */
694
695 static int s3fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
696 u_int transp, struct fb_info *fb)
697 {
698 switch (fb->var.bits_per_pixel) {
699 case 0:
700 case 4:
701 if (regno >= 16)
702 return -EINVAL;
703
704 if ((fb->var.bits_per_pixel == 4) &&
705 (fb->var.nonstd == 0)) {
706 outb(0xF0, VGA_PEL_MSK);
707 outb(regno*16, VGA_PEL_IW);
708 } else {
709 outb(0x0F, VGA_PEL_MSK);
710 outb(regno, VGA_PEL_IW);
711 }
712 outb(red >> 10, VGA_PEL_D);
713 outb(green >> 10, VGA_PEL_D);
714 outb(blue >> 10, VGA_PEL_D);
715 break;
716 case 8:
717 if (regno >= 256)
718 return -EINVAL;
719
720 outb(0xFF, VGA_PEL_MSK);
721 outb(regno, VGA_PEL_IW);
722 outb(red >> 10, VGA_PEL_D);
723 outb(green >> 10, VGA_PEL_D);
724 outb(blue >> 10, VGA_PEL_D);
725 break;
726 case 16:
727 if (regno >= 16)
728 return 0;
729
730 if (fb->var.green.length == 5)
731 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) |
732 ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11);
733 else if (fb->var.green.length == 6)
734 ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) |
735 ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
736 else return -EINVAL;
737 break;
738 case 24:
739 case 32:
740 if (regno >= 16)
741 return 0;
742
743 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) |
744 (green & 0xFF00) | ((blue & 0xFF00) >> 8);
745 break;
746 default:
747 return -EINVAL;
748 }
749
750 return 0;
751 }
752
753
754 /* Set the display blanking state */
755
756 static int s3fb_blank(int blank_mode, struct fb_info *info)
757 {
758 switch (blank_mode) {
759 case FB_BLANK_UNBLANK:
760 pr_debug("fb%d: unblank\n", info->node);
761 svga_wcrt_mask(0x56, 0x00, 0x06);
762 svga_wseq_mask(0x01, 0x00, 0x20);
763 break;
764 case FB_BLANK_NORMAL:
765 pr_debug("fb%d: blank\n", info->node);
766 svga_wcrt_mask(0x56, 0x00, 0x06);
767 svga_wseq_mask(0x01, 0x20, 0x20);
768 break;
769 case FB_BLANK_HSYNC_SUSPEND:
770 pr_debug("fb%d: hsync\n", info->node);
771 svga_wcrt_mask(0x56, 0x02, 0x06);
772 svga_wseq_mask(0x01, 0x20, 0x20);
773 break;
774 case FB_BLANK_VSYNC_SUSPEND:
775 pr_debug("fb%d: vsync\n", info->node);
776 svga_wcrt_mask(0x56, 0x04, 0x06);
777 svga_wseq_mask(0x01, 0x20, 0x20);
778 break;
779 case FB_BLANK_POWERDOWN:
780 pr_debug("fb%d: sync down\n", info->node);
781 svga_wcrt_mask(0x56, 0x06, 0x06);
782 svga_wseq_mask(0x01, 0x20, 0x20);
783 break;
784 }
785
786 return 0;
787 }
788
789
790 /* Pan the display */
791
792 static int s3fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) {
793
794 unsigned int offset;
795
796 /* Calculate the offset */
797 if (var->bits_per_pixel == 0) {
798 offset = (var->yoffset / 16) * (var->xres_virtual / 2) + (var->xoffset / 2);
799 offset = offset >> 2;
800 } else {
801 offset = (var->yoffset * info->fix.line_length) +
802 (var->xoffset * var->bits_per_pixel / 8);
803 offset = offset >> 2;
804 }
805
806 /* Set the offset */
807 svga_wcrt_multi(s3_start_address_regs, offset);
808
809 return 0;
810 }
811
812 /* ------------------------------------------------------------------------- */
813
814 /* Frame buffer operations */
815
816 static struct fb_ops s3fb_ops = {
817 .owner = THIS_MODULE,
818 .fb_open = s3fb_open,
819 .fb_release = s3fb_release,
820 .fb_check_var = s3fb_check_var,
821 .fb_set_par = s3fb_set_par,
822 .fb_setcolreg = s3fb_setcolreg,
823 .fb_blank = s3fb_blank,
824 .fb_pan_display = s3fb_pan_display,
825 .fb_fillrect = s3fb_fillrect,
826 .fb_copyarea = cfb_copyarea,
827 .fb_imageblit = s3fb_imageblit,
828 .fb_get_caps = svga_get_caps,
829 };
830
831 /* ------------------------------------------------------------------------- */
832
833 static int __devinit s3_identification(int chip)
834 {
835 if (chip == CHIP_XXX_TRIO) {
836 u8 cr30 = vga_rcrt(NULL, 0x30);
837 u8 cr2e = vga_rcrt(NULL, 0x2e);
838 u8 cr2f = vga_rcrt(NULL, 0x2f);
839
840 if ((cr30 == 0xE0) || (cr30 == 0xE1)) {
841 if (cr2e == 0x10)
842 return CHIP_732_TRIO32;
843 if (cr2e == 0x11) {
844 if (! (cr2f & 0x40))
845 return CHIP_764_TRIO64;
846 else
847 return CHIP_765_TRIO64VP;
848 }
849 }
850 }
851
852 if (chip == CHIP_XXX_TRIO64V2_DXGX) {
853 u8 cr6f = vga_rcrt(NULL, 0x6f);
854
855 if (! (cr6f & 0x01))
856 return CHIP_775_TRIO64V2_DX;
857 else
858 return CHIP_785_TRIO64V2_GX;
859 }
860
861 if (chip == CHIP_XXX_VIRGE_DXGX) {
862 u8 cr6f = vga_rcrt(NULL, 0x6f);
863
864 if (! (cr6f & 0x01))
865 return CHIP_375_VIRGE_DX;
866 else
867 return CHIP_385_VIRGE_GX;
868 }
869
870 return CHIP_UNKNOWN;
871 }
872
873
874 /* PCI probe */
875
876 static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
877 {
878 struct fb_info *info;
879 struct s3fb_info *par;
880 int rc;
881 u8 regval, cr38, cr39;
882
883 /* Ignore secondary VGA device because there is no VGA arbitration */
884 if (! svga_primary_device(dev)) {
885 dev_info(&(dev->dev), "ignoring secondary device\n");
886 return -ENODEV;
887 }
888
889 /* Allocate and fill driver data structure */
890 info = framebuffer_alloc(sizeof(struct s3fb_info), &(dev->dev));
891 if (!info) {
892 dev_err(&(dev->dev), "cannot allocate memory\n");
893 return -ENOMEM;
894 }
895
896 par = info->par;
897 mutex_init(&par->open_lock);
898
899 info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN;
900 info->fbops = &s3fb_ops;
901
902 /* Prepare PCI device */
903 rc = pci_enable_device(dev);
904 if (rc < 0) {
905 dev_err(info->device, "cannot enable PCI device\n");
906 goto err_enable_device;
907 }
908
909 rc = pci_request_regions(dev, "s3fb");
910 if (rc < 0) {
911 dev_err(info->device, "cannot reserve framebuffer region\n");
912 goto err_request_regions;
913 }
914
915
916 info->fix.smem_start = pci_resource_start(dev, 0);
917 info->fix.smem_len = pci_resource_len(dev, 0);
918
919 /* Map physical IO memory address into kernel space */
920 info->screen_base = pci_iomap(dev, 0, 0);
921 if (! info->screen_base) {
922 rc = -ENOMEM;
923 dev_err(info->device, "iomap for framebuffer failed\n");
924 goto err_iomap;
925 }
926
927 /* Unlock regs */
928 cr38 = vga_rcrt(NULL, 0x38);
929 cr39 = vga_rcrt(NULL, 0x39);
930 vga_wseq(NULL, 0x08, 0x06);
931 vga_wcrt(NULL, 0x38, 0x48);
932 vga_wcrt(NULL, 0x39, 0xA5);
933
934 /* Find how many physical memory there is on card */
935 /* 0x36 register is accessible even if other registers are locked */
936 regval = vga_rcrt(NULL, 0x36);
937 info->screen_size = s3_memsizes[regval >> 5] << 10;
938 info->fix.smem_len = info->screen_size;
939
940 par->chip = id->driver_data & CHIP_MASK;
941 par->rev = vga_rcrt(NULL, 0x2f);
942 if (par->chip & CHIP_UNDECIDED_FLAG)
943 par->chip = s3_identification(par->chip);
944
945 /* Find MCLK frequency */
946 regval = vga_rseq(NULL, 0x10);
947 par->mclk_freq = ((vga_rseq(NULL, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2);
948 par->mclk_freq = par->mclk_freq >> (regval >> 5);
949
950 /* Restore locks */
951 vga_wcrt(NULL, 0x38, cr38);
952 vga_wcrt(NULL, 0x39, cr39);
953
954 strcpy(info->fix.id, s3_names [par->chip]);
955 info->fix.mmio_start = 0;
956 info->fix.mmio_len = 0;
957 info->fix.type = FB_TYPE_PACKED_PIXELS;
958 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
959 info->fix.ypanstep = 0;
960 info->fix.accel = FB_ACCEL_NONE;
961 info->pseudo_palette = (void*) (par->pseudo_palette);
962
963 /* Prepare startup mode */
964 rc = fb_find_mode(&(info->var), info, mode_option, NULL, 0, NULL, 8);
965 if (! ((rc == 1) || (rc == 2))) {
966 rc = -EINVAL;
967 dev_err(info->device, "mode %s not found\n", mode_option);
968 goto err_find_mode;
969 }
970
971 rc = fb_alloc_cmap(&info->cmap, 256, 0);
972 if (rc < 0) {
973 dev_err(info->device, "cannot allocate colormap\n");
974 goto err_alloc_cmap;
975 }
976
977 rc = register_framebuffer(info);
978 if (rc < 0) {
979 dev_err(info->device, "cannot register framebuffer\n");
980 goto err_reg_fb;
981 }
982
983 printk(KERN_INFO "fb%d: %s on %s, %d MB RAM, %d MHz MCLK\n", info->node, info->fix.id,
984 pci_name(dev), info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000);
985
986 if (par->chip == CHIP_UNKNOWN)
987 printk(KERN_INFO "fb%d: unknown chip, CR2D=%x, CR2E=%x, CRT2F=%x, CRT30=%x\n",
988 info->node, vga_rcrt(NULL, 0x2d), vga_rcrt(NULL, 0x2e),
989 vga_rcrt(NULL, 0x2f), vga_rcrt(NULL, 0x30));
990
991 /* Record a reference to the driver data */
992 pci_set_drvdata(dev, info);
993
994 #ifdef CONFIG_MTRR
995 if (mtrr) {
996 par->mtrr_reg = -1;
997 par->mtrr_reg = mtrr_add(info->fix.smem_start, info->fix.smem_len, MTRR_TYPE_WRCOMB, 1);
998 }
999 #endif
1000
1001 return 0;
1002
1003 /* Error handling */
1004 err_reg_fb:
1005 fb_dealloc_cmap(&info->cmap);
1006 err_alloc_cmap:
1007 err_find_mode:
1008 pci_iounmap(dev, info->screen_base);
1009 err_iomap:
1010 pci_release_regions(dev);
1011 err_request_regions:
1012 /* pci_disable_device(dev); */
1013 err_enable_device:
1014 framebuffer_release(info);
1015 return rc;
1016 }
1017
1018
1019 /* PCI remove */
1020
1021 static void __devexit s3_pci_remove(struct pci_dev *dev)
1022 {
1023 struct fb_info *info = pci_get_drvdata(dev);
1024
1025 if (info) {
1026
1027 #ifdef CONFIG_MTRR
1028 struct s3fb_info *par = info->par;
1029
1030 if (par->mtrr_reg >= 0) {
1031 mtrr_del(par->mtrr_reg, 0, 0);
1032 par->mtrr_reg = -1;
1033 }
1034 #endif
1035
1036 unregister_framebuffer(info);
1037 fb_dealloc_cmap(&info->cmap);
1038
1039 pci_iounmap(dev, info->screen_base);
1040 pci_release_regions(dev);
1041 /* pci_disable_device(dev); */
1042
1043 pci_set_drvdata(dev, NULL);
1044 framebuffer_release(info);
1045 }
1046 }
1047
1048 /* PCI suspend */
1049
1050 static int s3_pci_suspend(struct pci_dev* dev, pm_message_t state)
1051 {
1052 struct fb_info *info = pci_get_drvdata(dev);
1053 struct s3fb_info *par = info->par;
1054
1055 dev_info(info->device, "suspend\n");
1056
1057 acquire_console_sem();
1058 mutex_lock(&(par->open_lock));
1059
1060 if ((state.event == PM_EVENT_FREEZE) || (par->ref_count == 0)) {
1061 mutex_unlock(&(par->open_lock));
1062 release_console_sem();
1063 return 0;
1064 }
1065
1066 fb_set_suspend(info, 1);
1067
1068 pci_save_state(dev);
1069 pci_disable_device(dev);
1070 pci_set_power_state(dev, pci_choose_state(dev, state));
1071
1072 mutex_unlock(&(par->open_lock));
1073 release_console_sem();
1074
1075 return 0;
1076 }
1077
1078
1079 /* PCI resume */
1080
1081 static int s3_pci_resume(struct pci_dev* dev)
1082 {
1083 struct fb_info *info = pci_get_drvdata(dev);
1084 struct s3fb_info *par = info->par;
1085 int err;
1086
1087 dev_info(info->device, "resume\n");
1088
1089 acquire_console_sem();
1090 mutex_lock(&(par->open_lock));
1091
1092 if (par->ref_count == 0) {
1093 mutex_unlock(&(par->open_lock));
1094 release_console_sem();
1095 return 0;
1096 }
1097
1098 pci_set_power_state(dev, PCI_D0);
1099 pci_restore_state(dev);
1100 err = pci_enable_device(dev);
1101 if (err) {
1102 mutex_unlock(&(par->open_lock));
1103 release_console_sem();
1104 dev_err(info->device, "error %d enabling device for resume\n", err);
1105 return err;
1106 }
1107 pci_set_master(dev);
1108
1109 s3fb_set_par(info);
1110 fb_set_suspend(info, 0);
1111
1112 mutex_unlock(&(par->open_lock));
1113 release_console_sem();
1114
1115 return 0;
1116 }
1117
1118
1119 /* List of boards that we are trying to support */
1120
1121 static struct pci_device_id s3_devices[] __devinitdata = {
1122 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8810), .driver_data = CHIP_XXX_TRIO},
1123 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8811), .driver_data = CHIP_XXX_TRIO},
1124 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8812), .driver_data = CHIP_M65_AURORA64VP},
1125 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8814), .driver_data = CHIP_767_TRIO64UVP},
1126 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8901), .driver_data = CHIP_XXX_TRIO64V2_DXGX},
1127 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8902), .driver_data = CHIP_551_PLATO_PX},
1128
1129 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x5631), .driver_data = CHIP_325_VIRGE},
1130 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x883D), .driver_data = CHIP_988_VIRGE_VX},
1131 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A01), .driver_data = CHIP_XXX_VIRGE_DXGX},
1132 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A10), .driver_data = CHIP_356_VIRGE_GX2},
1133 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A11), .driver_data = CHIP_357_VIRGE_GX2P},
1134 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A12), .driver_data = CHIP_359_VIRGE_GX2P},
1135
1136 {0, 0, 0, 0, 0, 0, 0}
1137 };
1138
1139
1140 MODULE_DEVICE_TABLE(pci, s3_devices);
1141
1142 static struct pci_driver s3fb_pci_driver = {
1143 .name = "s3fb",
1144 .id_table = s3_devices,
1145 .probe = s3_pci_probe,
1146 .remove = __devexit_p(s3_pci_remove),
1147 .suspend = s3_pci_suspend,
1148 .resume = s3_pci_resume,
1149 };
1150
1151 /* Parse user speficied options */
1152
1153 #ifndef MODULE
1154 static int __init s3fb_setup(char *options)
1155 {
1156 char *opt;
1157
1158 if (!options || !*options)
1159 return 0;
1160
1161 while ((opt = strsep(&options, ",")) != NULL) {
1162
1163 if (!*opt)
1164 continue;
1165 #ifdef CONFIG_MTRR
1166 else if (!strncmp(opt, "mtrr:", 5))
1167 mtrr = simple_strtoul(opt + 5, NULL, 0);
1168 #endif
1169 else if (!strncmp(opt, "fasttext:", 9))
1170 fasttext = simple_strtoul(opt + 9, NULL, 0);
1171 else
1172 mode_option = opt;
1173 }
1174
1175 return 0;
1176 }
1177 #endif
1178
1179 /* Cleanup */
1180
1181 static void __exit s3fb_cleanup(void)
1182 {
1183 pr_debug("s3fb: cleaning up\n");
1184 pci_unregister_driver(&s3fb_pci_driver);
1185 }
1186
1187 /* Driver Initialisation */
1188
1189 static int __init s3fb_init(void)
1190 {
1191
1192 #ifndef MODULE
1193 char *option = NULL;
1194
1195 if (fb_get_options("s3fb", &option))
1196 return -ENODEV;
1197 s3fb_setup(option);
1198 #endif
1199
1200 pr_debug("s3fb: initializing\n");
1201 return pci_register_driver(&s3fb_pci_driver);
1202 }
1203
1204 /* ------------------------------------------------------------------------- */
1205
1206 /* Modularization */
1207
1208 module_init(s3fb_init);
1209 module_exit(s3fb_cleanup);
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