2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
23 * This driver supports an Intel I/OAT DMA engine, which does asynchronous
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/interrupt.h>
31 #include <linux/dmaengine.h>
32 #include <linux/delay.h>
33 #include <linux/dma-mapping.h>
35 #include "ioatdma_io.h"
36 #include "ioatdma_registers.h"
37 #include "ioatdma_hw.h"
39 #define to_ioat_chan(chan) container_of(chan, struct ioat_dma_chan, common)
40 #define to_ioat_device(dev) container_of(dev, struct ioat_device, common)
41 #define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node)
43 /* internal functions */
44 static int __devinit
ioat_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
45 static void __devexit
ioat_remove(struct pci_dev
*pdev
);
47 static int enumerate_dma_channels(struct ioat_device
*device
)
52 struct ioat_dma_chan
*ioat_chan
;
54 device
->common
.chancnt
= ioatdma_read8(device
, IOAT_CHANCNT_OFFSET
);
55 xfercap_scale
= ioatdma_read8(device
, IOAT_XFERCAP_OFFSET
);
56 xfercap
= (xfercap_scale
== 0 ? -1 : (1UL << xfercap_scale
));
58 for (i
= 0; i
< device
->common
.chancnt
; i
++) {
59 ioat_chan
= kzalloc(sizeof(*ioat_chan
), GFP_KERNEL
);
61 device
->common
.chancnt
= i
;
65 ioat_chan
->device
= device
;
66 ioat_chan
->reg_base
= device
->reg_base
+ (0x80 * (i
+ 1));
67 ioat_chan
->xfercap
= xfercap
;
68 spin_lock_init(&ioat_chan
->cleanup_lock
);
69 spin_lock_init(&ioat_chan
->desc_lock
);
70 INIT_LIST_HEAD(&ioat_chan
->free_desc
);
71 INIT_LIST_HEAD(&ioat_chan
->used_desc
);
72 /* This should be made common somewhere in dmaengine.c */
73 ioat_chan
->common
.device
= &device
->common
;
74 ioat_chan
->common
.client
= NULL
;
75 list_add_tail(&ioat_chan
->common
.device_node
,
76 &device
->common
.channels
);
78 return device
->common
.chancnt
;
81 static struct ioat_desc_sw
*ioat_dma_alloc_descriptor(
82 struct ioat_dma_chan
*ioat_chan
,
85 struct ioat_dma_descriptor
*desc
;
86 struct ioat_desc_sw
*desc_sw
;
87 struct ioat_device
*ioat_device
;
90 ioat_device
= to_ioat_device(ioat_chan
->common
.device
);
91 desc
= pci_pool_alloc(ioat_device
->dma_pool
, flags
, &phys
);
95 desc_sw
= kzalloc(sizeof(*desc_sw
), flags
);
96 if (unlikely(!desc_sw
)) {
97 pci_pool_free(ioat_device
->dma_pool
, desc
, phys
);
101 memset(desc
, 0, sizeof(*desc
));
103 desc_sw
->phys
= phys
;
108 #define INITIAL_IOAT_DESC_COUNT 128
110 static void ioat_start_null_desc(struct ioat_dma_chan
*ioat_chan
);
112 /* returns the actual number of allocated descriptors */
113 static int ioat_dma_alloc_chan_resources(struct dma_chan
*chan
)
115 struct ioat_dma_chan
*ioat_chan
= to_ioat_chan(chan
);
116 struct ioat_desc_sw
*desc
= NULL
;
123 * In-use bit automatically set by reading chanctrl
124 * If 0, we got it, if 1, someone else did
126 chanctrl
= ioatdma_chan_read16(ioat_chan
, IOAT_CHANCTRL_OFFSET
);
127 if (chanctrl
& IOAT_CHANCTRL_CHANNEL_IN_USE
)
130 /* Setup register to interrupt and write completion status on error */
131 chanctrl
= IOAT_CHANCTRL_CHANNEL_IN_USE
|
132 IOAT_CHANCTRL_ERR_INT_EN
|
133 IOAT_CHANCTRL_ANY_ERR_ABORT_EN
|
134 IOAT_CHANCTRL_ERR_COMPLETION_EN
;
135 ioatdma_chan_write16(ioat_chan
, IOAT_CHANCTRL_OFFSET
, chanctrl
);
137 chanerr
= ioatdma_chan_read32(ioat_chan
, IOAT_CHANERR_OFFSET
);
139 printk("IOAT: CHANERR = %x, clearing\n", chanerr
);
140 ioatdma_chan_write32(ioat_chan
, IOAT_CHANERR_OFFSET
, chanerr
);
143 /* Allocate descriptors */
144 for (i
= 0; i
< INITIAL_IOAT_DESC_COUNT
; i
++) {
145 desc
= ioat_dma_alloc_descriptor(ioat_chan
, GFP_KERNEL
);
147 printk(KERN_ERR
"IOAT: Only %d initial descriptors\n", i
);
150 list_add_tail(&desc
->node
, &tmp_list
);
152 spin_lock_bh(&ioat_chan
->desc_lock
);
153 list_splice(&tmp_list
, &ioat_chan
->free_desc
);
154 spin_unlock_bh(&ioat_chan
->desc_lock
);
156 /* allocate a completion writeback area */
157 /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
158 ioat_chan
->completion_virt
=
159 pci_pool_alloc(ioat_chan
->device
->completion_pool
,
161 &ioat_chan
->completion_addr
);
162 memset(ioat_chan
->completion_virt
, 0,
163 sizeof(*ioat_chan
->completion_virt
));
164 ioatdma_chan_write32(ioat_chan
, IOAT_CHANCMP_OFFSET_LOW
,
165 ((u64
) ioat_chan
->completion_addr
) & 0x00000000FFFFFFFF);
166 ioatdma_chan_write32(ioat_chan
, IOAT_CHANCMP_OFFSET_HIGH
,
167 ((u64
) ioat_chan
->completion_addr
) >> 32);
169 ioat_start_null_desc(ioat_chan
);
173 static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan
*ioat_chan
);
175 static void ioat_dma_free_chan_resources(struct dma_chan
*chan
)
177 struct ioat_dma_chan
*ioat_chan
= to_ioat_chan(chan
);
178 struct ioat_device
*ioat_device
= to_ioat_device(chan
->device
);
179 struct ioat_desc_sw
*desc
, *_desc
;
181 int in_use_descs
= 0;
183 ioat_dma_memcpy_cleanup(ioat_chan
);
185 ioatdma_chan_write8(ioat_chan
, IOAT_CHANCMD_OFFSET
, IOAT_CHANCMD_RESET
);
187 spin_lock_bh(&ioat_chan
->desc_lock
);
188 list_for_each_entry_safe(desc
, _desc
, &ioat_chan
->used_desc
, node
) {
190 list_del(&desc
->node
);
191 pci_pool_free(ioat_device
->dma_pool
, desc
->hw
, desc
->phys
);
194 list_for_each_entry_safe(desc
, _desc
, &ioat_chan
->free_desc
, node
) {
195 list_del(&desc
->node
);
196 pci_pool_free(ioat_device
->dma_pool
, desc
->hw
, desc
->phys
);
199 spin_unlock_bh(&ioat_chan
->desc_lock
);
201 pci_pool_free(ioat_device
->completion_pool
,
202 ioat_chan
->completion_virt
,
203 ioat_chan
->completion_addr
);
205 /* one is ok since we left it on there on purpose */
206 if (in_use_descs
> 1)
207 printk(KERN_ERR
"IOAT: Freeing %d in use descriptors!\n",
210 ioat_chan
->last_completion
= ioat_chan
->completion_addr
= 0;
212 /* Tell hw the chan is free */
213 chanctrl
= ioatdma_chan_read16(ioat_chan
, IOAT_CHANCTRL_OFFSET
);
214 chanctrl
&= ~IOAT_CHANCTRL_CHANNEL_IN_USE
;
215 ioatdma_chan_write16(ioat_chan
, IOAT_CHANCTRL_OFFSET
, chanctrl
);
219 * do_ioat_dma_memcpy - actual function that initiates a IOAT DMA transaction
220 * @ioat_chan: IOAT DMA channel handle
221 * @dest: DMA destination address
222 * @src: DMA source address
223 * @len: transaction length in bytes
226 static dma_cookie_t
do_ioat_dma_memcpy(struct ioat_dma_chan
*ioat_chan
,
231 struct ioat_desc_sw
*first
;
232 struct ioat_desc_sw
*prev
;
233 struct ioat_desc_sw
*new;
235 LIST_HEAD(new_chain
);
238 dma_addr_t orig_src
, orig_dst
;
239 unsigned int desc_count
= 0;
240 unsigned int append
= 0;
242 if (!ioat_chan
|| !dest
|| !src
)
246 return ioat_chan
->common
.cookie
;
255 spin_lock_bh(&ioat_chan
->desc_lock
);
258 if (!list_empty(&ioat_chan
->free_desc
)) {
259 new = to_ioat_desc(ioat_chan
->free_desc
.next
);
260 list_del(&new->node
);
262 /* try to get another desc */
263 new = ioat_dma_alloc_descriptor(ioat_chan
, GFP_ATOMIC
);
264 /* will this ever happen? */
265 /* TODO add upper limit on these */
269 copy
= min((u32
) len
, ioat_chan
->xfercap
);
271 new->hw
->size
= copy
;
273 new->hw
->src_addr
= src
;
274 new->hw
->dst_addr
= dest
;
277 /* chain together the physical address list for the HW */
281 prev
->hw
->next
= (u64
) new->phys
;
289 list_add_tail(&new->node
, &new_chain
);
292 new->hw
->ctl
= IOAT_DMA_DESCRIPTOR_CTL_CP_STS
;
295 /* cookie incr and addition to used_list must be atomic */
297 cookie
= ioat_chan
->common
.cookie
;
301 ioat_chan
->common
.cookie
= new->cookie
= cookie
;
303 pci_unmap_addr_set(new, src
, orig_src
);
304 pci_unmap_addr_set(new, dst
, orig_dst
);
305 pci_unmap_len_set(new, src_len
, orig_len
);
306 pci_unmap_len_set(new, dst_len
, orig_len
);
308 /* write address into NextDescriptor field of last desc in chain */
309 to_ioat_desc(ioat_chan
->used_desc
.prev
)->hw
->next
= first
->phys
;
310 list_splice_init(&new_chain
, ioat_chan
->used_desc
.prev
);
312 ioat_chan
->pending
+= desc_count
;
313 if (ioat_chan
->pending
>= 20) {
315 ioat_chan
->pending
= 0;
318 spin_unlock_bh(&ioat_chan
->desc_lock
);
321 ioatdma_chan_write8(ioat_chan
,
323 IOAT_CHANCMD_APPEND
);
328 * ioat_dma_memcpy_buf_to_buf - wrapper that takes src & dest bufs
329 * @chan: IOAT DMA channel handle
330 * @dest: DMA destination address
331 * @src: DMA source address
332 * @len: transaction length in bytes
335 static dma_cookie_t
ioat_dma_memcpy_buf_to_buf(struct dma_chan
*chan
,
340 dma_addr_t dest_addr
;
342 struct ioat_dma_chan
*ioat_chan
= to_ioat_chan(chan
);
344 dest_addr
= pci_map_single(ioat_chan
->device
->pdev
,
345 dest
, len
, PCI_DMA_FROMDEVICE
);
346 src_addr
= pci_map_single(ioat_chan
->device
->pdev
,
347 src
, len
, PCI_DMA_TODEVICE
);
349 return do_ioat_dma_memcpy(ioat_chan
, dest_addr
, src_addr
, len
);
353 * ioat_dma_memcpy_buf_to_pg - wrapper, copying from a buf to a page
354 * @chan: IOAT DMA channel handle
355 * @page: pointer to the page to copy to
356 * @offset: offset into that page
357 * @src: DMA source address
358 * @len: transaction length in bytes
361 static dma_cookie_t
ioat_dma_memcpy_buf_to_pg(struct dma_chan
*chan
,
367 dma_addr_t dest_addr
;
369 struct ioat_dma_chan
*ioat_chan
= to_ioat_chan(chan
);
371 dest_addr
= pci_map_page(ioat_chan
->device
->pdev
,
372 page
, offset
, len
, PCI_DMA_FROMDEVICE
);
373 src_addr
= pci_map_single(ioat_chan
->device
->pdev
,
374 src
, len
, PCI_DMA_TODEVICE
);
376 return do_ioat_dma_memcpy(ioat_chan
, dest_addr
, src_addr
, len
);
380 * ioat_dma_memcpy_pg_to_pg - wrapper, copying between two pages
381 * @chan: IOAT DMA channel handle
382 * @dest_pg: pointer to the page to copy to
383 * @dest_off: offset into that page
384 * @src_pg: pointer to the page to copy from
385 * @src_off: offset into that page
386 * @len: transaction length in bytes. This is guaranteed not to make a copy
387 * across a page boundary.
390 static dma_cookie_t
ioat_dma_memcpy_pg_to_pg(struct dma_chan
*chan
,
391 struct page
*dest_pg
,
392 unsigned int dest_off
,
394 unsigned int src_off
,
397 dma_addr_t dest_addr
;
399 struct ioat_dma_chan
*ioat_chan
= to_ioat_chan(chan
);
401 dest_addr
= pci_map_page(ioat_chan
->device
->pdev
,
402 dest_pg
, dest_off
, len
, PCI_DMA_FROMDEVICE
);
403 src_addr
= pci_map_page(ioat_chan
->device
->pdev
,
404 src_pg
, src_off
, len
, PCI_DMA_TODEVICE
);
406 return do_ioat_dma_memcpy(ioat_chan
, dest_addr
, src_addr
, len
);
410 * ioat_dma_memcpy_issue_pending - push potentially unrecognized appended descriptors to hw
411 * @chan: DMA channel handle
414 static void ioat_dma_memcpy_issue_pending(struct dma_chan
*chan
)
416 struct ioat_dma_chan
*ioat_chan
= to_ioat_chan(chan
);
418 if (ioat_chan
->pending
!= 0) {
419 ioat_chan
->pending
= 0;
420 ioatdma_chan_write8(ioat_chan
,
422 IOAT_CHANCMD_APPEND
);
426 static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan
*chan
)
428 unsigned long phys_complete
;
429 struct ioat_desc_sw
*desc
, *_desc
;
430 dma_cookie_t cookie
= 0;
432 prefetch(chan
->completion_virt
);
434 if (!spin_trylock(&chan
->cleanup_lock
))
437 /* The completion writeback can happen at any time,
438 so reads by the driver need to be atomic operations
439 The descriptor physical addresses are limited to 32-bits
440 when the CPU can only do a 32-bit mov */
442 #if (BITS_PER_LONG == 64)
444 chan
->completion_virt
->full
& IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR
;
446 phys_complete
= chan
->completion_virt
->low
& IOAT_LOW_COMPLETION_MASK
;
449 if ((chan
->completion_virt
->full
& IOAT_CHANSTS_DMA_TRANSFER_STATUS
) ==
450 IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED
) {
451 printk("IOAT: Channel halted, chanerr = %x\n",
452 ioatdma_chan_read32(chan
, IOAT_CHANERR_OFFSET
));
454 /* TODO do something to salvage the situation */
457 if (phys_complete
== chan
->last_completion
) {
458 spin_unlock(&chan
->cleanup_lock
);
462 spin_lock_bh(&chan
->desc_lock
);
463 list_for_each_entry_safe(desc
, _desc
, &chan
->used_desc
, node
) {
466 * Incoming DMA requests may use multiple descriptors, due to
467 * exceeding xfercap, perhaps. If so, only the last one will
468 * have a cookie, and require unmapping.
471 cookie
= desc
->cookie
;
473 /* yes we are unmapping both _page and _single alloc'd
474 regions with unmap_page. Is this *really* that bad?
476 pci_unmap_page(chan
->device
->pdev
,
477 pci_unmap_addr(desc
, dst
),
478 pci_unmap_len(desc
, dst_len
),
480 pci_unmap_page(chan
->device
->pdev
,
481 pci_unmap_addr(desc
, src
),
482 pci_unmap_len(desc
, src_len
),
486 if (desc
->phys
!= phys_complete
) {
487 /* a completed entry, but not the last, so cleanup */
488 list_del(&desc
->node
);
489 list_add_tail(&desc
->node
, &chan
->free_desc
);
491 /* last used desc. Do not remove, so we can append from
492 it, but don't look at it next time, either */
495 /* TODO check status bits? */
500 spin_unlock_bh(&chan
->desc_lock
);
502 chan
->last_completion
= phys_complete
;
504 chan
->completed_cookie
= cookie
;
506 spin_unlock(&chan
->cleanup_lock
);
510 * ioat_dma_is_complete - poll the status of a IOAT DMA transaction
511 * @chan: IOAT DMA channel handle
512 * @cookie: DMA transaction identifier
513 * @done: if not %NULL, updated with last completed transaction
514 * @used: if not %NULL, updated with last used transaction
517 static enum dma_status
ioat_dma_is_complete(struct dma_chan
*chan
,
522 struct ioat_dma_chan
*ioat_chan
= to_ioat_chan(chan
);
523 dma_cookie_t last_used
;
524 dma_cookie_t last_complete
;
527 last_used
= chan
->cookie
;
528 last_complete
= ioat_chan
->completed_cookie
;
531 *done
= last_complete
;
535 ret
= dma_async_is_complete(cookie
, last_complete
, last_used
);
536 if (ret
== DMA_SUCCESS
)
539 ioat_dma_memcpy_cleanup(ioat_chan
);
541 last_used
= chan
->cookie
;
542 last_complete
= ioat_chan
->completed_cookie
;
545 *done
= last_complete
;
549 return dma_async_is_complete(cookie
, last_complete
, last_used
);
554 static struct pci_device_id ioat_pci_tbl
[] = {
555 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_IOAT
) },
559 static struct pci_driver ioat_pci_drv
= {
561 .id_table
= ioat_pci_tbl
,
563 .remove
= __devexit_p(ioat_remove
),
566 static irqreturn_t
ioat_do_interrupt(int irq
, void *data
)
568 struct ioat_device
*instance
= data
;
569 unsigned long attnstatus
;
572 intrctrl
= ioatdma_read8(instance
, IOAT_INTRCTRL_OFFSET
);
574 if (!(intrctrl
& IOAT_INTRCTRL_MASTER_INT_EN
))
577 if (!(intrctrl
& IOAT_INTRCTRL_INT_STATUS
)) {
578 ioatdma_write8(instance
, IOAT_INTRCTRL_OFFSET
, intrctrl
);
582 attnstatus
= ioatdma_read32(instance
, IOAT_ATTNSTATUS_OFFSET
);
584 printk(KERN_ERR
"ioatdma error: interrupt! status %lx\n", attnstatus
);
586 ioatdma_write8(instance
, IOAT_INTRCTRL_OFFSET
, intrctrl
);
590 static void ioat_start_null_desc(struct ioat_dma_chan
*ioat_chan
)
592 struct ioat_desc_sw
*desc
;
594 spin_lock_bh(&ioat_chan
->desc_lock
);
596 if (!list_empty(&ioat_chan
->free_desc
)) {
597 desc
= to_ioat_desc(ioat_chan
->free_desc
.next
);
598 list_del(&desc
->node
);
600 /* try to get another desc */
601 spin_unlock_bh(&ioat_chan
->desc_lock
);
602 desc
= ioat_dma_alloc_descriptor(ioat_chan
, GFP_KERNEL
);
603 spin_lock_bh(&ioat_chan
->desc_lock
);
604 /* will this ever happen? */
608 desc
->hw
->ctl
= IOAT_DMA_DESCRIPTOR_NUL
;
611 list_add_tail(&desc
->node
, &ioat_chan
->used_desc
);
612 spin_unlock_bh(&ioat_chan
->desc_lock
);
614 #if (BITS_PER_LONG == 64)
615 ioatdma_chan_write64(ioat_chan
, IOAT_CHAINADDR_OFFSET
, desc
->phys
);
617 ioatdma_chan_write32(ioat_chan
,
618 IOAT_CHAINADDR_OFFSET_LOW
,
620 ioatdma_chan_write32(ioat_chan
, IOAT_CHAINADDR_OFFSET_HIGH
, 0);
622 ioatdma_chan_write8(ioat_chan
, IOAT_CHANCMD_OFFSET
, IOAT_CHANCMD_START
);
626 * Perform a IOAT transaction to verify the HW works.
628 #define IOAT_TEST_SIZE 2000
630 static int ioat_self_test(struct ioat_device
*device
)
635 struct dma_chan
*dma_chan
;
639 src
= kzalloc(sizeof(u8
) * IOAT_TEST_SIZE
, GFP_KERNEL
);
642 dest
= kzalloc(sizeof(u8
) * IOAT_TEST_SIZE
, GFP_KERNEL
);
648 /* Fill in src buffer */
649 for (i
= 0; i
< IOAT_TEST_SIZE
; i
++)
652 /* Start copy, using first DMA channel */
653 dma_chan
= container_of(device
->common
.channels
.next
,
656 if (ioat_dma_alloc_chan_resources(dma_chan
) < 1) {
661 cookie
= ioat_dma_memcpy_buf_to_buf(dma_chan
, dest
, src
, IOAT_TEST_SIZE
);
662 ioat_dma_memcpy_issue_pending(dma_chan
);
665 if (ioat_dma_is_complete(dma_chan
, cookie
, NULL
, NULL
) != DMA_SUCCESS
) {
666 printk(KERN_ERR
"ioatdma: Self-test copy timed out, disabling\n");
670 if (memcmp(src
, dest
, IOAT_TEST_SIZE
)) {
671 printk(KERN_ERR
"ioatdma: Self-test copy failed compare, disabling\n");
677 ioat_dma_free_chan_resources(dma_chan
);
684 static int __devinit
ioat_probe(struct pci_dev
*pdev
,
685 const struct pci_device_id
*ent
)
688 unsigned long mmio_start
, mmio_len
;
689 void __iomem
*reg_base
;
690 struct ioat_device
*device
;
692 err
= pci_enable_device(pdev
);
694 goto err_enable_device
;
696 err
= pci_set_dma_mask(pdev
, DMA_64BIT_MASK
);
698 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
700 goto err_set_dma_mask
;
702 err
= pci_request_regions(pdev
, ioat_pci_drv
.name
);
704 goto err_request_regions
;
706 mmio_start
= pci_resource_start(pdev
, 0);
707 mmio_len
= pci_resource_len(pdev
, 0);
709 reg_base
= ioremap(mmio_start
, mmio_len
);
715 device
= kzalloc(sizeof(*device
), GFP_KERNEL
);
721 /* DMA coherent memory pool for DMA descriptor allocations */
722 device
->dma_pool
= pci_pool_create("dma_desc_pool", pdev
,
723 sizeof(struct ioat_dma_descriptor
), 64, 0);
724 if (!device
->dma_pool
) {
729 device
->completion_pool
= pci_pool_create("completion_pool", pdev
, sizeof(u64
), SMP_CACHE_BYTES
, SMP_CACHE_BYTES
);
730 if (!device
->completion_pool
) {
732 goto err_completion_pool
;
736 pci_set_drvdata(pdev
, device
);
737 #ifdef CONFIG_PCI_MSI
738 if (pci_enable_msi(pdev
) == 0) {
744 err
= request_irq(pdev
->irq
, &ioat_do_interrupt
, IRQF_SHARED
, "ioat",
749 device
->reg_base
= reg_base
;
751 ioatdma_write8(device
, IOAT_INTRCTRL_OFFSET
, IOAT_INTRCTRL_MASTER_INT_EN
);
752 pci_set_master(pdev
);
754 INIT_LIST_HEAD(&device
->common
.channels
);
755 enumerate_dma_channels(device
);
757 device
->common
.device_alloc_chan_resources
= ioat_dma_alloc_chan_resources
;
758 device
->common
.device_free_chan_resources
= ioat_dma_free_chan_resources
;
759 device
->common
.device_memcpy_buf_to_buf
= ioat_dma_memcpy_buf_to_buf
;
760 device
->common
.device_memcpy_buf_to_pg
= ioat_dma_memcpy_buf_to_pg
;
761 device
->common
.device_memcpy_pg_to_pg
= ioat_dma_memcpy_pg_to_pg
;
762 device
->common
.device_memcpy_complete
= ioat_dma_is_complete
;
763 device
->common
.device_memcpy_issue_pending
= ioat_dma_memcpy_issue_pending
;
764 printk(KERN_INFO
"Intel(R) I/OAT DMA Engine found, %d channels\n",
765 device
->common
.chancnt
);
767 err
= ioat_self_test(device
);
771 dma_async_device_register(&device
->common
);
777 pci_pool_destroy(device
->completion_pool
);
779 pci_pool_destroy(device
->dma_pool
);
785 pci_release_regions(pdev
);
788 pci_disable_device(pdev
);
793 static void __devexit
ioat_remove(struct pci_dev
*pdev
)
795 struct ioat_device
*device
;
796 struct dma_chan
*chan
, *_chan
;
797 struct ioat_dma_chan
*ioat_chan
;
799 device
= pci_get_drvdata(pdev
);
800 dma_async_device_unregister(&device
->common
);
802 free_irq(device
->pdev
->irq
, device
);
803 #ifdef CONFIG_PCI_MSI
805 pci_disable_msi(device
->pdev
);
807 pci_pool_destroy(device
->dma_pool
);
808 pci_pool_destroy(device
->completion_pool
);
809 iounmap(device
->reg_base
);
810 pci_release_regions(pdev
);
811 pci_disable_device(pdev
);
812 list_for_each_entry_safe(chan
, _chan
, &device
->common
.channels
, device_node
) {
813 ioat_chan
= to_ioat_chan(chan
);
814 list_del(&chan
->device_node
);
821 MODULE_VERSION("1.7");
822 MODULE_LICENSE("GPL");
823 MODULE_AUTHOR("Intel Corporation");
825 static int __init
ioat_init_module(void)
827 /* it's currently unsafe to unload this module */
828 /* if forced, worst case is that rmmod hangs */
829 __unsafe(THIS_MODULE
);
831 return pci_register_driver(&ioat_pci_drv
);
834 module_init(ioat_init_module
);
836 static void __exit
ioat_exit_module(void)
838 pci_unregister_driver(&ioat_pci_drv
);
841 module_exit(ioat_exit_module
);