drivers/usb/host/ehci.h

   1 /*
   2  * Copyright (c) 2001-2002 by David Brownell
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the
   6  * Free Software Foundation; either version 2 of the License, or (at your
   7  * option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software Foundation,
  16  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17  */
  18
  19 #ifndef __LINUX_EHCI_HCD_H
  20 #define __LINUX_EHCI_HCD_H
  21
  22 /* definitions used for the EHCI driver */
  23
  24 /*
  25  * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
  26  * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
  27  * the host controller implementation.
  28  *
  29  * To facilitate the strongest possible byte-order checking from "sparse"
  30  * and so on, we use __leXX unless that's not practical.
  31  */
  32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
  33 typedef __u32 __bitwise __hc32;
  34 typedef __u16 __bitwise __hc16;
  35 #else
  36 #define __hc32  __le32
  37 #define __hc16  __le16
  38 #endif
  39
  40 /* statistics can be kept for for tuning/monitoring */
  41 struct ehci_stats {
  42         /* irq usage */
  43         unsigned long           normal;
  44         unsigned long           error;
  45         unsigned long           reclaim;
  46         unsigned long           lost_iaa;
  47
  48         /* termination of urbs from core */
  49         unsigned long           complete;
  50         unsigned long           unlink;
  51 };
  52
  53 /* ehci_hcd->lock guards shared data against other CPUs:
  54  *   ehci_hcd:  async, reclaim, periodic (and shadow), ...
  55  *   usb_host_endpoint: hcpriv
  56  *   ehci_qh:   qh_next, qtd_list
  57  *   ehci_qtd:  qtd_list
  58  *
  59  * Also, hold this lock when talking to HC registers or
  60  * when updating hw_* fields in shared qh/qtd/... structures.
  61  */
  62
  63 #define EHCI_MAX_ROOT_PORTS     15              /* see HCS_N_PORTS */
  64
  65 struct ehci_hcd {                       /* one per controller */
  66         /* glue to PCI and HCD framework */
  67         struct ehci_caps __iomem *caps;
  68         struct ehci_regs __iomem *regs;
  69         struct ehci_dbg_port __iomem *debug;
  70
  71         __u32                   hcs_params;     /* cached register copy */
  72         spinlock_t              lock;
  73
  74         /* async schedule support */
  75         struct ehci_qh          *async;
  76         struct ehci_qh          *reclaim;
  77         unsigned                scanning : 1;
  78
  79         /* periodic schedule support */
  80 #define DEFAULT_I_TDPS          1024            /* some HCs can do less */
  81         unsigned                periodic_size;
  82         __hc32                  *periodic;      /* hw periodic table */
  83         dma_addr_t              periodic_dma;
  84         unsigned                i_thresh;       /* uframes HC might cache */
  85
  86         union ehci_shadow       *pshadow;       /* mirror hw periodic table */
  87         int                     next_uframe;    /* scan periodic, start here */
  88         unsigned                periodic_sched; /* periodic activity count */
  89
  90         /* per root hub port */
  91         unsigned long           reset_done [EHCI_MAX_ROOT_PORTS];
  92
  93         /* bit vectors (one bit per port) */
  94         unsigned long           bus_suspended;          /* which ports were
  95                         already suspended at the start of a bus suspend */
  96         unsigned long           companion_ports;        /* which ports are
  97                         dedicated to the companion controller */
  98         unsigned long           owned_ports;            /* which ports are
  99                         owned by the companion during a bus suspend */
 100         unsigned long           port_c_suspend;         /* which ports have
 101                         the change-suspend feature turned on */
 102
 103         /* per-HC memory pools (could be per-bus, but ...) */
 104         struct dma_pool         *qh_pool;       /* qh per active urb */
 105         struct dma_pool         *qtd_pool;      /* one or more per qh */
 106         struct dma_pool         *itd_pool;      /* itd per iso urb */
 107         struct dma_pool         *sitd_pool;     /* sitd per split iso urb */
 108
 109         struct timer_list       iaa_watchdog;
 110         struct timer_list       watchdog;
 111         unsigned long           actions;
 112         unsigned                stamp;
 113         unsigned long           next_statechange;
 114         u32                     command;
 115
 116         /* SILICON QUIRKS */
 117         unsigned                no_selective_suspend:1;
 118         unsigned                has_fsl_port_bug:1; /* FreeScale */
 119         unsigned                big_endian_mmio:1;
 120         unsigned                big_endian_desc:1;
 121
 122         u8                      sbrn;           /* packed release number */
 123
 124         /* irq statistics */
 125 #ifdef EHCI_STATS
 126         struct ehci_stats       stats;
 127 #       define COUNT(x) do { (x)++; } while (0)
 128 #else
 129 #       define COUNT(x) do {} while (0)
 130 #endif
 131
 132         /* debug files */
 133 #ifdef DEBUG
 134         struct dentry           *debug_dir;
 135         struct dentry           *debug_async;
 136         struct dentry           *debug_periodic;
 137         struct dentry           *debug_registers;
 138 #endif
 139 };
 140
 141 /* convert between an HCD pointer and the corresponding EHCI_HCD */
 142 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
 143 {
 144         return (struct ehci_hcd *) (hcd->hcd_priv);
 145 }
 146 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
 147 {
 148         return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
 149 }
 150
 151
 152 static inline void
 153 iaa_watchdog_start(struct ehci_hcd *ehci)
 154 {
 155         WARN_ON(timer_pending(&ehci->iaa_watchdog));
 156         mod_timer(&ehci->iaa_watchdog,
 157                         jiffies + msecs_to_jiffies(EHCI_IAA_MSECS));
 158 }
 159
 160 static inline void iaa_watchdog_done(struct ehci_hcd *ehci)
 161 {
 162         del_timer(&ehci->iaa_watchdog);
 163 }
 164
 165 enum ehci_timer_action {
 166         TIMER_IO_WATCHDOG,
 167         TIMER_ASYNC_SHRINK,
 168         TIMER_ASYNC_OFF,
 169 };
 170
 171 static inline void
 172 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
 173 {
 174         clear_bit (action, &ehci->actions);
 175 }
 176
 177 static inline void
 178 timer_action (struct ehci_hcd *ehci, enum ehci_timer_action action)
 179 {
 180         if (!test_and_set_bit (action, &ehci->actions)) {
 181                 unsigned long t;
 182
 183                 switch (action) {
 184                 case TIMER_IO_WATCHDOG:
 185                         t = EHCI_IO_JIFFIES;
 186                         break;
 187                 case TIMER_ASYNC_OFF:
 188                         t = EHCI_ASYNC_JIFFIES;
 189                         break;
 190                 // case TIMER_ASYNC_SHRINK:
 191                 default:
 192                         t = EHCI_SHRINK_JIFFIES;
 193                         break;
 194                 }
 195                 t += jiffies;
 196                 // all timings except IAA watchdog can be overridden.
 197                 // async queue SHRINK often precedes IAA.  while it's ready
 198                 // to go OFF neither can matter, and afterwards the IO
 199                 // watchdog stops unless there's still periodic traffic.
 200                 if (time_before_eq(t, ehci->watchdog.expires)
 201                                 && timer_pending (&ehci->watchdog))
 202                         return;
 203                 mod_timer (&ehci->watchdog, t);
 204         }
 205 }
 206
 207 /*-------------------------------------------------------------------------*/
 208
 209 /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
 210
 211 /* Section 2.2 Host Controller Capability Registers */
 212 struct ehci_caps {
 213         /* these fields are specified as 8 and 16 bit registers,
 214          * but some hosts can't perform 8 or 16 bit PCI accesses.
 215          */
 216         u32             hc_capbase;
 217 #define HC_LENGTH(p)            (((p)>>00)&0x00ff)      /* bits 7:0 */
 218 #define HC_VERSION(p)           (((p)>>16)&0xffff)      /* bits 31:16 */
 219         u32             hcs_params;     /* HCSPARAMS - offset 0x4 */
 220 #define HCS_DEBUG_PORT(p)       (((p)>>20)&0xf) /* bits 23:20, debug port? */
 221 #define HCS_INDICATOR(p)        ((p)&(1 << 16)) /* true: has port indicators */
 222 #define HCS_N_CC(p)             (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
 223 #define HCS_N_PCC(p)            (((p)>>8)&0xf)  /* bits 11:8, ports per CC */
 224 #define HCS_PORTROUTED(p)       ((p)&(1 << 7))  /* true: port routing */
 225 #define HCS_PPC(p)              ((p)&(1 << 4))  /* true: port power control */
 226 #define HCS_N_PORTS(p)          (((p)>>0)&0xf)  /* bits 3:0, ports on HC */
 227
 228         u32             hcc_params;      /* HCCPARAMS - offset 0x8 */
 229 #define HCC_EXT_CAPS(p)         (((p)>>8)&0xff) /* for pci extended caps */
 230 #define HCC_ISOC_CACHE(p)       ((p)&(1 << 7))  /* true: can cache isoc frame */
 231 #define HCC_ISOC_THRES(p)       (((p)>>4)&0x7)  /* bits 6:4, uframes cached */
 232 #define HCC_CANPARK(p)          ((p)&(1 << 2))  /* true: can park on async qh */
 233 #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1))  /* true: periodic_size changes*/
 234 #define HCC_64BIT_ADDR(p)       ((p)&(1))       /* true: can use 64-bit addr */
 235         u8              portroute [8];   /* nibbles for routing - offset 0xC */
 236 } __attribute__ ((packed));
 237
 238
 239 /* Section 2.3 Host Controller Operational Registers */
 240 struct ehci_regs {
 241
 242         /* USBCMD: offset 0x00 */
 243         u32             command;
 244 /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
 245 #define CMD_PARK        (1<<11)         /* enable "park" on async qh */
 246 #define CMD_PARK_CNT(c) (((c)>>8)&3)    /* how many transfers to park for */
 247 #define CMD_LRESET      (1<<7)          /* partial reset (no ports, etc) */
 248 #define CMD_IAAD        (1<<6)          /* "doorbell" interrupt async advance */
 249 #define CMD_ASE         (1<<5)          /* async schedule enable */
 250 #define CMD_PSE         (1<<4)          /* periodic schedule enable */
 251 /* 3:2 is periodic frame list size */
 252 #define CMD_RESET       (1<<1)          /* reset HC not bus */
 253 #define CMD_RUN         (1<<0)          /* start/stop HC */
 254
 255         /* USBSTS: offset 0x04 */
 256         u32             status;
 257 #define STS_ASS         (1<<15)         /* Async Schedule Status */
 258 #define STS_PSS         (1<<14)         /* Periodic Schedule Status */
 259 #define STS_RECL        (1<<13)         /* Reclamation */
 260 #define STS_HALT        (1<<12)         /* Not running (any reason) */
 261 /* some bits reserved */
 262         /* these STS_* flags are also intr_enable bits (USBINTR) */
 263 #define STS_IAA         (1<<5)          /* Interrupted on async advance */
 264 #define STS_FATAL       (1<<4)          /* such as some PCI access errors */
 265 #define STS_FLR         (1<<3)          /* frame list rolled over */
 266 #define STS_PCD         (1<<2)          /* port change detect */
 267 #define STS_ERR         (1<<1)          /* "error" completion (overflow, ...) */
 268 #define STS_INT         (1<<0)          /* "normal" completion (short, ...) */
 269
 270         /* USBINTR: offset 0x08 */
 271         u32             intr_enable;
 272
 273         /* FRINDEX: offset 0x0C */
 274         u32             frame_index;    /* current microframe number */
 275         /* CTRLDSSEGMENT: offset 0x10 */
 276         u32             segment;        /* address bits 63:32 if needed */
 277         /* PERIODICLISTBASE: offset 0x14 */
 278         u32             frame_list;     /* points to periodic list */
 279         /* ASYNCLISTADDR: offset 0x18 */
 280         u32             async_next;     /* address of next async queue head */
 281
 282         u32             reserved [9];
 283
 284         /* CONFIGFLAG: offset 0x40 */
 285         u32             configured_flag;
 286 #define FLAG_CF         (1<<0)          /* true: we'll support "high speed" */
 287
 288         /* PORTSC: offset 0x44 */
 289         u32             port_status [0];        /* up to N_PORTS */
 290 /* 31:23 reserved */
 291 #define PORT_WKOC_E     (1<<22)         /* wake on overcurrent (enable) */
 292 #define PORT_WKDISC_E   (1<<21)         /* wake on disconnect (enable) */
 293 #define PORT_WKCONN_E   (1<<20)         /* wake on connect (enable) */
 294 /* 19:16 for port testing */
 295 #define PORT_LED_OFF    (0<<14)
 296 #define PORT_LED_AMBER  (1<<14)
 297 #define PORT_LED_GREEN  (2<<14)
 298 #define PORT_LED_MASK   (3<<14)
 299 #define PORT_OWNER      (1<<13)         /* true: companion hc owns this port */
 300 #define PORT_POWER      (1<<12)         /* true: has power (see PPC) */
 301 #define PORT_USB11(x) (((x)&(3<<10))==(1<<10))  /* USB 1.1 device */
 302 /* 11:10 for detecting lowspeed devices (reset vs release ownership) */
 303 /* 9 reserved */
 304 #define PORT_RESET      (1<<8)          /* reset port */
 305 #define PORT_SUSPEND    (1<<7)          /* suspend port */
 306 #define PORT_RESUME     (1<<6)          /* resume it */
 307 #define PORT_OCC        (1<<5)          /* over current change */
 308 #define PORT_OC         (1<<4)          /* over current active */
 309 #define PORT_PEC        (1<<3)          /* port enable change */
 310 #define PORT_PE         (1<<2)          /* port enable */
 311 #define PORT_CSC        (1<<1)          /* connect status change */
 312 #define PORT_CONNECT    (1<<0)          /* device connected */
 313 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_OCC)
 314 } __attribute__ ((packed));
 315
 316 #define USBMODE         0x68            /* USB Device mode */
 317 #define USBMODE_SDIS    (1<<3)          /* Stream disable */
 318 #define USBMODE_BE      (1<<2)          /* BE/LE endianness select */
 319 #define USBMODE_CM_HC   (3<<0)          /* host controller mode */
 320 #define USBMODE_CM_IDLE (0<<0)          /* idle state */
 321
 322 /* Appendix C, Debug port ... intended for use with special "debug devices"
 323  * that can help if there's no serial console.  (nonstandard enumeration.)
 324  */
 325 struct ehci_dbg_port {
 326         u32     control;
 327 #define DBGP_OWNER      (1<<30)
 328 #define DBGP_ENABLED    (1<<28)
 329 #define DBGP_DONE       (1<<16)
 330 #define DBGP_INUSE      (1<<10)
 331 #define DBGP_ERRCODE(x) (((x)>>7)&0x07)
 332 #       define DBGP_ERR_BAD     1
 333 #       define DBGP_ERR_SIGNAL  2
 334 #define DBGP_ERROR      (1<<6)
 335 #define DBGP_GO         (1<<5)
 336 #define DBGP_OUT        (1<<4)
 337 #define DBGP_LEN(x)     (((x)>>0)&0x0f)
 338         u32     pids;
 339 #define DBGP_PID_GET(x)         (((x)>>16)&0xff)
 340 #define DBGP_PID_SET(data,tok)  (((data)<<8)|(tok))
 341         u32     data03;
 342         u32     data47;
 343         u32     address;
 344 #define DBGP_EPADDR(dev,ep)     (((dev)<<8)|(ep))
 345 } __attribute__ ((packed));
 346
 347 /*-------------------------------------------------------------------------*/
 348
 349 #define QTD_NEXT(ehci, dma)     cpu_to_hc32(ehci, (u32)dma)
 350
 351 /*
 352  * EHCI Specification 0.95 Section 3.5
 353  * QTD: describe data transfer components (buffer, direction, ...)
 354  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
 355  *
 356  * These are associated only with "QH" (Queue Head) structures,
 357  * used with control, bulk, and interrupt transfers.
 358  */
 359 struct ehci_qtd {
 360         /* first part defined by EHCI spec */
 361         __hc32                  hw_next;        /* see EHCI 3.5.1 */
 362         __hc32                  hw_alt_next;    /* see EHCI 3.5.2 */
 363         __hc32                  hw_token;       /* see EHCI 3.5.3 */
 364 #define QTD_TOGGLE      (1 << 31)       /* data toggle */
 365 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
 366 #define QTD_IOC         (1 << 15)       /* interrupt on complete */
 367 #define QTD_CERR(tok)   (((tok)>>10) & 0x3)
 368 #define QTD_PID(tok)    (((tok)>>8) & 0x3)
 369 #define QTD_STS_ACTIVE  (1 << 7)        /* HC may execute this */
 370 #define QTD_STS_HALT    (1 << 6)        /* halted on error */
 371 #define QTD_STS_DBE     (1 << 5)        /* data buffer error (in HC) */
 372 #define QTD_STS_BABBLE  (1 << 4)        /* device was babbling (qtd halted) */
 373 #define QTD_STS_XACT    (1 << 3)        /* device gave illegal response */
 374 #define QTD_STS_MMF     (1 << 2)        /* incomplete split transaction */
 375 #define QTD_STS_STS     (1 << 1)        /* split transaction state */
 376 #define QTD_STS_PING    (1 << 0)        /* issue PING? */
 377
 378 #define ACTIVE_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_ACTIVE)
 379 #define HALT_BIT(ehci)          cpu_to_hc32(ehci, QTD_STS_HALT)
 380 #define STATUS_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_STS)
 381
 382         __hc32                  hw_buf [5];        /* see EHCI 3.5.4 */
 383         __hc32                  hw_buf_hi [5];        /* Appendix B */
 384
 385         /* the rest is HCD-private */
 386         dma_addr_t              qtd_dma;                /* qtd address */
 387         struct list_head        qtd_list;               /* sw qtd list */
 388         struct urb              *urb;                   /* qtd's urb */
 389         size_t                  length;                 /* length of buffer */
 390 } __attribute__ ((aligned (32)));
 391
 392 /* mask NakCnt+T in qh->hw_alt_next */
 393 #define QTD_MASK(ehci)  cpu_to_hc32 (ehci, ~0x1f)
 394
 395 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
 396
 397 /*-------------------------------------------------------------------------*/
 398
 399 /* type tag from {qh,itd,sitd,fstn}->hw_next */
 400 #define Q_NEXT_TYPE(ehci,dma)   ((dma) & cpu_to_hc32(ehci, 3 << 1))
 401
 402 /*
 403  * Now the following defines are not converted using the
 404  * __constant_cpu_to_le32() macro anymore, since we have to support
 405  * "dynamic" switching between be and le support, so that the driver
 406  * can be used on one system with SoC EHCI controller using big-endian
 407  * descriptors as well as a normal little-endian PCI EHCI controller.
 408  */
 409 /* values for that type tag */
 410 #define Q_TYPE_ITD      (0 << 1)
 411 #define Q_TYPE_QH       (1 << 1)
 412 #define Q_TYPE_SITD     (2 << 1)
 413 #define Q_TYPE_FSTN     (3 << 1)
 414
 415 /* next async queue entry, or pointer to interrupt/periodic QH */
 416 #define QH_NEXT(ehci,dma)       (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
 417
 418 /* for periodic/async schedules and qtd lists, mark end of list */
 419 #define EHCI_LIST_END(ehci)     cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
 420
 421 /*
 422  * Entries in periodic shadow table are pointers to one of four kinds
 423  * of data structure.  That's dictated by the hardware; a type tag is
 424  * encoded in the low bits of the hardware's periodic schedule.  Use
 425  * Q_NEXT_TYPE to get the tag.
 426  *
 427  * For entries in the async schedule, the type tag always says "qh".
 428  */
 429 union ehci_shadow {
 430         struct ehci_qh          *qh;            /* Q_TYPE_QH */
 431         struct ehci_itd         *itd;           /* Q_TYPE_ITD */
 432         struct ehci_sitd        *sitd;          /* Q_TYPE_SITD */
 433         struct ehci_fstn        *fstn;          /* Q_TYPE_FSTN */
 434         __hc32                  *hw_next;       /* (all types) */
 435         void                    *ptr;
 436 };
 437
 438 /*-------------------------------------------------------------------------*/
 439
 440 /*
 441  * EHCI Specification 0.95 Section 3.6
 442  * QH: describes control/bulk/interrupt endpoints
 443  * See Fig 3-7 "Queue Head Structure Layout".
 444  *
 445  * These appear in both the async and (for interrupt) periodic schedules.
 446  */
 447
 448 struct ehci_qh {
 449         /* first part defined by EHCI spec */
 450         __hc32                  hw_next;        /* see EHCI 3.6.1 */
 451         __hc32                  hw_info1;       /* see EHCI 3.6.2 */
 452 #define QH_HEAD         0x00008000
 453         __hc32                  hw_info2;        /* see EHCI 3.6.2 */
 454 #define QH_SMASK        0x000000ff
 455 #define QH_CMASK        0x0000ff00
 456 #define QH_HUBADDR      0x007f0000
 457 #define QH_HUBPORT      0x3f800000
 458 #define QH_MULT         0xc0000000
 459         __hc32                  hw_current;     /* qtd list - see EHCI 3.6.4 */
 460
 461         /* qtd overlay (hardware parts of a struct ehci_qtd) */
 462         __hc32                  hw_qtd_next;
 463         __hc32                  hw_alt_next;
 464         __hc32                  hw_token;
 465         __hc32                  hw_buf [5];
 466         __hc32                  hw_buf_hi [5];
 467
 468         /* the rest is HCD-private */
 469         dma_addr_t              qh_dma;         /* address of qh */
 470         union ehci_shadow       qh_next;        /* ptr to qh; or periodic */
 471         struct list_head        qtd_list;       /* sw qtd list */
 472         struct ehci_qtd         *dummy;
 473         struct ehci_qh          *reclaim;       /* next to reclaim */
 474
 475         struct ehci_hcd         *ehci;
 476
 477         /*
 478          * Do NOT use atomic operations for QH refcounting. On some CPUs
 479          * (PPC7448 for example), atomic operations cannot be performed on
 480          * memory that is cache-inhibited (i.e. being used for DMA).
 481          * Spinlocks are used to protect all QH fields.
 482          */
 483         u32                     refcount;
 484         unsigned                stamp;
 485
 486         u8                      qh_state;
 487 #define QH_STATE_LINKED         1               /* HC sees this */
 488 #define QH_STATE_UNLINK         2               /* HC may still see this */
 489 #define QH_STATE_IDLE           3               /* HC doesn't see this */
 490 #define QH_STATE_UNLINK_WAIT    4               /* LINKED and on reclaim q */
 491 #define QH_STATE_COMPLETING     5               /* don't touch token.HALT */
 492
 493         /* periodic schedule info */
 494         u8                      usecs;          /* intr bandwidth */
 495         u8                      gap_uf;         /* uframes split/csplit gap */
 496         u8                      c_usecs;        /* ... split completion bw */
 497         u16                     tt_usecs;       /* tt downstream bandwidth */
 498         unsigned short          period;         /* polling interval */
 499         unsigned short          start;          /* where polling starts */
 500 #define NO_FRAME ((unsigned short)~0)                   /* pick new start */
 501         struct usb_device       *dev;           /* access to TT */
 502 } __attribute__ ((aligned (32)));
 503
 504 /*-------------------------------------------------------------------------*/
 505
 506 /* description of one iso transaction (up to 3 KB data if highspeed) */
 507 struct ehci_iso_packet {
 508         /* These will be copied to iTD when scheduling */
 509         u64                     bufp;           /* itd->hw_bufp{,_hi}[pg] |= */
 510         __hc32                  transaction;    /* itd->hw_transaction[i] |= */
 511         u8                      cross;          /* buf crosses pages */
 512         /* for full speed OUT splits */
 513         u32                     buf1;
 514 };
 515
 516 /* temporary schedule data for packets from iso urbs (both speeds)
 517  * each packet is one logical usb transaction to the device (not TT),
 518  * beginning at stream->next_uframe
 519  */
 520 struct ehci_iso_sched {
 521         struct list_head        td_list;
 522         unsigned                span;
 523         struct ehci_iso_packet  packet [0];
 524 };
 525
 526 /*
 527  * ehci_iso_stream - groups all (s)itds for this endpoint.
 528  * acts like a qh would, if EHCI had them for ISO.
 529  */
 530 struct ehci_iso_stream {
 531         /* first two fields match QH, but info1 == 0 */
 532         __hc32                  hw_next;
 533         __hc32                  hw_info1;
 534
 535         u32                     refcount;
 536         u8                      bEndpointAddress;
 537         u8                      highspeed;
 538         u16                     depth;          /* depth in uframes */
 539         struct list_head        td_list;        /* queued itds/sitds */
 540         struct list_head        free_list;      /* list of unused itds/sitds */
 541         struct usb_device       *udev;
 542         struct usb_host_endpoint *ep;
 543
 544         /* output of (re)scheduling */
 545         unsigned long           start;          /* jiffies */
 546         unsigned long           rescheduled;
 547         int                     next_uframe;
 548         __hc32                  splits;
 549
 550         /* the rest is derived from the endpoint descriptor,
 551          * trusting urb->interval == f(epdesc->bInterval) and
 552          * including the extra info for hw_bufp[0..2]
 553          */
 554         u8                      usecs, c_usecs;
 555         u16                     interval;
 556         u16                     tt_usecs;
 557         u16                     maxp;
 558         u16                     raw_mask;
 559         unsigned                bandwidth;
 560
 561         /* This is used to initialize iTD's hw_bufp fields */
 562         __hc32                  buf0;
 563         __hc32                  buf1;
 564         __hc32                  buf2;
 565
 566         /* this is used to initialize sITD's tt info */
 567         __hc32                  address;
 568 };
 569
 570 /*-------------------------------------------------------------------------*/
 571
 572 /*
 573  * EHCI Specification 0.95 Section 3.3
 574  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
 575  *
 576  * Schedule records for high speed iso xfers
 577  */
 578 struct ehci_itd {
 579         /* first part defined by EHCI spec */
 580         __hc32                  hw_next;           /* see EHCI 3.3.1 */
 581         __hc32                  hw_transaction [8]; /* see EHCI 3.3.2 */
 582 #define EHCI_ISOC_ACTIVE        (1<<31)        /* activate transfer this slot */
 583 #define EHCI_ISOC_BUF_ERR       (1<<30)        /* Data buffer error */
 584 #define EHCI_ISOC_BABBLE        (1<<29)        /* babble detected */
 585 #define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
 586 #define EHCI_ITD_LENGTH(tok)    (((tok)>>16) & 0x0fff)
 587 #define EHCI_ITD_IOC            (1 << 15)       /* interrupt on complete */
 588
 589 #define ITD_ACTIVE(ehci)        cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
 590
 591         __hc32                  hw_bufp [7];    /* see EHCI 3.3.3 */
 592         __hc32                  hw_bufp_hi [7]; /* Appendix B */
 593
 594         /* the rest is HCD-private */
 595         dma_addr_t              itd_dma;        /* for this itd */
 596         union ehci_shadow       itd_next;       /* ptr to periodic q entry */
 597
 598         struct urb              *urb;
 599         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 600         struct list_head        itd_list;       /* list of stream's itds */
 601
 602         /* any/all hw_transactions here may be used by that urb */
 603         unsigned                frame;          /* where scheduled */
 604         unsigned                pg;
 605         unsigned                index[8];       /* in urb->iso_frame_desc */
 606 } __attribute__ ((aligned (32)));
 607
 608 /*-------------------------------------------------------------------------*/
 609
 610 /*
 611  * EHCI Specification 0.95 Section 3.4
 612  * siTD, aka split-transaction isochronous Transfer Descriptor
 613  *       ... describe full speed iso xfers through TT in hubs
 614  * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
 615  */
 616 struct ehci_sitd {
 617         /* first part defined by EHCI spec */
 618         __hc32                  hw_next;
 619 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
 620         __hc32                  hw_fullspeed_ep;        /* EHCI table 3-9 */
 621         __hc32                  hw_uframe;              /* EHCI table 3-10 */
 622         __hc32                  hw_results;             /* EHCI table 3-11 */
 623 #define SITD_IOC        (1 << 31)       /* interrupt on completion */
 624 #define SITD_PAGE       (1 << 30)       /* buffer 0/1 */
 625 #define SITD_LENGTH(x)  (0x3ff & ((x)>>16))
 626 #define SITD_STS_ACTIVE (1 << 7)        /* HC may execute this */
 627 #define SITD_STS_ERR    (1 << 6)        /* error from TT */
 628 #define SITD_STS_DBE    (1 << 5)        /* data buffer error (in HC) */
 629 #define SITD_STS_BABBLE (1 << 4)        /* device was babbling */
 630 #define SITD_STS_XACT   (1 << 3)        /* illegal IN response */
 631 #define SITD_STS_MMF    (1 << 2)        /* incomplete split transaction */
 632 #define SITD_STS_STS    (1 << 1)        /* split transaction state */
 633
 634 #define SITD_ACTIVE(ehci)       cpu_to_hc32(ehci, SITD_STS_ACTIVE)
 635
 636         __hc32                  hw_buf [2];             /* EHCI table 3-12 */
 637         __hc32                  hw_backpointer;         /* EHCI table 3-13 */
 638         __hc32                  hw_buf_hi [2];          /* Appendix B */
 639
 640         /* the rest is HCD-private */
 641         dma_addr_t              sitd_dma;
 642         union ehci_shadow       sitd_next;      /* ptr to periodic q entry */
 643
 644         struct urb              *urb;
 645         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 646         struct list_head        sitd_list;      /* list of stream's sitds */
 647         unsigned                frame;
 648         unsigned                index;
 649 } __attribute__ ((aligned (32)));
 650
 651 /*-------------------------------------------------------------------------*/
 652
 653 /*
 654  * EHCI Specification 0.96 Section 3.7
 655  * Periodic Frame Span Traversal Node (FSTN)
 656  *
 657  * Manages split interrupt transactions (using TT) that span frame boundaries
 658  * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
 659  * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
 660  * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
 661  */
 662 struct ehci_fstn {
 663         __hc32                  hw_next;        /* any periodic q entry */
 664         __hc32                  hw_prev;        /* qh or EHCI_LIST_END */
 665
 666         /* the rest is HCD-private */
 667         dma_addr_t              fstn_dma;
 668         union ehci_shadow       fstn_next;      /* ptr to periodic q entry */
 669 } __attribute__ ((aligned (32)));
 670
 671 /*-------------------------------------------------------------------------*/
 672
 673 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
 674
 675 /*
 676  * Some EHCI controllers have a Transaction Translator built into the
 677  * root hub. This is a non-standard feature.  Each controller will need
 678  * to add code to the following inline functions, and call them as
 679  * needed (mostly in root hub code).
 680  */
 681
 682 #define ehci_is_TDI(e)                  (ehci_to_hcd(e)->has_tt)
 683
 684 /* Returns the speed of a device attached to a port on the root hub. */
 685 static inline unsigned int
 686 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
 687 {
 688         if (ehci_is_TDI(ehci)) {
 689                 switch ((portsc>>26)&3) {
 690                 case 0:
 691                         return 0;
 692                 case 1:
 693                         return (1<<USB_PORT_FEAT_LOWSPEED);
 694                 case 2:
 695                 default:
 696                         return (1<<USB_PORT_FEAT_HIGHSPEED);
 697                 }
 698         }
 699         return (1<<USB_PORT_FEAT_HIGHSPEED);
 700 }
 701
 702 #else
 703
 704 #define ehci_is_TDI(e)                  (0)
 705
 706 #define ehci_port_speed(ehci, portsc)   (1<<USB_PORT_FEAT_HIGHSPEED)
 707 #endif
 708
 709 /*-------------------------------------------------------------------------*/
 710
 711 #ifdef CONFIG_PPC_83xx
 712 /* Some Freescale processors have an erratum in which the TT
 713  * port number in the queue head was 0..N-1 instead of 1..N.
 714  */
 715 #define ehci_has_fsl_portno_bug(e)              ((e)->has_fsl_port_bug)
 716 #else
 717 #define ehci_has_fsl_portno_bug(e)              (0)
 718 #endif
 719
 720 /*
 721  * While most USB host controllers implement their registers in
 722  * little-endian format, a minority (celleb companion chip) implement
 723  * them in big endian format.
 724  *
 725  * This attempts to support either format at compile time without a
 726  * runtime penalty, or both formats with the additional overhead
 727  * of checking a flag bit.
 728  */
 729
 730 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 731 #define ehci_big_endian_mmio(e)         ((e)->big_endian_mmio)
 732 #else
 733 #define ehci_big_endian_mmio(e)         0
 734 #endif
 735
 736 /*
 737  * Big-endian read/write functions are arch-specific.
 738  * Other arches can be added if/when they're needed.
 739  *
 740  * REVISIT: arch/powerpc now has readl/writel_be, so the
 741  * definition below can die once the 4xx support is
 742  * finally ported over.
 743  */
 744 #if defined(CONFIG_PPC) && !defined(CONFIG_PPC_MERGE)
 745 #define readl_be(addr)          in_be32((__force unsigned *)addr)
 746 #define writel_be(val, addr)    out_be32((__force unsigned *)addr, val)
 747 #endif
 748
 749 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
 750 #define readl_be(addr)          __raw_readl((__force unsigned *)addr)
 751 #define writel_be(val, addr)    __raw_writel(val, (__force unsigned *)addr)
 752 #endif
 753
 754 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
 755                 __u32 __iomem * regs)
 756 {
 757 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 758         return ehci_big_endian_mmio(ehci) ?
 759                 readl_be(regs) :
 760                 readl(regs);
 761 #else
 762         return readl(regs);
 763 #endif
 764 }
 765
 766 static inline void ehci_writel(const struct ehci_hcd *ehci,
 767                 const unsigned int val, __u32 __iomem *regs)
 768 {
 769 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 770         ehci_big_endian_mmio(ehci) ?
 771                 writel_be(val, regs) :
 772                 writel(val, regs);
 773 #else
 774         writel(val, regs);
 775 #endif
 776 }
 777
 778 /*-------------------------------------------------------------------------*/
 779
 780 /*
 781  * The AMCC 440EPx not only implements its EHCI registers in big-endian
 782  * format, but also its DMA data structures (descriptors).
 783  *
 784  * EHCI controllers accessed through PCI work normally (little-endian
 785  * everywhere), so we won't bother supporting a BE-only mode for now.
 786  */
 787 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
 788 #define ehci_big_endian_desc(e)         ((e)->big_endian_desc)
 789
 790 /* cpu to ehci */
 791 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
 792 {
 793         return ehci_big_endian_desc(ehci)
 794                 ? (__force __hc32)cpu_to_be32(x)
 795                 : (__force __hc32)cpu_to_le32(x);
 796 }
 797
 798 /* ehci to cpu */
 799 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
 800 {
 801         return ehci_big_endian_desc(ehci)
 802                 ? be32_to_cpu((__force __be32)x)
 803                 : le32_to_cpu((__force __le32)x);
 804 }
 805
 806 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
 807 {
 808         return ehci_big_endian_desc(ehci)
 809                 ? be32_to_cpup((__force __be32 *)x)
 810                 : le32_to_cpup((__force __le32 *)x);
 811 }
 812
 813 #else
 814
 815 /* cpu to ehci */
 816 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
 817 {
 818         return cpu_to_le32(x);
 819 }
 820
 821 /* ehci to cpu */
 822 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
 823 {
 824         return le32_to_cpu(x);
 825 }
 826
 827 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
 828 {
 829         return le32_to_cpup(x);
 830 }
 831
 832 #endif
 833
 834 /*-------------------------------------------------------------------------*/
 835
 836 #ifndef DEBUG
 837 #define STUB_DEBUG_FILES
 838 #endif  /* DEBUG */
 839
 840 /*-------------------------------------------------------------------------*/
 841
 842 #endif /* __LINUX_EHCI_HCD_H */