2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/kernel_stat.h>
18 #include <linux/mc146818rtc.h>
19 #include <linux/acpi_pmtmr.h>
20 #include <linux/clockchips.h>
21 #include <linux/interrupt.h>
22 #include <linux/bootmem.h>
23 #include <linux/ftrace.h>
24 #include <linux/ioport.h>
25 #include <linux/module.h>
26 #include <linux/sysdev.h>
27 #include <linux/delay.h>
28 #include <linux/timex.h>
29 #include <linux/dmar.h>
30 #include <linux/init.h>
31 #include <linux/cpu.h>
32 #include <linux/dmi.h>
33 #include <linux/nmi.h>
34 #include <linux/smp.h>
37 #include <asm/arch_hooks.h>
38 #include <asm/pgalloc.h>
39 #include <asm/genapic.h>
40 #include <asm/atomic.h>
41 #include <asm/mpspec.h>
42 #include <asm/i8253.h>
43 #include <asm/i8259.h>
44 #include <asm/proto.h>
55 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
56 # error SPURIOUS_APIC_VECTOR definition error
59 unsigned int num_processors
;
60 unsigned disabled_cpus __cpuinitdata
;
61 /* Processor that is doing the boot up */
62 unsigned int boot_cpu_physical_apicid
= -1U;
63 EXPORT_SYMBOL(boot_cpu_physical_apicid
);
64 unsigned int max_physical_apicid
;
66 /* Bitmask of physically existing CPUs */
67 physid_mask_t phys_cpu_present_map
;
70 * Map cpu index to physical APIC ID
72 DEFINE_EARLY_PER_CPU(u16
, x86_cpu_to_apicid
, BAD_APICID
);
73 DEFINE_EARLY_PER_CPU(u16
, x86_bios_cpu_apicid
, BAD_APICID
);
74 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid
);
75 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid
);
79 * Knob to control our willingness to enable the local APIC.
83 static int force_enable_local_apic
;
85 * APIC command line parameters
87 static int __init
parse_lapic(char *arg
)
89 force_enable_local_apic
= 1;
92 early_param("lapic", parse_lapic
);
93 /* Local APIC was disabled by the BIOS and enabled by the kernel */
94 static int enabled_via_apicbase
;
99 static int apic_calibrate_pmtmr __initdata
;
100 static __init
int setup_apicpmtimer(char *s
)
102 apic_calibrate_pmtmr
= 1;
106 __setup("apicpmtimer", setup_apicpmtimer
);
115 /* x2apic enabled before OS handover */
116 static int x2apic_preenabled
;
117 static int disable_x2apic
;
118 static __init
int setup_nox2apic(char *str
)
121 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
124 early_param("nox2apic", setup_nox2apic
);
127 unsigned long mp_lapic_addr
;
129 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
130 static int disable_apic_timer __cpuinitdata
;
131 /* Local APIC timer works in C2 */
132 int local_apic_timer_c2_ok
;
133 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
135 int first_system_vector
= 0xfe;
138 * Debug level, exported for io_apic.c
140 unsigned int apic_verbosity
;
144 /* Have we found an MP table */
145 int smp_found_config
;
147 static struct resource lapic_resource
= {
148 .name
= "Local APIC",
149 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
152 static unsigned int calibration_result
;
154 static int lapic_next_event(unsigned long delta
,
155 struct clock_event_device
*evt
);
156 static void lapic_timer_setup(enum clock_event_mode mode
,
157 struct clock_event_device
*evt
);
158 static void lapic_timer_broadcast(const struct cpumask
*mask
);
159 static void apic_pm_activate(void);
162 * The local apic timer can be used for any function which is CPU local.
164 static struct clock_event_device lapic_clockevent
= {
166 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
167 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
169 .set_mode
= lapic_timer_setup
,
170 .set_next_event
= lapic_next_event
,
171 .broadcast
= lapic_timer_broadcast
,
175 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
177 static unsigned long apic_phys
;
180 * Get the LAPIC version
182 static inline int lapic_get_version(void)
184 return GET_APIC_VERSION(apic_read(APIC_LVR
));
188 * Check, if the APIC is integrated or a separate chip
190 static inline int lapic_is_integrated(void)
195 return APIC_INTEGRATED(lapic_get_version());
200 * Check, whether this is a modern or a first generation APIC
202 static int modern_apic(void)
204 /* AMD systems use old APIC versions, so check the CPU */
205 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
206 boot_cpu_data
.x86
>= 0xf)
208 return lapic_get_version() >= 0x14;
212 * Paravirt kernels also might be using these below ops. So we still
213 * use generic apic_read()/apic_write(), which might be pointing to different
214 * ops in PARAVIRT case.
216 void xapic_wait_icr_idle(void)
218 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
222 u32
safe_xapic_wait_icr_idle(void)
229 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
233 } while (timeout
++ < 1000);
238 void xapic_icr_write(u32 low
, u32 id
)
240 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
241 apic_write(APIC_ICR
, low
);
244 static u64
xapic_icr_read(void)
248 icr2
= apic_read(APIC_ICR2
);
249 icr1
= apic_read(APIC_ICR
);
251 return icr1
| ((u64
)icr2
<< 32);
254 static struct apic_ops xapic_ops
= {
255 .read
= native_apic_mem_read
,
256 .write
= native_apic_mem_write
,
257 .icr_read
= xapic_icr_read
,
258 .icr_write
= xapic_icr_write
,
259 .wait_icr_idle
= xapic_wait_icr_idle
,
260 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
263 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
264 EXPORT_SYMBOL_GPL(apic_ops
);
267 static void x2apic_wait_icr_idle(void)
269 /* no need to wait for icr idle in x2apic */
273 static u32
safe_x2apic_wait_icr_idle(void)
275 /* no need to wait for icr idle in x2apic */
279 void x2apic_icr_write(u32 low
, u32 id
)
281 wrmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), ((__u64
) id
) << 32 | low
);
284 static u64
x2apic_icr_read(void)
288 rdmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), val
);
292 static struct apic_ops x2apic_ops
= {
293 .read
= native_apic_msr_read
,
294 .write
= native_apic_msr_write
,
295 .icr_read
= x2apic_icr_read
,
296 .icr_write
= x2apic_icr_write
,
297 .wait_icr_idle
= x2apic_wait_icr_idle
,
298 .safe_wait_icr_idle
= safe_x2apic_wait_icr_idle
,
303 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
305 void __cpuinit
enable_NMI_through_LVT0(void)
309 /* unmask and set to NMI */
312 /* Level triggered for 82489DX (32bit mode) */
313 if (!lapic_is_integrated())
314 v
|= APIC_LVT_LEVEL_TRIGGER
;
316 apic_write(APIC_LVT0
, v
);
321 * get_physical_broadcast - Get number of physical broadcast IDs
323 int get_physical_broadcast(void)
325 return modern_apic() ? 0xff : 0xf;
330 * lapic_get_maxlvt - get the maximum number of local vector table entries
332 int lapic_get_maxlvt(void)
336 v
= apic_read(APIC_LVR
);
338 * - we always have APIC integrated on 64bit mode
339 * - 82489DXs do not report # of LVT entries
341 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
349 #define APIC_DIVISOR 16
352 * This function sets up the local APIC timer, with a timeout of
353 * 'clocks' APIC bus clock. During calibration we actually call
354 * this function twice on the boot CPU, once with a bogus timeout
355 * value, second time for real. The other (noncalibrating) CPUs
356 * call this function only once, with the real, calibrated value.
358 * We do reads before writes even if unnecessary, to get around the
359 * P5 APIC double write bug.
361 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
363 unsigned int lvtt_value
, tmp_value
;
365 lvtt_value
= LOCAL_TIMER_VECTOR
;
367 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
368 if (!lapic_is_integrated())
369 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
372 lvtt_value
|= APIC_LVT_MASKED
;
374 apic_write(APIC_LVTT
, lvtt_value
);
379 tmp_value
= apic_read(APIC_TDCR
);
380 apic_write(APIC_TDCR
,
381 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
385 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
389 * Setup extended LVT, AMD specific (K8, family 10h)
391 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
392 * MCE interrupts are supported. Thus MCE offset must be set to 0.
394 * If mask=1, the LVT entry does not generate interrupts while mask=0
395 * enables the vector. See also the BKDGs.
398 #define APIC_EILVT_LVTOFF_MCE 0
399 #define APIC_EILVT_LVTOFF_IBS 1
401 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
403 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
404 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
409 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
411 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
412 return APIC_EILVT_LVTOFF_MCE
;
415 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
417 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
418 return APIC_EILVT_LVTOFF_IBS
;
420 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs
);
423 * Program the next event, relative to now
425 static int lapic_next_event(unsigned long delta
,
426 struct clock_event_device
*evt
)
428 apic_write(APIC_TMICT
, delta
);
433 * Setup the lapic timer in periodic or oneshot mode
435 static void lapic_timer_setup(enum clock_event_mode mode
,
436 struct clock_event_device
*evt
)
441 /* Lapic used as dummy for broadcast ? */
442 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
445 local_irq_save(flags
);
448 case CLOCK_EVT_MODE_PERIODIC
:
449 case CLOCK_EVT_MODE_ONESHOT
:
450 __setup_APIC_LVTT(calibration_result
,
451 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
453 case CLOCK_EVT_MODE_UNUSED
:
454 case CLOCK_EVT_MODE_SHUTDOWN
:
455 v
= apic_read(APIC_LVTT
);
456 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
457 apic_write(APIC_LVTT
, v
);
458 apic_write(APIC_TMICT
, 0xffffffff);
460 case CLOCK_EVT_MODE_RESUME
:
461 /* Nothing to do here */
465 local_irq_restore(flags
);
469 * Local APIC timer broadcast function
471 static void lapic_timer_broadcast(const struct cpumask
*mask
)
474 apic
->send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
479 * Setup the local APIC timer for this CPU. Copy the initilized values
480 * of the boot CPU and register the clock event in the framework.
482 static void __cpuinit
setup_APIC_timer(void)
484 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
486 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
487 levt
->cpumask
= cpumask_of(smp_processor_id());
489 clockevents_register_device(levt
);
493 * In this functions we calibrate APIC bus clocks to the external timer.
495 * We want to do the calibration only once since we want to have local timer
496 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
499 * This was previously done by reading the PIT/HPET and waiting for a wrap
500 * around to find out, that a tick has elapsed. I have a box, where the PIT
501 * readout is broken, so it never gets out of the wait loop again. This was
502 * also reported by others.
504 * Monitoring the jiffies value is inaccurate and the clockevents
505 * infrastructure allows us to do a simple substitution of the interrupt
508 * The calibration routine also uses the pm_timer when possible, as the PIT
509 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
510 * back to normal later in the boot process).
513 #define LAPIC_CAL_LOOPS (HZ/10)
515 static __initdata
int lapic_cal_loops
= -1;
516 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
517 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
518 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
519 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
522 * Temporary interrupt handler.
524 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
526 unsigned long long tsc
= 0;
527 long tapic
= apic_read(APIC_TMCCT
);
528 unsigned long pm
= acpi_pm_read_early();
533 switch (lapic_cal_loops
++) {
535 lapic_cal_t1
= tapic
;
536 lapic_cal_tsc1
= tsc
;
538 lapic_cal_j1
= jiffies
;
541 case LAPIC_CAL_LOOPS
:
542 lapic_cal_t2
= tapic
;
543 lapic_cal_tsc2
= tsc
;
544 if (pm
< lapic_cal_pm1
)
545 pm
+= ACPI_PM_OVRRUN
;
547 lapic_cal_j2
= jiffies
;
552 static int __init
calibrate_by_pmtimer(long deltapm
, long *delta
)
554 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/ 10;
555 const long pm_thresh
= pm_100ms
/ 100;
559 #ifndef CONFIG_X86_PM_TIMER
563 apic_printk(APIC_VERBOSE
, "... PM timer delta = %ld\n", deltapm
);
565 /* Check, if the PM timer is available */
569 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
571 if (deltapm
> (pm_100ms
- pm_thresh
) &&
572 deltapm
< (pm_100ms
+ pm_thresh
)) {
573 apic_printk(APIC_VERBOSE
, "... PM timer result ok\n");
575 res
= (((u64
)deltapm
) * mult
) >> 22;
576 do_div(res
, 1000000);
577 pr_warning("APIC calibration not consistent "
578 "with PM Timer: %ldms instead of 100ms\n",
580 /* Correct the lapic counter value */
581 res
= (((u64
)(*delta
)) * pm_100ms
);
582 do_div(res
, deltapm
);
583 pr_info("APIC delta adjusted to PM-Timer: "
584 "%lu (%ld)\n", (unsigned long)res
, *delta
);
591 static int __init
calibrate_APIC_clock(void)
593 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
594 void (*real_handler
)(struct clock_event_device
*dev
);
595 unsigned long deltaj
;
597 int pm_referenced
= 0;
601 /* Replace the global interrupt handler */
602 real_handler
= global_clock_event
->event_handler
;
603 global_clock_event
->event_handler
= lapic_cal_handler
;
606 * Setup the APIC counter to maximum. There is no way the lapic
607 * can underflow in the 100ms detection time frame
609 __setup_APIC_LVTT(0xffffffff, 0, 0);
611 /* Let the interrupts run */
614 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
619 /* Restore the real event handler */
620 global_clock_event
->event_handler
= real_handler
;
622 /* Build delta t1-t2 as apic timer counts down */
623 delta
= lapic_cal_t1
- lapic_cal_t2
;
624 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
626 /* we trust the PM based calibration if possible */
627 pm_referenced
= !calibrate_by_pmtimer(lapic_cal_pm2
- lapic_cal_pm1
,
630 /* Calculate the scaled math multiplication factor */
631 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
632 lapic_clockevent
.shift
);
633 lapic_clockevent
.max_delta_ns
=
634 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
635 lapic_clockevent
.min_delta_ns
=
636 clockevent_delta2ns(0xF, &lapic_clockevent
);
638 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
640 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
641 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
642 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
646 delta
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
647 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
649 (delta
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
650 (delta
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
653 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
655 calibration_result
/ (1000000 / HZ
),
656 calibration_result
% (1000000 / HZ
));
659 * Do a sanity check on the APIC calibration result
661 if (calibration_result
< (1000000 / HZ
)) {
663 pr_warning("APIC frequency too slow, disabling apic timer\n");
667 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
670 * PM timer calibration failed or not turned on
671 * so lets try APIC timer based calibration
673 if (!pm_referenced
) {
674 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
677 * Setup the apic timer manually
679 levt
->event_handler
= lapic_cal_handler
;
680 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
681 lapic_cal_loops
= -1;
683 /* Let the interrupts run */
686 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
689 /* Stop the lapic timer */
690 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
693 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
694 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
696 /* Check, if the jiffies result is consistent */
697 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
698 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
700 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
704 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
705 pr_warning("APIC timer disabled due to verification failure\n");
713 * Setup the boot APIC
715 * Calibrate and verify the result.
717 void __init
setup_boot_APIC_clock(void)
720 * The local apic timer can be disabled via the kernel
721 * commandline or from the CPU detection code. Register the lapic
722 * timer as a dummy clock event source on SMP systems, so the
723 * broadcast mechanism is used. On UP systems simply ignore it.
725 if (disable_apic_timer
) {
726 pr_info("Disabling APIC timer\n");
727 /* No broadcast on UP ! */
728 if (num_possible_cpus() > 1) {
729 lapic_clockevent
.mult
= 1;
735 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
736 "calibrating APIC timer ...\n");
738 if (calibrate_APIC_clock()) {
739 /* No broadcast on UP ! */
740 if (num_possible_cpus() > 1)
746 * If nmi_watchdog is set to IO_APIC, we need the
747 * PIT/HPET going. Otherwise register lapic as a dummy
750 if (nmi_watchdog
!= NMI_IO_APIC
)
751 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
753 pr_warning("APIC timer registered as dummy,"
754 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
756 /* Setup the lapic or request the broadcast */
760 void __cpuinit
setup_secondary_APIC_clock(void)
766 * The guts of the apic timer interrupt
768 static void local_apic_timer_interrupt(void)
770 int cpu
= smp_processor_id();
771 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
774 * Normally we should not be here till LAPIC has been initialized but
775 * in some cases like kdump, its possible that there is a pending LAPIC
776 * timer interrupt from previous kernel's context and is delivered in
777 * new kernel the moment interrupts are enabled.
779 * Interrupts are enabled early and LAPIC is setup much later, hence
780 * its possible that when we get here evt->event_handler is NULL.
781 * Check for event_handler being NULL and discard the interrupt as
784 if (!evt
->event_handler
) {
785 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
787 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
792 * the NMI deadlock-detector uses this.
794 inc_irq_stat(apic_timer_irqs
);
796 evt
->event_handler(evt
);
800 * Local APIC timer interrupt. This is the most natural way for doing
801 * local interrupts, but local timer interrupts can be emulated by
802 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
804 * [ if a single-CPU system runs an SMP kernel then we call the local
805 * interrupt as well. Thus we cannot inline the local irq ... ]
807 void __irq_entry
smp_apic_timer_interrupt(struct pt_regs
*regs
)
809 struct pt_regs
*old_regs
= set_irq_regs(regs
);
812 * NOTE! We'd better ACK the irq immediately,
813 * because timer handling can be slow.
817 * update_process_times() expects us to have done irq_enter().
818 * Besides, if we don't timer interrupts ignore the global
819 * interrupt lock, which is the WrongThing (tm) to do.
823 local_apic_timer_interrupt();
826 set_irq_regs(old_regs
);
829 int setup_profiling_timer(unsigned int multiplier
)
835 * Local APIC start and shutdown
839 * clear_local_APIC - shutdown the local APIC
841 * This is called, when a CPU is disabled and before rebooting, so the state of
842 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
843 * leftovers during boot.
845 void clear_local_APIC(void)
850 /* APIC hasn't been mapped yet */
854 maxlvt
= lapic_get_maxlvt();
856 * Masking an LVT entry can trigger a local APIC error
857 * if the vector is zero. Mask LVTERR first to prevent this.
860 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
861 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
864 * Careful: we have to set masks only first to deassert
865 * any level-triggered sources.
867 v
= apic_read(APIC_LVTT
);
868 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
869 v
= apic_read(APIC_LVT0
);
870 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
871 v
= apic_read(APIC_LVT1
);
872 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
874 v
= apic_read(APIC_LVTPC
);
875 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
878 /* lets not touch this if we didn't frob it */
879 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
881 v
= apic_read(APIC_LVTTHMR
);
882 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
886 * Clean APIC state for other OSs:
888 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
889 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
890 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
892 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
894 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
896 /* Integrated APIC (!82489DX) ? */
897 if (lapic_is_integrated()) {
899 /* Clear ESR due to Pentium errata 3AP and 11AP */
900 apic_write(APIC_ESR
, 0);
906 * disable_local_APIC - clear and disable the local APIC
908 void disable_local_APIC(void)
912 /* APIC hasn't been mapped yet */
919 * Disable APIC (implies clearing of registers
922 value
= apic_read(APIC_SPIV
);
923 value
&= ~APIC_SPIV_APIC_ENABLED
;
924 apic_write(APIC_SPIV
, value
);
928 * When LAPIC was disabled by the BIOS and enabled by the kernel,
929 * restore the disabled state.
931 if (enabled_via_apicbase
) {
934 rdmsr(MSR_IA32_APICBASE
, l
, h
);
935 l
&= ~MSR_IA32_APICBASE_ENABLE
;
936 wrmsr(MSR_IA32_APICBASE
, l
, h
);
942 * If Linux enabled the LAPIC against the BIOS default disable it down before
943 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
944 * not power-off. Additionally clear all LVT entries before disable_local_APIC
945 * for the case where Linux didn't enable the LAPIC.
947 void lapic_shutdown(void)
954 local_irq_save(flags
);
957 if (!enabled_via_apicbase
)
961 disable_local_APIC();
964 local_irq_restore(flags
);
968 * This is to verify that we're looking at a real local APIC.
969 * Check these against your board if the CPUs aren't getting
970 * started for no apparent reason.
972 int __init
verify_local_APIC(void)
974 unsigned int reg0
, reg1
;
977 * The version register is read-only in a real APIC.
979 reg0
= apic_read(APIC_LVR
);
980 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
981 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
982 reg1
= apic_read(APIC_LVR
);
983 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
986 * The two version reads above should print the same
987 * numbers. If the second one is different, then we
988 * poke at a non-APIC.
994 * Check if the version looks reasonably.
996 reg1
= GET_APIC_VERSION(reg0
);
997 if (reg1
== 0x00 || reg1
== 0xff)
999 reg1
= lapic_get_maxlvt();
1000 if (reg1
< 0x02 || reg1
== 0xff)
1004 * The ID register is read/write in a real APIC.
1006 reg0
= apic_read(APIC_ID
);
1007 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
1008 apic_write(APIC_ID
, reg0
^ apic
->apic_id_mask
);
1009 reg1
= apic_read(APIC_ID
);
1010 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
1011 apic_write(APIC_ID
, reg0
);
1012 if (reg1
!= (reg0
^ apic
->apic_id_mask
))
1016 * The next two are just to see if we have sane values.
1017 * They're only really relevant if we're in Virtual Wire
1018 * compatibility mode, but most boxes are anymore.
1020 reg0
= apic_read(APIC_LVT0
);
1021 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
1022 reg1
= apic_read(APIC_LVT1
);
1023 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
1029 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1031 void __init
sync_Arb_IDs(void)
1034 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1037 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1043 apic_wait_icr_idle();
1045 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1046 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1047 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1051 * An initial setup of the virtual wire mode.
1053 void __init
init_bsp_APIC(void)
1058 * Don't do the setup now if we have a SMP BIOS as the
1059 * through-I/O-APIC virtual wire mode might be active.
1061 if (smp_found_config
|| !cpu_has_apic
)
1065 * Do not trust the local APIC being empty at bootup.
1072 value
= apic_read(APIC_SPIV
);
1073 value
&= ~APIC_VECTOR_MASK
;
1074 value
|= APIC_SPIV_APIC_ENABLED
;
1076 #ifdef CONFIG_X86_32
1077 /* This bit is reserved on P4/Xeon and should be cleared */
1078 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1079 (boot_cpu_data
.x86
== 15))
1080 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1083 value
|= APIC_SPIV_FOCUS_DISABLED
;
1084 value
|= SPURIOUS_APIC_VECTOR
;
1085 apic_write(APIC_SPIV
, value
);
1088 * Set up the virtual wire mode.
1090 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1091 value
= APIC_DM_NMI
;
1092 if (!lapic_is_integrated()) /* 82489DX */
1093 value
|= APIC_LVT_LEVEL_TRIGGER
;
1094 apic_write(APIC_LVT1
, value
);
1097 static void __cpuinit
lapic_setup_esr(void)
1099 unsigned int oldvalue
, value
, maxlvt
;
1101 if (!lapic_is_integrated()) {
1102 pr_info("No ESR for 82489DX.\n");
1106 if (apic
->disable_esr
) {
1108 * Something untraceable is creating bad interrupts on
1109 * secondary quads ... for the moment, just leave the
1110 * ESR disabled - we can't do anything useful with the
1111 * errors anyway - mbligh
1113 pr_info("Leaving ESR disabled.\n");
1117 maxlvt
= lapic_get_maxlvt();
1118 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1119 apic_write(APIC_ESR
, 0);
1120 oldvalue
= apic_read(APIC_ESR
);
1122 /* enables sending errors */
1123 value
= ERROR_APIC_VECTOR
;
1124 apic_write(APIC_LVTERR
, value
);
1127 * spec says clear errors after enabling vector.
1130 apic_write(APIC_ESR
, 0);
1131 value
= apic_read(APIC_ESR
);
1132 if (value
!= oldvalue
)
1133 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1134 "vector: 0x%08x after: 0x%08x\n",
1140 * setup_local_APIC - setup the local APIC
1142 void __cpuinit
setup_local_APIC(void)
1148 #ifdef CONFIG_X86_IO_APIC
1149 disable_ioapic_setup();
1154 #ifdef CONFIG_X86_32
1155 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1156 if (lapic_is_integrated() && apic
->disable_esr
) {
1157 apic_write(APIC_ESR
, 0);
1158 apic_write(APIC_ESR
, 0);
1159 apic_write(APIC_ESR
, 0);
1160 apic_write(APIC_ESR
, 0);
1167 * Double-check whether this APIC is really registered.
1168 * This is meaningless in clustered apic mode, so we skip it.
1170 if (!apic
->apic_id_registered())
1174 * Intel recommends to set DFR, LDR and TPR before enabling
1175 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1176 * document number 292116). So here it goes...
1178 apic
->init_apic_ldr();
1181 * Set Task Priority to 'accept all'. We never change this
1184 value
= apic_read(APIC_TASKPRI
);
1185 value
&= ~APIC_TPRI_MASK
;
1186 apic_write(APIC_TASKPRI
, value
);
1189 * After a crash, we no longer service the interrupts and a pending
1190 * interrupt from previous kernel might still have ISR bit set.
1192 * Most probably by now CPU has serviced that pending interrupt and
1193 * it might not have done the ack_APIC_irq() because it thought,
1194 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1195 * does not clear the ISR bit and cpu thinks it has already serivced
1196 * the interrupt. Hence a vector might get locked. It was noticed
1197 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1199 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1200 value
= apic_read(APIC_ISR
+ i
*0x10);
1201 for (j
= 31; j
>= 0; j
--) {
1208 * Now that we are all set up, enable the APIC
1210 value
= apic_read(APIC_SPIV
);
1211 value
&= ~APIC_VECTOR_MASK
;
1215 value
|= APIC_SPIV_APIC_ENABLED
;
1217 #ifdef CONFIG_X86_32
1219 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1220 * certain networking cards. If high frequency interrupts are
1221 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1222 * entry is masked/unmasked at a high rate as well then sooner or
1223 * later IOAPIC line gets 'stuck', no more interrupts are received
1224 * from the device. If focus CPU is disabled then the hang goes
1227 * [ This bug can be reproduced easily with a level-triggered
1228 * PCI Ne2000 networking cards and PII/PIII processors, dual
1232 * Actually disabling the focus CPU check just makes the hang less
1233 * frequent as it makes the interrupt distributon model be more
1234 * like LRU than MRU (the short-term load is more even across CPUs).
1235 * See also the comment in end_level_ioapic_irq(). --macro
1239 * - enable focus processor (bit==0)
1240 * - 64bit mode always use processor focus
1241 * so no need to set it
1243 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1247 * Set spurious IRQ vector
1249 value
|= SPURIOUS_APIC_VECTOR
;
1250 apic_write(APIC_SPIV
, value
);
1253 * Set up LVT0, LVT1:
1255 * set up through-local-APIC on the BP's LINT0. This is not
1256 * strictly necessary in pure symmetric-IO mode, but sometimes
1257 * we delegate interrupts to the 8259A.
1260 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1262 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1263 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1264 value
= APIC_DM_EXTINT
;
1265 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1266 smp_processor_id());
1268 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1269 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1270 smp_processor_id());
1272 apic_write(APIC_LVT0
, value
);
1275 * only the BP should see the LINT1 NMI signal, obviously.
1277 if (!smp_processor_id())
1278 value
= APIC_DM_NMI
;
1280 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1281 if (!lapic_is_integrated()) /* 82489DX */
1282 value
|= APIC_LVT_LEVEL_TRIGGER
;
1283 apic_write(APIC_LVT1
, value
);
1288 void __cpuinit
end_local_APIC_setup(void)
1292 #ifdef CONFIG_X86_32
1295 /* Disable the local apic timer */
1296 value
= apic_read(APIC_LVTT
);
1297 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1298 apic_write(APIC_LVTT
, value
);
1302 setup_apic_nmi_watchdog(NULL
);
1307 void check_x2apic(void)
1311 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1313 if (msr
& X2APIC_ENABLE
) {
1314 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1315 x2apic_preenabled
= x2apic
= 1;
1316 apic_ops
= &x2apic_ops
;
1320 void enable_x2apic(void)
1324 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1325 if (!(msr
& X2APIC_ENABLE
)) {
1326 pr_info("Enabling x2apic\n");
1327 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1331 void __init
enable_IR_x2apic(void)
1333 #ifdef CONFIG_INTR_REMAP
1335 unsigned long flags
;
1337 if (!cpu_has_x2apic
)
1340 if (!x2apic_preenabled
&& disable_x2apic
) {
1341 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1342 "because of nox2apic\n");
1346 if (x2apic_preenabled
&& disable_x2apic
)
1347 panic("Bios already enabled x2apic, can't enforce nox2apic");
1349 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1350 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1351 "because of skipping io-apic setup\n");
1355 ret
= dmar_table_init();
1357 pr_info("dmar_table_init() failed with %d:\n", ret
);
1359 if (x2apic_preenabled
)
1360 panic("x2apic enabled by bios. But IR enabling failed");
1362 pr_info("Not enabling x2apic,Intr-remapping\n");
1366 local_irq_save(flags
);
1369 ret
= save_mask_IO_APIC_setup();
1371 pr_info("Saving IO-APIC state failed: %d\n", ret
);
1375 ret
= enable_intr_remapping(1);
1377 if (ret
&& x2apic_preenabled
) {
1378 local_irq_restore(flags
);
1379 panic("x2apic enabled by bios. But IR enabling failed");
1387 apic_ops
= &x2apic_ops
;
1394 * IR enabling failed
1396 restore_IO_APIC_setup();
1398 reinit_intr_remapped_IO_APIC(x2apic_preenabled
);
1402 local_irq_restore(flags
);
1405 if (!x2apic_preenabled
)
1406 pr_info("Enabled x2apic and interrupt-remapping\n");
1408 pr_info("Enabled Interrupt-remapping\n");
1410 pr_err("Failed to enable Interrupt-remapping and x2apic\n");
1412 if (!cpu_has_x2apic
)
1415 if (x2apic_preenabled
)
1416 panic("x2apic enabled prior OS handover,"
1417 " enable CONFIG_INTR_REMAP");
1419 pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1425 #endif /* HAVE_X2APIC */
1427 #ifdef CONFIG_X86_64
1429 * Detect and enable local APICs on non-SMP boards.
1430 * Original code written by Keir Fraser.
1431 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1432 * not correctly set up (usually the APIC timer won't work etc.)
1434 static int __init
detect_init_APIC(void)
1436 if (!cpu_has_apic
) {
1437 pr_info("No local APIC present\n");
1441 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1442 boot_cpu_physical_apicid
= 0;
1447 * Detect and initialize APIC
1449 static int __init
detect_init_APIC(void)
1453 /* Disabled by kernel option? */
1457 switch (boot_cpu_data
.x86_vendor
) {
1458 case X86_VENDOR_AMD
:
1459 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1460 (boot_cpu_data
.x86
== 15))
1463 case X86_VENDOR_INTEL
:
1464 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1465 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1472 if (!cpu_has_apic
) {
1474 * Over-ride BIOS and try to enable the local APIC only if
1475 * "lapic" specified.
1477 if (!force_enable_local_apic
) {
1478 pr_info("Local APIC disabled by BIOS -- "
1479 "you can enable it with \"lapic\"\n");
1483 * Some BIOSes disable the local APIC in the APIC_BASE
1484 * MSR. This can only be done in software for Intel P6 or later
1485 * and AMD K7 (Model > 1) or later.
1487 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1488 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1489 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1490 l
&= ~MSR_IA32_APICBASE_BASE
;
1491 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1492 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1493 enabled_via_apicbase
= 1;
1497 * The APIC feature bit should now be enabled
1500 features
= cpuid_edx(1);
1501 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1502 pr_warning("Could not enable APIC!\n");
1505 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1506 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1508 /* The BIOS may have set up the APIC at some other address */
1509 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1510 if (l
& MSR_IA32_APICBASE_ENABLE
)
1511 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1513 pr_info("Found and enabled local APIC!\n");
1520 pr_info("No local APIC present or hardware disabled\n");
1525 #ifdef CONFIG_X86_64
1526 void __init
early_init_lapic_mapping(void)
1528 unsigned long phys_addr
;
1531 * If no local APIC can be found then go out
1532 * : it means there is no mpatable and MADT
1534 if (!smp_found_config
)
1537 phys_addr
= mp_lapic_addr
;
1539 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1540 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1541 APIC_BASE
, phys_addr
);
1544 * Fetch the APIC ID of the BSP in case we have a
1545 * default configuration (or the MP table is broken).
1547 boot_cpu_physical_apicid
= read_apic_id();
1552 * init_apic_mappings - initialize APIC mappings
1554 void __init
init_apic_mappings(void)
1558 boot_cpu_physical_apicid
= read_apic_id();
1564 * If no local APIC can be found then set up a fake all
1565 * zeroes page to simulate the local APIC and another
1566 * one for the IO-APIC.
1568 if (!smp_found_config
&& detect_init_APIC()) {
1569 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1570 apic_phys
= __pa(apic_phys
);
1572 apic_phys
= mp_lapic_addr
;
1574 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1575 apic_printk(APIC_VERBOSE
, "mapped APIC to %08lx (%08lx)\n",
1576 APIC_BASE
, apic_phys
);
1579 * Fetch the APIC ID of the BSP in case we have a
1580 * default configuration (or the MP table is broken).
1582 if (boot_cpu_physical_apicid
== -1U)
1583 boot_cpu_physical_apicid
= read_apic_id();
1587 * This initializes the IO-APIC and APIC hardware if this is
1590 int apic_version
[MAX_APICS
];
1592 int __init
APIC_init_uniprocessor(void)
1595 pr_info("Apic disabled\n");
1598 #ifdef CONFIG_X86_64
1599 if (!cpu_has_apic
) {
1601 pr_info("Apic disabled by BIOS\n");
1605 if (!smp_found_config
&& !cpu_has_apic
)
1609 * Complain if the BIOS pretends there is one.
1611 if (!cpu_has_apic
&&
1612 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1613 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1614 boot_cpu_physical_apicid
);
1615 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1623 #ifdef CONFIG_X86_64
1624 default_setup_apic_routing();
1627 verify_local_APIC();
1630 #ifdef CONFIG_X86_64
1631 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1634 * Hack: In case of kdump, after a crash, kernel might be booting
1635 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1636 * might be zero if read from MP tables. Get it from LAPIC.
1638 # ifdef CONFIG_CRASH_DUMP
1639 boot_cpu_physical_apicid
= read_apic_id();
1642 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1645 #ifdef CONFIG_X86_64
1647 * Now enable IO-APICs, actually call clear_IO_APIC
1648 * We need clear_IO_APIC before enabling vector on BP
1650 if (!skip_ioapic_setup
&& nr_ioapics
)
1654 #ifdef CONFIG_X86_IO_APIC
1655 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1657 localise_nmi_watchdog();
1658 end_local_APIC_setup();
1660 #ifdef CONFIG_X86_IO_APIC
1661 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1663 # ifdef CONFIG_X86_64
1669 #ifdef CONFIG_X86_64
1670 setup_boot_APIC_clock();
1671 check_nmi_watchdog();
1680 * Local APIC interrupts
1684 * This interrupt should _never_ happen with our APIC/SMP architecture
1686 void smp_spurious_interrupt(struct pt_regs
*regs
)
1693 * Check if this really is a spurious interrupt and ACK it
1694 * if it is a vectored one. Just in case...
1695 * Spurious interrupts should not be ACKed.
1697 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1698 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1701 inc_irq_stat(irq_spurious_count
);
1703 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1704 pr_info("spurious APIC interrupt on CPU#%d, "
1705 "should never happen.\n", smp_processor_id());
1710 * This interrupt should never happen with our APIC/SMP architecture
1712 void smp_error_interrupt(struct pt_regs
*regs
)
1718 /* First tickle the hardware, only then report what went on. -- REW */
1719 v
= apic_read(APIC_ESR
);
1720 apic_write(APIC_ESR
, 0);
1721 v1
= apic_read(APIC_ESR
);
1723 atomic_inc(&irq_err_count
);
1726 * Here is what the APIC error bits mean:
1728 * 1: Receive CS error
1729 * 2: Send accept error
1730 * 3: Receive accept error
1732 * 5: Send illegal vector
1733 * 6: Received illegal vector
1734 * 7: Illegal register address
1736 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1737 smp_processor_id(), v
, v1
);
1742 * connect_bsp_APIC - attach the APIC to the interrupt system
1744 void __init
connect_bsp_APIC(void)
1746 #ifdef CONFIG_X86_32
1749 * Do not trust the local APIC being empty at bootup.
1753 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1754 * local APIC to INT and NMI lines.
1756 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1757 "enabling APIC mode.\n");
1762 if (apic
->enable_apic_mode
)
1763 apic
->enable_apic_mode();
1767 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1768 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1770 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1773 void disconnect_bsp_APIC(int virt_wire_setup
)
1777 #ifdef CONFIG_X86_32
1780 * Put the board back into PIC mode (has an effect only on
1781 * certain older boards). Note that APIC interrupts, including
1782 * IPIs, won't work beyond this point! The only exception are
1785 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1786 "entering PIC mode.\n");
1793 /* Go back to Virtual Wire compatibility mode */
1795 /* For the spurious interrupt use vector F, and enable it */
1796 value
= apic_read(APIC_SPIV
);
1797 value
&= ~APIC_VECTOR_MASK
;
1798 value
|= APIC_SPIV_APIC_ENABLED
;
1800 apic_write(APIC_SPIV
, value
);
1802 if (!virt_wire_setup
) {
1804 * For LVT0 make it edge triggered, active high,
1805 * external and enabled
1807 value
= apic_read(APIC_LVT0
);
1808 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1809 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1810 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1811 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1812 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1813 apic_write(APIC_LVT0
, value
);
1816 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1820 * For LVT1 make it edge triggered, active high,
1823 value
= apic_read(APIC_LVT1
);
1824 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1825 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1826 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1827 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1828 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1829 apic_write(APIC_LVT1
, value
);
1832 void __cpuinit
generic_processor_info(int apicid
, int version
)
1839 if (version
== 0x0) {
1840 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1841 "fixing up to 0x10. (tell your hw vendor)\n",
1845 apic_version
[apicid
] = version
;
1847 if (num_processors
>= nr_cpu_ids
) {
1848 int max
= nr_cpu_ids
;
1849 int thiscpu
= max
+ disabled_cpus
;
1852 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1853 " Processor %d/0x%x ignored.\n", max
, thiscpu
, apicid
);
1860 cpu
= cpumask_next_zero(-1, cpu_present_mask
);
1862 if (version
!= apic_version
[boot_cpu_physical_apicid
])
1864 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1865 apic_version
[boot_cpu_physical_apicid
], cpu
, version
);
1867 physid_set(apicid
, phys_cpu_present_map
);
1868 if (apicid
== boot_cpu_physical_apicid
) {
1870 * x86_bios_cpu_apicid is required to have processors listed
1871 * in same order as logical cpu numbers. Hence the first
1872 * entry is BSP, and so on.
1876 if (apicid
> max_physical_apicid
)
1877 max_physical_apicid
= apicid
;
1879 #ifdef CONFIG_X86_32
1881 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1882 * but we need to work other dependencies like SMP_SUSPEND etc
1883 * before this can be done without some confusion.
1884 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1885 * - Ashok Raj <ashok.raj@intel.com>
1887 if (max_physical_apicid
>= 8) {
1888 switch (boot_cpu_data
.x86_vendor
) {
1889 case X86_VENDOR_INTEL
:
1890 if (!APIC_XAPIC(version
)) {
1894 /* If P4 and above fall through */
1895 case X86_VENDOR_AMD
:
1901 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
1902 early_per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1903 early_per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1906 set_cpu_possible(cpu
, true);
1907 set_cpu_present(cpu
, true);
1910 int hard_smp_processor_id(void)
1912 return read_apic_id();
1915 void default_init_apic_ldr(void)
1919 apic_write(APIC_DFR
, APIC_DFR_VALUE
);
1920 val
= apic_read(APIC_LDR
) & ~APIC_LDR_MASK
;
1921 val
|= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
1922 apic_write(APIC_LDR
, val
);
1925 #ifdef CONFIG_X86_32
1926 int default_apicid_to_node(int logical_apicid
)
1929 return apicid_2_node
[hard_smp_processor_id()];
1943 * 'active' is true if the local APIC was enabled by us and
1944 * not the BIOS; this signifies that we are also responsible
1945 * for disabling it before entering apm/acpi suspend
1948 /* r/w apic fields */
1949 unsigned int apic_id
;
1950 unsigned int apic_taskpri
;
1951 unsigned int apic_ldr
;
1952 unsigned int apic_dfr
;
1953 unsigned int apic_spiv
;
1954 unsigned int apic_lvtt
;
1955 unsigned int apic_lvtpc
;
1956 unsigned int apic_lvt0
;
1957 unsigned int apic_lvt1
;
1958 unsigned int apic_lvterr
;
1959 unsigned int apic_tmict
;
1960 unsigned int apic_tdcr
;
1961 unsigned int apic_thmr
;
1964 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1966 unsigned long flags
;
1969 if (!apic_pm_state
.active
)
1972 maxlvt
= lapic_get_maxlvt();
1974 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1975 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1976 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1977 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1978 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1979 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1981 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1982 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1983 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1984 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1985 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1986 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1987 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1989 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1992 local_irq_save(flags
);
1993 disable_local_APIC();
1994 local_irq_restore(flags
);
1998 static int lapic_resume(struct sys_device
*dev
)
2001 unsigned long flags
;
2004 if (!apic_pm_state
.active
)
2007 maxlvt
= lapic_get_maxlvt();
2009 local_irq_save(flags
);
2018 * Make sure the APICBASE points to the right address
2020 * FIXME! This will be wrong if we ever support suspend on
2021 * SMP! We'll need to do this as part of the CPU restore!
2023 rdmsr(MSR_IA32_APICBASE
, l
, h
);
2024 l
&= ~MSR_IA32_APICBASE_BASE
;
2025 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
2026 wrmsr(MSR_IA32_APICBASE
, l
, h
);
2029 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
2030 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
2031 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
2032 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
2033 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
2034 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
2035 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
2036 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
2037 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2039 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
2042 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
2043 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
2044 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
2045 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
2046 apic_write(APIC_ESR
, 0);
2047 apic_read(APIC_ESR
);
2048 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
2049 apic_write(APIC_ESR
, 0);
2050 apic_read(APIC_ESR
);
2052 local_irq_restore(flags
);
2058 * This device has no shutdown method - fully functioning local APICs
2059 * are needed on every CPU up until machine_halt/restart/poweroff.
2062 static struct sysdev_class lapic_sysclass
= {
2064 .resume
= lapic_resume
,
2065 .suspend
= lapic_suspend
,
2068 static struct sys_device device_lapic
= {
2070 .cls
= &lapic_sysclass
,
2073 static void __cpuinit
apic_pm_activate(void)
2075 apic_pm_state
.active
= 1;
2078 static int __init
init_lapic_sysfs(void)
2084 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2086 error
= sysdev_class_register(&lapic_sysclass
);
2088 error
= sysdev_register(&device_lapic
);
2091 device_initcall(init_lapic_sysfs
);
2093 #else /* CONFIG_PM */
2095 static void apic_pm_activate(void) { }
2097 #endif /* CONFIG_PM */
2099 #ifdef CONFIG_X86_64
2101 * apic_is_clustered_box() -- Check if we can expect good TSC
2103 * Thus far, the major user of this is IBM's Summit2 series:
2105 * Clustered boxes may have unsynced TSC problems if they are
2106 * multi-chassis. Use available data to take a good guess.
2107 * If in doubt, go HPET.
2109 __cpuinit
int apic_is_clustered_box(void)
2111 int i
, clusters
, zeros
;
2113 u16
*bios_cpu_apicid
;
2114 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
2117 * there is not this kind of box with AMD CPU yet.
2118 * Some AMD box with quadcore cpu and 8 sockets apicid
2119 * will be [4, 0x23] or [8, 0x27] could be thought to
2120 * vsmp box still need checking...
2122 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
2125 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
2126 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
2128 for (i
= 0; i
< nr_cpu_ids
; i
++) {
2129 /* are we being called early in kernel startup? */
2130 if (bios_cpu_apicid
) {
2131 id
= bios_cpu_apicid
[i
];
2132 } else if (i
< nr_cpu_ids
) {
2134 id
= per_cpu(x86_bios_cpu_apicid
, i
);
2140 if (id
!= BAD_APICID
)
2141 __set_bit(APIC_CLUSTERID(id
), clustermap
);
2144 /* Problem: Partially populated chassis may not have CPUs in some of
2145 * the APIC clusters they have been allocated. Only present CPUs have
2146 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2147 * Since clusters are allocated sequentially, count zeros only if
2148 * they are bounded by ones.
2152 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
2153 if (test_bit(i
, clustermap
)) {
2154 clusters
+= 1 + zeros
;
2160 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2161 * not guaranteed to be synced between boards
2163 if (is_vsmp_box() && clusters
> 1)
2167 * If clusters > 2, then should be multi-chassis.
2168 * May have to revisit this when multi-core + hyperthreaded CPUs come
2169 * out, but AFAIK this will work even for them.
2171 return (clusters
> 2);
2176 * APIC command line parameters
2178 static int __init
setup_disableapic(char *arg
)
2181 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2184 early_param("disableapic", setup_disableapic
);
2186 /* same as disableapic, for compatibility */
2187 static int __init
setup_nolapic(char *arg
)
2189 return setup_disableapic(arg
);
2191 early_param("nolapic", setup_nolapic
);
2193 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2195 local_apic_timer_c2_ok
= 1;
2198 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2200 static int __init
parse_disable_apic_timer(char *arg
)
2202 disable_apic_timer
= 1;
2205 early_param("noapictimer", parse_disable_apic_timer
);
2207 static int __init
parse_nolapic_timer(char *arg
)
2209 disable_apic_timer
= 1;
2212 early_param("nolapic_timer", parse_nolapic_timer
);
2214 static int __init
apic_set_verbosity(char *arg
)
2217 #ifdef CONFIG_X86_64
2218 skip_ioapic_setup
= 0;
2224 if (strcmp("debug", arg
) == 0)
2225 apic_verbosity
= APIC_DEBUG
;
2226 else if (strcmp("verbose", arg
) == 0)
2227 apic_verbosity
= APIC_VERBOSE
;
2229 pr_warning("APIC Verbosity level %s not recognised"
2230 " use apic=verbose or apic=debug\n", arg
);
2236 early_param("apic", apic_set_verbosity
);
2238 static int __init
lapic_insert_resource(void)
2243 /* Put local APIC into the resource map. */
2244 lapic_resource
.start
= apic_phys
;
2245 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2246 insert_resource(&iomem_resource
, &lapic_resource
);
2252 * need call insert after e820_reserve_resources()
2253 * that is using request_resource
2255 late_initcall(lapic_insert_resource
);