arch/x86/include/asm/summit/apic.h

   1 #ifndef __ASM_SUMMIT_APIC_H
   2 #define __ASM_SUMMIT_APIC_H
   3
   4 #include <asm/smp.h>
   5 #include <linux/gfp.h>
   6
   7 #define NO_BALANCE_IRQ (0)
   8
   9 /* In clustered mode, the high nibble of APIC ID is a cluster number.
  10  * The low nibble is a 4-bit bitmap. */
  11 #define XAPIC_DEST_CPUS_SHIFT   4
  12 #define XAPIC_DEST_CPUS_MASK    ((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
  13 #define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
  14
  15 #define APIC_DFR_VALUE  (APIC_DFR_CLUSTER)
  16
  17 static inline const cpumask_t *summit_target_cpus(void)
  18 {
  19         /* CPU_MASK_ALL (0xff) has undefined behaviour with
  20          * dest_LowestPrio mode logical clustered apic interrupt routing
  21          * Just start on cpu 0.  IRQ balancing will spread load
  22          */
  23         return &cpumask_of_cpu(0);
  24 }
  25
  26 static inline unsigned long
  27 summit_check_apicid_used(physid_mask_t bitmap, int apicid)
  28 {
  29         return 0;
  30 }
  31
  32 /* we don't use the phys_cpu_present_map to indicate apicid presence */
  33 static inline unsigned long summit_check_apicid_present(int bit)
  34 {
  35         return 1;
  36 }
  37
  38 #define apicid_cluster(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK)
  39
  40 extern u8 cpu_2_logical_apicid[];
  41
  42 static inline void init_apic_ldr(void)
  43 {
  44         unsigned long val, id;
  45         int count = 0;
  46         u8 my_id = (u8)hard_smp_processor_id();
  47         u8 my_cluster = (u8)apicid_cluster(my_id);
  48 #ifdef CONFIG_SMP
  49         u8 lid;
  50         int i;
  51
  52         /* Create logical APIC IDs by counting CPUs already in cluster. */
  53         for (count = 0, i = nr_cpu_ids; --i >= 0; ) {
  54                 lid = cpu_2_logical_apicid[i];
  55                 if (lid != BAD_APICID && apicid_cluster(lid) == my_cluster)
  56                         ++count;
  57         }
  58 #endif
  59         /* We only have a 4 wide bitmap in cluster mode.  If a deranged
  60          * BIOS puts 5 CPUs in one APIC cluster, we're hosed. */
  61         BUG_ON(count >= XAPIC_DEST_CPUS_SHIFT);
  62         id = my_cluster | (1UL << count);
  63         apic_write(APIC_DFR, APIC_DFR_VALUE);
  64         val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
  65         val |= SET_APIC_LOGICAL_ID(id);
  66         apic_write(APIC_LDR, val);
  67 }
  68
  69 static inline int multi_timer_check(int apic, int irq)
  70 {
  71         return 0;
  72 }
  73
  74 static inline int summit_apic_id_registered(void)
  75 {
  76         return 1;
  77 }
  78
  79 static inline void setup_apic_routing(void)
  80 {
  81         printk("Enabling APIC mode:  Summit.  Using %d I/O APICs\n",
  82                                                 nr_ioapics);
  83 }
  84
  85 static inline int apicid_to_node(int logical_apicid)
  86 {
  87 #ifdef CONFIG_SMP
  88         return apicid_2_node[hard_smp_processor_id()];
  89 #else
  90         return 0;
  91 #endif
  92 }
  93
  94 /* Mapping from cpu number to logical apicid */
  95 static inline int cpu_to_logical_apicid(int cpu)
  96 {
  97 #ifdef CONFIG_SMP
  98         if (cpu >= nr_cpu_ids)
  99                 return BAD_APICID;
 100         return (int)cpu_2_logical_apicid[cpu];
 101 #else
 102         return logical_smp_processor_id();
 103 #endif
 104 }
 105
 106 static inline int cpu_present_to_apicid(int mps_cpu)
 107 {
 108         if (mps_cpu < nr_cpu_ids)
 109                 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
 110         else
 111                 return BAD_APICID;
 112 }
 113
 114 static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_id_map)
 115 {
 116         /* For clustered we don't have a good way to do this yet - hack */
 117         return physids_promote(0x0F);
 118 }
 119
 120 static inline physid_mask_t apicid_to_cpu_present(int apicid)
 121 {
 122         return physid_mask_of_physid(0);
 123 }
 124
 125 static inline void setup_portio_remap(void)
 126 {
 127 }
 128
 129 static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
 130 {
 131         return 1;
 132 }
 133
 134 static inline void enable_apic_mode(void)
 135 {
 136 }
 137
 138 static inline unsigned int cpu_mask_to_apicid(const cpumask_t *cpumask)
 139 {
 140         int num_bits_set;
 141         int cpus_found = 0;
 142         int cpu;
 143         int apicid;
 144
 145         num_bits_set = cpus_weight(*cpumask);
 146         /* Return id to all */
 147         if (num_bits_set >= nr_cpu_ids)
 148                 return (int) 0xFF;
 149         /*
 150          * The cpus in the mask must all be on the apic cluster.  If are not
 151          * on the same apicid cluster return default value of target_cpus():
 152          */
 153         cpu = first_cpu(*cpumask);
 154         apicid = cpu_to_logical_apicid(cpu);
 155         while (cpus_found < num_bits_set) {
 156                 if (cpu_isset(cpu, *cpumask)) {
 157                         int new_apicid = cpu_to_logical_apicid(cpu);
 158                         if (apicid_cluster(apicid) !=
 159                                         apicid_cluster(new_apicid)){
 160                                 printk ("%s: Not a valid mask!\n", __func__);
 161                                 return 0xFF;
 162                         }
 163                         apicid = apicid | new_apicid;
 164                         cpus_found++;
 165                 }
 166                 cpu++;
 167         }
 168         return apicid;
 169 }
 170
 171 static inline unsigned int cpu_mask_to_apicid_and(const struct cpumask *inmask,
 172                                                   const struct cpumask *andmask)
 173 {
 174         int apicid = cpu_to_logical_apicid(0);
 175         cpumask_var_t cpumask;
 176
 177         if (!alloc_cpumask_var(&cpumask, GFP_ATOMIC))
 178                 return apicid;
 179
 180         cpumask_and(cpumask, inmask, andmask);
 181         cpumask_and(cpumask, cpumask, cpu_online_mask);
 182         apicid = cpu_mask_to_apicid(cpumask);
 183
 184         free_cpumask_var(cpumask);
 185         return apicid;
 186 }
 187
 188 /* cpuid returns the value latched in the HW at reset, not the APIC ID
 189  * register's value.  For any box whose BIOS changes APIC IDs, like
 190  * clustered APIC systems, we must use hard_smp_processor_id.
 191  *
 192  * See Intel's IA-32 SW Dev's Manual Vol2 under CPUID.
 193  */
 194 static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
 195 {
 196         return hard_smp_processor_id() >> index_msb;
 197 }
 198
 199 #endif /* __ASM_SUMMIT_APIC_H */