arch/x86/include/asm/mach-default/mach_apic.h

   1 #ifndef _ASM_X86_MACH_DEFAULT_MACH_APIC_H
   2 #define _ASM_X86_MACH_DEFAULT_MACH_APIC_H
   3
   4 #ifdef CONFIG_X86_LOCAL_APIC
   5
   6 #include <mach_apicdef.h>
   7 #include <asm/smp.h>
   8
   9 #define APIC_DFR_VALUE  (APIC_DFR_FLAT)
  10
  11 static inline const struct cpumask *default_target_cpus(void)
  12 {
  13 #ifdef CONFIG_SMP
  14         return cpu_online_mask;
  15 #else
  16         return cpumask_of(0);
  17 #endif
  18 }
  19
  20 #define NO_BALANCE_IRQ (0)
  21
  22 #ifdef CONFIG_X86_64
  23 #include <asm/genapic.h>
  24 #define init_apic_ldr (apic->init_apic_ldr)
  25 #define cpu_mask_to_apicid (apic->cpu_mask_to_apicid)
  26 #define cpu_mask_to_apicid_and (apic->cpu_mask_to_apicid_and)
  27 #define phys_pkg_id     (apic->phys_pkg_id)
  28 #define vector_allocation_domain    (apic->vector_allocation_domain)
  29 #define read_apic_id()  (GET_APIC_ID(apic_read(APIC_ID)))
  30 #define send_IPI_self (apic->send_IPI_self)
  31 #define wakeup_secondary_cpu (apic->wakeup_cpu)
  32 extern void setup_apic_routing(void);
  33 #else
  34 #define wakeup_secondary_cpu wakeup_secondary_cpu_via_init
  35 /*
  36  * Set up the logical destination ID.
  37  *
  38  * Intel recommends to set DFR, LDR and TPR before enabling
  39  * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
  40  * document number 292116).  So here it goes...
  41  */
  42 static inline void init_apic_ldr(void)
  43 {
  44         unsigned long val;
  45
  46         apic_write(APIC_DFR, APIC_DFR_VALUE);
  47         val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
  48         val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
  49         apic_write(APIC_LDR, val);
  50 }
  51
  52 static inline int default_apic_id_registered(void)
  53 {
  54         return physid_isset(read_apic_id(), phys_cpu_present_map);
  55 }
  56
  57 static inline unsigned int cpu_mask_to_apicid(const struct cpumask *cpumask)
  58 {
  59         return cpumask_bits(cpumask)[0];
  60 }
  61
  62 static inline unsigned int cpu_mask_to_apicid_and(const struct cpumask *cpumask,
  63                                                   const struct cpumask *andmask)
  64 {
  65         unsigned long mask1 = cpumask_bits(cpumask)[0];
  66         unsigned long mask2 = cpumask_bits(andmask)[0];
  67         unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];
  68
  69         return (unsigned int)(mask1 & mask2 & mask3);
  70 }
  71
  72 static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
  73 {
  74         return cpuid_apic >> index_msb;
  75 }
  76
  77 static inline void setup_apic_routing(void)
  78 {
  79 #ifdef CONFIG_X86_IO_APIC
  80         printk("Enabling APIC mode:  %s.  Using %d I/O APICs\n",
  81                                         "Flat", nr_ioapics);
  82 #endif
  83 }
  84
  85 static inline int apicid_to_node(int logical_apicid)
  86 {
  87 #ifdef CONFIG_SMP
  88         return apicid_2_node[hard_smp_processor_id()];
  89 #else
  90         return 0;
  91 #endif
  92 }
  93
  94 static inline void vector_allocation_domain(int cpu, struct cpumask *retmask)
  95 {
  96         /* Careful. Some cpus do not strictly honor the set of cpus
  97          * specified in the interrupt destination when using lowest
  98          * priority interrupt delivery mode.
  99          *
 100          * In particular there was a hyperthreading cpu observed to
 101          * deliver interrupts to the wrong hyperthread when only one
 102          * hyperthread was specified in the interrupt desitination.
 103          */
 104         *retmask = (cpumask_t) { { [0] = APIC_ALL_CPUS } };
 105 }
 106 #endif
 107
 108 static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid)
 109 {
 110         return physid_isset(apicid, bitmap);
 111 }
 112
 113 static inline unsigned long default_check_apicid_present(int bit)
 114 {
 115         return physid_isset(bit, phys_cpu_present_map);
 116 }
 117
 118 static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
 119 {
 120         return phys_map;
 121 }
 122
 123 static inline int multi_timer_check(int apic, int irq)
 124 {
 125         return 0;
 126 }
 127
 128 /* Mapping from cpu number to logical apicid */
 129 static inline int cpu_to_logical_apicid(int cpu)
 130 {
 131         return 1 << cpu;
 132 }
 133
 134 static inline int cpu_present_to_apicid(int mps_cpu)
 135 {
 136         if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
 137                 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
 138         else
 139                 return BAD_APICID;
 140 }
 141
 142 static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
 143 {
 144         return physid_mask_of_physid(phys_apicid);
 145 }
 146
 147 static inline void setup_portio_remap(void)
 148 {
 149 }
 150
 151 static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
 152 {
 153         return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map);
 154 }
 155
 156 static inline void enable_apic_mode(void)
 157 {
 158 }
 159 #endif /* CONFIG_X86_LOCAL_APIC */
 160 #endif /* _ASM_X86_MACH_DEFAULT_MACH_APIC_H */