ide: falconide/q40ide - Use __ide_mm_{in,out}sw() for data
[linux-2.6/mini2440.git] / drivers / ata / pata_cs5520.c
blob0df83cf742337d4d481822e2d705b3a1802196aa
1 /*
2 * IDE tuning and bus mastering support for the CS5510/CS5520
3 * chipsets
5 * The CS5510/CS5520 are slightly unusual devices. Unlike the
6 * typical IDE controllers they do bus mastering with the drive in
7 * PIO mode and smarter silicon.
9 * The practical upshot of this is that we must always tune the
10 * drive for the right PIO mode. We must also ignore all the blacklists
11 * and the drive bus mastering DMA information. Also to confuse matters
12 * further we can do DMA on PIO only drives.
14 * DMA on the 5510 also requires we disable_hlt() during DMA on early
15 * revisions.
17 * *** This driver is strictly experimental ***
19 * (c) Copyright Red Hat Inc 2002
21 * This program is free software; you can redistribute it and/or modify it
22 * under the terms of the GNU General Public License as published by the
23 * Free Software Foundation; either version 2, or (at your option) any
24 * later version.
26 * This program is distributed in the hope that it will be useful, but
27 * WITHOUT ANY WARRANTY; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
29 * General Public License for more details.
31 * Documentation:
32 * Not publically available.
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/init.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <scsi/scsi_host.h>
41 #include <linux/libata.h>
43 #define DRV_NAME "pata_cs5520"
44 #define DRV_VERSION "0.6.6"
46 struct pio_clocks
48 int address;
49 int assert;
50 int recovery;
53 static const struct pio_clocks cs5520_pio_clocks[]={
54 {3, 6, 11},
55 {2, 5, 6},
56 {1, 4, 3},
57 {1, 3, 2},
58 {1, 2, 1}
61 /**
62 * cs5520_set_timings - program PIO timings
63 * @ap: ATA port
64 * @adev: ATA device
66 * Program the PIO mode timings for the controller according to the pio
67 * clocking table.
70 static void cs5520_set_timings(struct ata_port *ap, struct ata_device *adev, int pio)
72 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
73 int slave = adev->devno;
75 pio -= XFER_PIO_0;
77 /* Channel command timing */
78 pci_write_config_byte(pdev, 0x62 + ap->port_no,
79 (cs5520_pio_clocks[pio].recovery << 4) |
80 (cs5520_pio_clocks[pio].assert));
81 /* FIXME: should these use address ? */
82 /* Read command timing */
83 pci_write_config_byte(pdev, 0x64 + 4*ap->port_no + slave,
84 (cs5520_pio_clocks[pio].recovery << 4) |
85 (cs5520_pio_clocks[pio].assert));
86 /* Write command timing */
87 pci_write_config_byte(pdev, 0x66 + 4*ap->port_no + slave,
88 (cs5520_pio_clocks[pio].recovery << 4) |
89 (cs5520_pio_clocks[pio].assert));
92 /**
93 * cs5520_enable_dma - turn on DMA bits
95 * Turn on the DMA bits for this disk. Needed because the BIOS probably
96 * has not done the work for us. Belongs in the core SATA code.
99 static void cs5520_enable_dma(struct ata_port *ap, struct ata_device *adev)
101 /* Set the DMA enable/disable flag */
102 u8 reg = ioread8(ap->ioaddr.bmdma_addr + 0x02);
103 reg |= 1<<(adev->devno + 5);
104 iowrite8(reg, ap->ioaddr.bmdma_addr + 0x02);
108 * cs5520_set_dmamode - program DMA timings
109 * @ap: ATA port
110 * @adev: ATA device
112 * Program the DMA mode timings for the controller according to the pio
113 * clocking table. Note that this device sets the DMA timings to PIO
114 * mode values. This may seem bizarre but the 5520 architecture talks
115 * PIO mode to the disk and DMA mode to the controller so the underlying
116 * transfers are PIO timed.
119 static void cs5520_set_dmamode(struct ata_port *ap, struct ata_device *adev)
121 static const int dma_xlate[3] = { XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 };
122 cs5520_set_timings(ap, adev, dma_xlate[adev->dma_mode]);
123 cs5520_enable_dma(ap, adev);
127 * cs5520_set_piomode - program PIO timings
128 * @ap: ATA port
129 * @adev: ATA device
131 * Program the PIO mode timings for the controller according to the pio
132 * clocking table. We know pio_mode will equal dma_mode because of the
133 * CS5520 architecture. At least once we turned DMA on and wrote a
134 * mode setter.
137 static void cs5520_set_piomode(struct ata_port *ap, struct ata_device *adev)
139 cs5520_set_timings(ap, adev, adev->pio_mode);
142 static struct scsi_host_template cs5520_sht = {
143 ATA_BMDMA_SHT(DRV_NAME),
144 .sg_tablesize = LIBATA_DUMB_MAX_PRD,
147 static struct ata_port_operations cs5520_port_ops = {
148 .inherits = &ata_bmdma_port_ops,
149 .qc_prep = ata_sff_dumb_qc_prep,
150 .cable_detect = ata_cable_40wire,
151 .set_piomode = cs5520_set_piomode,
152 .set_dmamode = cs5520_set_dmamode,
155 static int __devinit cs5520_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
157 static const unsigned int cmd_port[] = { 0x1F0, 0x170 };
158 static const unsigned int ctl_port[] = { 0x3F6, 0x376 };
159 struct ata_port_info pi = {
160 .flags = ATA_FLAG_SLAVE_POSS,
161 .pio_mask = ATA_PIO4,
162 .port_ops = &cs5520_port_ops,
164 const struct ata_port_info *ppi[2];
165 u8 pcicfg;
166 void __iomem *iomap[5];
167 struct ata_host *host;
168 struct ata_ioports *ioaddr;
169 int i, rc;
171 rc = pcim_enable_device(pdev);
172 if (rc)
173 return rc;
175 /* IDE port enable bits */
176 pci_read_config_byte(pdev, 0x60, &pcicfg);
178 /* Check if the ATA ports are enabled */
179 if ((pcicfg & 3) == 0)
180 return -ENODEV;
182 ppi[0] = ppi[1] = &ata_dummy_port_info;
183 if (pcicfg & 1)
184 ppi[0] = &pi;
185 if (pcicfg & 2)
186 ppi[1] = &pi;
188 if ((pcicfg & 0x40) == 0) {
189 dev_printk(KERN_WARNING, &pdev->dev,
190 "DMA mode disabled. Enabling.\n");
191 pci_write_config_byte(pdev, 0x60, pcicfg | 0x40);
194 pi.mwdma_mask = id->driver_data;
196 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
197 if (!host)
198 return -ENOMEM;
200 /* Perform set up for DMA */
201 if (pci_enable_device_io(pdev)) {
202 printk(KERN_ERR DRV_NAME ": unable to configure BAR2.\n");
203 return -ENODEV;
206 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
207 printk(KERN_ERR DRV_NAME ": unable to configure DMA mask.\n");
208 return -ENODEV;
210 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
211 printk(KERN_ERR DRV_NAME ": unable to configure consistent DMA mask.\n");
212 return -ENODEV;
215 /* Map IO ports and initialize host accordingly */
216 iomap[0] = devm_ioport_map(&pdev->dev, cmd_port[0], 8);
217 iomap[1] = devm_ioport_map(&pdev->dev, ctl_port[0], 1);
218 iomap[2] = devm_ioport_map(&pdev->dev, cmd_port[1], 8);
219 iomap[3] = devm_ioport_map(&pdev->dev, ctl_port[1], 1);
220 iomap[4] = pcim_iomap(pdev, 2, 0);
222 if (!iomap[0] || !iomap[1] || !iomap[2] || !iomap[3] || !iomap[4])
223 return -ENOMEM;
225 ioaddr = &host->ports[0]->ioaddr;
226 ioaddr->cmd_addr = iomap[0];
227 ioaddr->ctl_addr = iomap[1];
228 ioaddr->altstatus_addr = iomap[1];
229 ioaddr->bmdma_addr = iomap[4];
230 ata_sff_std_ports(ioaddr);
232 ata_port_desc(host->ports[0],
233 "cmd 0x%x ctl 0x%x", cmd_port[0], ctl_port[0]);
234 ata_port_pbar_desc(host->ports[0], 4, 0, "bmdma");
236 ioaddr = &host->ports[1]->ioaddr;
237 ioaddr->cmd_addr = iomap[2];
238 ioaddr->ctl_addr = iomap[3];
239 ioaddr->altstatus_addr = iomap[3];
240 ioaddr->bmdma_addr = iomap[4] + 8;
241 ata_sff_std_ports(ioaddr);
243 ata_port_desc(host->ports[1],
244 "cmd 0x%x ctl 0x%x", cmd_port[1], ctl_port[1]);
245 ata_port_pbar_desc(host->ports[1], 4, 8, "bmdma");
247 /* activate the host */
248 pci_set_master(pdev);
249 rc = ata_host_start(host);
250 if (rc)
251 return rc;
253 for (i = 0; i < 2; i++) {
254 static const int irq[] = { 14, 15 };
255 struct ata_port *ap = host->ports[i];
257 if (ata_port_is_dummy(ap))
258 continue;
260 rc = devm_request_irq(&pdev->dev, irq[ap->port_no],
261 ata_sff_interrupt, 0, DRV_NAME, host);
262 if (rc)
263 return rc;
265 ata_port_desc(ap, "irq %d", irq[i]);
268 return ata_host_register(host, &cs5520_sht);
271 #ifdef CONFIG_PM
273 * cs5520_reinit_one - device resume
274 * @pdev: PCI device
276 * Do any reconfiguration work needed by a resume from RAM. We need
277 * to restore DMA mode support on BIOSen which disabled it
280 static int cs5520_reinit_one(struct pci_dev *pdev)
282 struct ata_host *host = dev_get_drvdata(&pdev->dev);
283 u8 pcicfg;
284 int rc;
286 rc = ata_pci_device_do_resume(pdev);
287 if (rc)
288 return rc;
290 pci_read_config_byte(pdev, 0x60, &pcicfg);
291 if ((pcicfg & 0x40) == 0)
292 pci_write_config_byte(pdev, 0x60, pcicfg | 0x40);
294 ata_host_resume(host);
295 return 0;
299 * cs5520_pci_device_suspend - device suspend
300 * @pdev: PCI device
302 * We have to cut and waste bits from the standard method because
303 * the 5520 is a bit odd and not just a pure ATA device. As a result
304 * we must not disable it. The needed code is short and this avoids
305 * chip specific mess in the core code.
308 static int cs5520_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
310 struct ata_host *host = dev_get_drvdata(&pdev->dev);
311 int rc = 0;
313 rc = ata_host_suspend(host, mesg);
314 if (rc)
315 return rc;
317 pci_save_state(pdev);
318 return 0;
320 #endif /* CONFIG_PM */
322 /* For now keep DMA off. We can set it for all but A rev CS5510 once the
323 core ATA code can handle it */
325 static const struct pci_device_id pata_cs5520[] = {
326 { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5510), },
327 { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5520), },
329 { },
332 static struct pci_driver cs5520_pci_driver = {
333 .name = DRV_NAME,
334 .id_table = pata_cs5520,
335 .probe = cs5520_init_one,
336 .remove = ata_pci_remove_one,
337 #ifdef CONFIG_PM
338 .suspend = cs5520_pci_device_suspend,
339 .resume = cs5520_reinit_one,
340 #endif
343 static int __init cs5520_init(void)
345 return pci_register_driver(&cs5520_pci_driver);
348 static void __exit cs5520_exit(void)
350 pci_unregister_driver(&cs5520_pci_driver);
353 MODULE_AUTHOR("Alan Cox");
354 MODULE_DESCRIPTION("low-level driver for Cyrix CS5510/5520");
355 MODULE_LICENSE("GPL");
356 MODULE_DEVICE_TABLE(pci, pata_cs5520);
357 MODULE_VERSION(DRV_VERSION);
359 module_init(cs5520_init);
360 module_exit(cs5520_exit);